fpga: x400: Add makefiles for RF testbenches
Original-commit: 319d8c6411f62a2150b21b38bfe5fd55366ee700
This commit is contained in:
Wade Fife
@@ -1,6 +1,5 @@
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# This file contains all testbenches to exlcude from the filter
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# list discovered by run_testbenches.py
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# NOTE: Lines containing "#" are treated as a comment
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# This file contains all testbenches to exlcude from the filter list discovered
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# by run_testbenches.py with the Vivado simulator (xsim).
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top/e31x/sim/dram_test
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top/n3xx/sim/arm_to_sfp_loopback
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@@ -15,3 +14,4 @@ lib/axi4s_sv/axi4s_add_bytes_tb
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lib/rfnoc/xport_sv/eth_interface_tb
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top/x400/sim/x4xx_qsfp_wrapper
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top/x400/ip/eth_100g_bd/lbus_tb
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top/x400/rf/sim
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@@ -0,0 +1,15 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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RF_100M_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/100m/, \
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adc_3_1_clk_converter.vhd \
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dac_1_3_clk_converter.vhd \
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dac_2_1_clk_converter.vhd \
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adc_gearbox_2x1.v \
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ddc_saturate.vhd \
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duc_saturate.vhd \
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rf_core_100m.v \
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))
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@@ -0,0 +1,11 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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RF_200M_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/200m/, \
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rf_down_4to2.v \
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rf_up_2to4.v \
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rf_core_200m.v \
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))
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@@ -0,0 +1,17 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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RF_400M_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/400m/, \
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adc_gearbox_2x4.vhd \
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adc_gearbox_8x4.v \
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dac_gearbox_12x8.vhd \
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dac_gearbox_4x2.v \
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dac_gearbox_6x12.vhd \
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dac_gearbox_6x8.vhd \
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ddc_400m_saturate.vhd \
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duc_400m_saturate.vhd \
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rf_core_400m.v \
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))
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@@ -0,0 +1,18 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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RF_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/common/, \
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PkgRf.vhd \
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axis_mux.vhd \
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capture_sysref.v \
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clock_gates.vhd \
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gpio_to_axis_mux.vhd \
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rf_nco_reset.vhd \
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rf_reset.vhd \
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rf_reset_controller.vhd \
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scale_2x.vhd \
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sync_wrapper.v \
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))
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@@ -0,0 +1,91 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir. Note:
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# UHD_FPGA_DIR must be passed into this Makefile.
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BASE_DIR = ../../..
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = zynquplusRFSOC
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PART_ID = xczu28dr/ffvg1517/-1/e
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(FIFO_SRCS) \
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$(AXI_SRCS) \
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$(CONTROL_LIB_SRCS) \
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)
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include ../common/Makefile.srcs
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include ../100m/Makefile.srcs
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include ../200m/Makefile.srcs
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include ../400m/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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../../regmap/PkgRFDC_REGS_REGMAP.vhd \
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$(RF_COMMON_SRCS) \
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$(RF_100M_SRCS) \
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$(RF_200M_SRCS) \
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$(RF_400M_SRCS) \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = $(BASE_DIR)/x400/ip
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LIB_IP_DIR = $(BASE_DIR)/../lib/ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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#
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# These TBs don't use any IP yet :)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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include $(BASE_DIR)/../sim/general/Makefile.srcs
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# Define only one top-level module
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SIM_TOP = rf_all_tb
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# Simulation runtime in microseconds
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SIM_RUNTIME_US = 1000
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SIM_SRCS = \
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$(abspath tb_adc_gearbox_2x1.vhd ) \
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$(abspath tb_adc_gearbox_2x4.vhd ) \
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$(abspath tb_adc_gearbox_8x4.vhd ) \
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$(abspath tb_capture_sysref.vhd ) \
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$(abspath tb_dac_gearbox_12x8.vhd ) \
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$(abspath tb_dac_gearbox_4x2.vhd ) \
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$(abspath tb_dac_gearbox_6x12.vhd ) \
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$(abspath tb_ddc_400m_saturate.vhd ) \
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$(abspath tb_duc_400m_saturate.vhd ) \
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$(abspath tb_rf_nco_reset.vhd ) \
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$(abspath tb_rf_reset_controller.vhd) \
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$(abspath rf_all_tb.sv ) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,57 @@
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//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rf_all_tb
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//
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// Description:
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//
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// Top-level testbench for X400 RF components. This instantiates all the RF
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// testbenches.
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//
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module rf_all_tb;
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`include "test_exec.svh"
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import PkgTestExec::*;
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tb_adc_gearbox_2x1 tb_adc_gearbox_2x1_i ();
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tb_adc_gearbox_2x4 tb_adc_gearbox_2x4_i ();
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tb_adc_gearbox_8x4 tb_adc_gearbox_8x4_i ();
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tb_capture_sysref tb_capture_sysref_i ();
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tb_dac_gearbox_12x8 tb_dac_gearbox_12x8_i ();
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tb_dac_gearbox_4x2 tb_dac_gearbox_4x2_i ();
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tb_dac_gearbox_6x12 tb_dac_gearbox_6x12_i ();
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tb_ddc_400m_saturate tb_ddc_400m_saturate_i ();
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tb_duc_400m_saturate tb_duc_400m_saturate_i ();
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tb_rf_nco_reset tb_rf_nco_reset_i ();
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tb_rf_reset_controller tb_rf_reset_controller_i ();
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initial begin
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test.start_tb("rf_all_tb", 1ms);
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test.start_test("Run RF TBs");
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forever begin
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#100ns;
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if (
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tb_adc_gearbox_2x1_i.StopSim &&
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tb_adc_gearbox_2x4_i.StopSim &&
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tb_adc_gearbox_8x4_i.StopSim &&
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tb_capture_sysref_i.StopSim &&
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tb_dac_gearbox_12x8_i.StopSim &&
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tb_dac_gearbox_4x2_i.StopSim &&
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tb_dac_gearbox_6x12_i.StopSim &&
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tb_ddc_400m_saturate_i.StopSim &&
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tb_duc_400m_saturate_i.StopSim &&
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tb_rf_nco_reset_i.StopSim &&
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tb_rf_reset_controller_i.StopSim
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) break;
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end
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test.end_test();
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// If they all stop before the timeout, and there are no errors, then we
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// assume everything passed.
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test.end_tb();
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end
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endmodule : rf_all_tb
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