Wade Fife 3bc803026b fpga: lib: Pipeline ctrlport_timer ...

This pipelines ctrlport_timer to eliminate the long combinational path
caused by the time comparisons. This change also removes the
PRECISION_BITS parameter and converts it to a signal named
time_ignore_bits.


Original-commit: c6035320215f270d7658cfb6195a96a0b84d6aa7

2021-06-03 11:26:54 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Pipeline ctrlport_timer

2021-06-03 11:26:54 -05:00

sim

fpga: lib: Add PHASE parameter to sim_clk_gen

2021-06-03 11:26:54 -05:00

tools

fpga: tools: Add ability to run commands before route

2021-06-03 10:22:04 -05:00

top

fpga: e320: Improve timing on LVDS interface

2020-12-11 07:41:13 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%