miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: x300: Fix time register readback

Browse Source 
Original-commit: 610488690a5f7bf1dd828aa6b9a70dd0874ca87f
This commit is contained in:
Wade Fife
2021-12-15 17:16:32 -06:00
parent e7f0945319
commit 3566b21f6f
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x300/bus_int.v
+2 -2
View File
@@ -439,12 +439,12 @@ module bus_int #(
RB_FP_GPIO_SRC: rb_data = fp_gpio_src;
SR_BASE_TIME: begin
rb_data = radio_time[31:0];
radio_time_hi_ld = 1'b1;
radio_time_hi_ld = rb_rd_stb;
end
SR_BASE_TIME + 'h04: rb_data = radio_time_hi;
SR_BASE_TIME + 'h14: begin
rb_data = radio_time_last_pps[31:0];
radio_time_last_pps_hi_ld = 1'b1;
radio_time_last_pps_hi_ld = rb_rd_stb;
end
SR_BASE_TIME + 'h18: rb_data = radio_time_last_pps_hi;
SR_BASE_TIME + 'h1C: rb_data = period_ns_q32_tb[31:0];