Wade Fife cfb4ba7f0b fpga: tools: Add ability to patch IP during generation ...

This adds the ability to call BUILD_VIVADO_IP, as before, followed by
REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and
then rebuild the IP with the patched file.


Original-commit: 78315eca698333ad4dc32818e24c7bf6a740c0cb

2021-06-03 10:22:04 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Minor cleanup of axi_lite.vh

2021-06-03 09:34:20 -05:00

sim

fpga: sim: Fix stream command and status models

2020-08-31 08:16:43 -05:00

tools

fpga: tools: Add ability to patch IP during generation

2021-06-03 10:22:04 -05:00

top

fpga: e320: Improve timing on LVDS interface

2020-12-11 07:41:13 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%