Wade Fife d37cc533a7 fpga: tools: Put SIM_SRCS at end of compile order ...

VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.


Original-commit: b85b796cbc1f897a69ded1f3ecfba8ec92684c11

2021-06-17 08:16:59 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Update register comments in eth_regs.vh

2021-06-10 11:56:58 -05:00

sim

fpga: sim: Add slave_idle() to PkgAxiStreamBfm.sv

2021-06-10 11:56:58 -05:00

tools

fpga: tools: Put SIM_SRCS at end of compile order

2021-06-17 08:16:59 -05:00

top

fpga: x400: zbx: Add support for ZBX CPLD

2021-06-10 11:56:58 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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