Wade Fife d37cc533a7 fpga: tools: Put SIM_SRCS at end of compile order ...

VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.


Original-commit: b85b796cbc1f897a69ded1f3ecfba8ec92684c11

2021-06-17 08:16:59 -05:00

..

make

fpga: tools: Support new FPGA types in viv_simulator.mak

2021-06-17 08:16:59 -05:00

scripts

fpga: tools: Put SIM_SRCS at end of compile order

2021-06-17 08:16:59 -05:00

utils

fpga: tools: Add modelsim.excludes

2021-06-17 08:16:59 -05:00