Wade Fife 43e32abd11 fpga: Update rfnoc_image_core for all targets ...

Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.


Original-commit: b0033158a4c520063540881451d8daac91e98714

2021-06-10 11:56:58 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add modports to SV AXI-Stream blocks

2021-06-03 11:26:54 -05:00

sim

fpga: lib: Add PHASE parameter to sim_clk_gen

2021-06-03 11:26:54 -05:00

tools

fpga: tools: Fix part selection in setupenv

2021-06-10 08:33:22 -05:00

top

fpga: Update rfnoc_image_core for all targets

2021-06-10 11:56:58 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%