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fpga: Update testbenches to work in ModelSim

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Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
This commit is contained in:
Wade Fife
2021-06-17 08:16:59 -05:00
parent 162632e7c1
commit fcfc6bf387
11 changed files with 304 additions and 137 deletions
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lib/axi4s_sv/axi4s_remove_bytes_tb/axi4s_remove_bytes_tb.sv
+16 -11
View File
@@ -7,20 +7,23 @@
//
// Description: Testbench for axi_remove_bytes
//
// Parameters:
//
// TEST_NAME : Name of the test instance to run
// WIDTH : Packet data width to use
// REM_START : REM_START parameter to pass to the DUT
// REM_END : REM_END parameter to pass to the DUT
//
module axi4s_remove_bytes_tb #(
parameter TEST_NAME = "axi_remove_bytes",
WIDTH=32,REM_START=0,REM_END=7
)(
/* no IO */
parameter WIDTH = 32,
parameter REM_START = 0,
parameter REM_END = 7
);
// Include macros and time declarations for use with PkgTestExec
// To change the name of the TestExec object being used by the assertion
// macros, `define TEST_EXEC_OBJ before including this file and `undef it at
// the end of your testbench. Otherwise, it defaults to the shared object
// "PkgTestExec::test".
`define TEST_EXEC_OBJ test
`include "test_exec.svh"
import PkgAxiStreamBfm::*;
import PkgTestExec::*;
import PkgEthernet::*;
@@ -28,6 +31,7 @@ module axi4s_remove_bytes_tb #(
//---------------------------------------------------------------------------
// Local Parameters
//---------------------------------------------------------------------------
localparam UWIDTH = $clog2((WIDTH/8)+1);
localparam MAX_PACKET_BYTES = 16*1024;
@@ -41,13 +45,13 @@ module axi4s_remove_bytes_tb #(
bit clk;
bit reset;
sim_clock_gen #(.PERIOD(5.0), .AUTOSTART(1))
sim_clock_gen #(.PERIOD(5.0), .AUTOSTART(0))
clk_gen (.clk(clk), .rst(reset));
//---------------------------------------------------------------------------
// Bus Functional Models
//---------------------------------------------------------------------------
TestExec test = new();
AxiStreamIf #(.DATA_WIDTH(WIDTH),.USER_WIDTH(UWIDTH),.TKEEP(0),
.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
i (clk, reset);
@@ -191,7 +195,8 @@ module axi4s_remove_bytes_tb #(
initial begin : tb_main
automatic integer min_length;
test.tb_name = TEST_NAME;
test.start_tb(TEST_NAME);
clk_gen.start();
if (REM_END == -1)
min_length = REM_START-4;
lib/rfnoc/xport_sv/eth_interface_tb/eth_ifc_all_tb.sv
+6 -11
View File
@@ -8,17 +8,12 @@
// Description: Testbench for eth_ifc
//
module eth_ifc_all_tb #(
/* no PARAM */
)(
/* no IO */
);
module eth_ifc_all_tb;
eth_ifc_tb #(.TEST_NAME("ORIGINAL"),.ENET_W(64),.CPU_W(64),.CHDR_W(64),.SV_ETH_IFC(0)) ORIGINAL ();
eth_ifc_tb #(.TEST_NAME("64B"),.ENET_W(64),.CPU_W(64),.CHDR_W(64)) ETH64 ();
eth_ifc_tb #(.TEST_NAME("512_64B"),.ENET_W(512),.CPU_W(64),.CHDR_W(64)) ETH512_CHDR64 ();
eth_ifc_tb #(.TEST_NAME("512_128B"),.ENET_W(512),.CPU_W(64),.CHDR_W(128)) ETH512_CHDR128 ();
eth_ifc_tb #(.TEST_NAME("512B"),.ENET_W(512),.CPU_W(64),.CHDR_W(512)) ETH512_CHDR512 ();
eth_ifc_tb #(.TEST_NAME("ORIGINAL"), .ENET_W(64), .CPU_W(64), .CHDR_W(64), .SV_ETH_IFC(0)) ORIGINAL ();
eth_ifc_tb #(.TEST_NAME("64B"), .ENET_W(64), .CPU_W(64), .CHDR_W(64), .SV_ETH_IFC(1)) ETH64 ();
eth_ifc_tb #(.TEST_NAME("512B"), .ENET_W(512), .CPU_W(64), .CHDR_W(512), .SV_ETH_IFC(1)) ETH512_CHDR512 ();
eth_ifc_tb #(.TEST_NAME("512_64B"), .ENET_W(512), .CPU_W(64), .CHDR_W(64), .SV_ETH_IFC(1)) ETH512_CHDR64 ();
eth_ifc_tb #(.TEST_NAME("512_128B"), .ENET_W(512), .CPU_W(64), .CHDR_W(128), .SV_ETH_IFC(1)) ETH512_CHDR128 ();
endmodule
lib/rfnoc/xport_sv/eth_interface_tb/eth_ifc_tb.sv
+49 -25
View File
@@ -10,15 +10,14 @@
module eth_ifc_tb #(
parameter TEST_NAME = "eth_ifc_tb",
parameter SV_ETH_IFC =1,
parameter ENET_W =64,
parameter CPU_W =64,
parameter CHDR_W =64
parameter SV_ETH_IFC = 1,
parameter ENET_W = 64,
parameter CPU_W = 64,
parameter CHDR_W = 64
)(
/* no IO */
);
// Include macros and time declarations for use with PkgTestExec
`define TEST_EXEC_OBJ test
`include "test_exec.svh"
import PkgAxiStreamBfm::*;
import PkgTestExec::*;
@@ -54,18 +53,38 @@ module eth_ifc_tb #(
// Clocks
//---------------------------------------------------------------------------
// ModelSim should initialize the fields of ipv4_hdr to their default values,
// but there's a bug where it doesn't in some cases. This constant is used to
// initialize them to work around the bug.
localparam ipv4_hdr_t DEFAULT_IPV4_HDR = '{
header_length : 4'd5,
version : 4'd4,
dscp : 6'b0000_00,
ecn : 2'b00,
length : 16'hXXXX,
identification: 16'h462E,
rsv_zero : 1'b0,
dont_frag : 1'b1,
more_frag : 1'b0,
frag_offset : 16'd0,
time_to_live : 16'd64,
protocol : UDP,
checksum : 16'hXXXX,
src_ip : DEF_SRC_IP_ADDR,
dest_ip : DEF_DEST_IP_ADDR
};
bit clk;
bit reset;
sim_clock_gen #(.PERIOD(5.0), .AUTOSTART(1))
sim_clock_gen #(.PERIOD(5.0), .AUTOSTART(0))
clk_gen (.clk(clk), .rst(reset));
sim_clock_gen #(.PERIOD(ETH_PERIOD), .AUTOSTART(1))
sim_clock_gen #(.PERIOD(ETH_PERIOD), .AUTOSTART(0))
eth_clk_gen (.clk(eth_clk), .rst(eth_reset));
//---------------------------------------------------------------------------
// Bus Functional Models
//---------------------------------------------------------------------------
TestExec test = new();
localparam MAX_PACKET_BYTES = 2**16;
AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),
@@ -132,7 +151,7 @@ module eth_ifc_tb #(
.BASE(BASE),.SYNC(SYNC),
.ENET_W(ENET_W),.CPU_W(CPU_W),.CHDR_W(CHDR_W)
) eth_interface (
.bus_clk(clk),.bus_rst(reset),.*
.bus_clk(clk),.bus_rst(reset),.eth_pause_req(),.*
);
end else begin : gen_old_dut
logic [63:0] eth_tx_tdata;
@@ -272,7 +291,7 @@ module eth_ifc_tb #(
//---------------------------------------------------------------------------
task test_registers();
test.start_test({TEST_NAME,"Test/Setup Registers"}, 10us);
test.start_test({TEST_NAME,"::Test/Setup Registers"}, 10us);
// DEF_DEST_MAC/IP/UDP are defined in the
// sim_ethernet_lib.svh, as the destination
// addresses. Using the defaults means
@@ -341,7 +360,7 @@ module eth_ifc_tb #(
automatic CpuXportPacket_t expected[$];
automatic int sample_sum = 0;
test_e2c.start_test({TEST_NAME,"Ethernet to CPU"}, 60us);
test_e2c.start_test({TEST_NAME,"::Ethernet to CPU"}, 60us);
// This path is
// eth_rx -> s_mac(eth_adapter) -> s_mac(eth_dispatch) ->
//// in_reg(AXI_FIFO)(SIZE=1)
@@ -355,7 +374,7 @@ module eth_ifc_tb #(
foreach (num_samples[i]) begin
automatic eth_hdr_t eth_hdr;
automatic ipv4_hdr_t ipv4_hdr;
automatic ipv4_hdr_t ipv4_hdr = DEFAULT_IPV4_HDR;
automatic udp_hdr_t udp_hdr;
automatic raw_pkt_t pay,udp_raw;
automatic int preamble;
@@ -454,7 +473,7 @@ module eth_ifc_tb #(
automatic raw_pkt_t rcv_raw,rcv_pay;
automatic udp_hdr_t rcv_udp;
automatic eth_hdr_t rcv_eth;
automatic ipv4_hdr_t rcv_ip;
automatic ipv4_hdr_t rcv_ip = DEFAULT_IPV4_HDR;
automatic int try_count = 0;
do begin
@@ -477,7 +496,7 @@ module eth_ifc_tb #(
automatic EthXportPacket_t expected[$];
automatic int sample_sum = 0;
test_c2e.start_test({TEST_NAME,"CPU to Ethernet"}, 60us);
test_c2e.start_test({TEST_NAME,"::CPU to Ethernet"}, 60us);
// This path is
// c2e -> (eth_adapter) s_cpu ->
//// (ARM_DEFRAMER)(IF ARM)
@@ -487,7 +506,7 @@ module eth_ifc_tb #(
foreach (num_samples[i]) begin
automatic eth_hdr_t eth_hdr;
automatic ipv4_hdr_t ipv4_hdr;
automatic ipv4_hdr_t ipv4_hdr = DEFAULT_IPV4_HDR;
automatic udp_hdr_t udp_hdr;
automatic raw_pkt_t pay,udp_raw;
automatic int preamble;
@@ -532,7 +551,7 @@ module eth_ifc_tb #(
automatic raw_pkt_t rcv_raw,rcv_pay;
automatic udp_hdr_t rcv_udp;
automatic eth_hdr_t rcv_eth;
automatic ipv4_hdr_t rcv_ip;
automatic ipv4_hdr_t rcv_ip = DEFAULT_IPV4_HDR;
automatic int try_count = 0;
wait_for_udp_packets(DEF_DEST_UDP_PORT);
@@ -590,7 +609,7 @@ module eth_ifc_tb #(
automatic ChdrXportPacket_t expected[$];
automatic int sample_sum = 0;
test_e2v.start_test({TEST_NAME,"Ethernet to CHDR"}, 60us);
test_e2v.start_test({TEST_NAME,"::Ethernet to CHDR"}, 60us);
// This path is
// eth_rx -> s_mac(eth_adapter) -> s_mac(eth_dispatch) ->
//// in_reg(AXI_FIFO)(SIZE=1)
@@ -611,7 +630,7 @@ module eth_ifc_tb #(
foreach (num_samples[i]) begin
automatic eth_hdr_t eth_hdr;
automatic ipv4_hdr_t ipv4_hdr;
automatic ipv4_hdr_t ipv4_hdr = DEFAULT_IPV4_HDR;
automatic udp_hdr_t udp_hdr;
automatic raw_pkt_t pay,udp_raw,chdr_raw;
@@ -731,7 +750,7 @@ module eth_ifc_tb #(
automatic EthXportPacket_t expected[$];
automatic int sample_sum = 0;
test_v2e.start_test({TEST_NAME,"CHDR to Ethernet"}, 60us);
test_v2e.start_test({TEST_NAME,"::CHDR to Ethernet"}, 60us);
// This path is
// v2e -> s_chdr(eth_adapter) -> s_axis_rfnoc (xport_adapter_gen) ->
//// axi_demux_mgmt_filter (AXI_DEMUX) (IF ALLOW_DISC) (discards discovery packets)
@@ -750,7 +769,7 @@ module eth_ifc_tb #(
foreach (num_samples[i]) begin
automatic eth_hdr_t eth_hdr;
automatic ipv4_hdr_t ipv4_hdr;
automatic ipv4_hdr_t ipv4_hdr = DEFAULT_IPV4_HDR;
automatic udp_hdr_t udp_hdr;
automatic raw_pkt_t pay,udp_raw,chdr_raw;
@@ -831,7 +850,7 @@ module eth_ifc_tb #(
automatic EthAxisPacket_t actual_a;
automatic EthXportPacket_t actual = new();
automatic eth_hdr_t eth_hdr;
automatic ipv4_hdr_t ipv4_hdr;
automatic ipv4_hdr_t ipv4_hdr = DEFAULT_IPV4_HDR;
automatic udp_hdr_t udp_hdr;
automatic raw_pkt_t chdr_raw,actual_raw;
automatic ChdrPacket_t chdr_pkt;
@@ -874,7 +893,7 @@ module eth_ifc_tb #(
automatic int sample_sum = 0;
automatic eth_hdr_t eth_hdr;
automatic ipv4_hdr_t ipv4_hdr;
automatic ipv4_hdr_t ipv4_hdr = DEFAULT_IPV4_HDR;
automatic udp_hdr_t udp_hdr;
automatic raw_pkt_t pay,udp_raw,chdr_raw;
@@ -890,7 +909,7 @@ module eth_ifc_tb #(
automatic int preamble;
localparam NODE_INST=0;
test_e2v.start_test({TEST_NAME,"ChdrEndpoint"}, 60us);
test_e2v.start_test({TEST_NAME,"::ChdrEndpoint"}, 60us);
expected[0] = new;
@@ -985,7 +1004,7 @@ module eth_ifc_tb #(
automatic EthAxisPacket_t actual_a;
automatic EthXportPacket_t actual = new();
automatic eth_hdr_t eth_hdr;
automatic ipv4_hdr_t ipv4_hdr;
automatic ipv4_hdr_t ipv4_hdr = DEFAULT_IPV4_HDR;
automatic udp_hdr_t udp_hdr;
automatic raw_pkt_t chdr_raw,actual_raw;
automatic ChdrPacket_t chdr_pkt;
@@ -1022,7 +1041,12 @@ module eth_ifc_tb #(
automatic int cpu_num_samples[$];
automatic int expected_drops;
localparam QUICK = 0;
test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
test.start_tb(TEST_NAME);
test.start_test({TEST_NAME,"::Wait for Reset"}, 10us);
clk_gen.start();
eth_clk_gen.start();
clk_gen.reset();
eth_clk_gen.reset();
top/n3xx/sim/dram_fifo/Makefile
+32 -3
View File
@@ -50,16 +50,45 @@ $(IP_FIFO_4K_2CLK_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/sim/axi_intercon_4x64_256_bd.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/ip/*/sim/*.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_tb.sv) \
$(abspath axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/n3xx/sim/dram_fifo_bist/Makefile
+32 -3
View File
@@ -50,16 +50,45 @@ $(IP_FIFO_4K_2CLK_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/sim/axi_intercon_4x64_256_bd.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/ip/*/sim/*.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_bist_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_bist_tb.sv) \
$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x300/sim/aurora_loopback/Makefile
+26 -1
View File
@@ -50,6 +50,30 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \
$(AURORA_PHY_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi64_4k_2clk_fifo/sim/axi64_4k_2clk_fifo.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma_core.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/src/*.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/example_design/*.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/example_design/gt/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
unisims_ver \
unimacro_ver \
secureip \
fifo_generator_v13_2_4 \
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
@@ -66,7 +90,8 @@ SIM_SRCS = \
$(abspath aurora_loopback_tb.sv) \
$(SIM_GENERAL_SRCS) \
$(SIM_CONTROL_SRCS) \
$(SIM_AXI_SRCS)
$(SIM_AXI_SRCS) \
$(MODELSIM_IP_SRCS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x300/sim/dram_fifo/Makefile
+32 -3
View File
@@ -52,16 +52,45 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \
$(IP_AXI4_BRAM_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/sim/axi_intercon_2x64_128_bd.v \
$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/ip/*/sim/*.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS = glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_tb.sv) \
$(abspath axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x300/sim/dram_fifo_bist/Makefile
+21 -3
View File
@@ -52,16 +52,34 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \
$(IP_AXI4_BRAM_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi4_dualport_sram/sim/axi4_dualport_sram.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
fifo_generator_v13_2_4 \
blk_mem_gen_v8_4_3 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_bist_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_bist_tb.sv) \
$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x400/ip/eth_100g_bd/lbus_tb/Makefile
+1 -1
View File
@@ -25,6 +25,7 @@ include $(BASE_DIR)/../lib/fifo/Makefile.srcs
#$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top.v) \
DESIGN_SRCS = $(abspath \
$(abspath ../PkgEth100gLbus.sv) \
$(abspath ../eth_100g_axis2lbus.sv) \
$(abspath ../eth_100g_lbus2axis.sv) \
$(FIFO_SRCS) \
@@ -41,7 +42,6 @@ TB_TOP_MODULE ?= lbus_all_tb
SIM_TOP = $(TB_TOP_MODULE)
SIM_SRCS = \
$(abspath ../PkgEth100gLbus.sv) \
$(abspath axi_lbus_tb.sv) \
$(abspath lbus_axi_tb.sv) \
$(abspath $(TB_TOP_MODULE).sv) \
top/x400/sim/x4xx_qsfp_wrapper/Makefile
+87 -74
View File
@@ -9,12 +9,9 @@
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../../../top)
IP_DIR = $(BASE_DIR)/x400/ip
# Include viv_sim_preamble after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
IP_BUILD_DIR = $(BASE_DIR)/x400/build-ip/xczu28drffvg1517-1e
#-------------------------------------------------
# Design Specific
@@ -24,106 +21,122 @@ ARCH = zynquplusRFSOC
PART_ID = xczu28dr/ffvg1517/-1/e
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/control/Makefile.srcs
include $(BASE_DIR)/../lib/axi/Makefile.srcs
include $(BASE_DIR)/../lib/axi4_sv/Makefile.srcs
include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
include $(BASE_DIR)/../lib/axi4lite_sv/Makefile.srcs
include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
include $(BASE_DIR)/../lib/xge/Makefile.srcs
include $(BASE_DIR)/../lib/wb_spi/Makefile.srcs
include $(BASE_DIR)/../lib/fifo/Makefile.srcs
include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
include $(BASE_DIR)/../lib/xge/Makefile.srcs
include $(IP_DIR)/Makefile.inc
IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
sim/axi_eth_dma_bd.v\
ip/*/sim/*.h\
ip/*/sim/*.v\
ip/*/sim/*.vhd\
ip/*/bd_0/hdl/*.v\
ip/*/bd_0/sim/*.v\
ip/*/bd_0/ip/ip_*/sim/*.v\
ip/*/bd_0/ip/ip_*/sim/*.sv\
ip/*/bd_0/ip/ip_*/sim/*.vhd\
ipshared/*/hdl/*.sv\
ipshared/*/hdl/*.v\
ipshared/*/simulation/*.v\
ipshared/*/hdl/verilog/*.v\
ipshared/*/hdl/verilog/*.svh\
ipshared/*/hdl/verilog/*.vh\
))
IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
ip/*/sim/*.v\
))
TOP_SRC = \
$(abspath $(BASE_DIR)/x400/x4xx_qsfp_wrapper.sv) \
$(abspath $(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv) \
$(abspath $(BASE_DIR)/x400/x4xx_mgt_io_core.sv) \
$(abspath $(BASE_DIR)/x400/x4xx.v)
# Xilinx IP wants lots of libraries
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
# Needed for the HACK_SRC, speeds up the alignment phase (still long!)
VLOG_ARGS = +define+SIM_SPEED_UP
SVLOG_ARGS = -lint +define+BUILD_100G=1
# Xilinx IP wants a second file loaded
MODELSIM_ARGS = glbl -t 1fs
DESIGN_SRCS = $(abspath \
DESIGN_SRCS += $(abspath \
$(AXI4_SV_SRCS) \
$(AXI4S_SV_SRCS) \
$(AXI4LITE_SV_SRCS) \
$(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) \
$(AXI_SRCS) \
$(XGE_SRCS) \
$(XGE_INTERFACE_SRCS) \
$(PACKET_PROC_SRCS) \
$(RFNOC_UTIL_SRCS) \
$(RFNOC_XPORT_SRCS) \
$(RFNOC_XPORT_SV_SRCS) \
$(RFNOC_XBAR_SRCS) \
$(RFNOC_CORE_SRCS) \
$(WISHBONE_SRCS) \
$(XGE_SRCS) \
$(XGE_INTERFACE_SRCS) \
)
# Add files for the DUT
DESIGN_SRCS += $(abspath \
$(BASE_DIR)/x400/x4xx_mgt_io_core.sv \
$(BASE_DIR)/x400/x4xx_qsfp_wrapper.sv \
$(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv \
)
#-------------------------------------------------
# IP Specific
#-------------------------------------------------
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory
IP_DIR = ../../ip
# Include makefiles and sources for all IP components
# *after* defining the IP_DIR
include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc
include $(IP_DIR)/xge_pcs_pma/Makefile.inc
include $(IP_DIR)/eth_100g_bd/Makefile.inc
DESIGN_SRCS += $(abspath \
$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) \
$(IP_AXI_ETH_DMA_BD_HDL_SRCS) \
$(IP_AXI_ETH_DMA_BD_SRCS) \
$(XGE_PCS_PMA_SRCS) \
$(IP_100G_HDL_SRCS) \
$(IP_100G_BD_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
sim/axi_eth_dma_bd.v \
ip/*/sim/*.h \
ip/*/sim/*.v \
ip/*/sim/*.vhd \
ip/*/bd_0/hdl/*.v \
ip/*/bd_0/sim/*.v \
ip/*/bd_0/ip/ip_*/sim/*.v \
ip/*/bd_0/ip/ip_*/sim/*.sv \
ip/*/bd_0/ip/ip_*/sim/*.vhd \
ipshared/*/hdl/*.sv \
ipshared/*/hdl/*.v \
ipshared/*/simulation/*.v \
ipshared/*/hdl/verilog/*.v \
ipshared/*/hdl/verilog/*.svh \
ipshared/*/hdl/verilog/*.vh \
))
IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
sim/*.v \
ip/*/sim/*.v \
))
MISC_IP_SIM_SRCS += \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
$(abspath $(IP_BUILD_DIR)/xge_pcs_pma/model_10gbe.sv) \
DESIGN_SRCS += $(abspath \
$(IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS) \
$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
$(IP_AXI_ETH_DMA_BD_HDL_SRCS) \
$(IP_100G_HDL_SRCS) \
$(AURORA_PHY_SRCS) \
$(IP_HDL_SIM_SRCS) \
$(TOP_SRC) \
$(IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS) \
$(IP_100G_HDL_SIM_SRCS) \
$(IP_XGE_PCS_PMA_HDL_SIM_SRCS) \
$(MISC_IP_SIM_SRCS) \
)
# Xilinx IP wants lots of libraries
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
MODELSIM_ARGS += glbl -t 1fs
# Needed for the HACK_SRC, speeds up the alignment phase (still long!)
VLOG_ARGS += +define+SIM_SPEED_UP
# Suppressing the following worthless reminder.
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
SVLOG_ARGS += -suppress 2583
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
TB_TOP_MODULE ?= x4xx_qsfp_wrapper_all_tb
SIM_TOP = $(TB_TOP_MODULE)
SIM_SRCS = \
$(abspath x4xx_qsfp_wrapper_tb.sv) \
$(abspath $(TB_TOP_MODULE).sv)
# Suppressing the following worthless reminder.
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
SVLOG_ARGS = -suppress 2583
$(abspath $(TB_TOP_MODULE).sv) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_tb.sv
+2 -2
View File
@@ -154,8 +154,8 @@ module x4xx_qsfp_wrapper_tb #(
AxiLiteIf_v #(.DATA_WIDTH(32),.ADDR_WIDTH(40))
s_axi_v (clk40, clk40_rst);
`include "../../../../../../lib/axi4lite_sv/axi_lite.vh"
`include "../../../../../../lib/axi4_sv/axi.vh"
`include "../../../../lib/axi4lite_sv/axi_lite.vh"
`include "../../../../lib/axi4_sv/axi.vh"
always_comb begin
`AXI4LITE_ASSIGN(s_axi_v,s_axi)
axi_hp_v.arready = 1'b1;