Wade Fife fd541b0d1a fpga: hls: Add version to generated HLS IP ...

This change causes HLS IP to be exported with a version of 1.0.0
instead of a date code. Due to a bug in Vivado, date codes after
0x7FFFFFFF (anything in 2022 or beyond) cause an error. Setting
an explicit revision avoids this issue.

See Xilinx AR 76960 for details.


Original-commit: 51384afc2c5d4db9e2e45d97382edce8c8039b10

2022-01-13 14:33:59 -06:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

uhd: update git://github.com references to https

2022-01-11 13:01:09 -06:00

sim

fpga: sim: Add PkgComplex, PkgMath, and PkgRandom

2021-08-08 14:59:26 -05:00

tools

fpga: hls: Add version to generated HLS IP

2022-01-13 14:33:59 -06:00

top

fpga: x400: Fix rfnoc_image_core.vh path

2022-01-12 23:44:38 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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