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fpga: x400: Add support for X410 motherboard FPGA

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Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
2021-06-10 11:56:58 -05:00
committed by Aaron Rossetto
co-authored by Andrew Moch Daniel Jepson Javier Valenzuela Joerg Hofrichter Kumaran Subramoniam Max Köhler Michael Auchter Paul Butler Hector Rubio
parent bfef20ea45
commit 61782b02d7
205 changed files with 299634 additions and 0 deletions
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tools/utils/testbenches.excludes
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@@ -13,3 +13,5 @@ top/x300/sim/x300_pcie_int
lib/axi4s_sv/axi4s_remove_bytes_tb
lib/axi4s_sv/axi4s_add_bytes_tb
lib/rfnoc/xport_sv/eth_interface_tb
top/x400/sim/x4xx_qsfp_wrapper
top/x400/ip/eth_100g_bd/lbus_tb
top/x400/.gitignore
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@@ -0,0 +1,7 @@
build
build-*
*.log
*.jou
vivado*.str
ip/*/sim/
dts/x410-version-info.dtsi
top/x400/Makefile
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@@ -0,0 +1,192 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
##-------------------
##USRP X4XX FPGA Help
##-------------------
##Usage:
## make <Targets> <Options>
##
##Output:
## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
# Definitions
# MGT Types from x4xx_mgt_type.vh
MGT_100GbE = 5
MGT_Aurora = 3
MGT_10GbE = 2
MGT_Disabled = 0
# For a 4-lane MGT like 100GBE set QSFPx_0=MGT_100GbE and all others to
# MGT_Disabled. For a 1-lane MGT like 10GbE do not set anything for unused
# lanes. This ensures something is defined only for the lanes that are used, so
# that the TX/RX signals are connected. The presence of a define causes TX/RX
# to be declared, whereas declaring TX/RX on an unused lane will cause an error
# in bitgen for unconstrained pins after it is optimized out.
QSFP0_10GBE = QSFP0_0=$(MGT_10GbE)
QSFP0_4X10GBE = QSFP0_0=$(MGT_10GbE) QSFP0_1=$(MGT_10GbE) QSFP0_2=$(MGT_10GbE) QSFP0_3=$(MGT_10GbE)
QSFP0_100GBE = QSFP0_0=$(MGT_100GbE) QSFP0_1=$(MGT_Disabled) QSFP0_2=$(MGT_Disabled) QSFP0_3=$(MGT_Disabled)
QSFP1_10GBE = QSFP1_0=$(MGT_10GbE)
QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10GbE) QSFP1_3=$(MGT_10GbE)
QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled)
# Target specific variables
X410_IP: DEFS = $(QSFP0_10GBE) RFBW_100M=1
X410_X1_100: DEFS = $(QSFP0_10GBE) RFBW_100M=1
X410_XG_100: DEFS = $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1
X410_X4_100: DEFS = $(QSFP0_4X10GBE) RFBW_100M=1
X410_X4C_100: DEFS = $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 USE_100GBE=1
X410_CG_100: DEFS = $(QSFP0_100GBE) RFBW_100M=1 USE_100GBE=1
X410_CG_200: DEFS = $(QSFP0_100GBE) RFBW_200M=1 USE_100GBE=1
X410_XG_200: DEFS = $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1
X410_X4_200: DEFS = $(QSFP0_4X10GBE) RFBW_200M=1
X410_X4C_200: DEFS = $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 USE_100GBE=1
X410_C1_400: DEFS = $(QSFP0_100GBE) RFBW_400M=1 USE_100GBE=1
X410_CG_400: DEFS = $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 USE_100GBE=1
DEFS += $(OPTIONS)
# Defaults specific to the various targets:
X410_100_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
X410_200_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
X410_400_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
# Option to stop after RTL elaboration. Use this flag as a synthesis check.
ifndef TARGET
ifdef CHECK
TARGET = rtl
else ifdef SYNTH
TARGET = synth
else
TARGET = bin
endif
endif
TOP ?= x4xx
# vivado_build($1=Device, $2=Definitions)
vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
# vivado_build($1=Device, $2=Option)
ifeq ($(TARGET),bin)
post_build = @\
mkdir -p build; \
echo "Exporting bitstream file..."; \
cp build-$(1)_$(2)/x4xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
echo "Exporting build report..."; \
cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
echo "Build DONE ... $(1)_$(2)";
else
post_build = @echo "Skipping bitfile export."
endif
# vivado_ip($1=Device, $2=Definitions)
vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
##
##Supported Targets
##-----------------
all: X410_X4_200 ##(Default target)
##X410_X1_100: 10GbE on QSFP0 (Lane 0), 100MHz Bandwidth
X410_X1_100: build/usrp_x410_fpga_X1_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,X1_100)
##X410_XG_100: 10GbE on QSFP0 (Lane 0) and QSFP1 (Lane 0), 100MHz Bandwidth
X410_XG_100: build/usrp_x410_fpga_XG_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,XG_100)
##X410_X4_100: 4x10GbE on QSFP0, 100MHz Bandwidth
X410_X4_100: build/usrp_x410_fpga_X4_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,X4_100)
##X410_X4C_100: (EXPERIMENTAL) 4x10GbE on QSFP0, 100GbE on QSFP1, 100MHz Bandwidth
X410_X4C_100: build/usrp_x410_fpga_X4C_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,X4C_100)
##X410_CG_100: (EXPERIMENTAL) 100GbE on QSFP0, 100MHz Bandwidth
X410_CG_100: build/usrp_x410_fpga_CG_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,CG_100)
##X410_XG_200: 10GbE on QSFP0 (Lane 0) and QSFP1 (Lane 0), 200MHz Bandwidth
X410_XG_200: build/usrp_x410_fpga_XG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,XG_200)
##X410_X4_200: 4x10GbE on QSFP0, 200MHz Bandwidth
X410_X4_200: build/usrp_x410_fpga_X4_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4_200)
##X410_X4C_200: (EXPERIMENTAL) 4x10GbE on QSFP0, 100GbE on QSFP1, 200MHz Bandwidth
X410_X4C_200: build/usrp_x410_fpga_X4C_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,X4C_200)
##X410_CG_200: (EXPERIMENTAL) 100GbE on QSFP0, 200MHz Bandwidth
X410_CG_200: build/usrp_x410_fpga_CG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,CG_200)
##X410_C1_400: (EXPERIMENTAL) 100GbE on QSFP0, 400MHz Bandwidth
X410_C1_400: build/usrp_x410_fpga_C1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,C1_400)
##X410_CG_400: (EXPERIMENTAL) 100GbE on QSFP0 and QSFP1, 400MHz Bandwidth
X410_CG_400: build/usrp_x410_fpga_CG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,CG_400)
X410_IP: ##Build IPs only
$(call vivado_ip,X410,$(DEFS) X410=1)
build/%.dts: dts/*.dts dts/*.dtsi
-mkdir -p build
tools/parse_versions_for_dts.py \
--input regmap/versioning_regs_regmap_utils.vh \
--output dts/x410-version-info.dtsi \
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
$$(python3 tools/get_dts_input.py --target $@)
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf build-X4*
@rm -rf build
cleanall: ##Clean up all target and ip build outputs.
@echo "Cleaning targets and IP..."
@rm -rf build-ip
@rm -rf build-X4*
@rm -rf build
help: ##Show this help message.
@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
##
##Supported Options
##-----------------
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
.PHONY: all clean cleanall help
top/x400/Makefile.x4xx.inc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
##################################################
# Project Setup
##################################################
# TOP_MODULE = <Input arg>
# NAME = <Input arg>
# PART_ID = <Input arg>
# ARCH = <Input arg>
##################################################
# Include other makefiles
##################################################
BASE_DIR = $(abspath ..)
IP_DIR = $(abspath ./ip)
include $(BASE_DIR)/../tools/make/viv_design_builder.mak
# Include IP directory
include $(IP_DIR)/Makefile.inc
# Include any LIB dependencies
include coregen_dsp/Makefile.srcs
include $(LIB_DIR)/control/Makefile.srcs
include $(LIB_DIR)/fifo/Makefile.srcs
include $(LIB_DIR)/xge/Makefile.srcs
include $(LIB_DIR)/xge_interface/Makefile.srcs
include $(LIB_DIR)/axi/Makefile.srcs
include $(LIB_DIR)/packet_proc/Makefile.srcs
include $(LIB_DIR)/dsp/Makefile.srcs
include $(LIB_DIR)/ip/Makefile.inc
include $(LIB_DIR)/rfnoc/Makefile.srcs
include $(LIB_DIR)/wb_spi/Makefile.srcs
include $(LIB_DIR)/axi4_sv/Makefile.srcs
include $(LIB_DIR)/axi4s_sv/Makefile.srcs
include $(LIB_DIR)/axi4lite_sv/Makefile.srcs
include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
# DUC, Replay, and of course the radio. Any other block needs to use the
# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_null_src_sink/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
# If out-of-tree modules want to be compiled into this image, then they need to
# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
# source files.
include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
##################################################
# Sources
##################################################
TOP_SRCS =
ifdef X410
TOP_SRCS += \
x4xx.v \
x4xx_qsfp_wrapper_temp.sv \
x4xx_qsfp_wrapper.sv \
x4xx_mgt_io_core.sv \
x4xx_core.v \
x4xx_core_common.v \
x4xx_global_regs.v \
x4xx_versioning_regs.v \
x4xx_dio.v \
rf/100m/rf_core_100m.v \
rf/200m/rf_core_200m.v \
rf/200m/rf_down_4to2.v \
rf/200m/rf_up_2to4.v \
rf/400m/rf_core_400m.v \
rf/common/rf_reset_controller.vhd \
ctrlport_spi_master.v \
cpld_interface.v \
cpld_interface_regs.v \
qsfp_led_controller.v \
rfdc_timing_control.v \
x4xx_pps_sync.v \
../../lib/timing/pps_generator.v \
dboards/ctrlport_byte_serializer.v \
dboards/db_gpio_interface.v \
dboards/db_gpio_reordering.v \
ipass_present_controller.v \
$(IMAGE_CORE)
endif
MB_XDC = \
constraints/pins/common.xdc \
constraints/pins/rfdc_2x2.xdc \
constraints/timing/shared_constants.sdc \
constraints/timing/common.xdc
# Definitions
# MGT Types from x4xx_mgt_type.vh
MGT_100GbE = 5
MGT_Aurora = 3
MGT_10GbE = 2
MGT_Disabled = 0
# Check if any of the ports are set to 10Gbe
ifneq (,$(findstring =$(MGT_10GbE),$(EXTRA_DEFS)))
MB_XDC += constraints/timing/qsfp_10gbe.xdc
endif
# Add pin constraints for QSFP pins
ifneq (,$(findstring QSFP0_0,"$(EXTRA_DEFS)"))
MB_XDC += constraints/pins/qsfp0_0.xdc
endif
ifneq (,$(findstring QSFP0_1,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp0_1.xdc
endif
ifneq (,$(findstring QSFP0_2,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp0_2.xdc
endif
ifneq (,$(findstring QSFP0_3,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp0_3.xdc
endif
ifneq (,$(findstring QSFP1_0,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_0.xdc
endif
ifneq (,$(findstring QSFP1_1,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_1.xdc
endif
ifneq (,$(findstring QSFP1_2,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_2.xdc
endif
ifneq (,$(findstring QSFP1_3,$(EXTRA_DEFS)))
MB_XDC += constraints/pins/qsfp1_3.xdc
endif
ifndef NO_DRAM_FIFOS
DRAM_SRCS =
else
DRAM_SRCS =
endif
ifdef X410
DESIGN_SRCS = $(abspath $(MB_XDC))
endif
# The XDC files must be read in a specific order, motherboard first and then daughterboard.
# Outside of that, all the other sources can be read in any order desired.
DESIGN_SRCS += $(abspath \
$(AXI4_SV_SRCS) $(AXI4S_SV_SRCS) $(AXI4LITE_SV_SRCS) $(TOP_SRCS) \
$(AXI_SRCS) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) $(WISHBONE_SRCS) \
$(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \
$(XGE_PCS_PMA_SRCS) \
$(PACKET_PROC_SRCS) $(VITA_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
$(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) $(LIBCOREGEN_SRCS) \
$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) \
$(RFNOC_BLOCK_RADIO_SRCS) $(RFNOC_BLOCK_NULL_SRC_SINK_SRCS) \
$(DB_COMMON_SRCS) $(WHITE_RABBIT_SRCS) $(RFNOC_FRAMEWORK_SRCS) \
$(WB_SPI_SRCS) $(RFNOC_XPORT_SV_SRCS) \
)
# Pass the edge table and image core header files required by RFNoC
# to Vivado as Verilog definitions.
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)"
##################################################
# Dependency Targets
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs $$(DESIGN_SRCS) ip
@echo "Printing MB_XDC:: $(MB_XDC)"
@echo "Printing EXTRA_DEFS:: $(EXTRA_DEFS)"
$(call BUILD_VIVADO_DESIGN,$(abspath ./build_x4xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
synth: .prereqs $$(DESIGN_SRCS) ip
$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
rtl: .prereqs $$(DESIGN_SRCS) ip
$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
viv_ip: .prereqs $$(DESIGN_SRCS) ip
@echo "IP Build DONE ..."
.PHONY: bin
top/x400/build_x4xx.tcl
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
# STEP#1: Create project, add sources, refresh IP
vivado_utils::initialize_project
# STEP#2: Run synthesis
vivado_utils::synthesize_design
vivado_utils::generate_post_synth_reports
# STEP#3: Run implementation strategy
set strategy [vivado_strategies::get_impl_preset "Performance_ExplorePostRoutePhysOpt"]
# Turn up uncertainty on 100Gb clocks(-quiet so if it fails because the clocks don't exist, it won't error)
set_clock_uncertainty 0.5 -quiet -setup [get_clocks txoutclk_out*]
# Vivado has been underestimating routing delays.
dict set strategy "place_design.directive" "ExtraNetDelay_high"
# Turn down uncertainty on 100Gb clocks
dict set strategy "route_design.pre_hook" {set_clock_uncertainty 0.0 -quiet -setup [get_clocks txoutclk_out*]}
vivado_strategies::implement_design $strategy
# STEP#4: Generate reports
vivado_utils::generate_post_route_reports
# STEP#5: Generate a bitstream, netlist and debug probes
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [get_designs *]
set byte_swap_bin 1
vivado_utils::write_implementation_outputs $byte_swap_bin
# Cleanup
vivado_utils::close_batch_project
top/x400/constraints/pins/common.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Common pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs reference clocks
###############################################################################
set_property PACKAGE_PIN U33 [get_ports {MGT_REFCLK_LMK0_P}]
set_property PACKAGE_PIN U34 [get_ports {MGT_REFCLK_LMK0_N}]
set_property PACKAGE_PIN T31 [get_ports {MGT_REFCLK_LMK1_P}]
set_property PACKAGE_PIN T32 [get_ports {MGT_REFCLK_LMK1_N}]
set_property PACKAGE_PIN W33 [get_ports {MGT_REFCLK_LMK2_P}]
set_property PACKAGE_PIN W34 [get_ports {MGT_REFCLK_LMK2_N}]
set_property PACKAGE_PIN V31 [get_ports {MGT_REFCLK_LMK3_P}]
set_property PACKAGE_PIN V32 [get_ports {MGT_REFCLK_LMK3_N}]
###############################################################################
# Common pin constraints for the QSFP28 ports
###############################################################################
set_property PACKAGE_PIN AJ15 [get_ports {QSFP0_MODPRS_n}]
set_property PACKAGE_PIN AH16 [get_ports {QSFP0_RESET_n}]
set_property PACKAGE_PIN AH15 [get_ports {QSFP0_LPMODE_n}]
set_property PACKAGE_PIN AL11 [get_ports {QSFP1_MODPRS_n}]
set_property PACKAGE_PIN AR8 [get_ports {QSFP1_RESET_n}]
set_property PACKAGE_PIN AT9 [get_ports {QSFP1_LPMODE_n}]
set_property IOSTANDARD LVCMOS12 [get_ports {QSFP*_MODPRS_n QSFP*_RESET_n QSFP*_LPMODE_n}]
set_property SLEW SLOW [get_ports {QSFP*_RESET_n QSFP*_LPMODE_n}]
###############################################################################
# eCPRI future clocks
###############################################################################
# Input
set_property PACKAGE_PIN AK17 [get_ports {FPGA_AUX_REF}]
set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_AUX_REF}]
# Output
set_property PACKAGE_PIN AG17 [get_ports {FABRIC_CLK_OUT_P}]
set_property PACKAGE_PIN AH17 [get_ports {FABRIC_CLK_OUT_N}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {FABRIC_CLK_OUT_*}]
# GTY_RCV_CLK_P is defined in qsfp_port1
###############################################################################
# Pin constraints for the other PL pins (1.8 V)
###############################################################################
set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[*]}]
set_property IOB TRUE [get_ports {DB1_GPIO[*]}]
set_property PACKAGE_PIN A7 [get_ports {DB1_SYNTH_SYNC}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_SYNTH_SYNC}]
set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[*]}]
set_property IOB TRUE [get_ports {DB0_GPIO[*]}]
set_property PACKAGE_PIN AP5 [get_ports {DB0_SYNTH_SYNC}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_SYNTH_SYNC}]
set_property PACKAGE_PIN A9 [get_ports {LMK_SYNC}]
set_property IOB TRUE [get_ports {LMK_SYNC}]
set_property PACKAGE_PIN A10 [get_ports {TRIG_IO}]
set_property PACKAGE_PIN A6 [get_ports {PPS_IN}]
set_property PACKAGE_PIN AR7 [get_ports {PL_CPLD_SCLK}]
set_property PACKAGE_PIN AR6 [get_ports {PL_CPLD_MOSI}]
set_property PACKAGE_PIN AP6 [get_ports {PL_CPLD_MISO}]
set_property IOSTANDARD LVCMOS18 [get_ports {LMK_SYNC TRIG_IO PPS_IN PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_MISO}]
set_property DRIVE 16 [get_ports {PL_CPLD_SCLK}]
###############################################################################
# Pin constraints for the other PL pins (1.2 V)
###############################################################################
set_property PACKAGE_PIN AL16 [get_ports {PLL_REFCLK_FPGA_P}]
set_property PACKAGE_PIN AL15 [get_ports {PLL_REFCLK_FPGA_N}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {PLL_REFCLK_FPGA_*}]
set_property PACKAGE_PIN G17 [get_ports {BASE_REFCLK_FPGA_P}]
set_property PACKAGE_PIN F17 [get_ports {BASE_REFCLK_FPGA_N}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {BASE_REFCLK_FPGA_*}]
set_property PACKAGE_PIN AF17 [get_ports {SYSREF_FABRIC_P}]
set_property PACKAGE_PIN AF16 [get_ports {SYSREF_FABRIC_N}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {SYSREF_FABRIC_*}]
set_property PACKAGE_PIN J15 [get_ports {DIOA_FPGA[0]}]
set_property PACKAGE_PIN H15 [get_ports {DIOA_FPGA[1]}]
set_property PACKAGE_PIN L17 [get_ports {DIOA_FPGA[2]}]
set_property PACKAGE_PIN K17 [get_ports {DIOA_FPGA[3]}]
set_property PACKAGE_PIN K16 [get_ports {DIOA_FPGA[4]}]
set_property PACKAGE_PIN J16 [get_ports {DIOA_FPGA[5]}]
set_property PACKAGE_PIN K19 [get_ports {DIOA_FPGA[6]}]
set_property PACKAGE_PIN K18 [get_ports {DIOA_FPGA[7]}]
set_property PACKAGE_PIN H17 [get_ports {DIOA_FPGA[8]}]
set_property PACKAGE_PIN H16 [get_ports {DIOA_FPGA[9]}]
set_property PACKAGE_PIN J19 [get_ports {DIOA_FPGA[10]}]
set_property PACKAGE_PIN J18 [get_ports {DIOA_FPGA[11]}]
set_property PACKAGE_PIN M18 [get_ports {DIOB_FPGA[0]}]
set_property PACKAGE_PIN H18 [get_ports {DIOB_FPGA[1]}]
set_property PACKAGE_PIN G18 [get_ports {DIOB_FPGA[2]}]
set_property PACKAGE_PIN G15 [get_ports {DIOB_FPGA[3]}]
set_property PACKAGE_PIN F15 [get_ports {DIOB_FPGA[4]}]
set_property PACKAGE_PIN G19 [get_ports {DIOB_FPGA[5]}]
set_property PACKAGE_PIN F19 [get_ports {DIOB_FPGA[6]}]
set_property PACKAGE_PIN F16 [get_ports {DIOB_FPGA[7]}]
set_property PACKAGE_PIN E16 [get_ports {DIOB_FPGA[8]}]
set_property PACKAGE_PIN E18 [get_ports {DIOB_FPGA[9]}]
set_property PACKAGE_PIN E17 [get_ports {DIOB_FPGA[10]}]
set_property PACKAGE_PIN E19 [get_ports {DIOB_FPGA[11]}]
set_property IOSTANDARD LVCMOS12 [get_ports {DIO*_FPGA[*]}]
set_property PULLDOWN true [get_ports {DIO*_FPGA[*]}]
set_property PACKAGE_PIN AW13 [get_ports {PPS_LED}]
set_property IOSTANDARD LVCMOS12 [get_ports {PPS_LED}]
set_property PACKAGE_PIN B23 [get_ports {PL_CPLD_JTAGEN}]
set_property PACKAGE_PIN N21 [get_ports {PL_CPLD_CS0_n}]
set_property PACKAGE_PIN J24 [get_ports {PL_CPLD_CS1_n}]
set_property PACKAGE_PIN AN12 [get_ports {CPLD_JTAG_OE_n}]
set_property IOSTANDARD LVCMOS12 [get_ports {PL_CPLD_JTAGEN PL_CPLD_CS*_n CPLD_JTAG_OE_n}]
###############################################################################
# Unused pins
###############################################################################
# set_property PACKAGE_PIN D19 [get_ports {PL_CPLD_IRQ}]
# set_property PACKAGE_PIN AF15 [get_ports {FPGA_TEST}]
# set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_TEST PL_CPLD_IRQ}]
# set_property PACKAGE_PIN AK16 [get_ports {TDC_SPARE_0}]
# set_property PACKAGE_PIN AJ16 [get_ports {TDC_SPARE_1}]
# set_property IOSTANDARD LVCMOS12 [get_ports {TDC_SPARE_*}]
top/x400/constraints/pins/dram.xdc
+344
View File
@@ -0,0 +1,344 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# DRAM pin constraints for X410.
#
###############################################################################
# Pin constraints for DRAM controller 0
###############################################################################
set_property PACKAGE_PIN AH20 [get_ports DRAM0_ACT_n]
set_property PACKAGE_PIN AN22 [get_ports {DRAM0_ADDR[0]}]
set_property PACKAGE_PIN AJ18 [get_ports {DRAM0_ADDR[10]}]
set_property PACKAGE_PIN AN21 [get_ports {DRAM0_ADDR[11]}]
set_property PACKAGE_PIN AF20 [get_ports {DRAM0_ADDR[12]}]
set_property PACKAGE_PIN AJ20 [get_ports {DRAM0_ADDR[13]}]
set_property PACKAGE_PIN AG18 [get_ports {DRAM0_ADDR[14]}]
set_property PACKAGE_PIN AK18 [get_ports {DRAM0_ADDR[15]}]
set_property PACKAGE_PIN AN18 [get_ports {DRAM0_ADDR[16]}]
set_property PACKAGE_PIN AL20 [get_ports {DRAM0_ADDR[1]}]
set_property PACKAGE_PIN AK22 [get_ports {DRAM0_ADDR[2]}]
set_property PACKAGE_PIN AM19 [get_ports {DRAM0_ADDR[3]}]
set_property PACKAGE_PIN AG20 [get_ports {DRAM0_ADDR[4]}]
set_property PACKAGE_PIN AT20 [get_ports {DRAM0_ADDR[5]}]
set_property PACKAGE_PIN AL19 [get_ports {DRAM0_ADDR[6]}]
set_property PACKAGE_PIN AK21 [get_ports {DRAM0_ADDR[7]}]
set_property PACKAGE_PIN AL21 [get_ports {DRAM0_ADDR[8]}]
set_property PACKAGE_PIN AP21 [get_ports {DRAM0_ADDR[9]}]
set_property PACKAGE_PIN AK19 [get_ports {DRAM0_BA[0]}]
set_property PACKAGE_PIN AM18 [get_ports {DRAM0_BA[1]}]
set_property PACKAGE_PIN AJ19 [get_ports {DRAM0_BG[0]}]
set_property PACKAGE_PIN AL22 [get_ports {DRAM0_CLK_P[0]}]
set_property PACKAGE_PIN AM22 [get_ports {DRAM0_CLK_N[0]}]
set_property PACKAGE_PIN AF19 [get_ports {DRAM0_CKE[0]}]
set_property PACKAGE_PIN AH18 [get_ports {DRAM0_CS_n[0]}]
set_property PACKAGE_PIN AT17 [get_ports {DRAM0_ODT[0]}]
set_property PACKAGE_PIN AP15 [get_ports DRAM0_RESET_n]
set_property PACKAGE_PIN AM20 [get_ports DRAM0_REFCLK_P]
set_property PACKAGE_PIN AN20 [get_ports DRAM0_REFCLK_N]
set_property PACKAGE_PIN AR17 [get_ports {DRAM0_DM_n[0]}]
set_property PACKAGE_PIN AR22 [get_ports {DRAM0_DQS_p[0]}]
set_property PACKAGE_PIN AT22 [get_ports {DRAM0_DQS_n[0]}]
set_property PACKAGE_PIN AR18 [get_ports {DRAM0_DQ[0]}]
set_property PACKAGE_PIN AR19 [get_ports {DRAM0_DQ[1]}]
set_property PACKAGE_PIN AT19 [get_ports {DRAM0_DQ[2]}]
set_property PACKAGE_PIN AT21 [get_ports {DRAM0_DQ[3]}]
set_property PACKAGE_PIN AP18 [get_ports {DRAM0_DQ[4]}]
set_property PACKAGE_PIN AP19 [get_ports {DRAM0_DQ[5]}]
set_property PACKAGE_PIN AP20 [get_ports {DRAM0_DQ[6]}]
set_property PACKAGE_PIN AR21 [get_ports {DRAM0_DQ[7]}]
set_property PACKAGE_PIN AM12 [get_ports {DRAM0_DM_n[1]}]
set_property PACKAGE_PIN AM13 [get_ports {DRAM0_DQS_p[1]}]
set_property PACKAGE_PIN AN13 [get_ports {DRAM0_DQS_n[1]}]
set_property PACKAGE_PIN AM10 [get_ports {DRAM0_DQ[8]}]
set_property PACKAGE_PIN AP10 [get_ports {DRAM0_DQ[9]}]
set_property PACKAGE_PIN AN10 [get_ports {DRAM0_DQ[10]}]
set_property PACKAGE_PIN AR11 [get_ports {DRAM0_DQ[11]}]
set_property PACKAGE_PIN AL10 [get_ports {DRAM0_DQ[12]}]
set_property PACKAGE_PIN AP11 [get_ports {DRAM0_DQ[13]}]
set_property PACKAGE_PIN AN11 [get_ports {DRAM0_DQ[14]}]
set_property PACKAGE_PIN AR12 [get_ports {DRAM0_DQ[15]}]
set_property PACKAGE_PIN AW19 [get_ports {DRAM0_DM_n[2]}]
set_property PACKAGE_PIN AV21 [get_ports {DRAM0_DQS_p[2]}]
set_property PACKAGE_PIN AW21 [get_ports {DRAM0_DQS_n[2]}]
set_property PACKAGE_PIN AV17 [get_ports {DRAM0_DQ[16]}]
set_property PACKAGE_PIN AV18 [get_ports {DRAM0_DQ[17]}]
set_property PACKAGE_PIN AU19 [get_ports {DRAM0_DQ[18]}]
set_property PACKAGE_PIN AU18 [get_ports {DRAM0_DQ[19]}]
set_property PACKAGE_PIN AU17 [get_ports {DRAM0_DQ[20]}]
set_property PACKAGE_PIN AW20 [get_ports {DRAM0_DQ[21]}]
set_property PACKAGE_PIN AU20 [get_ports {DRAM0_DQ[22]}]
set_property PACKAGE_PIN AV20 [get_ports {DRAM0_DQ[23]}]
set_property PACKAGE_PIN AV10 [get_ports {DRAM0_DM_n[3]}]
set_property PACKAGE_PIN AT12 [get_ports {DRAM0_DQS_p[3]}]
set_property PACKAGE_PIN AT11 [get_ports {DRAM0_DQS_n[3]}]
set_property PACKAGE_PIN AW9 [get_ports {DRAM0_DQ[24]}]
set_property PACKAGE_PIN AU12 [get_ports {DRAM0_DQ[25]}]
set_property PACKAGE_PIN AU10 [get_ports {DRAM0_DQ[26]}]
set_property PACKAGE_PIN AV12 [get_ports {DRAM0_DQ[27]}]
set_property PACKAGE_PIN AW8 [get_ports {DRAM0_DQ[28]}]
set_property PACKAGE_PIN AT10 [get_ports {DRAM0_DQ[29]}]
set_property PACKAGE_PIN AV11 [get_ports {DRAM0_DQ[30]}]
set_property PACKAGE_PIN AW11 [get_ports {DRAM0_DQ[31]}]
set_property PACKAGE_PIN AW14 [get_ports {DRAM0_DM_n[4]}]
set_property PACKAGE_PIN AV16 [get_ports {DRAM0_DQS_p[4]}]
set_property PACKAGE_PIN AW16 [get_ports {DRAM0_DQS_n[4]}]
set_property PACKAGE_PIN AU13 [get_ports {DRAM0_DQ[32]}]
set_property PACKAGE_PIN AV15 [get_ports {DRAM0_DQ[33]}]
set_property PACKAGE_PIN AV13 [get_ports {DRAM0_DQ[34]}]
set_property PACKAGE_PIN AU14 [get_ports {DRAM0_DQ[35]}]
set_property PACKAGE_PIN AU15 [get_ports {DRAM0_DQ[36]}]
set_property PACKAGE_PIN AW15 [get_ports {DRAM0_DQ[37]}]
set_property PACKAGE_PIN AT15 [get_ports {DRAM0_DQ[38]}]
set_property PACKAGE_PIN AT16 [get_ports {DRAM0_DQ[39]}]
set_property PACKAGE_PIN AP8 [get_ports {DRAM0_DM_n[5]}]
set_property PACKAGE_PIN AN8 [get_ports {DRAM0_DQS_p[5]}]
set_property PACKAGE_PIN AN7 [get_ports {DRAM0_DQS_n[5]}]
set_property PACKAGE_PIN AM9 [get_ports {DRAM0_DQ[40]}]
set_property PACKAGE_PIN AR9 [get_ports {DRAM0_DQ[41]}]
set_property PACKAGE_PIN AL7 [get_ports {DRAM0_DQ[42]}]
set_property PACKAGE_PIN AM8 [get_ports {DRAM0_DQ[43]}]
set_property PACKAGE_PIN AL9 [get_ports {DRAM0_DQ[44]}]
set_property PACKAGE_PIN AP9 [get_ports {DRAM0_DQ[45]}]
set_property PACKAGE_PIN AL8 [get_ports {DRAM0_DQ[46]}]
set_property PACKAGE_PIN AM7 [get_ports {DRAM0_DQ[47]}]
set_property PACKAGE_PIN AK13 [get_ports {DRAM0_DM_n[6]}]
set_property PACKAGE_PIN AJ14 [get_ports {DRAM0_DQS_p[6]}]
set_property PACKAGE_PIN AK14 [get_ports {DRAM0_DQS_n[6]}]
set_property PACKAGE_PIN AH12 [get_ports {DRAM0_DQ[48]}]
set_property PACKAGE_PIN AJ13 [get_ports {DRAM0_DQ[49]}]
set_property PACKAGE_PIN AJ12 [get_ports {DRAM0_DQ[50]}]
set_property PACKAGE_PIN AK12 [get_ports {DRAM0_DQ[51]}]
set_property PACKAGE_PIN AG12 [get_ports {DRAM0_DQ[52]}]
set_property PACKAGE_PIN AL14 [get_ports {DRAM0_DQ[53]}]
set_property PACKAGE_PIN AH13 [get_ports {DRAM0_DQ[54]}]
set_property PACKAGE_PIN AM14 [get_ports {DRAM0_DQ[55]}]
set_property PACKAGE_PIN AP13 [get_ports {DRAM0_DM_n[7]}]
set_property PACKAGE_PIN AN17 [get_ports {DRAM0_DQS_p[7]}]
set_property PACKAGE_PIN AN16 [get_ports {DRAM0_DQS_n[7]}]
set_property PACKAGE_PIN AM15 [get_ports {DRAM0_DQ[56]}]
set_property PACKAGE_PIN AP14 [get_ports {DRAM0_DQ[57]}]
set_property PACKAGE_PIN AM17 [get_ports {DRAM0_DQ[58]}]
set_property PACKAGE_PIN AP16 [get_ports {DRAM0_DQ[59]}]
set_property PACKAGE_PIN AL17 [get_ports {DRAM0_DQ[60]}]
set_property PACKAGE_PIN AR14 [get_ports {DRAM0_DQ[61]}]
set_property PACKAGE_PIN AN15 [get_ports {DRAM0_DQ[62]}]
set_property PACKAGE_PIN AR16 [get_ports {DRAM0_DQ[63]}]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports {DRAM0_DQS_*[*]}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {DRAM0_REFCLK_*}]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {DRAM0_CLK_*[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports DRAM0_RESET_n]
set_property IOSTANDARD POD12_DCI [get_ports {DRAM0_DM_n[*] \
DRAM0_DQ[*]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {DRAM0_ACT_n \
DRAM0_ADDR[*] \
DRAM0_BA[*] \
DRAM0_BG[0] \
DRAM0_CKE[0] \
DRAM0_CS_n[0] \
DRAM0_ODT[0]}]
set_property DRIVE 8 [get_ports DRAM0_RESET_n]
set_property SLEW FAST [get_ports {DRAM0_ACT_n \
DRAM0_ADDR[*] \
DRAM0_BA[*] \
DRAM0_BG[0] \
DRAM0_CLK_*[0] \
DRAM0_CKE[0] \
DRAM0_CS_n[0] \
DRAM0_DM_n[*] \
DRAM0_DQ[*] \
DRAM0_DQS_*[*] \
DRAM0_ODT[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {DRAM0_ACT_n \
DRAM0_ADDR[*] \
DRAM0_BA[*] \
DRAM0_BG[0] \
DRAM0_CLK_*[0] \
DRAM0_CKE[0] \
DRAM0_CS_n[0] \
DRAM0_DM_n[*] \
DRAM0_DQ[*] \
DRAM0_DQS_*[*] \
DRAM0_ODT[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {DRAM0_DM_n[*] \
DRAM0_DQ[*] \
DRAM0_DQS_*[*]}]
###############################################################################
# Pin constraints for DRAM controller 0
###############################################################################
set_property PACKAGE_PIN E14 [get_ports DRAM1_ACT_n]
set_property PACKAGE_PIN B12 [get_ports {DRAM1_ADDR[0]}]
set_property PACKAGE_PIN G14 [get_ports {DRAM1_ADDR[1]}]
set_property PACKAGE_PIN D13 [get_ports {DRAM1_ADDR[2]}]
set_property PACKAGE_PIN F12 [get_ports {DRAM1_ADDR[3]}]
set_property PACKAGE_PIN C13 [get_ports {DRAM1_ADDR[4]}]
set_property PACKAGE_PIN D14 [get_ports {DRAM1_ADDR[5]}]
set_property PACKAGE_PIN C12 [get_ports {DRAM1_ADDR[6]}]
set_property PACKAGE_PIN C15 [get_ports {DRAM1_ADDR[7]}]
set_property PACKAGE_PIN H12 [get_ports {DRAM1_ADDR[8]}]
set_property PACKAGE_PIN H13 [get_ports {DRAM1_ADDR[9]}]
set_property PACKAGE_PIN A14 [get_ports {DRAM1_ADDR[10]}]
set_property PACKAGE_PIN K12 [get_ports {DRAM1_ADDR[11]}]
set_property PACKAGE_PIN D11 [get_ports {DRAM1_ADDR[12]}]
set_property PACKAGE_PIN J7 [get_ports {DRAM1_ADDR[13]}]
set_property PACKAGE_PIN A15 [get_ports {DRAM1_ADDR[14]}]
set_property PACKAGE_PIN B14 [get_ports {DRAM1_ADDR[15]}]
set_property PACKAGE_PIN E11 [get_ports {DRAM1_ADDR[16]}]
set_property PACKAGE_PIN A12 [get_ports {DRAM1_BA[0]}]
set_property PACKAGE_PIN A11 [get_ports {DRAM1_BA[1]}]
set_property PACKAGE_PIN B13 [get_ports {DRAM1_BG[0]}]
set_property PACKAGE_PIN E13 [get_ports {DRAM1_CLK_P[0]}]
set_property PACKAGE_PIN E12 [get_ports {DRAM1_CLK_N[0]}]
set_property PACKAGE_PIN C11 [get_ports {DRAM1_CKE[0]}]
set_property PACKAGE_PIN F14 [get_ports {DRAM1_CS_n[0]}]
set_property PACKAGE_PIN B15 [get_ports {DRAM1_ODT[0]}]
set_property PACKAGE_PIN G24 [get_ports DRAM1_RESET_n]
set_property PACKAGE_PIN G13 [get_ports DRAM1_REFCLK_P]
set_property PACKAGE_PIN G12 [get_ports DRAM1_REFCLK_N]
set_property PACKAGE_PIN J8 [get_ports {DRAM1_DM_n[0]}]
set_property PACKAGE_PIN H8 [get_ports {DRAM1_DQS_p[0]}]
set_property PACKAGE_PIN G8 [get_ports {DRAM1_DQS_n[0]}]
set_property PACKAGE_PIN G9 [get_ports {DRAM1_DQ[0]}]
set_property PACKAGE_PIN J9 [get_ports {DRAM1_DQ[1]}]
set_property PACKAGE_PIN H7 [get_ports {DRAM1_DQ[2]}]
set_property PACKAGE_PIN H6 [get_ports {DRAM1_DQ[3]}]
set_property PACKAGE_PIN G7 [get_ports {DRAM1_DQ[4]}]
set_property PACKAGE_PIN G6 [get_ports {DRAM1_DQ[5]}]
set_property PACKAGE_PIN F9 [get_ports {DRAM1_DQ[6]}]
set_property PACKAGE_PIN K9 [get_ports {DRAM1_DQ[7]}]
set_property PACKAGE_PIN K13 [get_ports {DRAM1_DM_n[1]}]
set_property PACKAGE_PIN J14 [get_ports {DRAM1_DQS_p[1]}]
set_property PACKAGE_PIN J13 [get_ports {DRAM1_DQS_n[1]}]
set_property PACKAGE_PIN F10 [get_ports {DRAM1_DQ[8]}]
set_property PACKAGE_PIN K10 [get_ports {DRAM1_DQ[9]}]
set_property PACKAGE_PIN F11 [get_ports {DRAM1_DQ[10]}]
set_property PACKAGE_PIN H10 [get_ports {DRAM1_DQ[11]}]
set_property PACKAGE_PIN H11 [get_ports {DRAM1_DQ[12]}]
set_property PACKAGE_PIN J10 [get_ports {DRAM1_DQ[13]}]
set_property PACKAGE_PIN J11 [get_ports {DRAM1_DQ[14]}]
set_property PACKAGE_PIN K11 [get_ports {DRAM1_DQ[15]}]
set_property PACKAGE_PIN D18 [get_ports {DRAM1_DM_n[2]}]
set_property PACKAGE_PIN B18 [get_ports {DRAM1_DQS_p[2]}]
set_property PACKAGE_PIN B17 [get_ports {DRAM1_DQS_n[2]}]
set_property PACKAGE_PIN A17 [get_ports {DRAM1_DQ[16]}]
set_property PACKAGE_PIN D15 [get_ports {DRAM1_DQ[17]}]
set_property PACKAGE_PIN A16 [get_ports {DRAM1_DQ[18]}]
set_property PACKAGE_PIN D16 [get_ports {DRAM1_DQ[19]}]
set_property PACKAGE_PIN C17 [get_ports {DRAM1_DQ[20]}]
set_property PACKAGE_PIN B19 [get_ports {DRAM1_DQ[21]}]
set_property PACKAGE_PIN A19 [get_ports {DRAM1_DQ[22]}]
set_property PACKAGE_PIN C16 [get_ports {DRAM1_DQ[23]}]
set_property PACKAGE_PIN N14 [get_ports {DRAM1_DM_n[3]}]
set_property PACKAGE_PIN L15 [get_ports {DRAM1_DQS_p[3]}]
set_property PACKAGE_PIN L14 [get_ports {DRAM1_DQS_n[3]}]
set_property PACKAGE_PIN N15 [get_ports {DRAM1_DQ[24]}]
set_property PACKAGE_PIN M12 [get_ports {DRAM1_DQ[25]}]
set_property PACKAGE_PIN M15 [get_ports {DRAM1_DQ[26]}]
set_property PACKAGE_PIN M13 [get_ports {DRAM1_DQ[27]}]
set_property PACKAGE_PIN N17 [get_ports {DRAM1_DQ[28]}]
set_property PACKAGE_PIN L12 [get_ports {DRAM1_DQ[29]}]
set_property PACKAGE_PIN M17 [get_ports {DRAM1_DQ[30]}]
set_property PACKAGE_PIN N13 [get_ports {DRAM1_DQ[31]}]
set_property PACKAGE_PIN C23 [get_ports {DRAM1_DM_n[4]}]
set_property PACKAGE_PIN B22 [get_ports {DRAM1_DQS_p[4]}]
set_property PACKAGE_PIN A22 [get_ports {DRAM1_DQS_n[4]}]
set_property PACKAGE_PIN B24 [get_ports {DRAM1_DQ[32]}]
set_property PACKAGE_PIN C21 [get_ports {DRAM1_DQ[33]}]
set_property PACKAGE_PIN C22 [get_ports {DRAM1_DQ[34]}]
set_property PACKAGE_PIN A21 [get_ports {DRAM1_DQ[35]}]
set_property PACKAGE_PIN A24 [get_ports {DRAM1_DQ[36]}]
set_property PACKAGE_PIN B20 [get_ports {DRAM1_DQ[37]}]
set_property PACKAGE_PIN C20 [get_ports {DRAM1_DQ[38]}]
set_property PACKAGE_PIN A20 [get_ports {DRAM1_DQ[39]}]
set_property PACKAGE_PIN F21 [get_ports {DRAM1_DM_n[5]}]
set_property PACKAGE_PIN D23 [get_ports {DRAM1_DQS_p[5]}]
set_property PACKAGE_PIN D24 [get_ports {DRAM1_DQS_n[5]}]
set_property PACKAGE_PIN E24 [get_ports {DRAM1_DQ[40]}]
set_property PACKAGE_PIN E22 [get_ports {DRAM1_DQ[41]}]
set_property PACKAGE_PIN F24 [get_ports {DRAM1_DQ[42]}]
set_property PACKAGE_PIN E23 [get_ports {DRAM1_DQ[43]}]
set_property PACKAGE_PIN E21 [get_ports {DRAM1_DQ[44]}]
set_property PACKAGE_PIN D21 [get_ports {DRAM1_DQ[45]}]
set_property PACKAGE_PIN F20 [get_ports {DRAM1_DQ[46]}]
set_property PACKAGE_PIN G20 [get_ports {DRAM1_DQ[47]}]
set_property PACKAGE_PIN J23 [get_ports {DRAM1_DM_n[6]}]
set_property PACKAGE_PIN J20 [get_ports {DRAM1_DQS_p[6]}]
set_property PACKAGE_PIN H20 [get_ports {DRAM1_DQS_n[6]}]
set_property PACKAGE_PIN L24 [get_ports {DRAM1_DQ[48]}]
set_property PACKAGE_PIN H23 [get_ports {DRAM1_DQ[49]}]
set_property PACKAGE_PIN J21 [get_ports {DRAM1_DQ[50]}]
set_property PACKAGE_PIN H22 [get_ports {DRAM1_DQ[51]}]
set_property PACKAGE_PIN K24 [get_ports {DRAM1_DQ[52]}]
set_property PACKAGE_PIN G23 [get_ports {DRAM1_DQ[53]}]
set_property PACKAGE_PIN H21 [get_ports {DRAM1_DQ[54]}]
set_property PACKAGE_PIN G22 [get_ports {DRAM1_DQ[55]}]
set_property PACKAGE_PIN N20 [get_ports {DRAM1_DM_n[7]}]
set_property PACKAGE_PIN K21 [get_ports {DRAM1_DQS_p[7]}]
set_property PACKAGE_PIN K22 [get_ports {DRAM1_DQS_n[7]}]
set_property PACKAGE_PIN M19 [get_ports {DRAM1_DQ[56]}]
set_property PACKAGE_PIN L21 [get_ports {DRAM1_DQ[57]}]
set_property PACKAGE_PIN M20 [get_ports {DRAM1_DQ[58]}]
set_property PACKAGE_PIN L23 [get_ports {DRAM1_DQ[59]}]
set_property PACKAGE_PIN N19 [get_ports {DRAM1_DQ[60]}]
set_property PACKAGE_PIN L22 [get_ports {DRAM1_DQ[61]}]
set_property PACKAGE_PIN L20 [get_ports {DRAM1_DQ[62]}]
set_property PACKAGE_PIN L19 [get_ports {DRAM1_DQ[63]}]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports {DRAM1_DQS_*[*]}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {DRAM1_REFCLK_*}]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {DRAM1_CLK_*[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports DRAM1_RESET_n]
set_property IOSTANDARD POD12_DCI [get_ports {DRAM1_DM_n[*] \
DRAM1_DQ[*]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {DRAM1_ACT_n \
DRAM1_ADDR[*] \
DRAM1_BA[*] \
DRAM1_BG[0] \
DRAM1_CKE[0] \
DRAM1_CS_n[0] \
DRAM1_ODT[0]}]
set_property DRIVE 8 [get_ports DRAM1_RESET_n]
set_property SLEW FAST [get_ports {DRAM1_ACT_n \
DRAM1_ADDR[*] \
DRAM1_BA[*] \
DRAM1_BG[0] \
DRAM1_CLK_*[0] \
DRAM1_CKE[0] \
DRAM1_CS_n[0] \
DRAM1_DM_n[*] \
DRAM1_DQ[*] \
DRAM1_DQS_*[*] \
DRAM1_ODT[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {DRAM1_ACT_n \
DRAM1_ADDR[*] \
DRAM1_BA[*] \
DRAM1_BG[0] \
DRAM1_CLK_*[0] \
DRAM1_CKE[0] \
DRAM1_CS_n[0] \
DRAM1_DM_n[*] \
DRAM1_DQ[*] \
DRAM1_DQS_*[*] \
DRAM1_ODT[0]}]
set_property IBUF_LOW_PWR FALSE [get_ports {DRAM1_DM_n[*] \
DRAM1_DQ[*] \
DRAM1_DQS_*[*]}]
top/x400/constraints/pins/ipass.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# zHD+iPASS ports (0 and 1) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (zHD+iPASS ports)
###############################################################################
# Quad 129
set_property PACKAGE_PIN N38 [get_ports {IPASS1_RX_P[0]}]
set_property PACKAGE_PIN N39 [get_ports {IPASS1_RX_N[0]}]
set_property PACKAGE_PIN M36 [get_ports {IPASS1_RX_P[1]}]
set_property PACKAGE_PIN M37 [get_ports {IPASS1_RX_N[1]}]
set_property PACKAGE_PIN L38 [get_ports {IPASS1_RX_P[2]}]
set_property PACKAGE_PIN L39 [get_ports {IPASS1_RX_N[2]}]
set_property PACKAGE_PIN K36 [get_ports {IPASS1_RX_P[3]}]
set_property PACKAGE_PIN K37 [get_ports {IPASS1_RX_N[3]}]
set_property PACKAGE_PIN P35 [get_ports {IPASS1_TX_P[0]}]
set_property PACKAGE_PIN P36 [get_ports {IPASS1_TX_N[0]}]
set_property PACKAGE_PIN N33 [get_ports {IPASS1_TX_P[1]}]
set_property PACKAGE_PIN N34 [get_ports {IPASS1_TX_N[1]}]
set_property PACKAGE_PIN L33 [get_ports {IPASS1_TX_P[2]}]
set_property PACKAGE_PIN L34 [get_ports {IPASS1_TX_N[2]}]
set_property PACKAGE_PIN J33 [get_ports {IPASS1_TX_P[3]}]
set_property PACKAGE_PIN J34 [get_ports {IPASS1_TX_N[3]}]
# Quad 130
set_property PACKAGE_PIN J38 [get_ports {IPASS0_RX_P[0]}]
set_property PACKAGE_PIN J39 [get_ports {IPASS0_RX_N[0]}]
set_property PACKAGE_PIN H36 [get_ports {IPASS0_RX_P[1]}]
set_property PACKAGE_PIN H37 [get_ports {IPASS0_RX_N[1]}]
set_property PACKAGE_PIN G38 [get_ports {IPASS0_RX_P[2]}]
set_property PACKAGE_PIN G39 [get_ports {IPASS0_RX_N[2]}]
set_property PACKAGE_PIN F36 [get_ports {IPASS0_RX_P[3]}]
set_property PACKAGE_PIN F37 [get_ports {IPASS0_RX_N[3]}]
set_property PACKAGE_PIN H31 [get_ports {IPASS0_TX_P[0]}]
set_property PACKAGE_PIN H32 [get_ports {IPASS0_TX_N[0]}]
set_property PACKAGE_PIN G33 [get_ports {IPASS0_TX_P[1]}]
set_property PACKAGE_PIN G34 [get_ports {IPASS0_TX_N[1]}]
set_property PACKAGE_PIN F31 [get_ports {IPASS0_TX_P[2]}]
set_property PACKAGE_PIN F32 [get_ports {IPASS0_TX_N[2]}]
set_property PACKAGE_PIN E33 [get_ports {IPASS0_TX_P[3]}]
set_property PACKAGE_PIN E34 [get_ports {IPASS0_TX_N[3]}]
###############################################################################
# Pin constraints for PCIe-related signals
###############################################################################
set_property PACKAGE_PIN F22 [get_ports {IPASS_SIDEBAND[0]}]
set_property PACKAGE_PIN D20 [get_ports {IPASS_SIDEBAND[1]}]
set_property PACKAGE_PIN AG14 [get_ports {PCIE_RESET}]
set_property IOSTANDARD LVCMOS12 [get_ports {IPASS_SIDEBAND[*] PCIE_RESET}]
top/x400/constraints/pins/qsfp0_0.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 0 (Lane 0) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
# Lane 0 (X0Y16)
set_property PACKAGE_PIN E38 [get_ports {QSFP0_0_RX_P}]
set_property PACKAGE_PIN E39 [get_ports {QSFP0_0_RX_N}]
set_property PACKAGE_PIN D31 [get_ports {QSFP0_0_TX_P}]
set_property PACKAGE_PIN D32 [get_ports {QSFP0_0_TX_N}]
top/x400/constraints/pins/qsfp0_1.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 0 (Lane 1) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
# Lane 1 (X0Y17)
set_property PACKAGE_PIN D36 [get_ports {QSFP0_1_RX_P}]
set_property PACKAGE_PIN D37 [get_ports {QSFP0_1_RX_N}]
set_property PACKAGE_PIN C33 [get_ports {QSFP0_1_TX_P}]
set_property PACKAGE_PIN C34 [get_ports {QSFP0_1_TX_N}]
top/x400/constraints/pins/qsfp0_2.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 0 (Lane 2) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
# Lane 2 (X0Y18)
set_property PACKAGE_PIN C38 [get_ports {QSFP0_2_RX_P}]
set_property PACKAGE_PIN C39 [get_ports {QSFP0_2_RX_N}]
set_property PACKAGE_PIN B31 [get_ports {QSFP0_2_TX_P}]
set_property PACKAGE_PIN B32 [get_ports {QSFP0_2_TX_N}]
top/x400/constraints/pins/qsfp0_3.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 0 (Lane 3) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
# Lane 3 (X0Y19)
set_property PACKAGE_PIN B36 [get_ports {QSFP0_3_RX_P}]
set_property PACKAGE_PIN B37 [get_ports {QSFP0_3_RX_N}]
set_property PACKAGE_PIN A33 [get_ports {QSFP0_3_TX_P}]
set_property PACKAGE_PIN A34 [get_ports {QSFP0_3_TX_N}]
top/x400/constraints/pins/qsfp1_0.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 1 (Lane 0) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
# Lane 0 (X0Y4)
set_property PACKAGE_PIN AA38 [get_ports {QSFP1_0_RX_P}]
set_property PACKAGE_PIN AA39 [get_ports {QSFP1_0_RX_N}]
set_property PACKAGE_PIN Y35 [get_ports {QSFP1_0_TX_P}]
set_property PACKAGE_PIN Y36 [get_ports {QSFP1_0_TX_N}]
###############################################################################
# GTY_RCV_CLK_P can only be used with QSFP1
###############################################################################
set_property PACKAGE_PIN Y31 [get_ports {GTY_RCV_CLK_P}]
set_property PACKAGE_PIN Y32 [get_ports {GTY_RCV_CLK_N}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {GTY_RCV_CLK_*}]
top/x400/constraints/pins/qsfp1_1.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 1 (Lane 1) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
# Lane 1 (X0Y5)
set_property PACKAGE_PIN W38 [get_ports {QSFP1_1_RX_P}]
set_property PACKAGE_PIN W39 [get_ports {QSFP1_1_RX_N}]
set_property PACKAGE_PIN V35 [get_ports {QSFP1_1_TX_P}]
set_property PACKAGE_PIN V36 [get_ports {QSFP1_1_TX_N}]
top/x400/constraints/pins/qsfp1_2.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 1 (Lane 2) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
# Lane 2 (X0Y6)
set_property PACKAGE_PIN U38 [get_ports {QSFP1_2_RX_P}]
set_property PACKAGE_PIN U39 [get_ports {QSFP1_2_RX_N}]
set_property PACKAGE_PIN T35 [get_ports {QSFP1_2_TX_P}]
set_property PACKAGE_PIN T36 [get_ports {QSFP1_2_TX_N}]
top/x400/constraints/pins/qsfp1_3.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 1 (Lane 3) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
# Lane 3 (X0Y7)
set_property PACKAGE_PIN R38 [get_ports {QSFP1_3_RX_P}]
set_property PACKAGE_PIN R39 [get_ports {QSFP1_3_RX_N}]
set_property PACKAGE_PIN R33 [get_ports {QSFP1_3_TX_P}]
set_property PACKAGE_PIN R34 [get_ports {QSFP1_3_TX_N}]
top/x400/constraints/pins/rfdc_2x2.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# RF data converters pin constraints for X410.
# Note: commented constraints are left for documentation purposes.
#
# SYSREF input for data converters.
set_property PACKAGE_PIN U4 [get_ports {SYSREF_RF_N}]
set_property PACKAGE_PIN U5 [get_ports {SYSREF_RF_P}]
###############################################################################
# Pin constraints for the ADCs
###############################################################################
# ADC Reference Clocks for Slot 0 (DBA)
set_property PACKAGE_PIN AF5 [get_ports {ADC_CLK_P[0]}]
set_property PACKAGE_PIN AF4 [get_ports {ADC_CLK_N[0]}]
set_property PACKAGE_PIN AD5 [get_ports {ADC_CLK_P[1]}]
set_property PACKAGE_PIN AD4 [get_ports {ADC_CLK_N[1]}]
# ADC Reference Clocks for Slot 1 (DBB)
set_property PACKAGE_PIN AB5 [get_ports {ADC_CLK_P[2]}]
set_property PACKAGE_PIN AB4 [get_ports {ADC_CLK_N[2]}]
set_property PACKAGE_PIN Y5 [get_ports {ADC_CLK_P[3]}]
set_property PACKAGE_PIN Y4 [get_ports {ADC_CLK_N[3]}]
# ADC Inputs for Slot 0 (DBA)
# Note: numbering here does NOT match schematic, but it is the right order
# according to RF BD Connection spec.
# set_property PACKAGE_PIN AH2 [get_ports {DB0_RX_P[3]}]
# set_property PACKAGE_PIN AH1 [get_ports {DB0_RX_N[3]}]
# set_property PACKAGE_PIN AK2 [get_ports {DB0_RX_P[2]}]
# set_property PACKAGE_PIN AK1 [get_ports {DB0_RX_N[2]}]
set_property PACKAGE_PIN AM2 [get_ports {DB0_RX_P[1]}]
set_property PACKAGE_PIN AM1 [get_ports {DB0_RX_N[1]}]
set_property PACKAGE_PIN AP2 [get_ports {DB0_RX_P[0]}]
set_property PACKAGE_PIN AP1 [get_ports {DB0_RX_N[0]}]
# ADC Inputs for Slot 1 (DBB)
# Note: numbering here does NOT match schematic, but it is the right order
# according to RF BD Connection spec.
# set_property PACKAGE_PIN Y2 [get_ports {DB1_RX_P[3]}]
# set_property PACKAGE_PIN Y1 [get_ports {DB1_RX_N[3]}]
# set_property PACKAGE_PIN AB2 [get_ports {DB1_RX_P[2]}]
# set_property PACKAGE_PIN AB1 [get_ports {DB1_RX_N[2]}]
set_property PACKAGE_PIN AD2 [get_ports {DB1_RX_P[1]}]
set_property PACKAGE_PIN AD1 [get_ports {DB1_RX_N[1]}]
set_property PACKAGE_PIN AF2 [get_ports {DB1_RX_P[0]}]
set_property PACKAGE_PIN AF1 [get_ports {DB1_RX_N[0]}]
###############################################################################
# Pin constraints for the DACs
###############################################################################
# DAC Reference Clock for Slot 0 (DBA)
set_property PACKAGE_PIN R5 [get_ports {DAC_CLK_P[0]}]
set_property PACKAGE_PIN R4 [get_ports {DAC_CLK_N[0]}]
# DAC Reference Clock for Slot 1 (DBB)
set_property PACKAGE_PIN N5 [get_ports {DAC_CLK_P[1]}]
set_property PACKAGE_PIN N4 [get_ports {DAC_CLK_N[1]}]
# DAC Outputs for Slot 0 (DBA)
set_property PACKAGE_PIN U2 [get_ports {DB0_TX_P[0]}]
set_property PACKAGE_PIN U1 [get_ports {DB0_TX_N[0]}]
set_property PACKAGE_PIN R2 [get_ports {DB0_TX_P[1]}]
set_property PACKAGE_PIN R1 [get_ports {DB0_TX_N[1]}]
# set_property PACKAGE_PIN N2 [get_ports {DB0_TX_P[2]}]
# set_property PACKAGE_PIN N1 [get_ports {DB0_TX_N[2]}]
# set_property PACKAGE_PIN L2 [get_ports {DB0_TX_P[3]}]
# set_property PACKAGE_PIN L1 [get_ports {DB0_TX_N[3]}]
# DAC Outputs for Slot 1 (DBB)
set_property PACKAGE_PIN J2 [get_ports {DB1_TX_P[0]}]
set_property PACKAGE_PIN J1 [get_ports {DB1_TX_N[0]}]
set_property PACKAGE_PIN G2 [get_ports {DB1_TX_P[1]}]
set_property PACKAGE_PIN G1 [get_ports {DB1_TX_N[1]}]
# set_property PACKAGE_PIN E2 [get_ports {DB1_TX_P[2]}]
# set_property PACKAGE_PIN E1 [get_ports {DB1_TX_N[2]}]
# set_property PACKAGE_PIN C2 [get_ports {DB1_TX_P[3]}]
# set_property PACKAGE_PIN C1 [get_ports {DB1_TX_N[3]}]
top/x400/constraints/timing/common.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Common timing constraints for X410.
#
###############################################################################
# Motherboard Clocks
###############################################################################
# 10/25 MHz reference clock from rear panel connector.
# Constrain to the fastest possible clock rate.
set ref_clk_period 40.00
create_clock -name ref_clk -period $ref_clk_period [get_ports BASE_REFCLK_FPGA_P]
# PLL Reference Clock. Used to derive data clocks.
# Constrain to the fastest possible clock rate supported in the driver.
# MPM supports 61.44 / 62.5 / 64.0 MHz.
set pll_ref_clk_period 15.625
create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P]
# MGT Clocks
# Clock Reference | Frequency | Purpose
# MGT_REFCLK_LMK0 | 156.25/125 MHz | 10 GbE
# MGT_REFCLK_LMK1 | 100.00 MHz | Reserved
# MGT_REFCLK_LMK2 | 100.00 MHz | Reserved
# MGT_REFCLK_LMK3 | 156.25/125 MHz | 10 GbE
create_clock -name mgt_ref_0 -period 6.400 [get_ports MGT_REFCLK_LMK0_P]
create_clock -name mgt_ref_1 -period 10.000 [get_ports MGT_REFCLK_LMK1_P]
create_clock -name mgt_ref_2 -period 10.400 [get_ports MGT_REFCLK_LMK2_P]
create_clock -name mgt_ref_3 -period 6.400 [get_ports MGT_REFCLK_LMK3_P]
# Virtual clocks for constraining misc. I/Os.
create_clock -name async_in_clk -period 50.00
create_clock -name async_out_clk -period 50.00
###############################################################################
# Aliases for auto-generated clocks
###############################################################################
# Name the PS clocks. These are originally declared in the PS8 IP block.
# Create the clocks based on the PS PLCLK pins.
# This generates critical warnings in the OSS flow because the clocks were already
# define and we are completely rewriting the old clock definition... this is OK.
create_clock -name clk100 -period 10.000 \
[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[0]}]
create_clock -name clk40 -period 25.000 \
[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[1]}]
create_clock -name clk166 -period 6.000 \
[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[2]}]
create_clock -name clk200 -period 5.000 \
[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[3]}]
###############################################################################
# Sync to DB synthesizer sync CPLD input
###############################################################################
# synth_sync_hold_requirement and synth_sync_setup_requirement are shared
# between the FPGA and DB CPLD. The values are set in shared_constants.sdc
set synth_sync_ports [get_ports {DB0_SYNTH_SYNC DB1_SYNTH_SYNC}]
set_output_delay -clock [get_clocks pll_ref_clk] -min -$synth_sync_hold_requirement $synth_sync_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $synth_sync_setup_requirement $synth_sync_ports
###############################################################################
# SPI to MB CPLD (PL)
# This interface is defined as system synchronous to pll_ref_clk.
###############################################################################
# The output delays are chosen to allow a large time window of valid data for
# the MB CPLD logic.
set spi_min_out_delay 0.000
set spi_max_out_delay 11.000
# Set output constraints for all ports.
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
# Both CPLD and FPGA use PLL reference clock from a common clock chip.
# The traces from that clock chip to the ICs are not length matched. Assume a
# worst case clock difference of 0.5 ns at the IC inputs. There is no direction
# defined. The clock can arrive faster or slower at one IC.
set pl_clock_diff 0.500
# The longest trace on the PL SPI interface is (assuming 170.0 ps/in)
# Longest trace | Trace length | Trace delay
# PL_CPLD_MISO | 3.863 in | 0.657 ns
set pl_spi_board_delay 0.657
# Output delay timings of the MB CPLD design, which still meet timing
set pl_spi_cpld_min_out -1.000
set pl_spi_cpld_max_out 8.000
set spi_in_port [get_ports {PL_CPLD_MISO}]
set_input_delay -clock [get_clocks pll_ref_clk] \
-min [expr {- $pl_spi_cpld_min_out - $pl_clock_diff}] \
$spi_in_port
set_input_delay -clock [get_clocks pll_ref_clk] \
-max [expr {$pll_ref_clk_period - $pl_spi_cpld_max_out + $pl_spi_board_delay + $pl_clock_diff}] \
$spi_in_port
###############################################################################
# 10 GbE
###############################################################################
# These are the exceptions from "xge_pcs_pma_exceptions.xdc" which are to be
# used when not using the example design.
#
# "clk100" used here is the clock that's connected to the "dclk" input in the core.
set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 6.40
set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 6.40
set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk100] -datapath_only 6.40
set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk100] -datapath_only 6.40
set_max_delay -from [get_clocks clk100] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 10.000
set_max_delay -from [get_clocks clk100] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 10.000
###############################################################################
# DIO
# Those GPIO pins are considered asynchronous paths. The user has to add
# constraints in case required. Therefore not setting false_paths from / to
# user logic to allow user generated timing constraints to be applied.
###############################################################################
# Ignore paths from "slow" PS interface to not interfere with user constraints.
set dio_ports [get_ports {DIOA_FPGA[*] DIOB_FPGA[*]}]
set dio_registers [get_cells -hierarchical -filter {NAME =~ *x4xx_dio_i* && IS_SEQUENTIAL && IS_PRIMITIVE}]
set_false_path -from $dio_registers -to $dio_ports
set_false_path -from $dio_ports -to $dio_registers
###############################################################################
# PPS
###############################################################################
# The TRIG_IO port may be driven by either the PPS in BRC domain to
# enable direct sync between 2 devices, or by any other user logic.
# When PPS is exported through Trigger I/O, timing must be analyzed
# to ensure determinism in the PPS exporting.
# But, when other user logic drives TRIG_IO, then the port should be
# treated as asynchronous (or close to async. at least).
# To achieve this conditional timing analysis, the following trick is
# used:
# 1. A virtual copy of ref_clk is created for I/O timing - virtual_ref_clk
# 2. Set output_delay constraints to assign a clock to the TRIG_IO port.
# 3. A set_max_delay constraint is used to time the output path to TRIG_IO
# set_max_delay makes the timing constraint driver agnostic, and as long
# as the critical output delay is met for driving PPS through TRIG_IO,
# we should be fine as this requirement is relatively loose.
# 1) Creating copy of ref_clk to only analyze timing to TRIG_IO port (output)
# when output is driven by ref_clk (PPS generation in ref_clk domain).
create_clock -name virtual_ref_clk -period $ref_clk_period
# Trigger IO port is used as output for the PPS signal
# TRIG_IO_1V8 trace length MB = 4.050 + 1.190 inch = 5.240 inch
# TRIG_IO_1V8 trace length DB = 2.401 + 0.120 + 0.457 + 0.261 inch = 3.239 inch
# TRIG_IO buffer max switching time = 3.3
set trig_max_out_delay [expr {8.479 * 0.17 + 3.3}]
# Set minimum output delay hold time to a small amount to grant external
# devices some hold time. Delay should be simple to achieve as there is no PLL
# in the clocking path and some combinatorial logic.
set trig_min_out_delay 2.000
# 2) set_output_delay for assigning clocks to TRIG_IO. Use zero for delay to
# avoid adding extra delay requirements on top of the set_max|min_delay
# constraints below.
set_output_delay -clock [get_clocks virtual_ref_clk] 0.0 [get_ports {TRIG_IO}]
# 3) Min and max delays make constraining driver agnostic. We just make sure
# the critical timing for PPS export is met though.
set_max_delay -through [get_port {TRIG_IO}] -to [get_clocks {virtual_ref_clk}] \
[expr {$ref_clk_period - $trig_max_out_delay}]
set_min_delay -through [get_port {TRIG_IO}] -to [get_clocks {virtual_ref_clk}] \
$trig_min_out_delay
# Treat TRIG_IO input as asynchronous.
set_false_path -from [get_ports {TRIG_IO}]
# For documentation purposes, these are the input max/min delays for TRIG_IO:
# - Input delay assuming zero trace delay and TRIG_IO buffer min switching
# time (B->A) = 0.1 ns.
# - TRIG_IO buffer max switching time (B->A = input) = 3.7 ns + same trace
# length as for output (8.479).
# Assuming no delay on external clock distribution.
# Account for the PPS min output delay only (for the case two X410 are directly
# connected to each other).
set pps_min_in_delay $trig_min_out_delay
# PPS_IN trace length DB = 0.535 + 0.133 + 0.117 + 0.061 + 2.745 inch = 3.591 inch
# PPS_IN trace length MB = 5.726 inch
# PPS switch max propagation delay = 3.6
# Assume 50% of the clock period is used for external PPS clock distribution as
# the PPS out is used to synchronize one X410 (master) with another X410
# (slave) the PPS out (trig_io) delay is added to the PPS input.
set pps_max_in_delay [expr {9.317 * 0.17 + 3.6 + 0.5 * $ref_clk_period + $trig_max_out_delay}]
# Apply PPS input constraints.
set_input_delay -clock [get_clocks ref_clk] -min $pps_min_in_delay [get_ports {PPS_IN}]
set_input_delay -clock [get_clocks ref_clk] -max $pps_max_in_delay [get_ports {PPS_IN}]
# PPS clock domain crossing BRC -> PRC on the aligned edge.
# Use a data path of half PLL reference clock period to make sure the value is
# captured without metastability.
set_max_delay -from [get_cells -hierarchical pps_delayed_brc_reg] \
-to [get_clocks pll_ref_clk*] [expr {$pll_ref_clk_period/2}]
###############################################################################
# LMK sync
###############################################################################
# The timings are derived from simulation.
# Clock Buffer ADCLK944 -> FPGA.
set buffer_to_fpga_min_clk_delay 0.997
set buffer_to_fpga_max_clk_delay 1.154
# Clock Buffer ADCLK944 -> Sample clock PLL (LMK04832).
set buffer_to_spll_min_clk_delay 0.000
set buffer_to_spll_max_clk_delay 0.014
# FPGA -> Sample clock PLL SYNC input.
set fpga_to_spll_min_clk_delay 0.381
set fpga_to_spll_max_clk_delay 0.460
# Sample clock PLL requirements.
set lmk_sync_input_hold 4.000
set lmk_sync_input_setup 4.000
set lmk_sync_output_max_delay [expr {$fpga_to_spll_max_clk_delay + $buffer_to_fpga_max_clk_delay + \
$lmk_sync_input_setup - $buffer_to_spll_min_clk_delay}]
set lmk_sync_output_min_delay [expr {$fpga_to_spll_min_clk_delay + $buffer_to_fpga_min_clk_delay - \
$buffer_to_spll_max_clk_delay - $lmk_sync_input_hold}]
set_output_delay -clock ref_clk -max $lmk_sync_output_max_delay [get_ports {LMK_SYNC}]
set_output_delay -clock ref_clk -min $lmk_sync_output_min_delay [get_ports {LMK_SYNC}]
###############################################################################
# SPLL SYSREF Capture
###############################################################################
# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
# SYSREF and PLL reference clock are directly fed into the RFSoC.
# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
# output) with a double synchronizer and then transfered to the RFDC clock
# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
# sync. purposes.
# SYSREF is a continuous signal running at PRC freq. / 25, and it is
# intentionally shifted in the LMK chip to align it closer to the
# PRC's falling edge.
# The added delay follows the formula:
# SYSREF LMK delay = 22 * sample clock period
# The highest sampling frequency supported in MPM (3.072 GHz) is used for
# timing constrains. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9).
set sysref_lmk_delay 7.161
#
# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
#
# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
# which essentially over-constrains SYSREF.
#
# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
# calculated as follows:
# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
# - PRC prop. delay (min)
set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
#
# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
# is calculated as follows:
# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
# - PRC prop. delay (min)
set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
###############################################################################
# DB GPIO
# This interface is defined as system synchronous to pll_ref_clk.
# Some timing constants in this section are declared in
# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
###############################################################################
# Set output constraints for all ports.
set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_fpga_min_out $db_gpio_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_fpga_max_out $db_gpio_ports
# Output enable signal is available one clock cycle ahead of valid data, this
# enables the use of multi-cycle paths.
set db_gpio_out_en_regs [get_cells -hierarchical -filter \
{PRIMITIVE_TYPE =~ REGISTER.*.* && NAME =~ "*bytestream_output_enable*"}]
set_multicycle_path 2 -setup -from $db_gpio_out_en_regs -to $db_gpio_ports
set_multicycle_path 1 -hold -from $db_gpio_out_en_regs -to $db_gpio_ports
# Calculate output delays back from capturing edge, add board delay and clock
# difference.
# Assume worst case as data being generated late and receiving an early clock:
# - Max CPLD TCO
# - Max data propagation delay
# - Max CPLD clock propagation delay and minimum FPGA clock propagation delay
# - Maximum delay from MC100EPT23 clock buffer
set_input_delay -clock pll_ref_clk \
-max [expr {$pll_ref_clk_period - $db_gpio_cpld_max_out + $db_gpio_board_max_delay \
+ $db_cpld_prc_clock_prop_max - $fpga_prc_clock_prop_min + $clock_translate_max}] \
$db_gpio_ports
# Negate minimum output delay as it is defined from the change to the start
# clock edge.
# Assume worst case as data being generated early and receiving an late clock:
# - Min CPLD TCO
# - Min data propagation delay (0)
# - Min CPLD clock propagation delay and max FPGA clock propagation delay
set_input_delay -clock pll_ref_clk \
-min [expr {- $db_gpio_cpld_min_out \
- $db_gpio_board_min_delay \
- $db_cpld_prc_clock_prop_min + $fpga_prc_clock_prop_max}] \
$db_gpio_ports
###############################################################################
# x4xx_ps_rfdc_bd
###############################################################################
# The calibration_muxes component contains a clock crossing from some GPIO
# component instances that are synchronous to a configuration clock and ending
# in some AXI registers synchronous to data clock. The GPIO registers are
# essentially constant. When they are changing (due to a register write), the
# latching registers can definitely become metastable, so the software must
# ensure that the corrupted data appears at a safe time.
set gpio_regs [get_pins -of [get_cells -filter {IS_SEQUENTIAL && NAME =~ *rfdc/calibration_muxes/axi_gpio*} -hier] -filter {IS_CLOCK}]
set mux_regs [get_cells -hier -filter {IS_SEQUENTIAL && NAME =~ *rfdc/calibration_muxes/gpio_to_axis_mux*}]
set_false_path -from $gpio_regs -to $mux_regs
# This property tells Vivado that we require these clocks to be well aligned.
# We have synchronous clock domain crossings between these clocks that can have
# large hold violations after placement due to uneven clock loading.
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \
}]
# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that
# code clocked in this domain will be reset after this clocked is enabled. This
# will make timing easier to meet on these clock domains.
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}]
###############################################################################
# Misc Constraints
###############################################################################
# Double synchronizer false paths.
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */rf_reset_controller*/*_ms_reg/D}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_nco_reset_0/*_ms*/D}]
# GTY_RCV_CLK_* is driven by a OBUFDS_GTE4 buffer, which has an asynchronous
# clock-enable pin.
# By experimentation, it was observed that explicitly setting a false_path to
# this pin improved timing.
set gty_rcv_clk_buff_ceb [get_pins -of_objects [get_cells -of_objects [all_fanin -flat -startpoints_only [get_ports {GTY_RCV_CLK_P}]]] -filter {NAME=~ "*CEB"}]
set_false_path -from [get_clocks {clk40}] -through $gty_rcv_clk_buff_ceb
###############################################################################
# Asynchronous / misc. I/O constraints
# Loosely constrain these to prevent warnings in Vivado.
# Using set_input_delay associates the I/Os to a clock group, but
# set_(min|max)_delay overwrites the setup/hold analysis values.
###############################################################################
set async_inputs [get_ports {FPGA_AUX_REF}]
set_input_delay -clock [get_clocks async_in_clk] 0.000 $async_inputs
set_max_delay -from $async_inputs 50.000
set_min_delay -from $async_inputs 0.000
set async_outputs [get_ports {FABRIC_CLK_OUT_P PPS_LED}]
set_output_delay -clock [get_clocks async_out_clk] 0.000 $async_outputs
set_max_delay -to $async_outputs 50.000
set_min_delay -to $async_outputs 0.000
top/x400/constraints/timing/dram.xdc
+55
View File
@@ -0,0 +1,55 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# DRAM timing constraints for X410.
#
set DramSysClockPeriod 9.996
set DramSysClockWave {0.0 4.998}
create_clock -name Dram0SysClock -period $DramSysClockPeriod -waveform $DramSysClockWave [get_ports {DRAM0_REFCLK_P}]
create_clock -name Dram1SysClock -period $DramSysClockPeriod -waveform $DramSysClockWave [get_ports {DRAM1_REFCLK_P}]
## This calibration signal is a static signal. Once asserted it will stay HIGH.
## The multi cycle path constraint is added to improve timing.
set_multicycle_path -setup 8 -from [get_pins */inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone*/C]
set_multicycle_path -end -hold 7 -from [get_pins */inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone*/C]
## These signals once asserted, stay asserted for multiple clock cycles.
## False path constraint is added to improve the HOLD timing.
set_false_path -hold -to [get_pins */inst/*/*/*/*/*/*.u_xiphy_control/xiphy_control/RIU_ADDR*]
set_false_path -hold -to [get_pins */inst/*/*/*/*/*/*.u_xiphy_control/xiphy_control/RIU_WR_DATA*]
## Multi-cycle path constraints for Fabric - RIU clock domain crossing signals
set_max_delay 5.0 -datapath_only -from [get_pins */inst/*/*/*/u_ddr_cal_addr_decode/io_ready_lvl_reg/C] -to [get_pins */inst/*/u_io_ready_lvl_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 5.0 -datapath_only -from [get_pins */inst/*/*/*/u_ddr_cal_addr_decode/io_read_data_reg[*]/C] -to [get_pins */inst/*/u_io_read_data_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/*/phy_ready_riuclk_reg/C] -to [get_pins */inst/*/u_phy2clb_phy_ready_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/*/bisc_complete_riuclk_reg/C] -to [get_pins */inst/*/u_phy2clb_bisc_complete_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/io_addr_strobe_lvl_riuclk_reg/C] -to [get_pins */inst/*/u_io_addr_strobe_lvl_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/io_write_strobe_riuclk_reg/C] -to [get_pins */inst/*/u_io_write_strobe_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/io_address_riuclk_reg[*]/C] -to [get_pins */inst/*/u_io_addr_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/io_write_data_riuclk_reg[*]/C] -to [get_pins */inst/*/u_io_write_data_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */inst/*/en_vtc_in_reg/C] -to [get_pins */inst/*/u_en_vtc_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */inst/*/*/riu2clb_valid_r1_riuclk_reg[*]/C] -to [get_pins */inst/*/u_riu2clb_valid_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */inst/*/*/*/phy2clb_fixdly_rdy_low_riuclk_int_reg[*]/C] -to [get_pins */inst/*/u_phy2clb_fixdly_rdy_low/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */inst/*/*/*/phy2clb_fixdly_rdy_upp_riuclk_int_reg[*]/C] -to [get_pins */inst/*/u_phy2clb_fixdly_rdy_upp/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */inst/*/*/*/phy2clb_phy_rdy_low_riuclk_int_reg[*]/C] -to [get_pins */inst/*/u_phy2clb_phy_rdy_low/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */inst/*/*/*/phy2clb_phy_rdy_upp_riuclk_int_reg[*]/C] -to [get_pins */inst/*/u_phy2clb_phy_rdy_upp/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 10.0 -datapath_only -from [get_pins */inst/*/rst_r1_reg/C] -to [get_pins */inst/*/u_fab_rst_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/*/clb2phy_t_b_addr_riuclk_reg/C] -to [get_pins */inst/*/*/*/clb2phy_t_b_addr_i_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/*/*/slave_en_lvl_reg/C] -to [get_pins */inst/*/*/*/*/u_slave_en_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/*/*/slave_we_r_reg/C] -to [get_pins */inst/*/*/*/*/u_slave_we_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/*/*/slave_addr_r_reg[*]/C] -to [get_pins */inst/*/*/*/*/u_slave_addr_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/*/*/slave_di_r_reg[*]/C] -to [get_pins */inst/*/*/*/*/u_slave_di_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 3.0 -datapath_only -from [get_pins */inst/*/*/*/*/slave_rdy_cptd_sclk_reg/C] -to [get_pins */inst/*/*/*/*/u_slave_rdy_cptd_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 12.0 -datapath_only -from [get_pins */inst/*/*/*/*/slave_rdy_lvl_fclk_reg/C] -to [get_pins */inst/*/*/*/*/u_slave_rdy_sync/SYNC[*].sync_reg_reg[0]/D]
set_max_delay 12.0 -datapath_only -from [get_pins */inst/*/*/*/*/slave_do_fclk_reg[*]/C] -to [get_pins */inst/*/*/*/*/u_slave_do_sync/SYNC[*].sync_reg_reg[0]/D]
set_false_path -through [get_pins */inst/u_ddr4_infrastructure/sys_rst]
set_false_path -from [get_pins */inst/*/input_rst_design_reg/C] -to [get_pins */inst/*/rst_div_sync_r_reg[0]/D]
set_false_path -from [get_pins */inst/*/input_rst_design_reg/C] -to [get_pins */inst/*/rst_riu_sync_r_reg[0]/D]
set_false_path -from [get_pins */inst/*/input_rst_design_reg/C] -to [get_pins */inst/*/rst_mb_sync_r_reg[0]/D]
set_false_path -from [get_pins */inst/*/rst_async_riu_div_reg/C] -to [get_pins */inst/*/rst_div_sync_r_reg[0]/D]
set_false_path -from [get_pins */inst/*/rst_async_mb_reg/C] -to [get_pins */inst/*/rst_mb_sync_r_reg[0]/D]
set_false_path -from [get_pins */inst/*/rst_async_riu_div_reg/C] -to [get_pins */inst/*/rst_riu_sync_r_reg[0]/D]
top/x400/constraints/timing/qsfp_10gbe.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# 10 GbE Timing Constraints.
#
# Specify which clock is used for dclk in the 10 GbE IP.
set DCLK_NAME clk100
# Constraints taken from xge_pcs_pma_exceptions.xdc in the example design.
set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 6.40
set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 6.40
set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks $DCLK_NAME] -datapath_only 6.40
set_max_delay -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks $DCLK_NAME] -datapath_only 6.40
set_max_delay -from [get_clocks $DCLK_NAME] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -datapath_only 10.000
set_max_delay -from [get_clocks $DCLK_NAME] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -datapath_only 10.000
top/x400/constraints/timing/shared_constants.sdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Shared constants for the X410 FPGA and the ZBX CPLD.
#
# These output delays are more or less arbitrarily chosen, but they dictate the
# delays at the input of the DB CPLD.
# Since the CPLD is built in Quartus, the file extension is .sdc.
set synth_sync_hold_requirement 1.0
set synth_sync_setup_requirement 8.5
# A MC100EPT23 clock translator is placed on the daughterboard to convert
# pll_ref_clk clock IO Standard to 3.3V. The minimum and maximum delays across
# this part are 1.1 ns and 1.8 ns, respectively.
# https://www.onsemi.com/pub/Collateral/MC100EPT23-D.PDF
set clock_translate_min 1.1
set clock_translate_max 1.8
## DB GPIO interface.
# The following values have been adjusted after verifying the slack on input
# and output path for the Post-synthesized designs for FPGA (Vivado) and CPLD
# (Quartus). Values are chosen as those that provide the most slack for FPGA
# timing, while still meeting timing on the CPLD.
# FPGA output constraints
set db_gpio_fpga_min_out 0.000
set db_gpio_fpga_max_out 3.250
# CPLD output constraints
set db_gpio_cpld_min_out -2.000
set db_gpio_cpld_max_out 8.500
# The longest traces on the DB GPIO interface.
# In order to compute the db_gpio_board_max_delay, the longest GPIO trace from
# the FPGA to any of the DB connector was simulated, and its worst-case value
# was added to the worst-case value obtained while simulating the longest GPIO
# trace on the DB. Both directions (FPGA <-> CPLD) were considered when
# computing the longest propagation delays. Propagation through the Board to
# board connector is assumed shorter than the effect of having the edge
# propagation time twice, as well as adding the two longest traces, instead of
# the longest corresponding pair.
# Longest trace | Trace length | Worst-case delay
# MB: DB0_GPIO[19] | 4.25 in | 912 ps
# DB: MB_FPGA_GPIO_A8 | 3.83 in | 862 ps
set db_gpio_board_max_delay 1.774
# The shortest traces on the DB GPIO interface are (assuming 170.0 ps/in).
# A similar consideration was made as for db_gpio_board_max_delay, but using
# the shortest traces in each CCA.
# In this case, edge propagation was not taken into account, as the trace delay
# can act as the worst-case minimum.
# Shorted trace | Trace length | Trace delay
# MB: DB1_GPIO[8] | 2.23 in | 379 ps
# DB: MB_FPGA_GPIO_B12| 2.57 in | 436 ps
set db_gpio_board_min_delay 0.815
# DB and FPGA both use PLL reference clock from a common clock chip.
# The common chip that drives these clocks is a LMK04832.
# There exist two additional clock buffers within the trace taking the clock to
# the daughterboard CPLD, a ADCLK944 located in the DB, and a MC100EPT23 near
# the CPLD which takes care of level translation.
# The largest delay that can exist between clocks exists when the LMK04832
# presents its max skew between outputs and when all clock buffers present
# their maximum delay.
# MC100EPT23 propagation delays will be handled separately in constraints due
# to their significant impact in timing closure, as well as to enable support
# for various corner-cases.
# Board delays were simulated in HyperLynx. Minimum delays considered time
# between start of edge at the source to the start of edge at destination.
# Maximum delays considered time between the start of an edge at the source and
# the settling of the edge at destination. Corner cases were considered for IC
# modeling.
#
# The clock path to the FPGA is composed by a single trace:
# - Minimum clock propagation delay to FPGA = 815 ps.
# - Maximum clock propagation delay to FPGA = 1.329 ps.
#
# The clock path to the CPLD (w/o MC100EPT23) is comprised by multiple traces:
# - Path from MB LMK04832 to DB connector
# - Minimum delay : 1636 ps
# - Path from DB Connector to DB ADCLK944
# - Minimum delay : 299 ps
# - Path from DB ADCLK944 to CPLD:
# - Minimum delay : 197 ps
#
# The clock path to the CPLD (w/ MC100EPT23) is comprised of multiple traces:
# - Path from MB LMK04832 to DB connector
# - Minimum delay : 1636 ps
# - Maximum delay : 1890 ps
# - Path from DB Connector to DB ADCLK944
# - Minimum delay : 299 ps
# - Maximum delay : 397 ps
# - Path from DB ADCLK944 to MC100EPT23:
# - Minimum delay : 120 ps
# - Maximum delay : 411 ps
# - Path from MC100EPT23 to CPLD:
# - Minimum delay : 365 ps
# - Maximum delay : 847 ps
#
# The minimum and maximum delays for all traces can be added to account for the
# total board delay to the CPLD:
#
# Max total Board delay = 1890 + 397 + 411 + 847 = 3545 ps
#
# Min total Board delay = 1636 + 299 + 197 = 2132 ps
# This leaves the worst-case clock arrival values for the different ICs as:
# Max total Board delay + (Max LMK Skew) + (Max DB ADCLK Prop)
# 3.545 + .1 + .130 = 3.775 ns,
set db_cpld_prc_clock_prop_max 3.775
# Min total Board delay - (Max LMK Skew) + (Min DB ADCLK Prop)
# 2.132 - .1 + .07 = 2.102 ns,
set db_cpld_prc_clock_prop_min 2.102
# Board delay + (Max LMK Skew)
# 1.329 + .1 = 1.429 ns
set fpga_prc_clock_prop_max 1.429
# Board delay - (Max LMK Skew)
# .815 - .1 = 0.715 ns
set fpga_prc_clock_prop_min 0.715
# When combining these values, the LMK Skew will be accounted for twice,
# which will just result in more conservative constraints.
top/x400/coregen_dsp/Makefile.srcs
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#
# Copyright 2021 Ettus Research, A National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
##################################################
# Coregen Sources
##################################################
COREGEN_DSP_SRCS = $(abspath $(addprefix $(IP_DIR)/../coregen_dsp/, \
hbdec1.v \
hbdec1.edif \
hbdec1_stub.v \
hbdec2.v \
hbdec2.edif \
hbdec2_stub.v \
hbdec3.v \
hbdec3.edif \
hbdec3_stub.v \
))
top/x400/coregen_dsp/hbdec1.edif
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top/x400/coregen_dsp/hbdec1.v
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top/x400/coregen_dsp/hbdec1_stub.v
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module hbdec1(
sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk,
coef_ld, dout_1, dout_2, din_1, din_2, coef_din
)
/* synthesis syn_black_box black_box_pad_pin="sclr,ce,rfd,rdy,data_valid,coef_we,nd,clk,coef_ld,dout_1[47:0],dout_2[47:0],din_1[23:0],din_2[23:0],coef_din[17:0]" */;
input sclr;
input ce;
output rfd;
output rdy;
output data_valid;
input coef_we;
input nd;
input clk;
input coef_ld;
output [46:0]dout_1;
output [46:0]dout_2;
input [23:0]din_1;
input [23:0]din_2;
input [17:0]coef_din;
endmodule
top/x400/coregen_dsp/hbdec2.edif
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top/x400/coregen_dsp/hbdec2.v
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top/x400/coregen_dsp/hbdec2_stub.v
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module hbdec2(
sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk,
coef_ld, dout_1, dout_2, din_1, din_2, coef_din
)
/* synthesis syn_black_box black_box_pad_pin="sclr,ce,rfd,rdy,data_valid,coef_we,nd,clk,coef_ld,dout_1[47:0],dout_2[47:0],din_1[23:0],din_2[23:0],coef_din[17:0]" */;
input sclr;
input ce;
output rfd;
output rdy;
output data_valid;
input coef_we;
input nd;
input clk;
input coef_ld;
output [46:0]dout_1;
output [46:0]dout_2;
input [23:0]din_1;
input [23:0]din_2;
input [17:0]coef_din;
endmodule
top/x400/coregen_dsp/hbdec3.edif
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top/x400/coregen_dsp/hbdec3.v
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top/x400/coregen_dsp/hbdec3_stub.v
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module hbdec3(
sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk,
coef_ld, dout_1, dout_2, din_1, din_2, coef_din
)
/* synthesis syn_black_box black_box_pad_pin="sclr,ce,rfd,rdy,data_valid,coef_we,nd,clk,coef_ld,dout_1[47:0],dout_2[47:0],din_1[23:0],din_2[23:0],coef_din[17:0]" */;
input sclr;
input ce;
output rfd;
output rdy;
output data_valid;
input coef_we;
input nd;
input clk;
input coef_ld;
output [47:0]dout_1;
output [47:0]dout_2;
input [23:0]din_1;
input [23:0]din_2;
input [17:0]coef_din;
endmodule
top/x400/cpld_interface.v
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: cpld_interface.v
//
// Description:
//
// This module comprises the logic on the FPGA to connect with the
// motherboard CPLD.
//
// As a first step each request source is transferred to PRC domain.
// Timestamps are removed in the timer modules. All requests are bundled in
// one combiner and then split / decoded across all targets. By inserting of
// ctrlport termination modules a ctrlport answer will be available for all
// addresses to avoid blocking the main ctrlport combiner.
//
`default_nettype none
module cpld_interface (
// Clocks
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire pll_ref_clk,
input wire radio_clk,
// Reset (domain: pll_ref_clk)
input wire ctrlport_rst,
// Timestamp (domain: radio_clk)
input wire [63:0] radio_time,
input wire radio_time_stb,
input wire [ 3:0] time_ignore_bits,
// AXI4-Lite: Write address port (domain: s_axi_aclk)
input wire [16:0] s_axi_awaddr,
input wire s_axi_awvalid,
output wire s_axi_awready,
// AXI4-Lite: Write data port (domain: s_axi_aclk)
input wire [31:0] s_axi_wdata,
input wire [ 3:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
// AXI4-Lite: Write response port (domain: s_axi_aclk)
output wire[ 1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// AXI4-Lite: Read address port (domain: s_axi_aclk)
input wire [16:0] s_axi_araddr,
input wire s_axi_arvalid,
output wire s_axi_arready,
// AXI4-Lite: Read data port (domain: s_axi_aclk)
output wire [31:0] s_axi_rdata,
output wire [ 1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Control port from / to application (domain: radio_clk)
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
input wire [ 3:0] s_ctrlport_req_byte_en,
input wire s_ctrlport_req_has_time,
input wire [63:0] s_ctrlport_req_time,
output wire s_ctrlport_resp_ack,
output wire [ 1:0] s_ctrlport_resp_status,
output wire [31:0] s_ctrlport_resp_data,
// SPI Bus to connect to MB CPLD
output wire [ 1:0] ss,
output wire sclk,
output wire mosi,
input wire miso,
// QSFP port LED (domain: any)
input wire [ 3:0] qsfp0_led_active,
input wire [ 3:0] qsfp0_led_link,
input wire [ 3:0] qsfp1_led_active,
input wire [ 3:0] qsfp1_led_link,
// iPass present signals
input wire [ 1:0] ipass_present_n,
// Version (Constant)
output wire [95:0] version_info
);
`include "../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/pl_cpld_regmap_utils.vh"
`include "cpld/regmap/mb_cpld_pl_regmap_utils.vh"
`include "cpld/regmap/pl_cpld_base_regmap_utils.vh"
//---------------------------------------------------------------------------
// Internal clocks and resets
//---------------------------------------------------------------------------
wire s_axi_areset;
wire ctrlport_clk;
assign s_axi_areset = ~s_axi_aresetn;
assign ctrlport_clk = pll_ref_clk;
//---------------------------------------------------------------------------
// Timestamp synchronization
//---------------------------------------------------------------------------
reg [ 3:0] radio_time_stb_shift_reg;
wire radio_time_stb_prc;
reg [63:0] radio_time_prc;
// radio_clk and pll_ref_clk are synchronous clocks with an integer
// multiplier <= 4.
//
// A simple register can be used to capture the latest timestamp the strobe
// pulse is preserved for up to 4 clock cycles and used in pll_ref_clk domain
// to driver timers.
always @(posedge radio_clk) begin
radio_time_stb_shift_reg <= {radio_time_stb_shift_reg[2:0], radio_time_stb};
if (radio_time_stb) begin
radio_time_prc <= radio_time;
end
end
assign radio_time_stb_prc = | radio_time_stb_shift_reg;
//---------------------------------------------------------------------------
// MPM Endpoint connection
//---------------------------------------------------------------------------
// Translate AXI lite to control port.
// Timeout based on the 40 MHz AXI clock is about 0.839 seconds.
wire [19:0] mpm_endpoint_ctrlport_axi_clk_req_addr;
wire [ 3:0] mpm_endpoint_ctrlport_axi_clk_req_byte_en;
wire [31:0] mpm_endpoint_ctrlport_axi_clk_req_data;
wire mpm_endpoint_ctrlport_axi_clk_req_has_time;
wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_portid;
wire mpm_endpoint_ctrlport_axi_clk_req_rd;
wire [15:0] mpm_endpoint_ctrlport_axi_clk_req_rem_epid;
wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_rem_portid;
wire [63:0] mpm_endpoint_ctrlport_axi_clk_req_time;
wire mpm_endpoint_ctrlport_axi_clk_req_wr;
wire mpm_endpoint_ctrlport_axi_clk_resp_ack;
wire [31:0] mpm_endpoint_ctrlport_axi_clk_resp_data;
wire [ 1:0] mpm_endpoint_ctrlport_axi_clk_resp_status;
axil_ctrlport_master #(
.TIMEOUT (25),
.AXI_AWIDTH (17),
.CTRLPORT_AWIDTH (17)
) mpm_endpoint (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.m_ctrlport_req_wr (mpm_endpoint_ctrlport_axi_clk_req_wr),
.m_ctrlport_req_rd (mpm_endpoint_ctrlport_axi_clk_req_rd),
.m_ctrlport_req_addr (mpm_endpoint_ctrlport_axi_clk_req_addr),
.m_ctrlport_req_portid (mpm_endpoint_ctrlport_axi_clk_req_portid),
.m_ctrlport_req_rem_epid (mpm_endpoint_ctrlport_axi_clk_req_rem_epid),
.m_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid),
.m_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data),
.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en),
.m_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time),
.m_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time),
.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack),
.m_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status),
.m_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data)
);
// Transfer AXI clock based MPM endpoint control port request to pll_ref_clk
// domain.
wire [19:0] mpm_endpoint_ctrlport_pll_clk_req_addr;
wire [ 3:0] mpm_endpoint_ctrlport_pll_clk_req_byte_en;
wire [31:0] mpm_endpoint_ctrlport_pll_clk_req_data;
wire mpm_endpoint_ctrlport_pll_clk_req_has_time;
wire mpm_endpoint_ctrlport_pll_clk_req_rd;
wire [63:0] mpm_endpoint_ctrlport_pll_clk_req_time;
wire mpm_endpoint_ctrlport_pll_clk_req_wr;
wire mpm_endpoint_ctrlport_pll_clk_resp_ack;
wire [31:0] mpm_endpoint_ctrlport_pll_clk_resp_data;
wire [ 1:0] mpm_endpoint_ctrlport_pll_clk_resp_status;
ctrlport_clk_cross ctrlport_clk_cross_mpm (
.rst (s_axi_areset),
.s_ctrlport_clk (s_axi_aclk),
.s_ctrlport_req_wr (mpm_endpoint_ctrlport_axi_clk_req_wr),
.s_ctrlport_req_rd (mpm_endpoint_ctrlport_axi_clk_req_rd),
.s_ctrlport_req_addr (mpm_endpoint_ctrlport_axi_clk_req_addr),
.s_ctrlport_req_portid (mpm_endpoint_ctrlport_axi_clk_req_portid),
.s_ctrlport_req_rem_epid (mpm_endpoint_ctrlport_axi_clk_req_rem_epid),
.s_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid),
.s_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data),
.s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en),
.s_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time),
.s_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time),
.s_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack),
.s_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status),
.s_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data),
.m_ctrlport_clk (ctrlport_clk),
.m_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr),
.m_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd),
.m_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data),
.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en),
.m_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time),
.m_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time),
.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack),
.m_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status),
.m_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data)
);
// Apply time of ControlPort request to MPM endpoint request.
wire [19:0] mpm_endpoint_ctrlport_req_addr;
wire [ 3:0] mpm_endpoint_ctrlport_req_byte_en;
wire [31:0] mpm_endpoint_ctrlport_req_data;
wire mpm_endpoint_ctrlport_req_rd;
wire mpm_endpoint_ctrlport_req_wr;
wire mpm_endpoint_ctrlport_resp_ack;
wire [31:0] mpm_endpoint_ctrlport_resp_data;
wire [ 1:0] mpm_endpoint_ctrlport_resp_status;
ctrlport_timer #(
.EXEC_LATE_CMDS (1)
) ctrlport_timer_mpm (
.clk (ctrlport_clk),
.rst (ctrlport_rst),
.time_now (radio_time_prc),
.time_now_stb (radio_time_stb_prc),
.time_ignore_bits (time_ignore_bits),
.s_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr),
.s_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd),
.s_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr),
.s_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data),
.s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en),
.s_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time),
.s_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time),
.s_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack),
.s_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status),
.s_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data),
.m_ctrlport_req_wr (mpm_endpoint_ctrlport_req_wr),
.m_ctrlport_req_rd (mpm_endpoint_ctrlport_req_rd),
.m_ctrlport_req_addr (mpm_endpoint_ctrlport_req_addr),
.m_ctrlport_req_data (mpm_endpoint_ctrlport_req_data),
.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_req_byte_en),
.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_resp_ack),
.m_ctrlport_resp_status (mpm_endpoint_ctrlport_resp_status),
.m_ctrlport_resp_data (mpm_endpoint_ctrlport_resp_data)
);
//---------------------------------------------------------------------------
// User Application Request
//---------------------------------------------------------------------------
// Transfer request to pll_ref_clk domain.
wire [19:0] app_ctrlport_pll_clk_req_addr;
wire [ 3:0] app_ctrlport_pll_clk_req_byte_en;
wire [31:0] app_ctrlport_pll_clk_req_data;
wire app_ctrlport_pll_clk_req_has_time;
wire app_ctrlport_pll_clk_req_rd;
wire [63:0] app_ctrlport_pll_clk_req_time;
wire app_ctrlport_pll_clk_req_wr;
wire app_ctrlport_pll_clk_resp_ack;
wire [31:0] app_ctrlport_pll_clk_resp_data;
wire [ 1:0] app_ctrlport_pll_clk_resp_status;
ctrlport_clk_cross ctrlport_clk_cross_app (
.rst (ctrlport_rst),
.s_ctrlport_clk (radio_clk),
.s_ctrlport_req_wr (s_ctrlport_req_wr),
.s_ctrlport_req_rd (s_ctrlport_req_rd),
.s_ctrlport_req_addr (s_ctrlport_req_addr),
.s_ctrlport_req_portid (),
.s_ctrlport_req_rem_epid (),
.s_ctrlport_req_rem_portid (),
.s_ctrlport_req_data (s_ctrlport_req_data),
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
.s_ctrlport_req_time (s_ctrlport_req_time),
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
.s_ctrlport_resp_status (s_ctrlport_resp_status),
.s_ctrlport_resp_data (s_ctrlport_resp_data),
.m_ctrlport_clk (ctrlport_clk),
.m_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr),
.m_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd),
.m_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (app_ctrlport_pll_clk_req_data),
.m_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en),
.m_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time),
.m_ctrlport_req_time (app_ctrlport_pll_clk_req_time),
.m_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack),
.m_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status),
.m_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data)
);
// Apply timing to application based ControlPort request.
wire [19:0] app_ctrlport_req_addr;
wire [ 3:0] app_ctrlport_req_byte_en;
wire [31:0] app_ctrlport_req_data;
wire app_ctrlport_req_rd;
wire app_ctrlport_req_wr;
wire app_ctrlport_resp_ack;
wire [31:0] app_ctrlport_resp_data;
wire [ 1:0] app_ctrlport_resp_status;
ctrlport_timer #(
.EXEC_LATE_CMDS (1)
) ctrlport_timer_app (
.clk (ctrlport_clk),
.rst (ctrlport_rst),
.time_now (radio_time_prc),
.time_now_stb (radio_time_stb_prc),
.time_ignore_bits (time_ignore_bits),
.s_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr),
.s_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd),
.s_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr),
.s_ctrlport_req_data (app_ctrlport_pll_clk_req_data),
.s_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en),
.s_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time),
.s_ctrlport_req_time (app_ctrlport_pll_clk_req_time),
.s_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack),
.s_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status),
.s_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data),
.m_ctrlport_req_wr (app_ctrlport_req_wr),
.m_ctrlport_req_rd (app_ctrlport_req_rd),
.m_ctrlport_req_addr (app_ctrlport_req_addr),
.m_ctrlport_req_data (app_ctrlport_req_data),
.m_ctrlport_req_byte_en (app_ctrlport_req_byte_en),
.m_ctrlport_resp_ack (app_ctrlport_resp_ack),
.m_ctrlport_resp_status (app_ctrlport_resp_status),
.m_ctrlport_resp_data (app_ctrlport_resp_data)
);
//---------------------------------------------------------------------------
// QSFP LED Controller
//---------------------------------------------------------------------------
wire [19:0] led_ctrlport_req_addr;
wire [ 3:0] led_ctrlport_req_byte_en;
wire [31:0] led_ctrlport_req_data;
wire led_ctrlport_req_rd;
wire led_ctrlport_req_wr;
wire led_ctrlport_resp_ack;
wire [31:0] led_ctrlport_resp_data;
wire [ 1:0] led_ctrlport_resp_status;
qsfp_led_controller
# (.LED_REGISTER_ADDRESS(MB_CPLD + PL_REGISTERS + LED_REGISTER))
qsfp_led_controller_i (
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.m_ctrlport_req_wr (led_ctrlport_req_wr),
.m_ctrlport_req_rd (led_ctrlport_req_rd),
.m_ctrlport_req_addr (led_ctrlport_req_addr),
.m_ctrlport_req_data (led_ctrlport_req_data),
.m_ctrlport_req_byte_en (led_ctrlport_req_byte_en),
.m_ctrlport_resp_ack (led_ctrlport_resp_ack),
.m_ctrlport_resp_status (led_ctrlport_resp_status),
.m_ctrlport_resp_data (led_ctrlport_resp_data),
.qsfp0_led_active (qsfp0_led_active),
.qsfp0_led_link (qsfp0_led_link),
.qsfp1_led_active (qsfp1_led_active),
.qsfp1_led_link (qsfp1_led_link));
//---------------------------------------------------------------------------
// iPass present controller
//---------------------------------------------------------------------------
wire [19:0] ipass_ctrlport_req_addr;
wire [ 3:0] ipass_ctrlport_req_byte_en;
wire [31:0] ipass_ctrlport_req_data;
wire ipass_ctrlport_req_rd;
wire ipass_ctrlport_req_wr;
wire ipass_ctrlport_resp_ack;
wire [31:0] ipass_ctrlport_resp_data;
wire [ 1:0] ipass_ctrlport_resp_status;
wire ipass_enable;
ipass_present_controller ipass_present_controller_i (
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.m_ctrlport_req_wr (ipass_ctrlport_req_wr),
.m_ctrlport_req_rd (ipass_ctrlport_req_rd),
.m_ctrlport_req_addr (ipass_ctrlport_req_addr),
.m_ctrlport_req_data (ipass_ctrlport_req_data),
.m_ctrlport_req_byte_en (ipass_ctrlport_req_byte_en),
.m_ctrlport_resp_ack (ipass_ctrlport_resp_ack),
.m_ctrlport_resp_status (ipass_ctrlport_resp_status),
.m_ctrlport_resp_data (ipass_ctrlport_resp_data),
.enable (ipass_enable),
.ipass_present_n (ipass_present_n)
);
//---------------------------------------------------------------------------
// Combine all incoming combiner requests and provide to targets
//---------------------------------------------------------------------------
wire [19:0] m_ctrlport_req_addr;
wire [31:0] m_ctrlport_req_data;
wire m_ctrlport_req_rd;
wire m_ctrlport_req_wr;
wire m_ctrlport_resp_ack;
wire [31:0] m_ctrlport_resp_data;
wire [ 1:0] m_ctrlport_resp_status;
ctrlport_combiner #(
.NUM_MASTERS (4),
.PRIORITY (1)
) ctrlport_combiner_i (
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.s_ctrlport_req_wr ({ipass_ctrlport_req_wr, led_ctrlport_req_wr, mpm_endpoint_ctrlport_req_wr, app_ctrlport_req_wr}),
.s_ctrlport_req_rd ({ipass_ctrlport_req_rd, led_ctrlport_req_rd, mpm_endpoint_ctrlport_req_rd, app_ctrlport_req_rd}),
.s_ctrlport_req_addr ({ipass_ctrlport_req_addr, led_ctrlport_req_addr, mpm_endpoint_ctrlport_req_addr, app_ctrlport_req_addr}),
.s_ctrlport_req_portid (),
.s_ctrlport_req_rem_epid (),
.s_ctrlport_req_rem_portid (),
.s_ctrlport_req_data ({ipass_ctrlport_req_data, led_ctrlport_req_data, mpm_endpoint_ctrlport_req_data, app_ctrlport_req_data}),
.s_ctrlport_req_byte_en ({ipass_ctrlport_req_byte_en, led_ctrlport_req_byte_en, mpm_endpoint_ctrlport_req_byte_en, app_ctrlport_req_byte_en}),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_resp_ack ({ipass_ctrlport_resp_ack, led_ctrlport_resp_ack, mpm_endpoint_ctrlport_resp_ack, app_ctrlport_resp_ack}),
.s_ctrlport_resp_status ({ipass_ctrlport_resp_status, led_ctrlport_resp_status, mpm_endpoint_ctrlport_resp_status, app_ctrlport_resp_status}),
.s_ctrlport_resp_data ({ipass_ctrlport_resp_data, led_ctrlport_resp_data, mpm_endpoint_ctrlport_resp_data, app_ctrlport_resp_data}),
.m_ctrlport_req_wr (m_ctrlport_req_wr),
.m_ctrlport_req_rd (m_ctrlport_req_rd),
.m_ctrlport_req_addr (m_ctrlport_req_addr),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (m_ctrlport_req_data),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
.m_ctrlport_resp_status (m_ctrlport_resp_status),
.m_ctrlport_resp_data (m_ctrlport_resp_data)
);
// Split for CPLD facing requests and others.
wire [19:0] base_reg_ctrlport_req_addr;
wire [31:0] base_reg_ctrlport_req_data;
wire base_reg_ctrlport_req_rd;
wire base_reg_ctrlport_req_wr;
wire base_reg_ctrlport_resp_ack;
wire [31:0] base_reg_ctrlport_resp_data;
wire [ 1:0] base_reg_ctrlport_resp_status;
wire [19:0] spi_master_ctrlport_req_addr;
wire [31:0] spi_master_ctrlport_req_data;
wire spi_master_ctrlport_req_rd;
wire spi_master_ctrlport_req_wr;
wire spi_master_ctrlport_resp_ack;
wire [31:0] spi_master_ctrlport_resp_data;
wire [ 1:0] spi_master_ctrlport_resp_status;
wire [19:0] unused_fpga_intermediate_ctrlport_req_addr;
wire [31:0] unused_fpga_intermediate_ctrlport_req_data;
wire unused_fpga_intermediate_ctrlport_req_rd;
wire unused_fpga_intermediate_ctrlport_req_wr;
wire unused_fpga_intermediate_ctrlport_resp_ack;
wire [31:0] unused_fpga_intermediate_ctrlport_resp_data;
wire [ 1:0] unused_fpga_intermediate_ctrlport_resp_status;
wire [19:0] unused_fpga_msbs_ctrlport_req_addr;
wire [31:0] unused_fpga_msbs_ctrlport_req_data;
wire unused_fpga_msbs_ctrlport_req_rd;
wire unused_fpga_msbs_ctrlport_req_wr;
wire unused_fpga_msbs_ctrlport_resp_ack;
wire [31:0] unused_fpga_msbs_ctrlport_resp_data;
wire [ 1:0] unused_fpga_msbs_ctrlport_resp_status;
ctrlport_splitter #(
.NUM_SLAVES (4)
) ctrlport_splitter_i (
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.s_ctrlport_req_wr (m_ctrlport_req_wr),
.s_ctrlport_req_rd (m_ctrlport_req_rd),
.s_ctrlport_req_addr (m_ctrlport_req_addr),
.s_ctrlport_req_data (m_ctrlport_req_data),
.s_ctrlport_req_byte_en (),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_resp_ack (m_ctrlport_resp_ack),
.s_ctrlport_resp_status (m_ctrlport_resp_status),
.s_ctrlport_resp_data (m_ctrlport_resp_data),
.m_ctrlport_req_wr ({unused_fpga_msbs_ctrlport_req_wr, unused_fpga_intermediate_ctrlport_req_wr, base_reg_ctrlport_req_wr, spi_master_ctrlport_req_wr}),
.m_ctrlport_req_rd ({unused_fpga_msbs_ctrlport_req_rd, unused_fpga_intermediate_ctrlport_req_rd, base_reg_ctrlport_req_rd, spi_master_ctrlport_req_rd}),
.m_ctrlport_req_addr ({unused_fpga_msbs_ctrlport_req_addr, unused_fpga_intermediate_ctrlport_req_addr, base_reg_ctrlport_req_addr, spi_master_ctrlport_req_addr}),
.m_ctrlport_req_data ({unused_fpga_msbs_ctrlport_req_data, unused_fpga_intermediate_ctrlport_req_data, base_reg_ctrlport_req_data, spi_master_ctrlport_req_data}),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack ({unused_fpga_msbs_ctrlport_resp_ack, unused_fpga_intermediate_ctrlport_resp_ack, base_reg_ctrlport_resp_ack, spi_master_ctrlport_resp_ack}),
.m_ctrlport_resp_status ({unused_fpga_msbs_ctrlport_resp_status, unused_fpga_intermediate_ctrlport_resp_status, base_reg_ctrlport_resp_status, spi_master_ctrlport_resp_status}),
.m_ctrlport_resp_data ({unused_fpga_msbs_ctrlport_resp_data, unused_fpga_intermediate_ctrlport_resp_data, base_reg_ctrlport_resp_data, spi_master_ctrlport_resp_data})
);
//---------------------------------------------------------------------------
// Targets for Requests
//---------------------------------------------------------------------------
wire [15:0] db_clock_divider;
wire [15:0] mb_clock_divider;
cpld_interface_regs #(
.BASE_ADDRESS (BASE),
.NUM_ADDRESSES (BASE_SIZE)
) cpld_interface_regs_i (
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.s_ctrlport_req_wr (base_reg_ctrlport_req_wr),
.s_ctrlport_req_rd (base_reg_ctrlport_req_rd),
.s_ctrlport_req_addr (base_reg_ctrlport_req_addr),
.s_ctrlport_req_data (base_reg_ctrlport_req_data),
.s_ctrlport_resp_ack (base_reg_ctrlport_resp_ack),
.s_ctrlport_resp_status (base_reg_ctrlport_resp_status),
.s_ctrlport_resp_data (base_reg_ctrlport_resp_data),
.mb_clock_divider (mb_clock_divider),
.db_clock_divider (db_clock_divider),
.ipass_enable (ipass_enable),
.version_info (version_info)
);
ctrlport_spi_master #(
.CPLD_ADDRESS_WIDTH (15),
.MB_CPLD_BASE_ADDRESS (MB_CPLD),
.DB_0_CPLD_BASE_ADDRESS (DB0_CPLD),
.DB_1_CPLD_BASE_ADDRESS (DB1_CPLD)
) ctrlport_spi_master_i (
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.s_ctrlport_req_wr (spi_master_ctrlport_req_wr),
.s_ctrlport_req_rd (spi_master_ctrlport_req_rd),
.s_ctrlport_req_addr (spi_master_ctrlport_req_addr),
.s_ctrlport_req_data (spi_master_ctrlport_req_data),
.s_ctrlport_resp_ack (spi_master_ctrlport_resp_ack),
.s_ctrlport_resp_status (spi_master_ctrlport_resp_status),
.s_ctrlport_resp_data (spi_master_ctrlport_resp_data),
.ss (ss),
.sclk (sclk),
.mosi (mosi),
.miso (miso),
.mb_clock_divider (mb_clock_divider),
.db_clock_divider (db_clock_divider)
);
//---------------------------------------------------------------------------
// Invalid target address spaces
//---------------------------------------------------------------------------
ctrlport_terminator #(
.START_ADDRESS (BASE + BASE_SIZE),
.LAST_ADDRESS (MB_CPLD-1)
) ctrlport_terminator_intermediate (
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.s_ctrlport_req_wr (unused_fpga_intermediate_ctrlport_req_wr),
.s_ctrlport_req_rd (unused_fpga_intermediate_ctrlport_req_rd),
.s_ctrlport_req_addr (unused_fpga_intermediate_ctrlport_req_addr),
.s_ctrlport_req_data (unused_fpga_intermediate_ctrlport_req_data),
.s_ctrlport_resp_ack (unused_fpga_intermediate_ctrlport_resp_ack),
.s_ctrlport_resp_status (unused_fpga_intermediate_ctrlport_resp_status),
.s_ctrlport_resp_data (unused_fpga_intermediate_ctrlport_resp_data)
);
ctrlport_terminator #(
.START_ADDRESS (DB1_CPLD + DB1_CPLD_SIZE),
.LAST_ADDRESS (2**CTRLPORT_ADDR_W-1)
) ctrlport_terminator_msbs (
.ctrlport_clk (ctrlport_clk),
.ctrlport_rst (ctrlport_rst),
.s_ctrlport_req_wr (unused_fpga_msbs_ctrlport_req_wr),
.s_ctrlport_req_rd (unused_fpga_msbs_ctrlport_req_rd),
.s_ctrlport_req_addr (unused_fpga_msbs_ctrlport_req_addr),
.s_ctrlport_req_data (unused_fpga_msbs_ctrlport_req_data),
.s_ctrlport_resp_ack (unused_fpga_msbs_ctrlport_resp_ack),
.s_ctrlport_resp_status (unused_fpga_msbs_ctrlport_resp_status),
.s_ctrlport_resp_data (unused_fpga_msbs_ctrlport_resp_data)
);
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="PL_CPLD_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <info>
// This register map is available from the PS via AXI and MPM endpoint.
// Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.
// </info>
// <group name="PL_CPLD_WINDOWS">
// <window name="BASE" offset="0x0" size="0x40" targetregmap="CPLD_INTERFACE_REGMAP"/>
// <window name="MB_CPLD" offset="0x8000" size="0x8000" targetregmap="MB_CPLD_PL_REGMAP">
// <info>
// All registers of the MB CPLD (PL part).
// </info>
// </window>
// <window name="DB0_CPLD" offset="0x10000" size="0x8000">
// <info>
// All registers of the first DB CPLD. Register map will be added later on.
// </info>
// </window>
// <window name="DB1_CPLD" offset="0x18000" size="0x8000">
// <info>
// All registers of the second DB CPLD. Register map will be added later on.
// </info>
// </window>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld_interface_regs.v
+285
View File
@@ -0,0 +1,285 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: cpld_interface_regs
//
// Description:
//
// Basic registers to inform software about version and capabilities.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers.
// NUM_ADDRESSES : Number of bytes of address space to use.
//
`default_nettype none
module cpld_interface_regs #(
parameter BASE_ADDRESS = 0,
parameter NUM_ADDRESSES = 128
) (
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
// Configuration to the SPI master
output wire [15:0] mb_clock_divider,
output wire [15:0] db_clock_divider,
output reg ipass_enable = 1'b0,
// Version (Constant)
output wire [95:0] version_info
);
`include "regmap/cpld_interface_regmap_utils.vh"
`include "regmap/versioning_regs_regmap_utils.vh"
`include "regmap/versioning_utils.vh"
`include "../../lib/rfnoc/core/ctrlport.vh"
//----------------------------------------------------------
// Address calculation
//----------------------------------------------------------
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
//----------------------------------------------------------
// Static variables
//----------------------------------------------------------
localparam SIGNATURE_VALUE = 32'hCB1D1FAC;
//----------------------------------------------------------
// Internal registers
//----------------------------------------------------------
reg [SCRATCH_REGISTER_SIZE-1:0] scratch_reg;
reg [MB_DIVIDER_SIZE-1:0] mb_divider_reg = 2;
reg [DB_DIVIDER_SIZE-1:0] db_divider_reg = 5;
//----------------------------------------------------------
// Assign configuration signals
//----------------------------------------------------------
assign mb_clock_divider = mb_divider_reg;
assign db_clock_divider = db_divider_reg;
//----------------------------------------------------------
// Handling of ControlPort requests
//----------------------------------------------------------
always @(posedge ctrlport_clk) begin
// Reset internal registers and responses
if (ctrlport_rst) begin
scratch_reg <= 0;
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_data <= {32{1'bx}};
s_ctrlport_resp_status <= {2{1'bx}};
end else begin
// Write requests
if (s_ctrlport_req_wr) begin
// Always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {32{1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + SCRATCH_REGISTER: begin
scratch_reg <= s_ctrlport_req_data;
end
BASE_ADDRESS + IPASS_CONTROL: begin
ipass_enable <= s_ctrlport_req_data[IPASS_ENABLE_TRANSFER];
end
BASE_ADDRESS + MOTHERBOARD_CPLD_DIVIDER: begin
mb_divider_reg <= s_ctrlport_req_data[MB_DIVIDER_MSB:MB_DIVIDER];
end
BASE_ADDRESS + DAUGHTERBOARD_CPLD_DIVIDER: begin
db_divider_reg <= s_ctrlport_req_data[DB_DIVIDER_MSB:DB_DIVIDER];
end
// Error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// Read request
end else if (s_ctrlport_req_rd) begin
// Default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + SIGNATURE_REGISTER: begin
s_ctrlport_resp_data <= SIGNATURE_VALUE;
end
BASE_ADDRESS + SCRATCH_REGISTER: begin
s_ctrlport_resp_data <= scratch_reg;
end
BASE_ADDRESS + IPASS_CONTROL: begin
s_ctrlport_resp_data <= 32'h0;
s_ctrlport_resp_data[IPASS_ENABLE_TRANSFER] <= ipass_enable;
end
BASE_ADDRESS + MOTHERBOARD_CPLD_DIVIDER: begin
s_ctrlport_resp_data <= {{(CTRLPORT_DATA_W - MB_DIVIDER_SIZE){1'b0}}, mb_divider_reg};
end
BASE_ADDRESS + DAUGHTERBOARD_CPLD_DIVIDER: begin
s_ctrlport_resp_data <= {{(CTRLPORT_DATA_W - DB_DIVIDER_SIZE){1'b0}}, db_divider_reg};
end
// Error on undefined address
default: begin
s_ctrlport_resp_data <= {32{1'bx}};
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// No request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
//----------------------------------------------------------
// Version Info
//----------------------------------------------------------
// Version metadata. Constants come from auto-generated file
// versioning_regs_regmap_utils.vh.
assign version_info = build_component_versions(
CPLD_IFC_VERSION_LAST_MODIFIED_TIME,
build_version(
CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR,
CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR,
CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
),
build_version(
CPLD_IFC_CURRENT_VERSION_MAJOR,
CPLD_IFC_CURRENT_VERSION_MINOR,
CPLD_IFC_CURRENT_VERSION_BUILD
)
);
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="VERSIONING_REGS_REGMAP">
// <group name="VERSIONING_CONSTANTS">
// <enumeratedtype name="CPLD_IFC_VERSION" showhex="true">
// <info>
// CPLD interface module.{BR/}
// For guidance on when to update these revision numbers,
// please refer to the register map documentation accordingly:
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="CPLD_IFC_CURRENT_VERSION_MAJOR" integer="2"/>
// <value name="CPLD_IFC_CURRENT_VERSION_MINOR" integer="0"/>
// <value name="CPLD_IFC_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="2"/>
// <value name="CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="CPLD_IFC_VERSION_LAST_MODIFIED_TIME" integer="0x21011809"/>
// </enumeratedtype>
// </group>
//</regmap>
//
//<regmap name="CPLD_INTERFACE_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="CPLD_INTERFACE_REGS">
// <info>
// Basic registers containing version and capabilities information.
// </info>
//
// <register name="SIGNATURE_REGISTER" offset="0x00" writable="false" size="32">
// <info>Contains the product's signature.</info>
// <bitfield name="PRODUCT_SIGNATURE" range="31..0">
// <info>fixed value 0xCB1D1FAC</info>
// </bitfield>
// </register>
//
// <register name="SCRATCH_REGISTER" offset="0x0C" size="32">
// <info>Read/write register for general software use.</info>
// </register>
// </group>
//
// <group name="IPASS_REGS">
// <register name="IPASS_CONTROL" offset="0x10" size="32">
// <bitfield name="IPASS_ENABLE_TRANSFER" range="0">
// <info>
// If 1 enables the forwarding of iPass cable present signal to MB CPLD
// using ctrlport requests. On change from 0 to 1 the current status is
// transferred to the MB CPLD via SPI ctrlport request initially.
// </info>
// </bitfield>
// </register>
// </group>
//
// <group name="CPLD_SPI_CONTROL_REGS">
// <info>
// Registers to control the SPI clock frequency of the CPLD interfaces.
// The resulting clock frequency is calculated by <math><mrow><mfrac><mrow><msub><mi>f</mi><mrow><mi>PRC</mi></mrow></msub></mrow><mrow><mn>2</mn><mrow><mo form="prefix">(</mo><mo>divider</mi><mo>+</mo><mn>1</mn><mo form="postfix">)</mo></mrow></mrow></mfrac></mrow></math>.
// <br>
// Note that the PLL Reference Clock (PRC) is depending on the RF clocks.
// </info>
//
// <register name="MOTHERBOARD_CPLD_DIVIDER" offset="0x20" size="32">
// <info>
// Clock divider used for SPI transactions targeting the MB CPLD.<br/>
// Minimum required value is 2.
// </info>
// <bitfield name="MB_DIVIDER" range="15..0" initialvalue="2">
// <info>Divider value</info>
// </bitfield>
// </register>
//
// <register name="DAUGHTERBOARD_CPLD_DIVIDER" offset="0x24" size="32">
// <info>
// Clock divider used for SPI transactions targeting any of the DB CPLDs.<br/>
// Minimum required value is 5.
// </info>
// <bitfield name="DB_DIVIDER" range="15..0" initialvalue="5">
// <info>Divider value</info>
// </bitfield>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ctrlport_spi_master.v
+243
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_spi_master
//
// Description:
//
// This block transfers a control port request via SPI. The request format on
// SPI is defined as:
//
// Write request:
// 1'b1 = write, 15 bit address, 32 bit data (MOSI), 8 bit processing gap,
// 5 bit padding, 1 bit ack, 2 bit status
//
// Read request:
// 1'b0 = read, 15 bit address, 8 bit processing gap, 32 bit data (MISO),
// 5 bit padding, 1 bit ack, 2 bit status
//
// Parameters:
//
// CPLD_ADDRESS_WIDTH : Number of address bits to allocate to one CPLD
// register map.
// MB_CPLD_BASE_ADDRESS : Base address for the motherboard CPLD.
// DB_0_CPLD_BASE_ADDRESS : Base address for the first daughterboard CPLD.
// DB_1_CPLD_BASE_ADDRESS : Base address for the second daughterboard CPLD.
//
`default_nettype none
module ctrlport_spi_master #(
parameter CPLD_ADDRESS_WIDTH = 15,
parameter MB_CPLD_BASE_ADDRESS = 20'h8000,
parameter DB_0_CPLD_BASE_ADDRESS = 20'h10000,
parameter DB_1_CPLD_BASE_ADDRESS = 20'h18000
) (
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack = 1'b0,
output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
output reg [31:0] s_ctrlport_resp_data = 32'b0,
// SPI
output wire [1:0] ss,
output wire sclk,
output wire mosi,
input wire miso,
// Configuration from register interface
input wire [15:0] mb_clock_divider,
input wire [15:0] db_clock_divider
);
`include "../../lib/rfnoc/core/ctrlport.vh"
// Registers / wires for SPI core communication
reg [31:0] set_data = 0;
reg [ 7:0] set_addr = 0;
reg set_stb = 1'b0;
wire [63:0] readback;
wire readback_stb;
//---------------------------------------------------------------------------
// Address calculation
//---------------------------------------------------------------------------
// Define configuration for the address calculation
localparam [19:0] BASE_ADDRESS_MASK = {20{1'b1}} << CPLD_ADDRESS_WIDTH;
// Wires for saving access
wire mb_cpld_access = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == MB_CPLD_BASE_ADDRESS;
wire db_0_cpld_access = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == DB_0_CPLD_BASE_ADDRESS;
wire db_1_cpld_access = (s_ctrlport_req_addr & BASE_ADDRESS_MASK) == DB_1_CPLD_BASE_ADDRESS;
//---------------------------------------------------------------------------
// FSM to handle transfers
//---------------------------------------------------------------------------
localparam IDLE = 3'd0;
localparam SET_DIVIDER = 3'd1;
localparam WRITE_SPI_MSB = 3'd2;
localparam WRITE_SPI_LSB = 3'd3;
localparam CONFIG_TRANSFER = 3'd4;
localparam WAIT_SPI = 3'd5;
localparam DIVIDER_ADDRESS = 8'd0;
localparam CTRL_ADDRESS = 8'd1;
localparam DATA_UPPER_ADDRESS = 8'd2;
localparam DATA_LOWER_ADDRESS = 8'd3;
// Combined static configuration consisting of
// 0x4000 = in data bit latched on rising edge of sclk
// - out data launched on falling edge
// - num bits = 64
localparam CTRL_VALUE = 32'h40000000;
reg [ 2:0] state = IDLE;
reg [31:0] data_cache;
reg [19:0] address_cache;
reg wr_cache;
reg [15:0] divider;
reg [ 1:0] cs;
always @ (posedge ctrlport_clk) begin
// Moving reset to the end of the block to reduce fanout of ctrlport_rst
// Default assignments
s_ctrlport_resp_ack <= 1'b0;
set_stb <= 1'b0;
case (state)
IDLE: begin
// Requests appear
if (s_ctrlport_req_wr | s_ctrlport_req_rd) begin
// Any CPLD targeted
if (mb_cpld_access | db_0_cpld_access | db_1_cpld_access) begin
state <= CONFIG_TRANSFER;
end
end
// Select chip select and divider value
if (mb_cpld_access) begin
divider <= mb_clock_divider;
cs <= 2'b00;
end else begin
divider <= db_clock_divider;
if (db_0_cpld_access) begin
cs <= 2'b10;
end else begin
cs <= 2'b01;
end
end
// Save data and address for further steps
data_cache <= s_ctrlport_req_data;
address_cache <= s_ctrlport_req_addr;
wr_cache <= s_ctrlport_req_wr;
end
// Set slave select
CONFIG_TRANSFER: begin
state <= SET_DIVIDER;
set_stb <= 1'b1;
set_addr <= CTRL_ADDRESS;
// Slave select located in LSBs. Inverted against the desired value in
// cs register as 1 represents slave enabled in combination with
// generic IDLE value.
set_data <= CTRL_VALUE | {30'b0, ~cs};
end
// Write divider to SPI core
SET_DIVIDER: begin
state <= WRITE_SPI_LSB;
set_stb <= 1'b1;
set_addr <= DIVIDER_ADDRESS;
set_data <= {16'b0, divider};
end
// Write lower bits to SPI core (aligned to MSB)
WRITE_SPI_LSB: begin
state <= WRITE_SPI_MSB;
set_stb <= 1'b1;
set_addr <= DATA_LOWER_ADDRESS;
set_data <= {data_cache[15:0], 16'bx};
end
// Write upper bits, which triggers transaction to start
WRITE_SPI_MSB: begin
state <= WAIT_SPI;
set_stb <= 1'b1;
set_addr <= DATA_UPPER_ADDRESS;
set_data <= {wr_cache, address_cache[14:0], data_cache[31:16]};
end
// Wait for transaction to complete and translate to ctrlport response
WAIT_SPI: begin
s_ctrlport_resp_status <= readback[2] ? readback[1:0] : CTRL_STS_CMDERR;
s_ctrlport_resp_data <= wr_cache ? {CTRLPORT_DATA_W {1'b0}} : readback[39:8];
s_ctrlport_resp_ack <= readback_stb;
if (readback_stb) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
// Reset control registers only
if (ctrlport_rst) begin
state <= IDLE;
s_ctrlport_resp_ack <= 1'b0;
set_stb <= 1'b0;
end
end
//---------------------------------------------------------------------------
// SPI master
//---------------------------------------------------------------------------
simple_spi_core_64bit #(
.BASE (0),
.WIDTH (2),
.CLK_IDLE (0),
.SEN_IDLE (2'b11),
.MAX_BITS (64)
) simple_spi_core_64bit_i (
.clock (ctrlport_clk),
.reset (ctrlport_rst),
.set_stb (set_stb),
.set_addr (set_addr),
.set_data (set_data),
.readback (readback),
.readback_stb (readback_stb),
.ready (),
.sen (ss),
.sclk (sclk),
.mosi (mosi),
.miso (miso),
.debug ()
);
endmodule
`default_nettype wire
top/x400/dboards/ctrlport_byte_deserializer.v
+186
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_byte_deserializer
//
// Description:
// Slave interface of CtrlPort interface serialized as byte stream.
// See description in ctrlport_byte_serializer module for more details.
//
`default_nettype none
module ctrlport_byte_deserializer (
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
output wire m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [19:0] m_ctrlport_req_addr,
output wire [31:0] m_ctrlport_req_data,
// Response
input wire m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [31:0] m_ctrlport_resp_data,
// byte interface
input wire [ 7:0] bytestream_data_in,
input wire bytestream_valid_in,
input wire bytestream_direction,
output reg [ 7:0] bytestream_data_out = 8'b0,
output reg bytestream_valid_out = 1'b0,
output reg bytestream_output_enable = 1'b0
);
`include "../../../lib/rfnoc/core/ctrlport.vh"
//---------------------------------------------------------------
// transfer constants
//---------------------------------------------------------------
// derived from transaction specification
localparam NUM_BYTES_RX_READ = 2;
localparam NUM_BYTES_TX_READ = 5;
localparam NUM_BYTES_RX_WRITE = 6;
localparam NUM_BYTES_TX_WRITE = 1;
localparam SPI_TRANSFER_ADDRESS_WIDTH = 15;
//----------------------------------------------------------
// handle transfer
//----------------------------------------------------------
localparam INIT_RX = 2'd0;
localparam RECEIVE = 2'd1;
localparam WAIT_RESPONSE = 2'd2;
localparam SENDING = 2'd3;
// internal registers
reg [ 1:0] state = INIT_RX;
reg [NUM_BYTES_RX_WRITE*8-1:0] request_cache = {NUM_BYTES_RX_WRITE*8 {1'b0}};
reg [ NUM_BYTES_TX_READ*8-1:0] response_cache = {NUM_BYTES_TX_READ*8 {1'b0}};
reg [ 2:0] byte_counter = 3'b0;
reg transfer_complete = 1'b0;
reg write_transfer = 1'b0;
// input registers to relax input timing
reg [7:0] bytestream_data_in_reg = 8'b0;
reg bytestream_valid_in_reg = 1'b0;
reg bytestream_direction_reg = 1'b0;
always @ (posedge ctrlport_clk) begin
bytestream_data_in_reg <= bytestream_data_in;
bytestream_valid_in_reg <= bytestream_valid_in;
bytestream_direction_reg <= bytestream_direction;
end
// state machine
always @ (posedge ctrlport_clk) begin
if (ctrlport_rst) begin
state <= INIT_RX;
byte_counter <= 3'b0;
transfer_complete <= 1'b0;
bytestream_output_enable <= 1'b0;
end else begin
// default assignments
transfer_complete <= 1'b0;
// direction defined by master
bytestream_output_enable <= bytestream_direction;
bytestream_valid_out <= 1'b0;
case (state)
// additional cycle for switching to make sure valid signal is driven
// from master when being in RECEIVE state
INIT_RX: begin
byte_counter <= 3'b0;
if (bytestream_direction_reg == 0) begin
state <= RECEIVE;
end
end
// wait for reception of request from master
RECEIVE: begin
if (bytestream_valid_in_reg) begin
byte_counter <= byte_counter + 1'b1;
request_cache <= {request_cache[NUM_BYTES_RX_WRITE*8-9:0], bytestream_data_in_reg};
// capture write or read
if (byte_counter == 0) begin
write_transfer <= bytestream_data_in_reg[7];
end
// wait until request completes
if ((write_transfer && byte_counter == NUM_BYTES_RX_WRITE-1) ||
(~write_transfer && byte_counter == NUM_BYTES_RX_READ-1)) begin
transfer_complete <= 1'b1;
state <= WAIT_RESPONSE;
end
end
// Workaround for missing pull down resistor:
// Use pull up and schmitt trigger to detect FPGA reload by line going high unexpectedly
if (bytestream_direction_reg == 1) begin
state <= INIT_RX;
end
end
WAIT_RESPONSE: begin
byte_counter <= 3'b0;
if (m_ctrlport_resp_ack) begin
state <= SENDING;
if (write_transfer) begin
response_cache <= {5'b0, 1'b1, m_ctrlport_resp_status, 32'b0};
end else begin
response_cache <= {m_ctrlport_resp_data, 5'b0, 1'b1, m_ctrlport_resp_status};
end
end
//abort by host
if (bytestream_direction_reg == 0) begin
state <= INIT_RX;
end
end
SENDING: begin
bytestream_valid_out <= 1'b1;
bytestream_data_out <= response_cache[NUM_BYTES_TX_READ*8-8+:8];
response_cache <= {response_cache[NUM_BYTES_TX_READ*8-9:0], 8'b0};
byte_counter <= byte_counter + 1'b1;
// wait until request completes
if ((write_transfer && byte_counter == NUM_BYTES_TX_WRITE-1) ||
(~write_transfer && byte_counter == NUM_BYTES_TX_READ-1)) begin
state <= INIT_RX;
end
//abort by host
if (bytestream_direction_reg == 0) begin
state <= INIT_RX;
end
end
default: begin
state <= INIT_RX;
end
endcase
end
end
//----------------------------------------------------------
// assign request to ctrlport
//----------------------------------------------------------
assign m_ctrlport_req_wr = write_transfer & transfer_complete;
assign m_ctrlport_req_rd = ~write_transfer & transfer_complete;
assign m_ctrlport_req_data = request_cache[0+:CTRLPORT_DATA_W];
assign m_ctrlport_req_addr = (write_transfer) ?
// Skipping data in LSBs to get to the address for writes.
{5'b0, request_cache[CTRLPORT_DATA_W+:SPI_TRANSFER_ADDRESS_WIDTH]} :
// Full request = address of 2 bytes in LSBs.
{5'b0, request_cache[0+:SPI_TRANSFER_ADDRESS_WIDTH]};
endmodule
`default_nettype wire
top/x400/dboards/ctrlport_byte_serializer.v
+228
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_byte_serializer
//
// Description:
// Serializes CtrlPort requests into a byte stream.
//
// The serialized data is similar to an AXI4-Streaming interface with one byte
// per clock cycle and a valid signal. Direction controls the current transmission
// direction. 0 = Master to Slave, 1 = Slave to Master, where this module is the
// master. Direction is always present in direction master to slave where the
// other signals valid and data can be shared on a tri-state bus.
//
// The transmission is defined as described below. The bytes are transmitted MSB
// first.
// Write request:
// 1'b1 = write, 15 bit address, 32 bit data (MOSI) = 6 bytes request
// 5 bit padding, 1 bit ack, 2 bit status = 1 byte response
// Read request:
// 1'b0 = read, 15 bit address = 2 bytes request
// 32 bit data, 5 bit padding, 1 bit ack, 2 bit status = 5 bytes response
//
// When sharing valid and data signal lines between master and slave the
// timing is defined as:
//
// clk __/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\__
// direction _______________________/-----------------\____________
// master output enable _____/-----------------\______________________________
// slave output enable _____________________________/-----------------\______
// valid & data zzzzz| Master driven | zzz | Slave driven | zzzzz
// transaction <--- Request ---><--- Response --->
//
// The slave should use the direction signal to derive it's own output enable
// leaving the master the option to terminate the transaction.
// On switch from slave to master the direction has to be changed at least
// one clock cycle before enabling the master output enable to avoid driving the
// bus from two sources.
//
`default_nettype none
module ctrlport_byte_serializer (
// Clock and Reset
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack = 1'b0,
output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
output reg [31:0] s_ctrlport_resp_data = 32'b0,
// GPIO interface
input wire [ 7:0] bytestream_data_in,
input wire bytestream_valid_in,
output reg [ 7:0] bytestream_data_out = 8'b0,
output reg bytestream_valid_out = 1'b0,
output reg bytestream_direction = 1'b0,
output reg bytestream_output_enable = 1'b1
);
`include "../../../lib/rfnoc/core/ctrlport.vh"
//---------------------------------------------------------------
// transfer constants
//---------------------------------------------------------------
// derived from the transaction format (see description above)
localparam NUM_BYTES_TX_READ = 2;
localparam NUM_BYTES_RX_READ = 5;
localparam NUM_BYTES_TX_WRITE = 6;
localparam NUM_BYTES_RX_WRITE = 1;
localparam TIMEOUT_COUNTER_WIDTH = 6;
//----------------------------------------------------------
// FSM to handle transfers
//----------------------------------------------------------
localparam IDLE = 3'd0;
localparam SENDING = 3'd1;
localparam INIT_RX = 3'd2;
localparam DIR_SWITCH = 3'd3;
localparam DIR_SWITCH_DLY = 3'd4;
localparam RECEIVING = 3'd5;
localparam ACK = 3'd6;
localparam TIMEOUT = 3'd7;
// input registers to relax input timing
reg [7:0] bytestream_data_in_reg = 8'b0;
reg bytestream_valid_in_reg = 1'b0;
always @ (posedge ctrlport_clk) begin
bytestream_data_in_reg <= bytestream_data_in;
bytestream_valid_in_reg <= bytestream_valid_in;
end
// internal registers
reg [ 2:0] state = IDLE;
reg [NUM_BYTES_TX_WRITE*8-1:0] request_cache = {NUM_BYTES_TX_WRITE*8{1'b0}};
reg [ NUM_BYTES_RX_READ*8-1:0] response_cache = {NUM_BYTES_RX_READ*8{1'b0}};
reg [ 2:0] byte_counter = 3'b0;
reg write_transfer = 1'b0;
reg [TIMEOUT_COUNTER_WIDTH-1:0] timeout_counter = {TIMEOUT_COUNTER_WIDTH {1'b0}};
always @ (posedge ctrlport_clk) begin
if (ctrlport_rst) begin
state <= IDLE;
bytestream_valid_out <= 1'b0;
byte_counter <= 3'b0;
bytestream_direction <= 1'b0;
bytestream_output_enable <= 1'b1;
s_ctrlport_resp_ack <= 1'b0;
end else begin
case (state)
IDLE: begin
// reset values from previous states
s_ctrlport_resp_ack <= 1'b0;
bytestream_valid_out <= 1'b0;
bytestream_output_enable <= 1'b1;
byte_counter <= 3'b0;
timeout_counter <= {TIMEOUT_COUNTER_WIDTH {1'b0}};
// start transmission on read or write
if (s_ctrlport_req_rd || s_ctrlport_req_wr) begin
state <= SENDING;
request_cache <= {s_ctrlport_req_wr, s_ctrlport_req_addr[14:0], s_ctrlport_req_data};
write_transfer <= s_ctrlport_req_wr;
end
end
// send as many bytes as required for read / write
SENDING: begin
bytestream_data_out <= request_cache[NUM_BYTES_TX_WRITE*8-8+:8];
request_cache <= {request_cache[NUM_BYTES_TX_WRITE*8-9:0], 8'b0};
bytestream_valid_out <= 1'b1;
byte_counter <= byte_counter + 1'b1;
if ((write_transfer && byte_counter == NUM_BYTES_TX_WRITE-1) ||
(~write_transfer && byte_counter == NUM_BYTES_TX_READ-1)) begin
state <= INIT_RX;
end
end
// first cycle for switching to make sure valid signal is driven
// from slave when being in RECEIVING state
INIT_RX: begin
state <= DIR_SWITCH;
bytestream_direction <= 1'b1;
bytestream_output_enable <= 1'b0;
bytestream_valid_out <= 1'b0;
byte_counter <= 3'b0;
end
// second switching cycle to let CPLD load the lines based on direction
DIR_SWITCH: begin
state <= DIR_SWITCH_DLY;
end
// third switching cycle to compensate data input register
DIR_SWITCH_DLY: begin
state <= RECEIVING;
end
// wait for response to be received
// immediately change direction after successful reception to have one
// clock cycle of pause to avoid double driving the bus
RECEIVING: begin
timeout_counter <= timeout_counter + 1;
if (bytestream_valid_in_reg) begin
byte_counter <= byte_counter + 1'b1;
response_cache = {response_cache[NUM_BYTES_RX_READ*8-9:0], bytestream_data_in_reg};
if ((write_transfer && byte_counter == NUM_BYTES_RX_WRITE-1) ||
(~write_transfer && byte_counter == NUM_BYTES_RX_READ-1)) begin
state <= ACK;
bytestream_direction <= 1'b0;
end
end
if (timeout_counter == {TIMEOUT_COUNTER_WIDTH {1'b1}}) begin
state <= TIMEOUT;
bytestream_direction <= 1'b0;
end
end
// issue ctrlport response
ACK: begin
state <= IDLE;
s_ctrlport_resp_ack <= 1'b1;
// status based on received ack
s_ctrlport_resp_status <= response_cache[2] ? response_cache[1:0] : CTRL_STS_CMDERR;
if (write_transfer) begin
s_ctrlport_resp_data <= 32'b0;
end else begin
s_ctrlport_resp_data <= response_cache[39:8];
end
end
TIMEOUT: begin
state <= IDLE;
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
s_ctrlport_resp_data <= 32'b0;
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
`default_nettype wire
top/x400/dboards/db_gpio_interface.v
+323
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: db_gpio_interface
//
// Description:
// Interface for GPIO interface towards daughterboards.
//
// A ControlPort interface is serialized into bytes along with a valid signal.
// The ControlPort supports write requests only. Byte enables are not supported.
// There is support for timed commands.
// Furthermore there are 4 state wires towards the DB. Ensure an appropriate
// hold time on the states as the transmission happens in pll_ref_clk, which is
// slower than radio_clk. Pulses of e.g. just a single clock cycle may not get
// transferred to the DB.
//
// The 20 available GPIO lines are assigned with
// - 5x empty
// - bytestream direction
// - bytestream valid
// - bytestream data (8 bits)
// - 1x empty
// - db_state (4 bits)
//
`default_nettype none
module db_gpio_interface (
// Clocks and reset
input wire radio_clk,
input wire pll_ref_clk,
// DB state lines (domain: radio_clk)
input wire [ 3:0] db_state,
// time interfaces (domain: radio_clk)
input wire [63:0] radio_time,
input wire radio_time_stb,
input wire [ 3:0] time_ignore_bits,
// Request (domain: radio_clk)
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
input wire [ 3:0] s_ctrlport_req_byte_en,
input wire s_ctrlport_req_has_time,
input wire [63:0] s_ctrlport_req_time,
// Response (domain: radio_clk)
output wire s_ctrlport_resp_ack,
output wire [ 1:0] s_ctrlport_resp_status,
output wire [31:0] s_ctrlport_resp_data,
// GPIO interface (domain: pll_ref_clk)
input wire [19:0] gpio_in,
output wire [19:0] gpio_out,
output wire [19:0] gpio_out_en,
// Version (Constant)
output wire [95:0] version_info
);
`include "../regmap/versioning_regs_regmap_utils.vh"
`include "../regmap/versioning_utils.vh"
//----------------------------------------------------------------------------
// Timed command processing
//----------------------------------------------------------------------------
wire [19:0] ctrlport_timed_req_addr;
wire [31:0] ctrlport_timed_req_data;
wire ctrlport_timed_req_rd;
wire ctrlport_timed_req_wr;
wire ctrlport_timed_resp_ack;
reg [31:0] ctrlport_timed_resp_data = 0;
reg [ 1:0] ctrlport_timed_resp_status = 0;
ctrlport_timer #(
.EXEC_LATE_CMDS(1)
) ctrlport_timer_i (
.clk (radio_clk),
.rst (ctrlport_rst),
.time_now (radio_time),
.time_now_stb (radio_time_stb),
.time_ignore_bits (time_ignore_bits),
.s_ctrlport_req_wr (s_ctrlport_req_wr),
.s_ctrlport_req_rd (s_ctrlport_req_rd),
.s_ctrlport_req_addr (s_ctrlport_req_addr),
.s_ctrlport_req_data (s_ctrlport_req_data),
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
.s_ctrlport_req_time (s_ctrlport_req_time),
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
.s_ctrlport_resp_status (s_ctrlport_resp_status),
.s_ctrlport_resp_data (s_ctrlport_resp_data),
.m_ctrlport_req_wr (ctrlport_timed_req_wr),
.m_ctrlport_req_rd (ctrlport_timed_req_rd),
.m_ctrlport_req_addr (ctrlport_timed_req_addr),
.m_ctrlport_req_data (ctrlport_timed_req_data),
.m_ctrlport_req_byte_en (),
.m_ctrlport_resp_ack (ctrlport_timed_resp_ack),
.m_ctrlport_resp_status (ctrlport_timed_resp_status),
.m_ctrlport_resp_data (ctrlport_timed_resp_data)
);
//----------------------------------------------------------------------------
// Clock domain crossing (radio_clk -> pll_ref_clk)
//----------------------------------------------------------------------------
// Radio_clk is derived from pll_ref_clk by an integer multiplier and
// originate from the same PLL.
// Therefore the clock crossing can be achieved by using simple registers.
// Static timing analysis will be able to meet setup and hold requirements on
// them.
// holding read and write flags for multiple radio_clk cycles
reg ctrlport_timed_req_wr_hold = 1'b0;
reg ctrlport_timed_req_rd_hold = 1'b0;
reg [19:0] ctrlport_req_addr_prc = 20'b0;
reg [31:0] ctrlport_req_data_prc = 32'b0;
reg ctrlport_req_rd_prc = 1'b0;
reg ctrlport_req_wr_prc = 1'b0;
wire ctrlport_resp_ack_prc;
wire [31:0] ctrlport_resp_data_prc;
wire [ 1:0] ctrlport_resp_status_prc;
reg ctrlport_req_rd_fall = 1'b0;
reg ctrlport_req_wr_fall = 1'b0;
reg [31:0] ctrlport_resp_data_fall = 32'b0;
reg [ 1:0] ctrlport_resp_status_fall = 2'b0;
reg ctrlport_resp_ack_fall = 1'b0;
// Retime signals to falling edge of radio_clk.
// Because radio_clk is more heavily loaded than pll_ref_clk, it arrives at
// the FF's later, which leads to hold time violations when moving signals
// from pll_ref_clk to radio_clk. By sampling on the falling edge of
// radio_clk, we provide (nominally) half a radio_clk period of hold, while
// reducing setup time by half. The late arrival of radio_clk adds back some
// of the lost setup margin.
always @(negedge radio_clk) begin
ctrlport_req_rd_fall <= ctrlport_req_rd_prc;
ctrlport_req_wr_fall <= ctrlport_req_wr_prc;
ctrlport_resp_ack_fall <= ctrlport_resp_ack_prc;
ctrlport_resp_status_fall <= ctrlport_resp_status_prc;
ctrlport_resp_data_fall <= ctrlport_resp_data_prc;
end
always @(posedge radio_clk) begin
if (ctrlport_req_wr_fall) begin
ctrlport_timed_req_wr_hold <= 1'b0;
end else if (ctrlport_timed_req_wr) begin
ctrlport_timed_req_wr_hold <= 1'b1;
end
if (ctrlport_req_rd_fall) begin
ctrlport_timed_req_rd_hold <= 1'b0;
end else if (ctrlport_timed_req_rd) begin
ctrlport_timed_req_rd_hold <= 1'b1;
end
// capture request address and data
if (ctrlport_timed_req_wr || ctrlport_timed_req_rd) begin
ctrlport_req_addr_prc <= ctrlport_timed_req_addr;
ctrlport_req_data_prc <= ctrlport_timed_req_data;
end
end
// capture extended flags in pll_ref_clk domain
always @(posedge pll_ref_clk) begin
ctrlport_req_wr_prc <= ctrlport_timed_req_wr_hold;
ctrlport_req_rd_prc <= ctrlport_timed_req_rd_hold;
end
// search for rising edge in response
reg [1:0] ctrlport_timed_ack_reg = 2'b0;
always @(posedge radio_clk) begin
ctrlport_timed_ack_reg = {ctrlport_timed_ack_reg[0], ctrlport_resp_ack_fall};
end
assign ctrlport_timed_resp_ack = ctrlport_timed_ack_reg[0] & ~ctrlport_timed_ack_reg[1];
// capture response data
always @(posedge radio_clk) begin
if (ctrlport_resp_ack_fall) begin
ctrlport_timed_resp_status <= ctrlport_resp_status_fall;
ctrlport_timed_resp_data <= ctrlport_resp_data_fall;
end
end
// transfer state lines
reg [3:0] db_state_prc = 4'b0;
reg [3:0] db_state_prc_fe = 4'b0;
always @(posedge pll_ref_clk) begin
db_state_prc <= db_state;
end
always @(negedge pll_ref_clk) begin
db_state_prc_fe <= db_state_prc;
end
// transfer reset
reg ctrlport_rst_hold = 1'b0;
reg ctrlport_rst_prc = 1'b0;
reg ctrlport_rst_fall = 1'b0;
always @(posedge radio_clk) begin
if (ctrlport_rst) begin
ctrlport_rst_hold <= 1'b1;
end else if (ctrlport_rst_fall) begin
ctrlport_rst_hold <= 1'b0;
end
end
always @(posedge pll_ref_clk) begin
ctrlport_rst_prc <= ctrlport_rst_hold;
end
always @(negedge radio_clk) begin
ctrlport_rst_fall <= ctrlport_rst_prc;
end
//----------------------------------------------------------------------------
// Ctrlport serializer
//----------------------------------------------------------------------------
wire [7:0] bytestream_data_in;
wire [7:0] bytestream_data_out;
wire bytestream_direction;
wire bytestream_output_enable;
wire bytestream_valid_in;
wire bytestream_valid_out;
ctrlport_byte_serializer serializer_i (
.ctrlport_clk (pll_ref_clk),
.ctrlport_rst (ctrlport_rst_prc),
.s_ctrlport_req_wr (ctrlport_req_wr_prc),
.s_ctrlport_req_rd (ctrlport_req_rd_prc),
.s_ctrlport_req_addr (ctrlport_req_addr_prc),
.s_ctrlport_req_data (ctrlport_req_data_prc),
.s_ctrlport_resp_ack (ctrlport_resp_ack_prc),
.s_ctrlport_resp_status (ctrlport_resp_status_prc),
.s_ctrlport_resp_data (ctrlport_resp_data_prc),
.bytestream_data_in (bytestream_data_in),
.bytestream_valid_in (bytestream_valid_in),
.bytestream_data_out (bytestream_data_out),
.bytestream_valid_out (bytestream_valid_out),
.bytestream_direction (bytestream_direction),
.bytestream_output_enable (bytestream_output_enable)
);
// IOB registers to drive data on the falling edge
reg [7:0] bytestream_data_out_fe;
reg bytestream_direction_fe;
reg bytestream_output_enable_fe;
reg bytestream_valid_out_fe;
// Signals are shifted into a falling edge domain to help meet
// hold requirements at CPLD
always @(negedge pll_ref_clk) begin
if (ctrlport_rst_prc) begin
bytestream_data_out_fe <= 8'b0;
bytestream_valid_out_fe <= 1'b0;
bytestream_direction_fe <= 1'b0;
bytestream_output_enable_fe <= 1'b1;
end else begin
bytestream_data_out_fe <= bytestream_data_out;
bytestream_valid_out_fe <= bytestream_valid_out;
bytestream_direction_fe <= bytestream_direction;
bytestream_output_enable_fe <= bytestream_output_enable;
end
end
//----------------------------------------------------------------------------
// wire assignment
//----------------------------------------------------------------------------
// 5 unused, 10 used, 1 unused and 4 used signals
assign gpio_out = {5'b0, bytestream_direction_fe, bytestream_valid_out_fe, bytestream_data_out_fe, 1'b0, db_state_prc_fe};
assign gpio_out_en = {5'b0, 1'b1, {9 {bytestream_output_enable_fe}}, 1'b0, {4 {1'b1}} };
assign bytestream_valid_in = gpio_in[13];
assign bytestream_data_in = gpio_in[12:5];
//----------------------------------------------------------------------------
// version_info
//----------------------------------------------------------------------------
// Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh
assign version_info = build_component_versions(
DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME,
build_version(
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR,
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR,
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD),
build_version(
DB_GPIO_IFC_CURRENT_VERSION_MAJOR,
DB_GPIO_IFC_CURRENT_VERSION_MINOR,
DB_GPIO_IFC_CURRENT_VERSION_BUILD));
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="VERSIONING_REGS_REGMAP">
// <group name="VERSIONING_CONSTANTS">
// <enumeratedtype name="DB_GPIO_IFC_VERSION" showhex="true">
// <info>
// Daughterboard GPIO interface.{BR/}
// For guidance on when to update these revision numbers,
// please refer to the register map documentation accordingly:
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MAJOR" integer="1"/>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MINOR" integer="0"/>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME" integer="0x20110616"/>
// </enumeratedtype>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/dboards/db_gpio_reordering.v
+108
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: db_gpio_reordering
//
// Description:
// Reorders the GPIO wires towards the DB CPLDs in a common way for DB 0 and 1.
//
// The digital daughterboard connector has 120 pins [A-F][1-20].
// The numbering on the motherboard traces do not match for daughterboard 0 and 1.
// This module orders the FPGA outputs MSB first and connects it to the DB
// connection with increasing letter and increasing number.
// For DB 0 this results in:
// FPGA Bit 19 = A7 (trace: DB0/1_GPIO[19])
// FPGA Bit 18 = A8 (trace: DB0/1_GPIO[17])
// ...
// FPGA Bit 0 = C19 (trace: DB0/1_GPIO[12])
// This enables usages of the same daughterboard CPLD image on both connectors.
//
`default_nettype none
module db_gpio_reordering (
// 20 bit internal interface
output wire [19:0] db0_gpio_in_int,
input wire [19:0] db0_gpio_out_int,
input wire [19:0] db0_gpio_out_en_int,
output wire [19:0] db1_gpio_in_int,
input wire [19:0] db1_gpio_out_int,
input wire [19:0] db1_gpio_out_en_int,
// 20 bit external interface
input wire [19:0] db0_gpio_in_ext,
output wire [19:0] db0_gpio_out_ext,
output wire [19:0] db0_gpio_out_en_ext,
input wire [19:0] db1_gpio_in_ext,
output wire [19:0] db1_gpio_out_ext,
output wire [19:0] db1_gpio_out_en_ext
);
//port indexes
localparam ENTRY_BITWIDTH = 5;
localparam NUM_ENTRIES = 20;
localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT0_MAPPING = {
5'd 19,
5'd 17,
5'd 0,
5'd 14,
5'd 15,
5'd 10,
5'd 4,
5'd 5,
5'd 16,
5'd 18,
5'd 8,
5'd 6,
5'd 1,
5'd 9,
5'd 2,
5'd 3,
5'd 11,
5'd 7,
5'd 13,
5'd 12 };
localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT1_MAPPING = {
5'd 10,
5'd 6,
5'd 7,
5'd 2,
5'd 3,
5'd 0,
5'd 1,
5'd 4,
5'd 8,
5'd 9,
5'd 11,
5'd 5,
5'd 13,
5'd 12,
5'd 15,
5'd 14,
5'd 19,
5'd 18,
5'd 17,
5'd 16 };
// reordering assignments
generate
genvar i;
for (i=0; i<NUM_ENTRIES; i=i+1) begin : reordering_gen
// input data
assign db0_gpio_in_int[i] = db0_gpio_in_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];
assign db1_gpio_in_int[i] = db1_gpio_in_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];
// output data
assign db0_gpio_out_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_int[i];
assign db1_gpio_out_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_int[i];
// output enable
assign db0_gpio_out_en_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_en_int[i];
assign db1_gpio_out_en_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_en_int[i];
end
endgenerate
endmodule
`default_nettype wire
top/x400/doc/X4XX_FPGA.htm
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<HTML>
<HEAD>
<title>X4XX_FPGA</title>
<FRAMESET COLS="20%,*" onload=window.frames[1].location.hash=window.location.href.split("#")[1];>
<FRAME name="leftframe" SRC="X4XX_FPGA_left.htm">
<FRAME name="rightframe" SRC="X4XX_FPGA_right.htm">
</FRAMESET>
</HEAD>
</HTML>
top/x400/doc/X4XX_FPGA_left.htm
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<html>
<head>
<meta http-equiv="Content-Type" content="text/html;charset=utf-8"/>
<style type="text/css">
body {
margin: 5px;
font-family: verdana, "Trebuchet MS", arial, helvetica, sans-serif;
font-size: 80%;
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font-family: "courier new", courier, monospace;
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font-size: 95%;
}
div.sh {
display: none;
margin-left: 15px;
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display: block;
margin-left: 15px;
}
div.nav span.pm, div.nav span.pm_2 {
color: black;
font-family: courier new, courier;
margin-right: 5px;
}
div.nav span.pm {
cursor: pointer;
}
div.nav p {
margin: 0px;
padding: 0px;
white-space: nowrap;
}
div.nav span {
cursor: pointer;
}
div.nav span.regmap {
color: #000080;
}
div.nav span.group {
color: #006000;
}
div.nav span.enum {
color: #800000;
margin-left: 10px;
}
div.nav span.register {
color: #004040;
margin-left: 10px;
}
</style>
<script type="text/javascript">
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if (sign == "nochange") return;
if ( document.getElementById )
elem = document.getElementById( id );
else if ( document.all )
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if (elem) {
elemStyle = elem.style;
if (sign=="+") {
elemStyle.display = "block"
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/*if ( elemStyle.display == "block" ) {
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} else {
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}
}
function changePm( id ) {
if ( document.getElementById )
elem = document.getElementById( id );
else if ( document.all )
elem = eval( "document.all." + id );
else
return "nochange";
var val = elem.innerHTML;
if (val == "+") {
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function pm( id ) {
var sign = changePm("pm_" + id);
toggleText("div_" + id, sign);
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var currentURL= document.URL;
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<p><span class="register" id="a_X4XX_FPGA|ARM_M_AXI_HPM0" onclick="a('X4XX_FPGA|ARM_M_AXI_HPM0');">ARM_M_AXI_HPM0</span></p>
<p><span class="register" id="a_X4XX_FPGA|ARM_S_AXI_HPC0" onclick="a('X4XX_FPGA|ARM_S_AXI_HPC0');">ARM_S_AXI_HPC0</span></p>
<p><span class="register" id="a_X4XX_FPGA|ARM_S_AXI_HPC1" onclick="a('X4XX_FPGA|ARM_S_AXI_HPC1');">ARM_S_AXI_HPC1</span></p>
<p><span class="register" id="a_X4XX_FPGA|ARM_SPI1_CS3" onclick="a('X4XX_FPGA|ARM_SPI1_CS3');">ARM_SPI1_CS3</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_AXI_HPM0_REGMAP" onclick="pm('AXI_HPM0_REGMAP');">+</span>
<span class="regmap" id="a_AXI_HPM0_REGMAP" onclick="a('AXI_HPM0_REGMAP');">AXI_HPM0_REGMAP</span>
</p> <div class="sh" id="div_AXI_HPM0_REGMAP">
<p>
<span class="pm" id="pm_AXI_HPM0_REGMAP|COMMON" onclick="pm('AXI_HPM0_REGMAP|COMMON');">+</span>
<span class="group" id="a_AXI_HPM0_REGMAP|COMMON" onclick="a('AXI_HPM0_REGMAP|COMMON');">COMMON</span>
</p>
<div class="sh" id="div_AXI_HPM0_REGMAP|COMMON">
<p><span class="register" id="a_AXI_HPM0_REGMAP|RPU" onclick="a('AXI_HPM0_REGMAP|RPU');">RPU</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|JTAG_ENGINE" onclick="a('AXI_HPM0_REGMAP|JTAG_ENGINE');">JTAG_ENGINE</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|WR" onclick="a('AXI_HPM0_REGMAP|WR');">WR</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|MPM_ENDPOINT" onclick="a('AXI_HPM0_REGMAP|MPM_ENDPOINT');">MPM_ENDPOINT</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|CORE_REGS" onclick="a('AXI_HPM0_REGMAP|CORE_REGS');">CORE_REGS</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|INT_ETH_DMA" onclick="a('AXI_HPM0_REGMAP|INT_ETH_DMA');">INT_ETH_DMA</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|INT_ETH_REGS" onclick="a('AXI_HPM0_REGMAP|INT_ETH_REGS');">INT_ETH_REGS</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|RFDC" onclick="a('AXI_HPM0_REGMAP|RFDC');">RFDC</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|RFDC_REGS" onclick="a('AXI_HPM0_REGMAP|RFDC_REGS');">RFDC_REGS</span></p>
</div>
<p>
<span class="pm" id="pm_AXI_HPM0_REGMAP|UHD_ONLY" onclick="pm('AXI_HPM0_REGMAP|UHD_ONLY');">+</span>
<span class="group" id="a_AXI_HPM0_REGMAP|UHD_ONLY" onclick="a('AXI_HPM0_REGMAP|UHD_ONLY');">UHD_ONLY</span>
</p>
<div class="sh" id="div_AXI_HPM0_REGMAP|UHD_ONLY">
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_0_0" onclick="a('AXI_HPM0_REGMAP|QSFP_0_0');">QSFP_0_0</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_0_1" onclick="a('AXI_HPM0_REGMAP|QSFP_0_1');">QSFP_0_1</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_0_2" onclick="a('AXI_HPM0_REGMAP|QSFP_0_2');">QSFP_0_2</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_0_3" onclick="a('AXI_HPM0_REGMAP|QSFP_0_3');">QSFP_0_3</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_1_0" onclick="a('AXI_HPM0_REGMAP|QSFP_1_0');">QSFP_1_0</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_1_1" onclick="a('AXI_HPM0_REGMAP|QSFP_1_1');">QSFP_1_1</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_1_2" onclick="a('AXI_HPM0_REGMAP|QSFP_1_2');">QSFP_1_2</span></p>
<p><span class="register" id="a_AXI_HPM0_REGMAP|QSFP_1_3" onclick="a('AXI_HPM0_REGMAP|QSFP_1_3');">QSFP_1_3</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_MB_CPLD_PS_REGMAP" onclick="pm('MB_CPLD_PS_REGMAP');">+</span>
<span class="regmap" id="a_MB_CPLD_PS_REGMAP" onclick="a('MB_CPLD_PS_REGMAP');">MB_CPLD_PS_REGMAP</span>
</p> <div class="sh" id="div_MB_CPLD_PS_REGMAP">
<p>
<span class="pm" id="pm_MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS" onclick="pm('MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS');">+</span>
<span class="group" id="a_MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS" onclick="a('MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS');">MB_CPLD_PS_WINDOWS</span>
</p>
<div class="sh" id="div_MB_CPLD_PS_REGMAP|MB_CPLD_PS_WINDOWS">
<p><span class="register" id="a_MB_CPLD_PS_REGMAP|PS_REGISTERS" onclick="a('MB_CPLD_PS_REGMAP|PS_REGISTERS');">PS_REGISTERS</span></p>
<p><span class="register" id="a_MB_CPLD_PS_REGMAP|RECONFIG" onclick="a('MB_CPLD_PS_REGMAP|RECONFIG');">RECONFIG</span></p>
<p><span class="register" id="a_MB_CPLD_PS_REGMAP|POWER_REGISTERS" onclick="a('MB_CPLD_PS_REGMAP|POWER_REGISTERS');">POWER_REGISTERS</span></p>
</div>
<p>
<span class="pm" id="pm_MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS" onclick="pm('MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS');">+</span>
<span class="group" id="a_MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS" onclick="a('MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS');">PS_SPI_ENDPOINTS</span>
</p>
<div class="sh" id="div_MB_CPLD_PS_REGMAP|PS_SPI_ENDPOINTS">
<p><span class="enum" id="a_MB_CPLD_PS_REGMAP|SPI_ENDPOINT" onclick="a('MB_CPLD_PS_REGMAP|SPI_ENDPOINT');">enum SPI_ENDPOINT</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_CMAC_REGMAP" onclick="pm('CMAC_REGMAP');">+</span>
<span class="regmap" id="a_CMAC_REGMAP" onclick="a('CMAC_REGMAP');">CMAC_REGMAP</span>
</p> <div class="sh" id="div_CMAC_REGMAP">
<p>
<span class="pm" id="pm_CMAC_REGMAP|XILINX_CMAC_REGISTERS" onclick="pm('CMAC_REGMAP|XILINX_CMAC_REGISTERS');">+</span>
<span class="group" id="a_CMAC_REGMAP|XILINX_CMAC_REGISTERS" onclick="a('CMAC_REGMAP|XILINX_CMAC_REGISTERS');">XILINX_CMAC_REGISTERS</span>
</p>
<div class="sh" id="div_CMAC_REGMAP|XILINX_CMAC_REGISTERS">
</div>
</div>
<p>
<span class="pm" id="pm_CONSTANTS_REGMAP" onclick="pm('CONSTANTS_REGMAP');">+</span>
<span class="regmap" id="a_CONSTANTS_REGMAP" onclick="a('CONSTANTS_REGMAP');">CONSTANTS_REGMAP</span>
</p> <div class="sh" id="div_CONSTANTS_REGMAP">
<p>
<span class="pm" id="pm_CONSTANTS_REGMAP|CONSTANTS_GROUP" onclick="pm('CONSTANTS_REGMAP|CONSTANTS_GROUP');">+</span>
<span class="group" id="a_CONSTANTS_REGMAP|CONSTANTS_GROUP" onclick="a('CONSTANTS_REGMAP|CONSTANTS_GROUP');">CONSTANTS_GROUP</span>
</p>
<div class="sh" id="div_CONSTANTS_REGMAP|CONSTANTS_GROUP">
<p><span class="enum" id="a_CONSTANTS_REGMAP|CONSTANTS_ENUM" onclick="a('CONSTANTS_REGMAP|CONSTANTS_ENUM');">enum CONSTANTS_ENUM</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_CORE_REGS_REGMAP" onclick="pm('CORE_REGS_REGMAP');">+</span>
<span class="regmap" id="a_CORE_REGS_REGMAP" onclick="a('CORE_REGS_REGMAP');">CORE_REGS_REGMAP</span>
</p> <div class="sh" id="div_CORE_REGS_REGMAP">
<p>
<span class="pm" id="pm_CORE_REGS_REGMAP|CORE_REGS" onclick="pm('CORE_REGS_REGMAP|CORE_REGS');">+</span>
<span class="group" id="a_CORE_REGS_REGMAP|CORE_REGS" onclick="a('CORE_REGS_REGMAP|CORE_REGS');">CORE_REGS</span>
</p>
<div class="sh" id="div_CORE_REGS_REGMAP|CORE_REGS">
<p><span class="register" id="a_CORE_REGS_REGMAP|GLOBAL_REGS" onclick="a('CORE_REGS_REGMAP|GLOBAL_REGS');">GLOBAL_REGS</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|VERSIONING_REGS" onclick="a('CORE_REGS_REGMAP|VERSIONING_REGS');">VERSIONING_REGS</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|TIMEKEEPER" onclick="a('CORE_REGS_REGMAP|TIMEKEEPER');">TIMEKEEPER</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|DIO" onclick="a('CORE_REGS_REGMAP|DIO');">DIO</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_CPLD_INTERFACE_REGMAP" onclick="pm('CPLD_INTERFACE_REGMAP');">+</span>
<span class="regmap" id="a_CPLD_INTERFACE_REGMAP" onclick="a('CPLD_INTERFACE_REGMAP');">CPLD_INTERFACE_REGMAP</span>
</p> <div class="sh" id="div_CPLD_INTERFACE_REGMAP">
<p>
<span class="pm" id="pm_CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS" onclick="pm('CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS');">+</span>
<span class="group" id="a_CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS" onclick="a('CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS');">CPLD_INTERFACE_REGS</span>
</p>
<div class="sh" id="div_CPLD_INTERFACE_REGMAP|CPLD_INTERFACE_REGS">
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER" onclick="a('CPLD_INTERFACE_REGMAP|SIGNATURE_REGISTER');">SIGNATURE_REGISTER</span></p>
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|SCRATCH_REGISTER" onclick="a('CPLD_INTERFACE_REGMAP|SCRATCH_REGISTER');">SCRATCH_REGISTER</span></p>
</div>
<p>
<span class="pm" id="pm_CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS" onclick="pm('CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS');">+</span>
<span class="group" id="a_CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS" onclick="a('CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS');">CPLD_SPI_CONTROL_REGS</span>
</p>
<div class="sh" id="div_CPLD_INTERFACE_REGMAP|CPLD_SPI_CONTROL_REGS">
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER" onclick="a('CPLD_INTERFACE_REGMAP|MOTHERBOARD_CPLD_DIVIDER');">MOTHERBOARD_CPLD_DIVIDER</span></p>
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER" onclick="a('CPLD_INTERFACE_REGMAP|DAUGHTERBOARD_CPLD_DIVIDER');">DAUGHTERBOARD_CPLD_DIVIDER</span></p>
</div>
<p>
<span class="pm" id="pm_CPLD_INTERFACE_REGMAP|IPASS_REGS" onclick="pm('CPLD_INTERFACE_REGMAP|IPASS_REGS');">+</span>
<span class="group" id="a_CPLD_INTERFACE_REGMAP|IPASS_REGS" onclick="a('CPLD_INTERFACE_REGMAP|IPASS_REGS');">IPASS_REGS</span>
</p>
<div class="sh" id="div_CPLD_INTERFACE_REGMAP|IPASS_REGS">
<p><span class="register" id="a_CPLD_INTERFACE_REGMAP|IPASS_CONTROL" onclick="a('CPLD_INTERFACE_REGMAP|IPASS_CONTROL');">IPASS_CONTROL</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_DIO_REGMAP" onclick="pm('DIO_REGMAP');">+</span>
<span class="regmap" id="a_DIO_REGMAP" onclick="a('DIO_REGMAP');">DIO_REGMAP</span>
</p> <div class="sh" id="div_DIO_REGMAP">
<p>
<span class="pm" id="pm_DIO_REGMAP|DIO_REGS" onclick="pm('DIO_REGMAP|DIO_REGS');">+</span>
<span class="group" id="a_DIO_REGMAP|DIO_REGS" onclick="a('DIO_REGMAP|DIO_REGS');">DIO_REGS</span>
</p>
<div class="sh" id="div_DIO_REGMAP|DIO_REGS">
<p><span class="register" id="a_DIO_REGMAP|DIO_MASTER_REGISTER" onclick="a('DIO_REGMAP|DIO_MASTER_REGISTER');">DIO_MASTER_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|DIO_DIRECTION_REGISTER" onclick="a('DIO_REGMAP|DIO_DIRECTION_REGISTER');">DIO_DIRECTION_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|DIO_INPUT_REGISTER" onclick="a('DIO_REGMAP|DIO_INPUT_REGISTER');">DIO_INPUT_REGISTER</span></p>
<p><span class="register" id="a_DIO_REGMAP|DIO_OUTPUT_REGISTER" onclick="a('DIO_REGMAP|DIO_OUTPUT_REGISTER');">DIO_OUTPUT_REGISTER</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_DMA_REGMAP" onclick="pm('DMA_REGMAP');">+</span>
<span class="regmap" id="a_DMA_REGMAP" onclick="a('DMA_REGMAP');">DMA_REGMAP</span>
</p> <div class="sh" id="div_DMA_REGMAP">
<p>
<span class="pm" id="pm_DMA_REGMAP|XILINX_DMA_REGISTERS" onclick="pm('DMA_REGMAP|XILINX_DMA_REGISTERS');">+</span>
<span class="group" id="a_DMA_REGMAP|XILINX_DMA_REGISTERS" onclick="a('DMA_REGMAP|XILINX_DMA_REGISTERS');">XILINX_DMA_REGISTERS</span>
</p>
<div class="sh" id="div_DMA_REGMAP|XILINX_DMA_REGISTERS">
</div>
</div>
<p>
<span class="pm" id="pm_ETH_DMA_CTRL_REGMAP" onclick="pm('ETH_DMA_CTRL_REGMAP');">+</span>
<span class="regmap" id="a_ETH_DMA_CTRL_REGMAP" onclick="a('ETH_DMA_CTRL_REGMAP');">ETH_DMA_CTRL_REGMAP</span>
</p> <div class="sh" id="div_ETH_DMA_CTRL_REGMAP">
<p>
<span class="pm" id="pm_ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL" onclick="pm('ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL');">+</span>
<span class="group" id="a_ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL" onclick="a('ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL');">ETH_DMA_CTRL</span>
</p>
<div class="sh" id="div_ETH_DMA_CTRL_REGMAP|ETH_DMA_CTRL">
<p><span class="register" id="a_ETH_DMA_CTRL_REGMAP|AXI_DMA_CTRL" onclick="a('ETH_DMA_CTRL_REGMAP|AXI_DMA_CTRL');">AXI_DMA_CTRL</span></p>
<p><span class="register" id="a_ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL" onclick="a('ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL');">ETH_IO_CTRL</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_GLOBAL_REGS_REGMAP" onclick="pm('GLOBAL_REGS_REGMAP');">+</span>
<span class="regmap" id="a_GLOBAL_REGS_REGMAP" onclick="a('GLOBAL_REGS_REGMAP');">GLOBAL_REGS_REGMAP</span>
</p> <div class="sh" id="div_GLOBAL_REGS_REGMAP">
<p>
<span class="pm" id="pm_GLOBAL_REGS_REGMAP|GLOBAL_REGS" onclick="pm('GLOBAL_REGS_REGMAP|GLOBAL_REGS');">+</span>
<span class="group" id="a_GLOBAL_REGS_REGMAP|GLOBAL_REGS" onclick="a('GLOBAL_REGS_REGMAP|GLOBAL_REGS');">GLOBAL_REGS</span>
</p>
<div class="sh" id="div_GLOBAL_REGS_REGMAP|GLOBAL_REGS">
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|COMPAT_NUM_REG" onclick="a('GLOBAL_REGS_REGMAP|COMPAT_NUM_REG');">COMPAT_NUM_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DATESTAMP_REG" onclick="a('GLOBAL_REGS_REGMAP|DATESTAMP_REG');">DATESTAMP_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GIT_HASH_REG" onclick="a('GLOBAL_REGS_REGMAP|GIT_HASH_REG');">GIT_HASH_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|SCRATCH_REG" onclick="a('GLOBAL_REGS_REGMAP|SCRATCH_REG');">SCRATCH_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DEVICE_ID_REG" onclick="a('GLOBAL_REGS_REGMAP|DEVICE_ID_REG');">DEVICE_ID_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|RFNOC_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|RFNOC_INFO_REG');">RFNOC_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|CLOCK_CTRL_REG');">CLOCK_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|PPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|PPS_CTRL_REG');">PPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_STATUS_REG');">DBOARD_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|NUM_TIMEKEEPERS_REG" onclick="a('GLOBAL_REGS_REGMAP|NUM_TIMEKEEPERS_REG');">NUM_TIMEKEEPERS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|SERIAL_NUM_LOW_REG" onclick="a('GLOBAL_REGS_REGMAP|SERIAL_NUM_LOW_REG');">SERIAL_NUM_LOW_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|SERIAL_NUM_HIGH_REG" onclick="a('GLOBAL_REGS_REGMAP|SERIAL_NUM_HIGH_REG');">SERIAL_NUM_HIGH_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|MFG_TEST_CTRL_REG');">MFG_TEST_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|MFG_TEST_STATUS_REG');">MFG_TEST_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_0_0_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_0_0_INFO_REG');">QSFP_PORT_0_0_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_0_1_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_0_1_INFO_REG');">QSFP_PORT_0_1_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_0_2_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_0_2_INFO_REG');">QSFP_PORT_0_2_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_0_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_0_3_INFO_REG');">QSFP_PORT_0_3_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_0_INFO_REG');">QSFP_PORT_1_0_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_1_INFO_REG');">QSFP_PORT_1_1_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_2_INFO_REG');">QSFP_PORT_1_2_INFO_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG" onclick="a('GLOBAL_REGS_REGMAP|QSFP_PORT_1_3_INFO_REG');">QSFP_PORT_1_3_INFO_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_JTAG_REGMAP" onclick="pm('JTAG_REGMAP');">+</span>
<span class="regmap" id="a_JTAG_REGMAP" onclick="a('JTAG_REGMAP');">JTAG_REGMAP</span>
</p> <div class="sh" id="div_JTAG_REGMAP">
<p>
<span class="pm" id="pm_JTAG_REGMAP|JTAG_REGS" onclick="pm('JTAG_REGMAP|JTAG_REGS');">+</span>
<span class="group" id="a_JTAG_REGMAP|JTAG_REGS" onclick="a('JTAG_REGMAP|JTAG_REGS');">JTAG_REGS</span>
</p>
<div class="sh" id="div_JTAG_REGMAP|JTAG_REGS">
<p><span class="register" id="a_JTAG_REGMAP|TX_DATA" onclick="a('JTAG_REGMAP|TX_DATA');">TX_DATA</span></p>
<p><span class="register" id="a_JTAG_REGMAP|STB_DATA" onclick="a('JTAG_REGMAP|STB_DATA');">STB_DATA</span></p>
<p><span class="register" id="a_JTAG_REGMAP|CONTROL" onclick="a('JTAG_REGMAP|CONTROL');">CONTROL</span></p>
<p><span class="register" id="a_JTAG_REGMAP|RX_DATA" onclick="a('JTAG_REGMAP|RX_DATA');">RX_DATA</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_MB_CPLD_PL_REGMAP" onclick="pm('MB_CPLD_PL_REGMAP');">+</span>
<span class="regmap" id="a_MB_CPLD_PL_REGMAP" onclick="a('MB_CPLD_PL_REGMAP');">MB_CPLD_PL_REGMAP</span>
</p> <div class="sh" id="div_MB_CPLD_PL_REGMAP">
<p>
<span class="pm" id="pm_MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS" onclick="pm('MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS');">+</span>
<span class="group" id="a_MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS" onclick="a('MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS');">MB_CPLD_PL_WINDOWS</span>
</p>
<div class="sh" id="div_MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS">
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|PL_REGISTERS" onclick="a('MB_CPLD_PL_REGMAP|PL_REGISTERS');">PL_REGISTERS</span></p>
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|JTAG_DB0" onclick="a('MB_CPLD_PL_REGMAP|JTAG_DB0');">JTAG_DB0</span></p>
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|JTAG_DB1" onclick="a('MB_CPLD_PL_REGMAP|JTAG_DB1');">JTAG_DB1</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_NIXGE_REGMAP" onclick="pm('NIXGE_REGMAP');">+</span>
<span class="regmap" id="a_NIXGE_REGMAP" onclick="a('NIXGE_REGMAP');">NIXGE_REGMAP</span>
</p> <div class="sh" id="div_NIXGE_REGMAP">
<p>
<span class="pm" id="pm_NIXGE_REGMAP|XGE_MAC_REGS" onclick="pm('NIXGE_REGMAP|XGE_MAC_REGS');">+</span>
<span class="group" id="a_NIXGE_REGMAP|XGE_MAC_REGS" onclick="a('NIXGE_REGMAP|XGE_MAC_REGS');">XGE_MAC_REGS</span>
</p>
<div class="sh" id="div_NIXGE_REGMAP|XGE_MAC_REGS">
<p><span class="register" id="a_NIXGE_REGMAP|PORT_INFO" onclick="a('NIXGE_REGMAP|PORT_INFO');">PORT_INFO</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|MAC_CTRL_STATUS" onclick="a('NIXGE_REGMAP|MAC_CTRL_STATUS');">MAC_CTRL_STATUS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|MAC_PHY_STATUS" onclick="a('NIXGE_REGMAP|MAC_PHY_STATUS');">MAC_PHY_STATUS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|MAC_LED_CTL" onclick="a('NIXGE_REGMAP|MAC_LED_CTL');">MAC_LED_CTL</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|ETH_MDIO_BASE" onclick="a('NIXGE_REGMAP|ETH_MDIO_BASE');">ETH_MDIO_BASE</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|AURORA_OVERRUNS" onclick="a('NIXGE_REGMAP|AURORA_OVERRUNS');">AURORA_OVERRUNS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|AURORA_CHECKSUM_ERRORS" onclick="a('NIXGE_REGMAP|AURORA_CHECKSUM_ERRORS');">AURORA_CHECKSUM_ERRORS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|AURORA_BIST_CHECKER_SAMPS" onclick="a('NIXGE_REGMAP|AURORA_BIST_CHECKER_SAMPS');">AURORA_BIST_CHECKER_SAMPS</span></p>
<p><span class="register" id="a_NIXGE_REGMAP|AURORA_BIST_CHECKER_ERRORS" onclick="a('NIXGE_REGMAP|AURORA_BIST_CHECKER_ERRORS');">AURORA_BIST_CHECKER_ERRORS</span></p>
</div>
<p>
<span class="pm" id="pm_NIXGE_REGMAP|XGE_MAC_WINDOW" onclick="pm('NIXGE_REGMAP|XGE_MAC_WINDOW');">+</span>
<span class="group" id="a_NIXGE_REGMAP|XGE_MAC_WINDOW" onclick="a('NIXGE_REGMAP|XGE_MAC_WINDOW');">XGE_MAC_WINDOW</span>
</p>
<div class="sh" id="div_NIXGE_REGMAP|XGE_MAC_WINDOW">
<p><span class="register" id="a_NIXGE_REGMAP|XGE_MAC" onclick="a('NIXGE_REGMAP|XGE_MAC');">XGE_MAC</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PL_CPLD_BASE_REGMAP" onclick="pm('PL_CPLD_BASE_REGMAP');">+</span>
<span class="regmap" id="a_PL_CPLD_BASE_REGMAP" onclick="a('PL_CPLD_BASE_REGMAP');">PL_CPLD_BASE_REGMAP</span>
</p> <div class="sh" id="div_PL_CPLD_BASE_REGMAP">
<p>
<span class="pm" id="pm_PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS" onclick="pm('PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS');">+</span>
<span class="group" id="a_PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS" onclick="a('PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS');">MB_CPLD_LED_REGS</span>
</p>
<div class="sh" id="div_PL_CPLD_BASE_REGMAP|MB_CPLD_LED_REGS">
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|LED_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|LED_REGISTER');">LED_REGISTER</span></p>
</div>
<p>
<span class="pm" id="pm_PL_CPLD_BASE_REGMAP|PL_CMI_REGS" onclick="pm('PL_CPLD_BASE_REGMAP|PL_CMI_REGS');">+</span>
<span class="group" id="a_PL_CPLD_BASE_REGMAP|PL_CMI_REGS" onclick="a('PL_CPLD_BASE_REGMAP|PL_CMI_REGS');">PL_CMI_REGS</span>
</p>
<div class="sh" id="div_PL_CPLD_BASE_REGMAP|PL_CMI_REGS">
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG" onclick="a('PL_CPLD_BASE_REGMAP|CABLE_PRESENT_REG');">CABLE_PRESENT_REG</span></p>
</div>
<p>
<span class="pm" id="pm_PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS" onclick="pm('PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS');">+</span>
<span class="group" id="a_PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS" onclick="a('PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS');">PL_CPLD_BASE_REGS</span>
</p>
<div class="sh" id="div_PL_CPLD_BASE_REGMAP|PL_CPLD_BASE_REGS">
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|SIGNATURE_REGISTER');">SIGNATURE_REGISTER</span></p>
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|REVISION_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|REVISION_REGISTER');">REVISION_REGISTER</span></p>
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER');">OLDEST_COMPATIBLE_REVISION_REGISTER</span></p>
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|SCRATCH_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|SCRATCH_REGISTER');">SCRATCH_REGISTER</span></p>
<p><span class="register" id="a_PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER" onclick="a('PL_CPLD_BASE_REGMAP|GIT_HASH_REGISTER');">GIT_HASH_REGISTER</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PL_CPLD_REGMAP" onclick="pm('PL_CPLD_REGMAP');">+</span>
<span class="regmap" id="a_PL_CPLD_REGMAP" onclick="a('PL_CPLD_REGMAP');">PL_CPLD_REGMAP</span>
</p> <div class="sh" id="div_PL_CPLD_REGMAP">
<p>
<span class="pm" id="pm_PL_CPLD_REGMAP|PL_CPLD_WINDOWS" onclick="pm('PL_CPLD_REGMAP|PL_CPLD_WINDOWS');">+</span>
<span class="group" id="a_PL_CPLD_REGMAP|PL_CPLD_WINDOWS" onclick="a('PL_CPLD_REGMAP|PL_CPLD_WINDOWS');">PL_CPLD_WINDOWS</span>
</p>
<div class="sh" id="div_PL_CPLD_REGMAP|PL_CPLD_WINDOWS">
<p><span class="register" id="a_PL_CPLD_REGMAP|BASE" onclick="a('PL_CPLD_REGMAP|BASE');">BASE</span></p>
<p><span class="register" id="a_PL_CPLD_REGMAP|MB_CPLD" onclick="a('PL_CPLD_REGMAP|MB_CPLD');">MB_CPLD</span></p>
<p><span class="register" id="a_PL_CPLD_REGMAP|DB0_CPLD" onclick="a('PL_CPLD_REGMAP|DB0_CPLD');">DB0_CPLD</span></p>
<p><span class="register" id="a_PL_CPLD_REGMAP|DB1_CPLD" onclick="a('PL_CPLD_REGMAP|DB1_CPLD');">DB1_CPLD</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PL_DMA_MASTER_REGMAP" onclick="pm('PL_DMA_MASTER_REGMAP');">+</span>
<span class="regmap" id="a_PL_DMA_MASTER_REGMAP" onclick="a('PL_DMA_MASTER_REGMAP');">PL_DMA_MASTER_REGMAP</span>
</p> <div class="sh" id="div_PL_DMA_MASTER_REGMAP">
<p>
<span class="pm" id="pm_PL_DMA_MASTER_REGMAP|HPC0_DMA" onclick="pm('PL_DMA_MASTER_REGMAP|HPC0_DMA');">+</span>
<span class="group" id="a_PL_DMA_MASTER_REGMAP|HPC0_DMA" onclick="a('PL_DMA_MASTER_REGMAP|HPC0_DMA');">HPC0_DMA</span>
</p>
<div class="sh" id="div_PL_DMA_MASTER_REGMAP|HPC0_DMA">
<p><span class="register" id="a_PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW" onclick="a('PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW');">AXI_HPC0_WINDOW</span></p>
</div>
<p>
<span class="pm" id="pm_PL_DMA_MASTER_REGMAP|HPC1_DMA" onclick="pm('PL_DMA_MASTER_REGMAP|HPC1_DMA');">+</span>
<span class="group" id="a_PL_DMA_MASTER_REGMAP|HPC1_DMA" onclick="a('PL_DMA_MASTER_REGMAP|HPC1_DMA');">HPC1_DMA</span>
</p>
<div class="sh" id="div_PL_DMA_MASTER_REGMAP|HPC1_DMA">
<p><span class="register" id="a_PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW" onclick="a('PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW');">AXI_HPC1_WINDOW</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP" onclick="pm('PS_CPLD_BASE_REGMAP');">+</span>
<span class="regmap" id="a_PS_CPLD_BASE_REGMAP" onclick="a('PS_CPLD_BASE_REGMAP');">PS_CPLD_BASE_REGMAP</span>
</p> <div class="sh" id="div_PS_CPLD_BASE_REGMAP">
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP|DIO_REGS" onclick="pm('PS_CPLD_BASE_REGMAP|DIO_REGS');">+</span>
<span class="group" id="a_PS_CPLD_BASE_REGMAP|DIO_REGS" onclick="a('PS_CPLD_BASE_REGMAP|DIO_REGS');">DIO_REGS</span>
</p>
<div class="sh" id="div_PS_CPLD_BASE_REGMAP|DIO_REGS">
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|DIO_DIRECTION_REGISTER');">DIO_DIRECTION_REGISTER</span></p>
</div>
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP|PS_CMI_REGS" onclick="pm('PS_CPLD_BASE_REGMAP|PS_CMI_REGS');">+</span>
<span class="group" id="a_PS_CPLD_BASE_REGMAP|PS_CMI_REGS" onclick="a('PS_CPLD_BASE_REGMAP|PS_CMI_REGS');">PS_CMI_REGS</span>
</p>
<div class="sh" id="div_PS_CPLD_BASE_REGMAP|PS_CMI_REGS">
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|SERIAL_NUM_LOW_REG" onclick="a('PS_CPLD_BASE_REGMAP|SERIAL_NUM_LOW_REG');">SERIAL_NUM_LOW_REG</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|SERIAL_NUM_HIGH_REG" onclick="a('PS_CPLD_BASE_REGMAP|SERIAL_NUM_HIGH_REG');">SERIAL_NUM_HIGH_REG</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS" onclick="a('PS_CPLD_BASE_REGMAP|CMI_CONTROL_STATUS');">CMI_CONTROL_STATUS</span></p>
</div>
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS" onclick="pm('PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS');">+</span>
<span class="group" id="a_PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS" onclick="a('PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS');">PS_CONTROL_REGS</span>
</p>
<div class="sh" id="div_PS_CPLD_BASE_REGMAP|PS_CONTROL_REGS">
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|PL_DB_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|PL_DB_REGISTER');">PL_DB_REGISTER</span></p>
</div>
<p>
<span class="pm" id="pm_PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS" onclick="pm('PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS');">+</span>
<span class="group" id="a_PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS" onclick="a('PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS');">PS_CPLD_BASE_REGS</span>
</p>
<div class="sh" id="div_PS_CPLD_BASE_REGMAP|PS_CPLD_BASE_REGS">
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|SIGNATURE_REGISTER');">SIGNATURE_REGISTER</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|REVISION_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|REVISION_REGISTER');">REVISION_REGISTER</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|OLDEST_COMPATIBLE_REVISION_REGISTER');">OLDEST_COMPATIBLE_REVISION_REGISTER</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|SCRATCH_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|SCRATCH_REGISTER');">SCRATCH_REGISTER</span></p>
<p><span class="register" id="a_PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER" onclick="a('PS_CPLD_BASE_REGMAP|GIT_HASH_REGISTER');">GIT_HASH_REGISTER</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_PS_POWER_REGMAP" onclick="pm('PS_POWER_REGMAP');">+</span>
<span class="regmap" id="a_PS_POWER_REGMAP" onclick="a('PS_POWER_REGMAP');">PS_POWER_REGMAP</span>
</p> <div class="sh" id="div_PS_POWER_REGMAP">
<p>
<span class="pm" id="pm_PS_POWER_REGMAP|PS_POWER_REGS" onclick="pm('PS_POWER_REGMAP|PS_POWER_REGS');">+</span>
<span class="group" id="a_PS_POWER_REGMAP|PS_POWER_REGS" onclick="a('PS_POWER_REGMAP|PS_POWER_REGS');">PS_POWER_REGS</span>
</p>
<div class="sh" id="div_PS_POWER_REGMAP|PS_POWER_REGS">
<p><span class="register" id="a_PS_POWER_REGMAP|IPASS_POWER_REG" onclick="a('PS_POWER_REGMAP|IPASS_POWER_REG');">IPASS_POWER_REG</span></p>
<p><span class="register" id="a_PS_POWER_REGMAP|OSC_POWER_REG" onclick="a('PS_POWER_REGMAP|OSC_POWER_REG');">OSC_POWER_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_QSFP_REGMAP" onclick="pm('QSFP_REGMAP');">+</span>
<span class="regmap" id="a_QSFP_REGMAP" onclick="a('QSFP_REGMAP');">QSFP_REGMAP</span>
</p> <div class="sh" id="div_QSFP_REGMAP">
<p>
<span class="pm" id="pm_QSFP_REGMAP|QSFP_WINDOWS" onclick="pm('QSFP_REGMAP|QSFP_WINDOWS');">+</span>
<span class="group" id="a_QSFP_REGMAP|QSFP_WINDOWS" onclick="a('QSFP_REGMAP|QSFP_WINDOWS');">QSFP_WINDOWS</span>
</p>
<div class="sh" id="div_QSFP_REGMAP|QSFP_WINDOWS">
<p><span class="register" id="a_QSFP_REGMAP|ETH_DMA" onclick="a('QSFP_REGMAP|ETH_DMA');">ETH_DMA</span></p>
<p><span class="register" id="a_QSFP_REGMAP|NIXGE" onclick="a('QSFP_REGMAP|NIXGE');">NIXGE</span></p>
<p><span class="register" id="a_QSFP_REGMAP|UIO" onclick="a('QSFP_REGMAP|UIO');">UIO</span></p>
<p><span class="register" id="a_QSFP_REGMAP|CMAC" onclick="a('QSFP_REGMAP|CMAC');">CMAC</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RADIO_CTRLPORT_REGMAP" onclick="pm('RADIO_CTRLPORT_REGMAP');">+</span>
<span class="regmap" id="a_RADIO_CTRLPORT_REGMAP" onclick="a('RADIO_CTRLPORT_REGMAP');">RADIO_CTRLPORT_REGMAP</span>
</p> <div class="sh" id="div_RADIO_CTRLPORT_REGMAP">
<p>
<span class="pm" id="pm_RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS" onclick="pm('RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS');">+</span>
<span class="group" id="a_RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS" onclick="a('RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS');">RADIO_CTRLPORT_WINDOWS</span>
</p>
<div class="sh" id="div_RADIO_CTRLPORT_REGMAP|RADIO_CTRLPORT_WINDOWS">
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|DB_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|DB_WINDOW');">DB_WINDOW</span></p>
<p><span class="register" id="a_RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW" onclick="a('RADIO_CTRLPORT_REGMAP|RFDC_TIMING_WINDOW');">RFDC_TIMING_WINDOW</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RECONFIG_REGMAP" onclick="pm('RECONFIG_REGMAP');">+</span>
<span class="regmap" id="a_RECONFIG_REGMAP" onclick="a('RECONFIG_REGMAP');">RECONFIG_REGMAP</span>
</p> <div class="sh" id="div_RECONFIG_REGMAP">
<p>
<span class="pm" id="pm_RECONFIG_REGMAP|RECONFIG_REGS" onclick="pm('RECONFIG_REGMAP|RECONFIG_REGS');">+</span>
<span class="group" id="a_RECONFIG_REGMAP|RECONFIG_REGS" onclick="a('RECONFIG_REGMAP|RECONFIG_REGS');">RECONFIG_REGS</span>
</p>
<div class="sh" id="div_RECONFIG_REGMAP|RECONFIG_REGS">
<p><span class="enum" id="a_RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM" onclick="a('RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM');">enum FLASH_PRIMARY_IMAGE_ADDR_ENUM</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_STATUS_REG" onclick="a('RECONFIG_REGMAP|FLASH_STATUS_REG');">FLASH_STATUS_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CONTROL_REG" onclick="a('RECONFIG_REGMAP|FLASH_CONTROL_REG');">FLASH_CONTROL_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_ADDR_REG');">FLASH_ADDR_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_WRITE_DATA_REG" onclick="a('RECONFIG_REGMAP|FLASH_WRITE_DATA_REG');">FLASH_WRITE_DATA_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_READ_DATA_REG" onclick="a('RECONFIG_REGMAP|FLASH_READ_DATA_REG');">FLASH_READ_DATA_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG');">FLASH_CFM0_START_ADDR_REG</span></p>
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG');">FLASH_CFM0_END_ADDR_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RFDC_REGS_REGMAP" onclick="pm('RFDC_REGS_REGMAP');">+</span>
<span class="regmap" id="a_RFDC_REGS_REGMAP" onclick="a('RFDC_REGS_REGMAP');">RFDC_REGS_REGMAP</span>
</p> <div class="sh" id="div_RFDC_REGS_REGMAP">
<p>
<span class="pm" id="pm_RFDC_REGS_REGMAP|RFDC_REGS" onclick="pm('RFDC_REGS_REGMAP|RFDC_REGS');">+</span>
<span class="group" id="a_RFDC_REGS_REGMAP|RFDC_REGS" onclick="a('RFDC_REGS_REGMAP|RFDC_REGS');">RFDC_REGS</span>
</p>
<div class="sh" id="div_RFDC_REGS_REGMAP|RFDC_REGS">
<p><span class="enum" id="a_RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM" onclick="a('RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM');">enum FABRIC_DSP_BW_ENUM</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|MMCM" onclick="a('RFDC_REGS_REGMAP|MMCM');">MMCM</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|INVERT_IQ_REG" onclick="a('RFDC_REGS_REGMAP|INVERT_IQ_REG');">INVERT_IQ_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|MMCM_RESET_REG" onclick="a('RFDC_REGS_REGMAP|MMCM_RESET_REG');">MMCM_RESET_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG" onclick="a('RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG');">RF_RESET_CONTROL_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_RESET_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_RESET_STATUS_REG');">RF_RESET_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_AXI_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_AXI_STATUS_REG');">RF_AXI_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|FABRIC_DSP_REG" onclick="a('RFDC_REGS_REGMAP|FABRIC_DSP_REG');">FABRIC_DSP_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|CALIBRATION_DATA" onclick="a('RFDC_REGS_REGMAP|CALIBRATION_DATA');">CALIBRATION_DATA</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|CALIBRATION_ENABLE" onclick="a('RFDC_REGS_REGMAP|CALIBRATION_ENABLE');">CALIBRATION_ENABLE</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|THRESHOLD_STATUS" onclick="a('RFDC_REGS_REGMAP|THRESHOLD_STATUS');">THRESHOLD_STATUS</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG" onclick="a('RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG');">RF_PLL_CONTROL_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_PLL_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_PLL_STATUS_REG');">RF_PLL_STATUS_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RFDC_TIMING_REGMAP" onclick="pm('RFDC_TIMING_REGMAP');">+</span>
<span class="regmap" id="a_RFDC_TIMING_REGMAP" onclick="a('RFDC_TIMING_REGMAP');">RFDC_TIMING_REGMAP</span>
</p> <div class="sh" id="div_RFDC_TIMING_REGMAP">
<p>
<span class="pm" id="pm_RFDC_TIMING_REGMAP|RFDC_TIMING_REGS" onclick="pm('RFDC_TIMING_REGMAP|RFDC_TIMING_REGS');">+</span>
<span class="group" id="a_RFDC_TIMING_REGMAP|RFDC_TIMING_REGS" onclick="a('RFDC_TIMING_REGMAP|RFDC_TIMING_REGS');">RFDC_TIMING_REGS</span>
</p>
<div class="sh" id="div_RFDC_TIMING_REGMAP|RFDC_TIMING_REGS">
<p><span class="register" id="a_RFDC_TIMING_REGMAP|NCO_RESET_REG" onclick="a('RFDC_TIMING_REGMAP|NCO_RESET_REG');">NCO_RESET_REG</span></p>
<p><span class="register" id="a_RFDC_TIMING_REGMAP|GEARBOX_RESET_REG" onclick="a('RFDC_TIMING_REGMAP|GEARBOX_RESET_REG');">GEARBOX_RESET_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_SPI_REGMAP" onclick="pm('SPI_REGMAP');">+</span>
<span class="regmap" id="a_SPI_REGMAP" onclick="a('SPI_REGMAP');">SPI_REGMAP</span>
</p> <div class="sh" id="div_SPI_REGMAP">
<p>
<span class="pm" id="pm_SPI_REGMAP|SPI_REGS" onclick="pm('SPI_REGMAP|SPI_REGS');">+</span>
<span class="group" id="a_SPI_REGMAP|SPI_REGS" onclick="a('SPI_REGMAP|SPI_REGS');">SPI_REGS</span>
</p>
<div class="sh" id="div_SPI_REGMAP|SPI_REGS">
<p><span class="register" id="a_SPI_REGMAP|RX_DATA_LOW" onclick="a('SPI_REGMAP|RX_DATA_LOW');">RX_DATA_LOW</span></p>
<p><span class="register" id="a_SPI_REGMAP|RX_DATA_HIGH" onclick="a('SPI_REGMAP|RX_DATA_HIGH');">RX_DATA_HIGH</span></p>
<p><span class="register" id="a_SPI_REGMAP|TX_DATA_LOW" onclick="a('SPI_REGMAP|TX_DATA_LOW');">TX_DATA_LOW</span></p>
<p><span class="register" id="a_SPI_REGMAP|TX_DATA_HIGH" onclick="a('SPI_REGMAP|TX_DATA_HIGH');">TX_DATA_HIGH</span></p>
<p><span class="register" id="a_SPI_REGMAP|CONTROL" onclick="a('SPI_REGMAP|CONTROL');">CONTROL</span></p>
<p><span class="register" id="a_SPI_REGMAP|CLOCK_DIVIDER" onclick="a('SPI_REGMAP|CLOCK_DIVIDER');">CLOCK_DIVIDER</span></p>
<p><span class="register" id="a_SPI_REGMAP|SLAVE_SELECT" onclick="a('SPI_REGMAP|SLAVE_SELECT');">SLAVE_SELECT</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_UIO_REGMAP" onclick="pm('UIO_REGMAP');">+</span>
<span class="regmap" id="a_UIO_REGMAP" onclick="a('UIO_REGMAP');">UIO_REGMAP</span>
</p> <div class="sh" id="div_UIO_REGMAP">
<p>
<span class="pm" id="pm_UIO_REGMAP|UIO_REGS" onclick="pm('UIO_REGMAP|UIO_REGS');">+</span>
<span class="group" id="a_UIO_REGMAP|UIO_REGS" onclick="a('UIO_REGMAP|UIO_REGS');">UIO_REGS</span>
</p>
<div class="sh" id="div_UIO_REGMAP|UIO_REGS">
<p><span class="register" id="a_UIO_REGMAP|IP" onclick="a('UIO_REGMAP|IP');">IP</span></p>
<p><span class="register" id="a_UIO_REGMAP|UDP" onclick="a('UIO_REGMAP|UDP');">UDP</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_MAC_LSB" onclick="a('UIO_REGMAP|BRIDGE_MAC_LSB');">BRIDGE_MAC_LSB</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_MAC_MSB" onclick="a('UIO_REGMAP|BRIDGE_MAC_MSB');">BRIDGE_MAC_MSB</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_IP" onclick="a('UIO_REGMAP|BRIDGE_IP');">BRIDGE_IP</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_UDP" onclick="a('UIO_REGMAP|BRIDGE_UDP');">BRIDGE_UDP</span></p>
<p><span class="register" id="a_UIO_REGMAP|BRIDGE_ENABLE" onclick="a('UIO_REGMAP|BRIDGE_ENABLE');">BRIDGE_ENABLE</span></p>
<p><span class="register" id="a_UIO_REGMAP|CHDR_DROPPED" onclick="a('UIO_REGMAP|CHDR_DROPPED');">CHDR_DROPPED</span></p>
<p><span class="register" id="a_UIO_REGMAP|CPU_DROPPED" onclick="a('UIO_REGMAP|CPU_DROPPED');">CPU_DROPPED</span></p>
<p><span class="register" id="a_UIO_REGMAP|PAUSE" onclick="a('UIO_REGMAP|PAUSE');">PAUSE</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_VERSIONING_REGS_REGMAP" onclick="pm('VERSIONING_REGS_REGMAP');">+</span>
<span class="regmap" id="a_VERSIONING_REGS_REGMAP" onclick="a('VERSIONING_REGS_REGMAP');">VERSIONING_REGS_REGMAP</span>
</p> <div class="sh" id="div_VERSIONING_REGS_REGMAP">
<p>
<span class="pm" id="pm_VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS" onclick="pm('VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS');">+</span>
<span class="group" id="a_VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS" onclick="a('VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS');">VERSIONING_CONSTANTS</span>
</p>
<div class="sh" id="div_VERSIONING_REGS_REGMAP|VERSIONING_CONSTANTS">
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION" onclick="a('VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION');">enum CPLD_IFC_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION" onclick="a('VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION');">enum DB_GPIO_IFC_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|FPGA_VERSION" onclick="a('VERSIONING_REGS_REGMAP|FPGA_VERSION');">enum FPGA_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION" onclick="a('VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION');">enum RF_CORE_100M_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION" onclick="a('VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION');">enum RF_CORE_400M_VERSION</span></p>
</div>
<p>
<span class="pm" id="pm_VERSIONING_REGS_REGMAP|VERSIONING_REGS" onclick="pm('VERSIONING_REGS_REGMAP|VERSIONING_REGS');">+</span>
<span class="group" id="a_VERSIONING_REGS_REGMAP|VERSIONING_REGS" onclick="a('VERSIONING_REGS_REGMAP|VERSIONING_REGS');">VERSIONING_REGS</span>
</p>
<div class="sh" id="div_VERSIONING_REGS_REGMAP|VERSIONING_REGS">
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES" onclick="a('VERSIONING_REGS_REGMAP|COMPONENTS_INDEXES');">enum COMPONENTS_INDEXES</span></p>
<p><span class="register" id="a_VERSIONING_REGS_REGMAP|CURRENT_VERSION" onclick="a('VERSIONING_REGS_REGMAP|CURRENT_VERSION');">CURRENT_VERSION</span></p>
<p><span class="register" id="a_VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION" onclick="a('VERSIONING_REGS_REGMAP|OLDEST_COMPATIBLE_VERSION');">OLDEST_COMPATIBLE_VERSION</span></p>
<p><span class="register" id="a_VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED" onclick="a('VERSIONING_REGS_REGMAP|VERSION_LAST_MODIFIED');">VERSION_LAST_MODIFIED</span></p>
<p><span class="register" id="a_VERSIONING_REGS_REGMAP|RESERVED" onclick="a('VERSIONING_REGS_REGMAP|RESERVED');">RESERVED</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_XGE_MAC_REGMAP" onclick="pm('XGE_MAC_REGMAP');">+</span>
<span class="regmap" id="a_XGE_MAC_REGMAP" onclick="a('XGE_MAC_REGMAP');">XGE_MAC_REGMAP</span>
</p> <div class="sh" id="div_XGE_MAC_REGMAP">
<p>
<span class="pm" id="pm_XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS" onclick="pm('XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS');">+</span>
<span class="group" id="a_XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS" onclick="a('XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS');">OPENCORE_XGE_REGISTERS</span>
</p>
<div class="sh" id="div_XGE_MAC_REGMAP|OPENCORE_XGE_REGISTERS">
</div>
</div>
</div>
</body>
</HTML>
top/x400/doc/X4XX_FPGA_right.htm
+22509
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top/x400/dts/usrp_x410_fpga_C1.dts
+20
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x410-version-info.dtsi"
#include "x410-fpga.dtsi"
#include "x410-common.dtsi"
#include "x410-rfdc.dtsi"
#include "x410-dma.dtsi"
#include "x410-100gbe-port0.dtsi"
top/x400/dts/usrp_x410_fpga_CG.dts
+22
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@@ -0,0 +1,22 @@
/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x410-version-info.dtsi"
#include "x410-fpga.dtsi"
#include "x410-common.dtsi"
#include "x410-rfdc.dtsi"
#include "x410-dma.dtsi"
#include "x410-100gbe-port0.dtsi"
#include "x410-100gbe-port1.dtsi"
top/x400/dts/usrp_x410_fpga_X1.dts
+21
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@@ -0,0 +1,21 @@
/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x410-version-info.dtsi"
#include "x410-fpga.dtsi"
#include "x410-common.dtsi"
#include "x410-rfdc.dtsi"
#include "x410-dma.dtsi"
#include "x410-10gbe-port0.dtsi"
top/x400/dts/usrp_x410_fpga_X4.dts
+20
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@@ -0,0 +1,20 @@
/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x410-version-info.dtsi"
#include "x410-fpga.dtsi"
#include "x410-common.dtsi"
#include "x410-rfdc.dtsi"
#include "x410-dma.dtsi"
#include "x410-10gbe-port0-x4.dtsi"
top/x400/dts/usrp_x410_fpga_X4C.dts
+22
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@@ -0,0 +1,22 @@
/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x410-version-info.dtsi"
#include "x410-fpga.dtsi"
#include "x410-common.dtsi"
#include "x410-rfdc.dtsi"
#include "x410-dma.dtsi"
#include "x410-10gbe-port0-x4.dtsi"
#include "x410-100gbe-port1.dtsi"
top/x400/dts/usrp_x410_fpga_XG.dts
+22
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@@ -0,0 +1,22 @@
/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x410-version-info.dtsi"
#include "x410-fpga.dtsi"
#include "x410-common.dtsi"
#include "x410-rfdc.dtsi"
#include "x410-dma.dtsi"
#include "x410-10gbe-port0.dtsi"
#include "x410-10gbe-port1.dtsi"
top/x400/dts/x410-100gbe-port0.dtsi
+41
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
nixge0: ethernet@1200000000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00000000 0x0 0x4000
0x12 0x00008000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 108 4 0 109 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth1_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
link-gpios = <&gpio 94 0>;
};
};
misc_enet_regs_0: uio@120000A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0000A000 0x0 0x2000>;
reg-names = "misc-enet-regs0";
};
};
top/x400/dts/x410-100gbe-port1.dtsi
+41
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
nixge1: ethernet@1200040000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00040000 0x0 0x4000
0x12 0x00048000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 110 4 0 111 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth5_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
link-gpios = <&gpio 98 0>;
};
};
misc_enet_regs_1: uio@120004A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0004A000 0x0 0x2000>;
reg-names = "misc-enet-regs1";
};
};
top/x400/dts/x410-10gbe-port0-x4.dtsi
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
nixge0: ethernet@1200000000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00000000 0x0 0x4000
0x12 0x00008000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 108 4 0 109 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth1_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 94 0>;
};
};
nixge0_1: ethernet@1200010000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00010000 0x0 0x4000
0x12 0x00018000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 108 4 0 109 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth2_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 95 0>;
};
};
nixge0_2: ethernet@1200020000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00020000 0x0 0x4000
0x12 0x00028000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 108 4 0 109 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth3_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 96 0>;
};
};
nixge0_3: ethernet@1200030000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00030000 0x0 0x4000
0x12 0x00038000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 108 4 0 109 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth4_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 97 0>;
};
};
misc_enet_regs_0: uio@120000A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0000A000 0x0 0x2000>;
reg-names = "misc-enet-regs0";
};
misc_enet_regs_0_1: uio@120001A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0001A000 0x0 0x2000>;
reg-names = "misc-enet-regs0-1";
};
misc_enet_regs_0_2: uio@120002A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0002A000 0x0 0x2000>;
reg-names = "misc-enet-regs0-2";
};
misc_enet_regs_0_3: uio@120003A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0003A000 0x0 0x2000>;
reg-names = "misc-enet-regs0-3";
};
};
top/x400/dts/x410-10gbe-port0.dtsi
+41
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
nixge0: ethernet@1200000000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00000000 0x0 0x4000
0x12 0x00008000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 108 4 0 109 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth1_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 94 0>;
};
};
misc_enet_regs_0: uio@120000A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0000A000 0x0 0x2000>;
reg-names = "misc-enet-regs0";
};
};
top/x400/dts/x410-10gbe-port1-x4.dtsi
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
nixge1: ethernet@1200040000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00040000 0x0 0x4000
0x12 0x00048000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 110 4 0 111 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth5_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 98 0>;
};
};
nixge1_1: ethernet@1200050000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00050000 0x0 0x4000
0x12 0x00058000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 110 4 0 111 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth6_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 99 0>;
};
};
nixge1_2: ethernet@1200060000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00060000 0x0 0x4000
0x12 0x00068000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 110 4 0 111 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth7_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 100 0>;
};
};
nixge1_3: ethernet@1200070000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00070000 0x0 0x4000
0x12 0x00078000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 110 4 0 111 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth8_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 101 0>;
};
};
misc_enet_regs_1: uio@120004A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0004A000 0x0 0x2000>;
reg-names = "misc-enet-regs1";
};
misc_enet_regs_1_1: uio@120005A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0005A000 0x0 0x2000>;
reg-names = "misc-enet-regs1-1";
};
misc_enet_regs_1_2: uio@120006A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0006A000 0x0 0x2000>;
reg-names = "misc-enet-regs1-2";
};
misc_enet_regs_1_3: uio@120007A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0007A000 0x0 0x2000>;
reg-names = "misc-enet-regs1-3";
};
};
top/x400/dts/x410-10gbe-port1.dtsi
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
nixge1: ethernet@1200040000 {
compatible = "ni,xge-enet-3.00";
reg = <0x12 0x00040000 0x0 0x4000
0x12 0x00048000 0x0 0x2000>;
reg-names = "dma", "ctrl";
interrupts = <0 110 4 0 111 4>;
interrupt-names = "rx", "tx";
interrupt-parent = <&gic>;
nvmem-cells = <&eth5_addr>;
nvmem-cell-names = "address";
status = "okay";
phy-mode = "xgmii";
fixed-link {
speed = <10000>;
full-duplex;
link-gpios = <&gpio 98 0>;
};
};
misc_enet_regs_1: uio@120004A000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x12 0x0004A000 0x0 0x2000>;
reg-names = "misc-enet-regs1";
};
};
top/x400/dts/x410-common.dtsi
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
uio@1000000000 {
compatible = "usrp-uio";
reg = <0x10 0x00000000 0x0 0x1000>;
reg-names = "jtag-0";
status = "okay";
};
uio@1000080000 {
compatible = "usrp-uio";
reg = <0x10 0x00080000 0x0 0x20000>;
reg-names = "ctrlport-mboard-regs";
status = "okay";
};
uio@10000A0000 {
compatible = "usrp-uio";
reg = <0x10 0x000A0000 0x0 0x4000>;
reg-names = "mboard-regs";
status = "okay";
};
};
top/x400/dts/x410-dma.dtsi
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
misc_clk_3: misc_clk_3 {
#clock-cells = <0>;
clock-frequency = <200000000>;
compatible = "fixed-clock";
};
// AXI DMA engine + control
nixge_internal: ethernet@10000A4000 {
compatible = "ni,xge-enet-3.00";
reg = <0x10 0x000A4000 0x0 0x4000
0x10 0x000A8000 0x0 0x2000>;
reg-names = "dma", "ctrl";
clocks = <&misc_clk_3>;
clock-names = "bus_clk";
interrupts = <0 104 4 0 105 4>;
interrupt-names = "tx", "rx";
interrupt-parent = <&gic>;
status = "okay";
phy-mode = "internal";
local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
// Misc internal Ethernet registers
uio@10000AA000 {
compatible = "usrp-uio";
reg = <0x10 0x000AA000 0x0 0x2000>;
reg-names = "misc-enet-int-regs";
status = "okay";
};
};
top/x400/dts/x410-fpga.dtsi
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
firmware-name = "x410.bin";
};
top/x400/dts/x410-rfdc.dtsi
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/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
misc_clk_1: misc_clk_1 {
#clock-cells = <0>;
clock-frequency = <40000000>;
compatible = "fixed-clock";
};
misc_clk_2: misc_clk_2 {
#clock-cells = <0>;
clock-frequency = <184320000>;
compatible = "fixed-clock";
};
rf_data_converter: usp_rf_data_converter@1000100000 {
clock-names = "s_axi_aclk", "m0_axis_aclk", "m2_axis_aclk", "s0_axis_aclk", "s1_axis_aclk";
clocks = <&misc_clk_1>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>;
compatible = "xlnx,usp-rf-data-converter-2.1";
num-insts = <0x1>;
param-list = [ 00 00 00 00 00 10 00 10 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a a7 40 0a d7 a3 70 3d 0a 67 40 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a a7 40 0a d7 a3 70 3d 0a 67 40 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 9a 99 99 99 99 99 19 40 00 00 00 00 00 00 b9 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 9a 99 99 99 99 99 19 40 00 00 00 00 00 00 b9 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a a7 40 0a d7 a3 70 3d 0a 67 40 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 40 9f 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a a7 40 0a d7 a3 70 3d 0a 67 40 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 40 9f 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00];
reg = <0x00000010 0x00100000 0x0 0x40000>;
};
rfdc_regs: uio@1000140000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x10 0x00140000 0x0 0x20000>;
reg-names = "rfdc-regs";
};
};
top/x400/ip/Makefile.inc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(IP_DIR)/xge_pcs_pma/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_app_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
include $(IP_DIR)/ddr4_64bits/Makefile.inc
include $(IP_DIR)/adc_100m_bd/Makefile.inc
include $(IP_DIR)/adc_400m_bd/Makefile.inc
include $(IP_DIR)/dac_100m_bd/Makefile.inc
include $(IP_DIR)/dac_400m_bd/Makefile.inc
include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
include $(IP_DIR)/fifo_short_2clk/Makefile.inc
include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
include $(IP_DIR)/eth_100g_bd/Makefile.inc
include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc
include $(IP_DIR)/hb47_1to2/Makefile.inc
include $(IP_DIR)/hb47_2to1/Makefile.inc
BD_SRCS = \
$(IP_X4XX_PS_RFDC_BD_SRCS) \
$(IP_X4XX_PS_RFDC_HDL_SRCS) \
$(IP_AXI_INTERCONNECT_APP_BD_SRCS) \
$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \
$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
$(IP_ADC_100M_BD_SRCS) \
$(IP_ADC_100M_HDL_SRCS) \
$(IP_DAC_100M_BD_SRCS) \
$(IP_DAC_100M_HDL_SRCS) \
$(IP_ADC_400M_BD_SRCS) \
$(IP_ADC_400M_HDL_SRCS) \
$(IP_DAC_400M_BD_SRCS) \
$(IP_DAC_400M_HDL_SRCS) \
$(IP_100G_BD_SRCS) \
$(IP_100G_HDL_SRCS) \
$(IP_AXI_ETH_DMA_BD_SRCS) \
$(IP_AXI_ETH_DMA_BD_HDL_SRCS)
IP_XCI_SRCS = \
$(IP_DDR4_64BITS_SRCS) \
$(IP_XGE_PCS_PMA_SRCS) \
$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
$(IP_FIFO_4K_2CLK_SRCS) \
$(IP_HB47_1TO2_SRCS) \
$(IP_HB47_2TO1_SRCS) \
BD_OUTPUTS = \
$(BD_X4XX_PS_RFDC_BD_OUTS) \
$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
$(BD_AXI_INTERCONNECT_ETH_BD_OUTS) \
$(BD_AXI_INTERCONNECT_DMA_BD_OUTS) \
$(BD_ADC_100M_BD_OUTS) \
$(BD_ADC_400M_BD_OUTS) \
$(BD_DAC_100M_BD_OUTS) \
$(BD_DAC_400M_BD_OUTS) \
$(BD_100G_BD_OUTS) \
$(BD_AXI_ETH_DMA_BD_OUTS)
IP_SYNTH_OUTPUTS = \
$(IP_DDR4_64BITS_OUTS) \
$(IP_XGE_PCS_PMA_OUTS) \
$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
$(IP_FIFO_SHORT_2CLK_OUTS) \
$(IP_FIFO_4K_2CLK_OUTS) \
$(IP_HB47_1TO2_OUTS) \
$(IP_HB47_2TO1_OUTS) \
IP_HDL_SIM_SRCS = \
$(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \
$(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \
$(IP_FIFO_SHORT_2CLK_HDL_SIM_SRCS) \
$(IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_HDL_SIM_SRCS) \
$(IP_100G_HDL_SIM_SRCS) \
$(IP_XGE_PCS_PMA_HDL_SIM_SRCS)
ip: $(IP_SYNTH_OUTPUTS) $(BD_OUTPUTS)
.PHONY: ip
top/x400/ip/adc_100m_bd/.gitignore
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synthstub/
top/x400/ip/adc_100m_bd/Makefile.inc
+38
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_ADC_100M_ORIG_SRCS = $(addprefix $(IP_DIR)/adc_100m_bd/, \
adc_100m_bd.tcl \
)
IP_ADC_100M_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/, \
100m/ddc_saturate.vhd \
100m/adc_3_1_clk_converter.vhd \
100m/adc_gearbox_2x1.v \
common/PkgRf.vhd \
common/scale_2x.vhd \
)
IP_ADC_100M_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_100m_bd/, \
adc_100m_bd.tcl \
)
IP_ADC_100M_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_100m_bd/, \
adc_100m_bd/adc_100m_bd.bd \
)
BD_ADC_100M_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/adc_100m_bd/, \
adc_100m_bd.bd.out \
adc_100m_bd/adc_100m_bd_ooc.xdc \
adc_100m_bd/synth/adc_100m_bd.v \
)
EMPTY_IP_SRCS =
$(IP_ADC_100M_BD_SRCS) $(BD_ADC_100M_BD_OUTS) $(IP_ADC_100M_BDTCL_SRCS): $(IP_ADC_100M_ORIG_SRCS) $(IP_ADC_100M_HDL_SRCS)
$(call BUILD_VIVADO_BDTCL,adc_100m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_100M_HDL_SRCS),)
top/x400/ip/adc_100m_bd/adc_100m_bd.tcl
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################################################################
# This is a generated script based on design: adc_100m_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source adc_100m_bd_script.tcl
# The design that will be created by this Tcl script contains the following
# module references:
# adc_3_1_clk_converter, adc_gearbox_2x1, ddc_saturate, scale_2x
# Please add the sources of those modules before sourcing this Tcl script.
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name adc_100m_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
# Add USER_COMMENTS on $design_name
set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name]
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axis_register_slice:1.1\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:fir_compiler:7.2\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
adc_3_1_clk_converter\
adc_gearbox_2x1\
ddc_saturate\
scale_2x\
"
set list_mods_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ]
set_property -dict [ list \
CONFIG.FREQ_HZ {122880000} \
] $adc_data_out
set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ]
set_property -dict [ list \
CONFIG.FREQ_HZ {184320000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {4} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $adc_i_data_in
set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ]
set_property -dict [ list \
CONFIG.FREQ_HZ {184320000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {4} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $adc_q_data_in
# Create ports
set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ]
set data_clk [ create_bd_port -dir I -type clk data_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {adc_data_out} \
CONFIG.FREQ_HZ {122880000} \
] $data_clk
set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ]
set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ]
set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ]
set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {adc_i_data_in:adc_q_data_in} \
CONFIG.ASSOCIATED_RESET {adc_gearbox_resetn_rclk:rfdc_adc_axi_resetn_rclk} \
CONFIG.FREQ_HZ {184320000} \
] $rfdc_clk
set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ]
set_property -dict [ list \
CONFIG.FREQ_HZ {368640000} \
] $rfdc_clk_2x
set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ]
# Create instance: adc_3_1_clk_converter_0, and set properties
set block_name adc_3_1_clk_converter
set block_cell_name adc_3_1_clk_converter_0
if { [catch {set adc_3_1_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $adc_3_1_clk_converter_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: adc_data_to_axi, and set properties
set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ]
set_property -dict [ list \
CONFIG.HAS_TREADY {0} \
CONFIG.REG_CONFIG {1} \
CONFIG.TDATA_NUM_BYTES {4} \
] $adc_data_to_axi
# Create instance: adc_gearbox_2x1_0, and set properties
set block_name adc_gearbox_2x1
set block_cell_name adc_gearbox_2x1_0
if { [catch {set adc_gearbox_2x1_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $adc_gearbox_2x1_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: adc_i_data_from_axi, and set properties
set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ]
set_property -dict [ list \
CONFIG.REG_CONFIG {0} \
CONFIG.TDATA_NUM_BYTES {4} \
] $adc_i_data_from_axi
# Create instance: adc_q_data_from_axi, and set properties
set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ]
set_property -dict [ list \
CONFIG.REG_CONFIG {0} \
CONFIG.TDATA_NUM_BYTES {4} \
] $adc_q_data_from_axi
# Create instance: const_1, and set properties
set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ]
# Create instance: ddc_saturate, and set properties
set block_name ddc_saturate
set block_cell_name ddc_saturate
if { [catch {set ddc_saturate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $ddc_saturate eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: fir_compiler_0, and set properties
set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ]
set_property -dict [ list \
CONFIG.Clock_Frequency {384} \
CONFIG.CoefficientVector {-2,0,8,12,0,-26,-36,0,63,81,0,-130,-161,0,241,291,0,-415,-491,0,676,788,0,-1059,-1223,0,1621,1864,0,-2473,-2860,0,3892,4607,0,-6820,-8705,0,17900,36048,43690,36048,17900,0,-8705,-6820,0,4607,3892,0,-2860,-2473,0,1864,1621,0,-1223,-1059,0,788,676,0,-491,-415,0,291,241,0,-161,-130,0,81,63,0,-36,-26,0,12,8,0,-2} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Non_Symmetric} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {27} \
CONFIG.Data_Fractional_Bits {0} \
CONFIG.Data_Width {16} \
CONFIG.Decimation_Rate {3} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
CONFIG.Has_ARESETn {true} \
CONFIG.Interpolation_Rate {1} \
CONFIG.M_DATA_Has_TREADY {false} \
CONFIG.Number_Channels {1} \
CONFIG.Number_Paths {2} \
CONFIG.Output_Rounding_Mode {Convergent_Rounding_to_Even} \
CONFIG.Output_Width {17} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Reset_Data_Vector {true} \
CONFIG.S_DATA_Has_FIFO {false} \
CONFIG.Sample_Frequency {384} \
CONFIG.Zero_Pack_Factor {1} \
] $fir_compiler_0
# Create instance: scale_2x_0, and set properties
set block_name scale_2x
set block_cell_name scale_2x_0
if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $scale_2x_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
set_property -dict [ list \
CONFIG.kDataWidth {32} \
] $scale_2x_0
# Create interface connections
connect_bd_intf_net -intf_net adc_data_combine_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS]
connect_bd_intf_net -intf_net adc_i_axi_data_1 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS]
connect_bd_intf_net -intf_net adc_q_axi_data_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS]
connect_bd_intf_net -intf_net fir_compiler_0_M_AXIS_DATA [get_bd_intf_pins adc_3_1_clk_converter_0/s_axis] [get_bd_intf_pins fir_compiler_0/M_AXIS_DATA]
# Create port connections
connect_bd_net -net adc_3_1_clk_converter_0_m_axis_tdata [get_bd_pins adc_3_1_clk_converter_0/m_axis_tdata] [get_bd_pins ddc_saturate/cDataIn]
connect_bd_net -net adc_3_1_clk_converter_0_m_axis_tvalid [get_bd_pins adc_3_1_clk_converter_0/m_axis_tvalid] [get_bd_pins ddc_saturate/cDataValidIn]
connect_bd_net -net adc_data_out_resetn_dclk_1 [get_bd_ports adc_data_out_resetn_dclk] [get_bd_pins adc_3_1_clk_converter_0/m_axis_resetn] [get_bd_pins adc_data_to_axi/aresetn]
connect_bd_net -net adc_gearbox_2x1_0_adc_data_out_2x [get_bd_pins adc_gearbox_2x1_0/adc_out_2x] [get_bd_pins fir_compiler_0/s_axis_data_tdata]
connect_bd_net -net adc_gearbox_2x1_0_rfi_1x [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout]
connect_bd_net -net adc_gearbox_2x1_0_valid_out_2x [get_bd_pins adc_gearbox_2x1_0/valid_out_2x] [get_bd_pins fir_compiler_0/s_axis_data_tvalid]
connect_bd_net -net adc_q_data_breakout_m_axis_tdata [get_bd_pins adc_gearbox_2x1_0/adc_q_in_1x] [get_bd_pins adc_q_data_from_axi/m_axis_tdata]
connect_bd_net -net aresetn_0_1 [get_bd_ports fir_resetn_rclk2x] [get_bd_pins adc_3_1_clk_converter_0/s_axis_resetn] [get_bd_pins fir_compiler_0/aresetn]
connect_bd_net -net axis_register_slice_0_m_axis_tdata [get_bd_pins adc_gearbox_2x1_0/adc_i_in_1x] [get_bd_pins adc_i_data_from_axi/m_axis_tdata]
connect_bd_net -net axis_register_slice_0_m_axis_tvalid [get_bd_pins adc_gearbox_2x1_0/valid_in_1x] [get_bd_pins adc_i_data_from_axi/m_axis_tvalid]
connect_bd_net -net data_clock_mmcm_data_clk [get_bd_ports data_clk] [get_bd_pins adc_3_1_clk_converter_0/m_axis_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins ddc_saturate/Clk]
connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_ports rfdc_clk] [get_bd_pins adc_gearbox_2x1_0/clk1x] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_q_data_from_axi/aclk]
connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_ports rfdc_clk_2x] [get_bd_pins adc_3_1_clk_converter_0/s_axis_clk] [get_bd_pins adc_gearbox_2x1_0/clk2x] [get_bd_pins fir_compiler_0/aclk]
connect_bd_net -net ddc_saturate_cDataOut [get_bd_pins ddc_saturate/cDataOut] [get_bd_pins scale_2x_0/cDataIn]
connect_bd_net -net ddc_saturate_cDataValidOut [get_bd_pins ddc_saturate/cDataValidOut] [get_bd_pins scale_2x_0/cDataValidIn]
connect_bd_net -net enable_data_to_fir_rclk_1 [get_bd_ports enable_data_to_fir_rclk] [get_bd_pins adc_gearbox_2x1_0/enable_1x]
connect_bd_net -net rfdc_adc_axi_resetn_rclk_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_gearbox_2x1_0/reset_n_1x] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn]
connect_bd_net -net scale_2x_0_cDataOut [get_bd_pins adc_data_to_axi/s_axis_tdata] [get_bd_pins scale_2x_0/cDataOut]
connect_bd_net -net scale_2x_0_cDataValidOut [get_bd_pins adc_data_to_axi/s_axis_tvalid] [get_bd_pins scale_2x_0/cDataValidOut]
connect_bd_net -net swap_iq_2x_1 [get_bd_ports swap_iq_2x] [get_bd_pins adc_gearbox_2x1_0/swap_iq_2x]
# Create address segments
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/adc_100m_bd/hdl_sources.tcl
+10
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@@ -0,0 +1,10 @@
set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
# Vivado's block diagram default library for files not belonging to any special
# library is called xil_defaultlib
read_verilog -library xil_defaultlib $script_dir/../../rf/100m/adc_gearbox_2x1.v
read_vhdl -library xil_defaultlib $script_dir/../../rf/100m/ddc_saturate.vhd
read_vhdl -library xil_defaultlib $script_dir/../../rf/100m/adc_3_1_clk_converter.vhd
read_vhdl -library xil_defaultlib $script_dir/../../rf/common/PkgRf.vhd
read_vhdl -library xil_defaultlib $script_dir/../../rf/common/scale_2x.vhd
top/x400/ip/adc_400m_bd/Makefile.inc
+38
View File
@@ -0,0 +1,38 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_ADC_400M_ORIG_SRCS = $(addprefix $(IP_DIR)/adc_400m_bd/, \
adc_400m_bd.tcl \
)
IP_ADC_400M_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/, \
400m/ddc_400m_saturate.vhd \
400m/adc_gearbox_8x4.v \
400m/adc_gearbox_2x4.vhd \
common/PkgRf.vhd \
common/scale_2x.vhd \
)
IP_ADC_400M_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_400m_bd/, \
adc_400m_bd.tcl \
)
IP_ADC_400M_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_400m_bd/, \
adc_400m_bd/adc_400m_bd.bd \
)
BD_ADC_400M_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/adc_400m_bd/, \
adc_400m_bd.bd.out \
adc_400m_bd/adc_400m_bd_ooc.xdc \
adc_400m_bd/synth/adc_400m_bd.v \
)
EMPTY_IP_SRCS =
$(IP_ADC_400M_BD_SRCS) $(BD_ADC_400M_BD_OUTS) $(IP_ADC_400M_BDTCL_SRCS): $(IP_ADC_400M_ORIG_SRCS) $(IP_ADC_400M_HDL_SRCS)
$(call BUILD_VIVADO_BDTCL,adc_400m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_400M_HDL_SRCS),)
top/x400/ip/adc_400m_bd/adc_400m_bd.tcl
+432
View File
@@ -0,0 +1,432 @@
################################################################
# This is a generated script based on design: adc_400m_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source adc_400m_bd_script.tcl
# The design that will be created by this Tcl script contains the following
# module references:
# adc_gearbox_2x4, adc_gearbox_8x4, ddc_400m_saturate, scale_2x
# Please add the sources of those modules before sourcing this Tcl script.
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name adc_400m_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
# Add USER_COMMENTS on $design_name
set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name]
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axis_register_slice:1.1\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:fir_compiler:7.2\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
adc_gearbox_2x4\
adc_gearbox_8x4\
ddc_400m_saturate\
scale_2x\
"
set list_mods_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ]
set_property -dict [ list \
CONFIG.FREQ_HZ {122880000} \
] $adc_data_out
set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ]
set_property -dict [ list \
CONFIG.FREQ_HZ {184320000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {16} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $adc_i_data_in
set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ]
set_property -dict [ list \
CONFIG.FREQ_HZ {184320000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {16} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $adc_q_data_in
# Create ports
set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ]
set data_clk [ create_bd_port -dir I -type clk data_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {adc_data_out_resetn_dclk} \
CONFIG.FREQ_HZ {122880000} \
] $data_clk
set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ]
set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ]
set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ]
set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {184320000} \
] $rfdc_clk
set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {fir_resetn_rclk2x} \
CONFIG.FREQ_HZ {368640000} \
] $rfdc_clk_2x
set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ]
# Create instance: adc_data_to_axi, and set properties
set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ]
set_property -dict [ list \
CONFIG.HAS_TREADY {0} \
CONFIG.REG_CONFIG {1} \
CONFIG.TDATA_NUM_BYTES {16} \
] $adc_data_to_axi
# Create instance: adc_gearbox_2x4_0, and set properties
set block_name adc_gearbox_2x4
set block_cell_name adc_gearbox_2x4_0
if { [catch {set adc_gearbox_2x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $adc_gearbox_2x4_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: adc_gearbox_8x4_0, and set properties
set block_name adc_gearbox_8x4
set block_cell_name adc_gearbox_8x4_0
if { [catch {set adc_gearbox_8x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $adc_gearbox_8x4_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: adc_i_data_from_axi, and set properties
set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ]
set_property -dict [ list \
CONFIG.REG_CONFIG {0} \
CONFIG.TDATA_NUM_BYTES {16} \
] $adc_i_data_from_axi
# Create instance: adc_q_data_from_axi, and set properties
set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ]
set_property -dict [ list \
CONFIG.REG_CONFIG {0} \
CONFIG.TDATA_NUM_BYTES {16} \
] $adc_q_data_from_axi
# Create instance: const_1, and set properties
set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ]
# Create instance: ddc_400m_saturate_0, and set properties
set block_name ddc_400m_saturate
set block_cell_name ddc_400m_saturate_0
if { [catch {set ddc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $ddc_400m_saturate_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: fir_compiler_0, and set properties
set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ]
set_property -dict [ list \
CONFIG.Clock_Frequency {384} \
CONFIG.CoefficientVector {2,5,0,-13,-20,0,40,55,0,-95,-121,0,191,236,0,-351,-422,0,599,708,0,-974,-1136,0,1534,1778,0,-2392,-2783,0,3825,4547,0,-6775,-8668,0,17881,36039,43691,36039,17881,0,-8668,-6775,0,4547,3825,0,-2783,-2392,0,1778,1534,0,-1136,-974,0,708,599,0,-422,-351,0,236,191,0,-121,-95,0,55,40,0,-20,-13,0,5,2} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {26} \
CONFIG.Decimation_Rate {3} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
CONFIG.Has_ARESETn {true} \
CONFIG.Interpolation_Rate {1} \
CONFIG.Number_Channels {1} \
CONFIG.Number_Paths {2} \
CONFIG.Output_Rounding_Mode {Convergent_Rounding_to_Even} \
CONFIG.Output_Width {17} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Reset_Data_Vector {false} \
CONFIG.S_DATA_Has_FIFO {false} \
CONFIG.Sample_Frequency {1536} \
CONFIG.Zero_Pack_Factor {1} \
] $fir_compiler_0
# Create instance: scale_2x_0, and set properties
set block_name scale_2x
set block_cell_name scale_2x_0
if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $scale_2x_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
set_property -dict [ list \
CONFIG.kDataWidth {128} \
] $scale_2x_0
# Create interface connections
connect_bd_intf_net -intf_net S_AXIS_0_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS]
connect_bd_intf_net -intf_net S_AXIS_0_2 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS]
connect_bd_intf_net -intf_net adc_data_to_axi_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS]
# Create port connections
connect_bd_net -net aclk_0_3 [get_bd_ports rfdc_clk_2x] [get_bd_pins adc_gearbox_2x4_0/Clk3x] [get_bd_pins adc_gearbox_8x4_0/clk2x] [get_bd_pins fir_compiler_0/aclk]
connect_bd_net -net adc_data_out_resetn_dclk [get_bd_ports adc_data_out_resetn_dclk] [get_bd_pins adc_data_to_axi/aresetn] [get_bd_pins adc_gearbox_2x4_0/ac1Reset_n]
connect_bd_net -net adc_gearbox_2x4_0_c1DataOut [get_bd_pins adc_gearbox_2x4_0/c1DataOut] [get_bd_pins ddc_400m_saturate_0/cDataIn]
connect_bd_net -net adc_gearbox_2x4_0_c1DataValidOut [get_bd_pins adc_gearbox_2x4_0/c1DataValidOut] [get_bd_pins ddc_400m_saturate_0/cDataValidIn]
connect_bd_net -net adc_gearbox_8x4_0_adc_out_2x [get_bd_pins adc_gearbox_8x4_0/adc_out_2x] [get_bd_pins fir_compiler_0/s_axis_data_tdata]
connect_bd_net -net adc_gearbox_8x4_0_valid_out_2x [get_bd_pins adc_gearbox_8x4_0/valid_out_2x] [get_bd_pins fir_compiler_0/s_axis_data_tvalid]
connect_bd_net -net adc_i_data_from_axi_m_axis_tdata [get_bd_pins adc_gearbox_8x4_0/adc_i_in_1x] [get_bd_pins adc_i_data_from_axi/m_axis_tdata]
connect_bd_net -net adc_q_data_from_axi_m_axis_tdata [get_bd_pins adc_gearbox_8x4_0/adc_q_in_1x] [get_bd_pins adc_q_data_from_axi/m_axis_tdata]
connect_bd_net -net adc_q_data_from_axi_m_axis_tvalid [get_bd_pins adc_gearbox_8x4_0/valid_in_1x] [get_bd_pins adc_q_data_from_axi/m_axis_tvalid]
connect_bd_net -net aresetn_0_1 [get_bd_ports fir_resetn_rclk2x] [get_bd_pins adc_gearbox_2x4_0/ac3Reset_n] [get_bd_pins fir_compiler_0/aresetn]
connect_bd_net -net const_1_dout [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout]
connect_bd_net -net data_clk_1 [get_bd_ports data_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins adc_gearbox_2x4_0/Clk1x] [get_bd_pins ddc_400m_saturate_0/Clk]
connect_bd_net -net ddc_400m_saturate_0_cDataOut [get_bd_pins ddc_400m_saturate_0/cDataOut] [get_bd_pins scale_2x_0/cDataIn]
connect_bd_net -net ddc_400m_saturate_0_cDataValidOut [get_bd_pins ddc_400m_saturate_0/cDataValidOut] [get_bd_pins scale_2x_0/cDataValidIn]
connect_bd_net -net enable_1x_0_1 [get_bd_ports enable_data_to_fir_rclk] [get_bd_pins adc_gearbox_8x4_0/enable_1x]
connect_bd_net -net fir_compiler_0_m_axis_data_tdata [get_bd_pins adc_gearbox_2x4_0/c3DataIn] [get_bd_pins fir_compiler_0/m_axis_data_tdata]
connect_bd_net -net fir_compiler_0_m_axis_data_tvalid [get_bd_pins adc_gearbox_2x4_0/c3DataValidIn] [get_bd_pins fir_compiler_0/m_axis_data_tvalid]
connect_bd_net -net reset_n_1x_0_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_gearbox_8x4_0/reset_n_1x] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn]
connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins adc_gearbox_8x4_0/clk1x] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_q_data_from_axi/aclk]
connect_bd_net -net scale_2x_0_cDataOut [get_bd_pins adc_data_to_axi/s_axis_tdata] [get_bd_pins scale_2x_0/cDataOut]
connect_bd_net -net scale_2x_0_cDataValidOut [get_bd_pins adc_data_to_axi/s_axis_tvalid] [get_bd_pins scale_2x_0/cDataValidOut]
connect_bd_net -net swap_iq_2x_0_1 [get_bd_ports swap_iq_2x] [get_bd_pins adc_gearbox_8x4_0/swap_iq_2x]
# Create address segments
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/adc_400m_bd/hdl_sources.tcl
+10
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@@ -0,0 +1,10 @@
set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
# Vivado's block diagram default library for files not belonging to any special
# library is called xil_defaultlib
read_verilog -library xil_defaultlib $script_dir/../../rf/400m/adc_gearbox_8x4.v
read_vhdl -library xil_defaultlib $script_dir/../../rf/common/PkgRf.vhd
read_vhdl -library xil_defaultlib $script_dir/../../rf/400m/adc_gearbox_2x4.vhd
read_vhdl -library xil_defaultlib $script_dir/../../rf/400m/ddc_400m_saturate.vhd
read_vhdl -library xil_defaultlib $script_dir/../../rf/common/scale_2x.vhd
top/x400/ip/adc_400m_bd/synthstub/adc_400m_bd.vhd
+48
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@@ -0,0 +1,48 @@
------------------------------------------------------------------------------------------
--
-- File: adc_400m_bd.vhd
-- Author: niBlockDesign::niBdExportStub
-- Original Project: HwBuildTools
-- Date: 21 October 2020
--
------------------------------------------------------------------------------------------
-- (c) Copyright National Instruments Corporation
-- All Rights Reserved
-- National Instruments Internal Information
------------------------------------------------------------------------------------------
--
-- Purpose: This is an automatically generated stub file to match the entity
-- declaration for 'adc_400m_bd'. This file was created using niBdExportStub
-- Do not modify this file directly!
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity adc_400m_bd is
port (
adc_data_out_resetn_dclk : in STD_LOGIC;
data_clk : in STD_LOGIC;
enable_data_to_fir_rclk : in STD_LOGIC;
fir_resetn_rclk2x : in STD_LOGIC;
rfdc_adc_axi_resetn_rclk : in STD_LOGIC;
rfdc_clk : in STD_LOGIC;
rfdc_clk_2x : in STD_LOGIC;
swap_iq_2x : in STD_LOGIC;
adc_q_data_in_tvalid : in STD_LOGIC;
adc_q_data_in_tready : out STD_LOGIC;
adc_q_data_in_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
adc_i_data_in_tvalid : in STD_LOGIC;
adc_i_data_in_tready : out STD_LOGIC;
adc_i_data_in_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
adc_data_out_tvalid : out STD_LOGIC;
adc_data_out_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 )
);
end entity adc_400m_bd;
architecture stub of adc_400m_bd is
begin
end architecture stub;
top/x400/ip/axi64_4k_2clk_fifo/Makefile.inc
+21
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@@ -0,0 +1,21 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \
axi64_4k_2clk_fifo_sim_netlist.v \
)
IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \
axi64_4k_2clk_fifo.xci.out \
synth/axi64_4k_2clk_fifo.vhd \
)
$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
$(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x400/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
+584
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@@ -0,0 +1,584 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axi64_4k_2clk_fifo</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Clock_Type_AXI" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_Data_Counts_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_TLAST" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_rdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wdch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_Implementation_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INTERFACE_TYPE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth_axis" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/x400/ip/axi_eth_dma_bd/Makefile.inc
+31
View File
@@ -0,0 +1,31 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_ETH_DMA_BD_HDL_SRCS = $(addprefix $(IP_DIR)/axi_eth_dma_bd/, \
axi_eth_dma.sv \
)
IP_AXI_ETH_DMA_BD_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_eth_dma_bd/, \
axi_eth_dma_bd.tcl \
)
IP_AXI_ETH_DMA_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \
axi_eth_dma_bd.tcl \
)
IP_AXI_ETH_DMA_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \
axi_eth_dma_bd/axi_eth_dma_bd.bd \
)
BD_AXI_ETH_DMA_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \
axi_eth_dma_bd.bd.out \
axi_eth_dma_bd/synth/axi_eth_dma_bd.v \
)
$(IP_AXI_ETH_DMA_BD_SRCS) $(BD_AXI_ETH_DMA_BD_OUTS) $(IP_AXI_ETH_DMA_BDTCL_SRCS): $(IP_AXI_ETH_DMA_BD_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_eth_dma_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_eth_dma_bd/axi_eth_dma.sv
+73
View File
@@ -0,0 +1,73 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: axi_eth_dma
//
// Description: Wrapper for the Xilinx AXI DMA
//
module axi_eth_dma (
// All interfaces on s_axi_eth_dma.clk domain
AxiStreamIf.slave e2c, // from enet mac
AxiStreamIf.master c2e, // to enet mac
AxiLiteIf.slave s_axi_eth_dma, // Register interface
AxiIf.master axi_hp, // DMA interface to host memory
output logic eth_rx_irq,
output logic eth_tx_irq
);
`include "../../../../lib/axi4lite_sv/axi_lite.vh"
`include "../../../../lib/axi4s_sv/axi4s.vh"
`include "../../../../lib/axi4_sv/axi.vh"
// _v versions have no procedural assignment so they can drive a port.
AxiLiteIf_v #(32,10)
s_axi_eth_dma_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst));
AxiIf_v #(128,49)
axi_hp_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst));
AxiStreamIf #(.DATA_WIDTH(c2e.DATA_WIDTH), .USER_WIDTH(c2e.USER_WIDTH), .TUSER(0))
c2e_v (c2e.clk, c2e.rst);
AxiStreamIf #(.DATA_WIDTH(e2c.DATA_WIDTH), .USER_WIDTH(e2c.USER_WIDTH), .TUSER(0))
e2c_v (e2c.clk, e2c.rst);
always_comb begin
// O = I; (O , I )
`AXI4LITE_ASSIGN(s_axi_eth_dma_v, s_axi_eth_dma)
// Overriding assignments to mask off upper address bits
s_axi_eth_dma_v.araddr = 0;
s_axi_eth_dma_v.araddr[9:0] = s_axi_eth_dma.araddr[9:0];
s_axi_eth_dma_v.awaddr = 0;
s_axi_eth_dma_v.awaddr[9:0] = s_axi_eth_dma.awaddr[9:0];
end
always_comb begin `AXI4S_ASSIGN(e2c_v, e2c) end
always_comb begin `AXI4S_ASSIGN(c2e, c2e_v) end
always_comb begin `AXI4_ASSIGN(axi_hp, axi_hp_v) end
axi_eth_dma_bd axi_eth_dma_bd_i (
.clk40 (s_axi_eth_dma.clk),
.clk40_rstn (!s_axi_eth_dma.rst),
.c2e_tdata (c2e_v.tdata),
.c2e_tkeep (c2e_v.tkeep),
.c2e_tlast (c2e_v.tlast),
.c2e_tready (c2e_v.tready),
.c2e_tvalid (c2e_v.tvalid),
.e2c_tdata (e2c_v.tdata),
.e2c_tkeep (e2c_v.tkeep),
.e2c_tlast (e2c_v.tlast),
.e2c_tready (e2c_v.tready),
.e2c_tvalid (e2c_v.tvalid),
`AXI4LITE_PORT_ASSIGN_NRS(axi_eth_dma, s_axi_eth_dma_v)
`AXI4_PORT_ASSIGN_NR(axi_hp, axi_hp_v)
.eth_tx_irq (eth_tx_irq),
.eth_rx_irq (eth_rx_irq)
);
endmodule
top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl
+325
View File
@@ -0,0 +1,325 @@
################################################################
# This is a generated script based on design: axi_eth_dma_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_eth_dma_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_eth_dma_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:smartconnect:1.0\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set axi_eth_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 axi_eth_dma ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {0} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {1} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4LITE} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $axi_eth_dma
set axi_hp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 axi_hp ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {49} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_REGION {0} \
CONFIG.NUM_READ_OUTSTANDING {16} \
CONFIG.NUM_WRITE_OUTSTANDING {16} \
CONFIG.PROTOCOL {AXI4} \
] $axi_hp
set c2e [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 c2e ]
set_property -dict [ list \
CONFIG.FREQ_HZ {40000000} \
] $c2e
set e2c [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 e2c ]
set_property -dict [ list \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_TKEEP {1} \
CONFIG.HAS_TLAST {1} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {8} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $e2c
# Create ports
set clk40 [ create_bd_port -dir I -type clk clk40 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {e2c:axi_eth_dma:axi_hp:c2e} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
set eth_rx_irq [ create_bd_port -dir O -type intr eth_rx_irq ]
set eth_tx_irq [ create_bd_port -dir O -type intr eth_tx_irq ]
# Create instance: axi_eth_dma, and set properties
set axi_eth_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_eth_dma ]
set_property -dict [ list \
CONFIG.c_addr_width {36} \
CONFIG.c_enable_multi_channel {0} \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_m_axi_mm2s_data_width {64} \
CONFIG.c_m_axi_s2mm_data_width {64} \
CONFIG.c_m_axis_mm2s_tdata_width {64} \
CONFIG.c_micro_dma {0} \
CONFIG.c_mm2s_burst_size {8} \
CONFIG.c_s2mm_burst_size {16} \
CONFIG.c_sg_include_stscntrl_strm {0} \
] $axi_eth_dma
# Create instance: smartconnect_eth_dma, and set properties
set smartconnect_eth_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_eth_dma ]
set_property -dict [ list \
CONFIG.NUM_SI {3} \
] $smartconnect_eth_dma
# Create interface connections
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_ports c2e] [get_bd_intf_pins axi_eth_dma/M_AXIS_MM2S]
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_ports e2c] [get_bd_intf_pins axi_eth_dma/S_AXIS_S2MM]
connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_MM2S [get_bd_intf_pins axi_eth_dma/M_AXI_MM2S] [get_bd_intf_pins smartconnect_eth_dma/S01_AXI]
connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_S2MM [get_bd_intf_pins axi_eth_dma/M_AXI_S2MM] [get_bd_intf_pins smartconnect_eth_dma/S02_AXI]
connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_SG [get_bd_intf_pins axi_eth_dma/M_AXI_SG] [get_bd_intf_pins smartconnect_eth_dma/S00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_eth_dma_ctrl [get_bd_intf_ports axi_eth_dma] [get_bd_intf_pins axi_eth_dma/S_AXI_LITE]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_ports axi_hp] [get_bd_intf_pins smartconnect_eth_dma/M00_AXI]
# Create port connections
connect_bd_net -net axi_eth_dma_mm2s_introut [get_bd_ports eth_tx_irq] [get_bd_pins axi_eth_dma/mm2s_introut]
connect_bd_net -net axi_eth_dma_s2mm_introut [get_bd_ports eth_rx_irq] [get_bd_pins axi_eth_dma/s2mm_introut]
connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_eth_dma/m_axi_mm2s_aclk] [get_bd_pins axi_eth_dma/m_axi_s2mm_aclk] [get_bd_pins axi_eth_dma/m_axi_sg_aclk] [get_bd_pins axi_eth_dma/s_axi_lite_aclk] [get_bd_pins smartconnect_eth_dma/aclk]
connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_eth_dma/axi_resetn] [get_bd_pins smartconnect_eth_dma/aresetn]
# Create address segments
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_SG] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_MM2S] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_S2MM] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
create_bd_addr_seg -range 0x010000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma] [get_bd_addr_segs axi_eth_dma/S_AXI_LITE/Reg] SEG_axi_eth_dma_Reg
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/axi_eth_dma_bd/synthstub/axi_eth_dma_bd.vhd
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--
-- Copyright 2021 Ettus Research, a National Instruments Brand
--
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: axi_eth_dma_bd
--
-- Description:
--
-- This is an automatically generated stub file to match the entity
-- declaration for 'axi_eth_dma_bd'. This file was created using
-- niBdExportStub Do not modify this file directly!
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity axi_eth_dma_bd is
port (
clk40 : in STD_LOGIC;
clk40_rstn : in STD_LOGIC;
eth_rx_irq : out STD_LOGIC;
eth_tx_irq : out STD_LOGIC;
c2e_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
c2e_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
c2e_tlast : out STD_LOGIC;
c2e_tready : in STD_LOGIC;
c2e_tvalid : out STD_LOGIC;
e2c_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
e2c_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
e2c_tlast : in STD_LOGIC;
e2c_tready : out STD_LOGIC;
e2c_tvalid : in STD_LOGIC;
axi_eth_dma_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_eth_dma_arready : out STD_LOGIC;
axi_eth_dma_arvalid : in STD_LOGIC;
axi_eth_dma_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_eth_dma_awready : out STD_LOGIC;
axi_eth_dma_awvalid : in STD_LOGIC;
axi_eth_dma_bready : in STD_LOGIC;
axi_eth_dma_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
axi_eth_dma_bvalid : out STD_LOGIC;
axi_eth_dma_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
axi_eth_dma_rready : in STD_LOGIC;
axi_eth_dma_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
axi_eth_dma_rvalid : out STD_LOGIC;
axi_eth_dma_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
axi_eth_dma_wready : out STD_LOGIC;
axi_eth_dma_wvalid : in STD_LOGIC;
axi_hp_awaddr : out STD_LOGIC_VECTOR ( 48 downto 0 );
axi_hp_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
axi_hp_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
axi_hp_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
axi_hp_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
axi_hp_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_hp_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
axi_hp_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_hp_awvalid : out STD_LOGIC;
axi_hp_awready : in STD_LOGIC;
axi_hp_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
axi_hp_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
axi_hp_wlast : out STD_LOGIC;
axi_hp_wvalid : out STD_LOGIC;
axi_hp_wready : in STD_LOGIC;
axi_hp_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
axi_hp_bvalid : in STD_LOGIC;
axi_hp_bready : out STD_LOGIC;
axi_hp_araddr : out STD_LOGIC_VECTOR ( 48 downto 0 );
axi_hp_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
axi_hp_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
axi_hp_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
axi_hp_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
axi_hp_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_hp_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
axi_hp_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_hp_arvalid : out STD_LOGIC;
axi_hp_arready : in STD_LOGIC;
axi_hp_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
axi_hp_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
axi_hp_rlast : in STD_LOGIC;
axi_hp_rvalid : in STD_LOGIC;
axi_hp_rready : out STD_LOGIC
);
end entity axi_eth_dma_bd;
architecture stub of axi_eth_dma_bd is
begin
end architecture stub;
top/x400/ip/axi_interconnect_app_bd/Makefile.inc
+28
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTERCONNECT_APP_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_app_bd/, \
axi_interconnect_app_bd.tcl \
)
IP_AXI_INTERCONNECT_APP_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_app_bd/, \
axi_interconnect_app_bd.tcl \
)
IP_AXI_INTERCONNECT_APP_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_app_bd/, \
axi_interconnect_app_bd/axi_interconnect_app_bd.bd \
)
BD_AXI_INTERCONNECT_APP_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_app_bd/, \
axi_interconnect_app_bd.bd.out \
axi_interconnect_app_bd/axi_interconnect_app_bd_ooc.xdc \
axi_interconnect_app_bd/synth/axi_interconnect_app_bd.v \
)
$(IP_AXI_INTERCONNECT_APP_BD_SRCS) $(BD_AXI_INTERCONNECT_APP_BD_OUTS) $(IP_AXI_INTERCONNECT_APP_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_APP_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_interconnect_app_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_interconnect_app_bd/axi_interconnect_app_bd.tcl
+303
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################################################################
# This is a generated script based on design: axi_interconnect_app_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_interconnect_app_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_interconnect_app_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set m_axi_qsfp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_qsfp0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_qsfp0
set m_axi_qsfp1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_qsfp1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_WSTRB {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_qsfp1
set s_axi_app [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_app ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {1} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {4} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {4} \
CONFIG.PROTOCOL {AXI4LITE} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi_app
# Create ports
set clk40 [ create_bd_port -dir I -type clk clk40 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axi_qsfp0:m_axi_qsfp1:s_axi_app} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \
CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {2} \
] $axi_interconnect_0
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_app] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_qsfp0] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_qsfp1] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
# Create port connections
connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK]
connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN]
# Create address segments
create_bd_addr_seg -range 0x00040000 -offset 0x001200000000 [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp0/Reg] SEG_m_axi_qsfp0_Reg
create_bd_addr_seg -range 0x00040000 -offset 0x001200040000 [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp1/Reg] SEG_m_axi_qsfp1_Reg
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/axi_interconnect_dma_bd/Makefile.inc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTERCONNECT_DMA_HDL_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_dma_bd/, \
axi_interconnect_dma.sv \
)
IP_AXI_INTERCONNECT_DMA_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
sim/axi_interconnect_dma_bd.v\
ip/axi_interconnect_dma_bd_xbar_0/sim/axi_interconnect_dma_bd_xbar_0.v\
ipshared/*/simulation/fifo_generator_vlog_beh.v\
ipshared/*/hdl/*.v\
))
IP_AXI_INTERCONNECT_DMA_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_dma_bd/, \
axi_interconnect_dma_bd.tcl \
)
IP_AXI_INTERCONNECT_DMA_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \
axi_interconnect_dma_bd.tcl \
)
IP_AXI_INTERCONNECT_DMA_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \
axi_interconnect_dma_bd/axi_interconnect_dma_bd.bd \
)
BD_AXI_INTERCONNECT_DMA_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \
axi_interconnect_dma_bd.bd.out \
axi_interconnect_dma_bd/axi_interconnect_dma_bd_ooc.xdc \
axi_interconnect_dma_bd/synth/axi_interconnect_dma_bd.v \
)
$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) $(BD_AXI_INTERCONNECT_DMA_BD_OUTS) $(IP_AXI_INTERCONNECT_DMA_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_DMA_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_interconnect_dma_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv
+40
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: axi_interconnect_dma
//
// Description: Wrapper for the Xilinx AXI interconnect block
//
module axi_interconnect_dma (
AxiIf.slave s_axi_hp_dma [3:0], // Incoming AXI from DMA engines
AxiIf.master m_axi_hp // Outgoing AXI to memory
);
// AxiIf_v has no procedural assignments so it can be driven by a port.
`include "../../../../lib/axi4_sv/axi.vh"
AxiIf_v #(128,49)
m_axi_hp_v(.clk(m_axi_hp.clk), .rst(m_axi_hp.rst));
AxiIf_v #(128,49)
s_axi_hp_dma_v[3:0](.clk(m_axi_hp.clk), .rst(m_axi_hp.rst));
// O = I; (O , I )
always_comb begin `AXI4_ASSIGN(m_axi_hp, m_axi_hp_v) end
always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[0], s_axi_hp_dma[0]) end
always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[1], s_axi_hp_dma[1]) end
always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[2], s_axi_hp_dma[2]) end
always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[3], s_axi_hp_dma[3]) end
axi_interconnect_dma_bd axi_interconnect_dma_bd_i (
`AXI4_PORT_ASSIGN_NR(m_axi_hp, m_axi_hp_v)
`AXI4_PORT_ASSIGN_NR(s_axi_hp_dma0, s_axi_hp_dma_v[0])
`AXI4_PORT_ASSIGN_NR(s_axi_hp_dma1, s_axi_hp_dma_v[1])
`AXI4_PORT_ASSIGN_NR(s_axi_hp_dma2, s_axi_hp_dma_v[2])
`AXI4_PORT_ASSIGN_NR(s_axi_hp_dma3, s_axi_hp_dma_v[3])
.clk40 (m_axi_hp.clk),
.clk40_rstn (!m_axi_hp.rst)
);
endmodule
top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl
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################################################################
# This is a generated script based on design: axi_interconnect_dma_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_interconnect_dma_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_interconnect_dma_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set m_axi_hp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_hp ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {49} \
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {0} \
CONFIG.NUM_READ_OUTSTANDING {16} \
CONFIG.NUM_WRITE_OUTSTANDING {16} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
] $m_axi_hp
set s_axi_hp_dma0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {49} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {16} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {4} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {4} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi_hp_dma0
set s_axi_hp_dma1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {49} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {16} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {4} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {4} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi_hp_dma1
set s_axi_hp_dma2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma2 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {49} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {16} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {4} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {4} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi_hp_dma2
set s_axi_hp_dma3 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma3 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {49} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
CONFIG.DATA_WIDTH {128} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {1} \
CONFIG.HAS_CACHE {1} \
CONFIG.HAS_LOCK {1} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {1} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {16} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {4} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {4} \
CONFIG.PROTOCOL {AXI4} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi_hp_dma3
# Create ports
set clk40 [ create_bd_port -dir I -type clk clk40 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {s_axi_hp_dma0:s_axi_hp_dma1:s_axi_hp_dma2:s_axi_hp_dma3:m_axi_hp} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.ENABLE_ADVANCED_OPTIONS {1} \
CONFIG.M00_HAS_DATA_FIFO {1} \
CONFIG.M00_HAS_REGSLICE {4} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {4} \
CONFIG.S00_HAS_DATA_FIFO {1} \
CONFIG.S00_HAS_REGSLICE {4} \
CONFIG.S01_ARB_PRIORITY {0} \
CONFIG.S01_HAS_DATA_FIFO {1} \
CONFIG.S01_HAS_REGSLICE {4} \
CONFIG.S02_ARB_PRIORITY {0} \
CONFIG.S02_HAS_DATA_FIFO {1} \
CONFIG.S02_HAS_REGSLICE {4} \
CONFIG.S03_ARB_PRIORITY {0} \
CONFIG.S03_HAS_DATA_FIFO {1} \
CONFIG.S03_HAS_REGSLICE {4} \
CONFIG.STRATEGY {1} \
] $axi_interconnect_0
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_hp_dma0] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_hp] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net s_axi_eth1_1 [get_bd_intf_ports s_axi_hp_dma1] [get_bd_intf_pins axi_interconnect_0/S01_AXI]
connect_bd_intf_net -intf_net s_axi_eth2_1 [get_bd_intf_ports s_axi_hp_dma2] [get_bd_intf_pins axi_interconnect_0/S02_AXI]
connect_bd_intf_net -intf_net s_axi_eth3_1 [get_bd_intf_ports s_axi_hp_dma3] [get_bd_intf_pins axi_interconnect_0/S03_AXI]
# Create port connections
connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/S02_ACLK] [get_bd_pins axi_interconnect_0/S03_ACLK]
connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/S02_ARESETN] [get_bd_pins axi_interconnect_0/S03_ARESETN]
# Create address segments
create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma0] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma1] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma2] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma3] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/axi_interconnect_eth_bd/Makefile.inc
+41
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_AXI_INTERCONNECT_ETH_HDL_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_eth_bd/, \
axi_interconnect_eth.sv \
)
IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/axi_interconnect_eth_bd/, \
sim/axi_interconnect_eth_bd.v\
ip/axi_interconnect_eth_bd_xbar_0/sim/axi_interconnect_eth_bd_xbar_0.v\
ipshared/*/simulation/fifo_generator_vlog_beh.v\
ipshared/*/hdl/*.v\
))
IP_AXI_INTERCONNECT_ETH_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_eth_bd/, \
axi_interconnect_eth_bd.tcl \
)
IP_AXI_INTERCONNECT_ETH_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \
axi_interconnect_eth_bd.tcl \
)
IP_AXI_INTERCONNECT_ETH_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \
axi_interconnect_eth_bd/axi_interconnect_eth_bd.bd \
)
BD_AXI_INTERCONNECT_ETH_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \
axi_interconnect_eth_bd.bd.out \
axi_interconnect_eth_bd/synth/axi_interconnect_eth_bd.v \
axi_interconnect_eth_bd/axi_interconnect_eth_bd_ooc.xdc \
)
$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) $(BD_AXI_INTERCONNECT_ETH_BD_OUTS) $(IP_AXI_INTERCONNECT_ETH_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_ETH_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,axi_interconnect_eth_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth.sv
+98
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: axi_interconnect_eth
//
// Description:
//
// Wrapper for the Xilinx AXI Lite interconnect block
//
module axi_interconnect_eth (
// All interfaces on s_axi_eth.clk domain
AxiLiteIf.master m_axi_dma[3:0], // maps to CPU_DMA +0x00000-0x07FFF
AxiLiteIf.master m_axi_misc[3:0], // maps to nixge +0x08000-0x09FFF
// UIO +0x0A000-0x0BFFF
AxiLiteIf.master m_axi_mac[3:0], // maps to 100G Mac +0x0C000-0x0DFFF
AxiLiteIf.slave s_axi_eth // incoming axi_net bus
);
// AxiLiteIf_v has no procedural assignments so it can be
// driven by a port.
`include "../../../../lib/axi4lite_sv/axi_lite.vh"
AxiLiteIf_v #(32,40)
m_axi_dma_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
AxiLiteIf_v #(32,40)
m_axi_misc_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
AxiLiteIf_v #(32,40)
m_axi_mac_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
AxiLiteIf_v #(32,40)
s_axi_eth_v(.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
// O = I;(O ,I )
always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[0],m_axi_dma_v[0]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[1],m_axi_dma_v[1]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[2],m_axi_dma_v[2]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[3],m_axi_dma_v[3]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[0],m_axi_misc_v[0]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[1],m_axi_misc_v[1]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[2],m_axi_misc_v[2]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[3],m_axi_misc_v[3]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[0],m_axi_mac_v[0]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[1],m_axi_mac_v[1]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[2],m_axi_mac_v[2]) end
always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[3],m_axi_mac_v[3]) end
always_comb begin `AXI4LITE_ASSIGN(s_axi_eth_v,s_axi_eth) end
axi_interconnect_eth_bd axi_interconnect_eth_bd_i
(
`AXI4LITE_PORT_ASSIGN_NR(m_axi_dma0,m_axi_dma_v[0])
.m_axi_dma0_arprot(),
.m_axi_dma0_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_dma1,m_axi_dma_v[1])
.m_axi_dma1_arprot(),
.m_axi_dma1_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_dma2,m_axi_dma_v[2])
.m_axi_dma2_arprot(),
.m_axi_dma2_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_dma3,m_axi_dma_v[3])
.m_axi_dma3_arprot(),
.m_axi_dma3_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_mac0,m_axi_mac_v[0])
.m_axi_mac0_arprot(),
.m_axi_mac0_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_mac1,m_axi_mac_v[1])
.m_axi_mac1_arprot(),
.m_axi_mac1_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_mac2,m_axi_mac_v[2])
.m_axi_mac2_arprot(),
.m_axi_mac2_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_mac3,m_axi_mac_v[3])
.m_axi_mac3_arprot(),
.m_axi_mac3_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_misc0,m_axi_misc_v[0])
.m_axi_misc0_arprot(),
.m_axi_misc0_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_misc1,m_axi_misc_v[1])
.m_axi_misc1_arprot(),
.m_axi_misc1_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_misc2,m_axi_misc_v[2])
.m_axi_misc2_arprot(),
.m_axi_misc2_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(m_axi_misc3,m_axi_misc_v[3])
.m_axi_misc3_arprot(),
.m_axi_misc3_awprot(),
`AXI4LITE_PORT_ASSIGN_NR(s_axi_eth,s_axi_eth_v)
.s_axi_eth_arprot(3'b0),
.s_axi_eth_awprot(3'b0),
.clk40(s_axi_eth.clk),
.clk40_rstn(!s_axi_eth.rst));
endmodule
top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl
+462
View File
@@ -0,0 +1,462 @@
################################################################
# This is a generated script based on design: axi_interconnect_eth_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source axi_interconnect_eth_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name axi_interconnect_eth_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set m_axi_dma0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_dma0
set m_axi_dma1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_dma1
set m_axi_dma2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma2 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_dma2
set m_axi_dma3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma3 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_dma3
set m_axi_mac0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_mac0
set m_axi_mac1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_mac1
set m_axi_mac2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac2 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_mac2
set m_axi_mac3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac3 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_mac3
set m_axi_misc0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc0 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.NUM_READ_OUTSTANDING {2} \
CONFIG.NUM_WRITE_OUTSTANDING {2} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_misc0
set m_axi_misc1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc1 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_misc1
set m_axi_misc2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc2 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_misc2
set m_axi_misc3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc3 ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.PROTOCOL {AXI4LITE} \
] $m_axi_misc3
set s_axi_eth [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {40} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.DATA_WIDTH {32} \
CONFIG.FREQ_HZ {40000000} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {1} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {1} \
CONFIG.NUM_READ_OUTSTANDING {8} \
CONFIG.NUM_READ_THREADS {4} \
CONFIG.NUM_WRITE_OUTSTANDING {8} \
CONFIG.NUM_WRITE_THREADS {4} \
CONFIG.PROTOCOL {AXI4LITE} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi_eth
# Create ports
set clk40 [ create_bd_port -dir I -type clk clk40 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {m_axi_misc0:m_axi_mac0:s_axi_eth:m_axi_misc3:m_axi_mac3:m_axi_dma1:m_axi_misc1:m_axi_mac2:m_axi_dma2:m_axi_mac1:m_axi_misc2:m_axi_dma0:m_axi_dma3} \
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
CONFIG.FREQ_HZ {40000000} \
] $clk40
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {12} \
] $axi_interconnect_0
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_eth] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_misc0] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_mac0] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports m_axi_dma0] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports m_axi_misc1] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports m_axi_mac1] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports m_axi_dma1] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports m_axi_misc2] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports m_axi_mac2] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_ports m_axi_dma2] [get_bd_intf_pins axi_interconnect_0/M08_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_ports m_axi_misc3] [get_bd_intf_pins axi_interconnect_0/M09_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_ports m_axi_mac3] [get_bd_intf_pins axi_interconnect_0/M10_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_ports m_axi_dma3] [get_bd_intf_pins axi_interconnect_0/M11_AXI]
# Create port connections
connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK]
connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN]
# Create address segments
create_bd_addr_seg -range 0x00008000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] SEG_m_axi_dma0_Reg
create_bd_addr_seg -range 0x00008000 -offset 0x00010000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] SEG_m_axi_dma1_Reg
create_bd_addr_seg -range 0x00008000 -offset 0x00020000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] SEG_m_axi_dma2_Reg
create_bd_addr_seg -range 0x00008000 -offset 0x00030000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] SEG_m_axi_dma3_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x0000C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] SEG_m_axi_mac0_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x0001C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] SEG_m_axi_mac1_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x0002C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] SEG_m_axi_mac2_Reg
create_bd_addr_seg -range 0x00002000 -offset 0x0003C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] SEG_m_axi_mac3_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x00008000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] SEG_m_axi_misc0_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x00018000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] SEG_m_axi_misc1_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x00028000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] SEG_m_axi_misc2_Reg
create_bd_addr_seg -range 0x00004000 -offset 0x00038000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] SEG_m_axi_misc3_Reg
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/dac_100m_bd/.gitignore
+1
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@@ -0,0 +1 @@
synthstub/
top/x400/ip/dac_100m_bd/Makefile.inc
+36
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_DAC_100M_ORIG_SRCS = $(addprefix $(IP_DIR)/dac_100m_bd/, \
dac_100m_bd.tcl \
)
IP_DAC_100M_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/100m/, \
duc_saturate.vhd \
dac_1_3_clk_converter.vhd \
dac_2_1_clk_converter.vhd \
)
IP_DAC_100M_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/dac_100m_bd/, \
dac_100m_bd.tcl \
)
IP_DAC_100M_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/dac_100m_bd/, \
dac_100m_bd/dac_100m_bd.bd \
)
BD_DAC_100M_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/dac_100m_bd/, \
dac_100m_bd.bd.out \
dac_100m_bd/dac_100m_bd_ooc.xdc \
dac_100m_bd/synth/dac_100m_bd.v \
)
EMPTY_IP_SRCS =
$(IP_DAC_100M_BD_SRCS) $(BD_DAC_100M_BD_OUTS) $(IP_DAC_100M_BDTCL_SRCS): $(IP_DAC_100M_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,dac_100m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_DAC_100M_HDL_SRCS),)
top/x400/ip/dac_100m_bd/dac_100m_bd.tcl
+389
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################################################################
# This is a generated script based on design: dac_100m_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source dac_100m_bd_script.tcl
# The design that will be created by this Tcl script contains the following
# module references:
# dac_1_3_clk_converter, dac_2_1_clk_converter, duc_saturate
# Please add the sources of those modules before sourcing this Tcl script.
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name dac_100m_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:fir_compiler:7.2\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:axis_register_slice:1.1\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
dac_1_3_clk_converter\
dac_2_1_clk_converter\
duc_saturate\
"
set list_mods_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set dac_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_data_in ]
set_property -dict [ list \
CONFIG.FREQ_HZ {122880000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {4} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $dac_data_in
set dac_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 dac_data_out ]
set_property -dict [ list \
CONFIG.FREQ_HZ {184320000} \
] $dac_data_out
# Create ports
set dac_data_in_resetn_dclk [ create_bd_port -dir I -type rst dac_data_in_resetn_dclk ]
set dac_data_in_resetn_rclk [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk ]
set dac_data_in_resetn_rclk2x [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk2x ]
set data_clk [ create_bd_port -dir I -type clk data_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {dac_data_in} \
CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_dclk} \
CONFIG.FREQ_HZ {122880000} \
] $data_clk
set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {dac_data_out} \
CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_rclk} \
CONFIG.FREQ_HZ {184320000} \
] $rfdc_clk
set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_rclk2x} \
CONFIG.FREQ_HZ {368640000} \
] $rfdc_clk_2x
# Create instance: constant_high, and set properties
set constant_high [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_high ]
# Create instance: dac_1_3_clk_converter_0, and set properties
set block_name dac_1_3_clk_converter
set block_cell_name dac_1_3_clk_converter_0
if { [catch {set dac_1_3_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $dac_1_3_clk_converter_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: dac_2_1_clk_converter_0, and set properties
set block_name dac_2_1_clk_converter
set block_cell_name dac_2_1_clk_converter_0
if { [catch {set dac_2_1_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $dac_2_1_clk_converter_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: dac_interpolator, and set properties
set dac_interpolator [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 dac_interpolator ]
set_property -dict [ list \
CONFIG.Clock_Frequency {368.64} \
CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Symmetric} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {14} \
CONFIG.Data_Fractional_Bits {0} \
CONFIG.Data_Width {16} \
CONFIG.Decimation_Rate {1} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Interpolation} \
CONFIG.Has_ARESETn {true} \
CONFIG.Interpolation_Rate {3} \
CONFIG.M_DATA_Has_TREADY {false} \
CONFIG.Number_Channels {1} \
CONFIG.Number_Paths {2} \
CONFIG.Output_Rounding_Mode {Convergent_Rounding_to_Even} \
CONFIG.Output_Width {18} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Reset_Data_Vector {false} \
CONFIG.S_DATA_Has_FIFO {false} \
CONFIG.Sample_Frequency {122.88} \
CONFIG.Zero_Pack_Factor {1} \
] $dac_interpolator
# Create instance: data_combiner, and set properties
set data_combiner [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 data_combiner ]
set_property -dict [ list \
CONFIG.IN0_WIDTH {32} \
CONFIG.IN1_WIDTH {32} \
] $data_combiner
# Create instance: duc_saturate, and set properties
set block_name duc_saturate
set block_cell_name duc_saturate
if { [catch {set duc_saturate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $duc_saturate eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: registered_dac_data, and set properties
set registered_dac_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 registered_dac_data ]
set_property -dict [ list \
CONFIG.REG_CONFIG {1} \
CONFIG.TDATA_NUM_BYTES {4} \
] $registered_dac_data
# Create interface connections
connect_bd_intf_net -intf_net dac_1_3_clk_converter_0_m_axis [get_bd_intf_pins dac_1_3_clk_converter_0/m_axis] [get_bd_intf_pins dac_interpolator/S_AXIS_DATA]
connect_bd_intf_net -intf_net dac_2_1_clk_converter_0_m_axis [get_bd_intf_ports dac_data_out] [get_bd_intf_pins dac_2_1_clk_converter_0/m_axis]
connect_bd_intf_net -intf_net dac_data_in_1 [get_bd_intf_ports dac_data_in] [get_bd_intf_pins dac_1_3_clk_converter_0/s_axis]
# Create port connections
connect_bd_net -net aclk_0_1 [get_bd_ports data_clk] [get_bd_pins dac_1_3_clk_converter_0/s_axis_aclk]
connect_bd_net -net aresetn_0_1 [get_bd_ports dac_data_in_resetn_dclk] [get_bd_pins dac_1_3_clk_converter_0/s_axis_aresetn]
connect_bd_net -net axis_register_slice_0_m_axis_tdata [get_bd_pins data_combiner/In0] [get_bd_pins registered_dac_data/m_axis_tdata]
connect_bd_net -net dac_data_in_resetn_rclk2x [get_bd_ports dac_data_in_resetn_rclk2x] [get_bd_pins dac_1_3_clk_converter_0/m_axis_aresetn] [get_bd_pins dac_2_1_clk_converter_0/s_axis_aresetn] [get_bd_pins dac_interpolator/aresetn] [get_bd_pins registered_dac_data/aresetn]
connect_bd_net -net dac_data_in_resetn_rclk_1 [get_bd_ports dac_data_in_resetn_rclk] [get_bd_pins dac_2_1_clk_converter_0/m_axis_aresetn]
connect_bd_net -net dac_interpolator_m_axis_data_tdata [get_bd_pins dac_interpolator/m_axis_data_tdata] [get_bd_pins duc_saturate/cDataIn]
connect_bd_net -net dac_interpolator_m_axis_data_tvalid [get_bd_pins dac_interpolator/m_axis_data_tvalid] [get_bd_pins duc_saturate/cDataValidIn]
connect_bd_net -net data_combiner_dout [get_bd_pins dac_2_1_clk_converter_0/s_axis_tdata] [get_bd_pins data_combiner/dout]
connect_bd_net -net ddc_saturate_0_cDataOut [get_bd_pins data_combiner/In1] [get_bd_pins duc_saturate/cDataOut] [get_bd_pins registered_dac_data/s_axis_tdata]
connect_bd_net -net duc_saturate_0_cDataValidOut [get_bd_pins duc_saturate/cDataValidOut] [get_bd_pins registered_dac_data/s_axis_tvalid]
connect_bd_net -net m_axis_aclk_0_1 [get_bd_ports rfdc_clk_2x] [get_bd_pins dac_1_3_clk_converter_0/m_axis_aclk] [get_bd_pins dac_2_1_clk_converter_0/s_axis_aclk] [get_bd_pins dac_interpolator/aclk] [get_bd_pins duc_saturate/Clk] [get_bd_pins registered_dac_data/aclk]
connect_bd_net -net registered_dac_data_m_axis_tvalid [get_bd_pins dac_2_1_clk_converter_0/s_axis_tvalid] [get_bd_pins registered_dac_data/m_axis_tvalid]
connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins dac_2_1_clk_converter_0/m_axis_aclk]
connect_bd_net -net xlconstant_0_dout [get_bd_pins constant_high/dout] [get_bd_pins registered_dac_data/m_axis_tready]
# Create address segments
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/dac_100m_bd/hdl_sources.tcl
+6
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set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_vhdl -library work $script_dir/../../rf/100m/duc_saturate.vhd
read_vhdl -library work $script_dir/../../rf/100m/dac_1_3_clk_converter.vhd
read_vhdl -library work $script_dir/../../rf/100m/dac_2_1_clk_converter.vhd
top/x400/ip/dac_400m_bd/Makefile.inc
+38
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_DAC_400M_ORIG_SRCS = $(addprefix $(IP_DIR)/dac_400m_bd/, \
dac_400m_bd.tcl \
)
IP_DAC_400M_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/400m/, \
duc_400m_saturate.vhd \
dac_gearbox_6x8.vhd \
dac_gearbox_6x12.vhd \
dac_gearbox_12x8.vhd \
dac_gearbox_4x2.v \
)
IP_DAC_400M_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/dac_400m_bd/, \
dac_400m_bd.tcl \
)
IP_DAC_400M_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/dac_400m_bd/, \
dac_400m_bd/dac_400m_bd.bd \
)
BD_DAC_400M_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/dac_400m_bd/, \
dac_400m_bd.bd.out \
dac_400m_bd/dac_400m_bd_ooc.xdc \
dac_400m_bd/synth/dac_400m_bd.v \
)
EMPTY_IP_SRCS =
$(IP_DAC_400M_BD_SRCS) $(BD_DAC_400M_BD_OUTS) $(IP_DAC_400M_BDTCL_SRCS): $(IP_DAC_400M_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,dac_400m_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_DAC_400M_HDL_SRCS),)
top/x400/ip/dac_400m_bd/dac_400m_bd.tcl
+348
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################################################################
# This is a generated script based on design: dac_400m_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source dac_400m_bd_script.tcl
# The design that will be created by this Tcl script contains the following
# module references:
# dac_gearbox_4x2, dac_gearbox_6x8, duc_400m_saturate
# Please add the sources of those modules before sourcing this Tcl script.
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name dac_400m_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:fir_compiler:7.2\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
dac_gearbox_4x2\
dac_gearbox_6x8\
duc_400m_saturate\
"
set list_mods_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
# Create ports
set dac_data_in_resetn_dclk [ create_bd_port -dir I -type rst dac_data_in_resetn_dclk ]
set dac_data_in_resetn_dclk2x [ create_bd_port -dir I -type rst dac_data_in_resetn_dclk2x ]
set dac_data_in_resetn_rclk [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk ]
set dac_data_in_tdata [ create_bd_port -dir I -from 127 -to 0 -type data dac_data_in_tdata ]
set dac_data_in_tready [ create_bd_port -dir O -type data dac_data_in_tready ]
set dac_data_in_tvalid [ create_bd_port -dir I -type data dac_data_in_tvalid ]
set dac_data_out_tdata [ create_bd_port -dir O -from 255 -to 0 -type data dac_data_out_tdata ]
set dac_data_out_tready [ create_bd_port -dir I -type data dac_data_out_tready ]
set dac_data_out_tvalid [ create_bd_port -dir O -type data dac_data_out_tvalid ]
set data_clk [ create_bd_port -dir I -type clk data_clk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {122880000} \
] $data_clk
set data_clk_2x [ create_bd_port -dir I -type clk data_clk_2x ]
set_property -dict [ list \
CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_dclk2x} \
CONFIG.FREQ_HZ {245760000} \
] $data_clk_2x
set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {184320000} \
] $rfdc_clk
# Create instance: dac_gearbox_4x2_0, and set properties
set block_name dac_gearbox_4x2
set block_cell_name dac_gearbox_4x2_0
if { [catch {set dac_gearbox_4x2_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $dac_gearbox_4x2_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: dac_gearbox_6x8_0, and set properties
set block_name dac_gearbox_6x8
set block_cell_name dac_gearbox_6x8_0
if { [catch {set dac_gearbox_6x8_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $dac_gearbox_6x8_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: dac_interpolator, and set properties
set dac_interpolator [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 dac_interpolator ]
set_property -dict [ list \
CONFIG.Clock_Frequency {245.76} \
CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {27} \
CONFIG.Decimation_Rate {1} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Interpolation} \
CONFIG.Has_ARESETn {true} \
CONFIG.Interpolation_Rate {3} \
CONFIG.Number_Channels {1} \
CONFIG.Number_Paths {2} \
CONFIG.Output_Rounding_Mode {Convergent_Rounding_to_Even} \
CONFIG.Output_Width {18} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Reset_Data_Vector {false} \
CONFIG.S_DATA_Has_FIFO {false} \
CONFIG.Sample_Frequency {491.52} \
CONFIG.Zero_Pack_Factor {1} \
] $dac_interpolator
# Create instance: duc_400m_saturate_0, and set properties
set block_name duc_400m_saturate
set block_cell_name duc_400m_saturate_0
if { [catch {set duc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $duc_400m_saturate_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create port connections
connect_bd_net -net dac_data_in_1 [get_bd_ports dac_data_in_tdata] [get_bd_pins dac_gearbox_4x2_0/data_in_1x]
connect_bd_net -net dac_data_in_resetn_dclk_1 [get_bd_ports dac_data_in_resetn_dclk] [get_bd_pins dac_gearbox_4x2_0/reset_n_1x] [get_bd_pins dac_gearbox_6x8_0/ac1Reset_n]
connect_bd_net -net dac_data_in_resetn_rclk_1 [get_bd_ports dac_data_in_resetn_rclk] [get_bd_pins dac_gearbox_6x8_0/arReset_n]
connect_bd_net -net dac_data_out_tready_1 [get_bd_ports dac_data_out_tready] [get_bd_pins dac_gearbox_6x8_0/rReadyForOutput]
connect_bd_net -net dac_data_valid_in_1 [get_bd_ports dac_data_in_tvalid] [get_bd_pins dac_gearbox_4x2_0/valid_in_1x]
connect_bd_net -net dac_gearbox_4x2_0_data_out_2x [get_bd_pins dac_gearbox_4x2_0/data_out_2x] [get_bd_pins dac_interpolator/s_axis_data_tdata]
connect_bd_net -net dac_gearbox_4x2_0_ready_out_1x [get_bd_ports dac_data_in_tready] [get_bd_pins dac_gearbox_4x2_0/ready_out_1x]
connect_bd_net -net dac_gearbox_4x2_0_valid_out_2x [get_bd_pins dac_gearbox_4x2_0/valid_out_2x] [get_bd_pins dac_interpolator/s_axis_data_tvalid]
connect_bd_net -net dac_gearbox_6x8_0_rDataOut [get_bd_ports dac_data_out_tdata] [get_bd_pins dac_gearbox_6x8_0/rDataOut]
connect_bd_net -net dac_gearbox_6x8_0_rDataValidOut [get_bd_ports dac_data_out_tvalid] [get_bd_pins dac_gearbox_6x8_0/rDataValidOut]
connect_bd_net -net dac_interpolator_m_axis_data_tdata [get_bd_pins dac_interpolator/m_axis_data_tdata] [get_bd_pins duc_400m_saturate_0/cDataIn]
connect_bd_net -net dac_interpolator_m_axis_data_tvalid [get_bd_pins dac_interpolator/m_axis_data_tvalid] [get_bd_pins duc_400m_saturate_0/cDataValidIn]
connect_bd_net -net data_clk_1 [get_bd_ports data_clk] [get_bd_pins dac_gearbox_4x2_0/clk1x] [get_bd_pins dac_gearbox_6x8_0/Clk1x]
connect_bd_net -net data_clk_2x_1 [get_bd_ports data_clk_2x] [get_bd_pins dac_gearbox_4x2_0/clk2x] [get_bd_pins dac_gearbox_6x8_0/Clk2x] [get_bd_pins dac_interpolator/aclk] [get_bd_pins duc_400m_saturate_0/Clk]
connect_bd_net -net data_resetn_dclk2x_1 [get_bd_ports dac_data_in_resetn_dclk2x] [get_bd_pins dac_gearbox_6x8_0/ac2Reset_n] [get_bd_pins dac_interpolator/aresetn]
connect_bd_net -net duc_400m_saturate_0_cDataOut [get_bd_pins dac_gearbox_6x8_0/c2DataIn] [get_bd_pins duc_400m_saturate_0/cDataOut]
connect_bd_net -net duc_400m_saturate_0_cDataValidOut [get_bd_pins dac_gearbox_6x8_0/c2DataValidIn] [get_bd_pins duc_400m_saturate_0/cDataValidOut]
connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins dac_gearbox_6x8_0/RfClk]
# Create address segments
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/dac_400m_bd/hdl_sources.tcl
+9
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set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../rf/400m/dac_gearbox_4x2.v
read_vhdl -library work $script_dir/../../rf/common/PkgRf.vhd
read_vhdl -library work $script_dir/../../rf/400m/dac_gearbox_6x8.vhd
read_vhdl -library work $script_dir/../../rf/400m/dac_gearbox_6x12.vhd
read_vhdl -library work $script_dir/../../rf/400m/dac_gearbox_12x8.vhd
read_vhdl -library work $script_dir/../../rf/400m/duc_400m_saturate.vhd
top/x400/ip/dac_400m_bd/synthstub/dac_400m_bd.vhd
+44
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@@ -0,0 +1,44 @@
------------------------------------------------------------------------------------------
--
-- File: dac_400m_bd.vhd
-- Author: niBlockDesign::niBdExportStub
-- Original Project: HwBuildTools
-- Date: 22 April 2020
--
------------------------------------------------------------------------------------------
-- (c) Copyright National Instruments Corporation
-- All Rights Reserved
-- National Instruments Internal Information
------------------------------------------------------------------------------------------
--
-- Purpose: This is an automatically generated stub file to match the entity
-- declaration for 'dac_400m_bd'. This file was created using niBdExportStub
-- Do not modify this file directly!
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity dac_400m_bd is
port (
dac_data_in_resetn_dclk : in STD_LOGIC;
dac_data_in_resetn_dclk2x : in STD_LOGIC;
dac_data_in_resetn_rclk : in STD_LOGIC;
dac_data_in_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
dac_data_in_tready : out STD_LOGIC;
dac_data_in_tvalid : in STD_LOGIC;
dac_data_out_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
dac_data_out_tready : in STD_LOGIC;
dac_data_out_tvalid : out STD_LOGIC;
data_clk : in STD_LOGIC;
data_clk_2x : in STD_LOGIC;
rfdc_clk : in STD_LOGIC
);
end entity dac_400m_bd;
architecture stub of dac_400m_bd is
begin
end architecture stub;
top/x400/ip/ddr4_64bits/Makefile.inc
+18
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@@ -0,0 +1,18 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_DDR4_64BITS_SRCS = \
$(IP_BUILD_DIR)/ddr4_64bits/ddr4_64bits.xci
IP_DDR4_64BITS_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr4_64bits/, \
ddr4_64bits.xci.out \
)
$(IP_DDR4_64BITS_SRCS) $(IP_DDR4_64BITS_OUTS) : $(IP_DIR)/ddr4_64bits/ddr4_64bits.xci
$(call BUILD_VIVADO_IP,ddr4_64bits,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x400/ip/ddr4_64bits/ddr4_64bits.xci
+450
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@@ -0,0 +1,450 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>ddr4_64bits</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ddr4" spirit:version="2.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AL_SEL">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ACT_SKEW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_10">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_13">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_14">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_17">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_3">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_7">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_9">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AutoPrecharge">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiArbitrationScheme">RD_PRI_REG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiIDWidth">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiNarrowBurst">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstLength">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstType">Sequential</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_1">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">15</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_0">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CustomParts">no_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">DM_NO_DBI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">64</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">9996</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MCS_ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryName">MainMemory</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MT40A512M16HA-075E</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">Components</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_1">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OnDieTermination">RZQ/6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ordering">Normal</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl">RZQ/7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PAR_SKEW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_RESTORE_CRC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCustom">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.BANK_GROUP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/x400/ip/eth_100g_bd/Makefile.inc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_100G_HDL_SRCS = $(addprefix $(IP_DIR)/eth_100g_bd/, \
PkgEth100gLbus.sv \
eth_100g.sv \
eth_100g_axis2lbus.sv \
eth_100g_lbus2axis.sv \
)
IP_100G_HDL_SIM_SRCS = $(addprefix $(IP_DIR)/eth_100g_bd/, \
model_100gbe.sv \
) \
$(wildcard $(addprefix $(IP_BUILD_DIR)/eth_100g_bd/eth_100g_bd/, \
sim/eth_100g_bd.v\
ip/*/ip_0/sim/*.v\
ip/*/sim/*.h\
ip/*/sim/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v2_6_1/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/header_files/*.h\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0.v\
ipshared/*/hdl/*.v\
ipshared/*/hdl/*.sv\
))
IP_100G_ORIG_SRCS = $(addprefix $(IP_DIR)/eth_100g_bd/, \
eth_100g_bd.tcl \
)
IP_100G_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/eth_100g_bd/, \
eth_100g_bd.tcl \
)
IP_100G_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/eth_100g_bd/, \
eth_100g_bd/eth_100g_bd.bd \
)
BD_100G_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/eth_100g_bd/, \
eth_100g_bd.bd.out \
eth_100g_bd/eth_100g_bd_ooc.xdc \
eth_100g_bd/synth/eth_100g_bd.v \
)
EMPTY_IP_SRCS =
$(IP_100G_BD_SRCS) $(BD_100G_BD_OUTS) $(IP_100G_BDTCL_SRCS): $(IP_100G_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,eth_100g_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS))
top/x400/ip/eth_100g_bd/PkgEth100gLbus.sv
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: PkgEth100gLbus
//
// Description:
//
// Package to define an Lbus record
//
//-----------------------------------------------------------------------------
// Lbus interface
//
// This is the segmented local bus interface on the Xilinx CMAC IP
// see Xilinx CMAC documentation for detail
// https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
//-----------------------------------------------------------------------------
package PkgEth100gLbus;
localparam DATA_WIDTH = 512;
localparam NUM_SEG = 4;
localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG;
typedef struct packed {
logic [SEG_DATA_WIDTH-1:0] data;
logic [$clog2(SEG_DATA_WIDTH/8)-1:0] mty;
logic sop;
logic eop;
logic err;
logic ena;
} lbus_t;
endpackage : PkgEth100gLbus
top/x400/ip/eth_100g_bd/eth_100g.sv
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top/x400/ip/eth_100g_bd/eth_100g_axis2lbus.sv
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: eth_100g_axi2lbus
//
// Description:
// Translate from AXI4S (Xilinx segmented ifc) to lbus.
//
// Built using example provided from Xilinx
//
// Parameters:
// - FIFO_DEPTH - FIFO will be 2** deep
// - NUM_SEG - Number of lbus segments coming in
import PkgEth100gLbus::*;
module eth_100g_axi2lbus #(
parameter FIFO_DEPTH = 5,
parameter NUM_SEG = 4
)
(
// AXIS IF
AxiStreamIf.slave axis,
// Lbus Segments
input logic lbus_rdy,
output lbus_t lbus_out [NUM_SEG-1:0]
);
localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG;
localparam SEG_BYTES = SEG_DATA_WIDTH/8;
localparam SEG_MTY_WIDTH = $clog2(SEG_BYTES);
// post rotation lbus signals
lbus_t lbus_d [NUM_SEG-1:0];
// Find last so we can find SOP
logic found_last;
// Propagate ready when asserting , propagate delayed ready while deasserting
logic axis_tready_i;
assign axis.tready = axis_tready_i | lbus_rdy;
always @(posedge axis.clk) begin
axis_tready_i <= lbus_rdy;
end
//declare a segment width axis bus so I can use it's methods
AxiStreamIf #(.DATA_WIDTH(SEG_DATA_WIDTH),.USER_WIDTH($clog2(SEG_BYTES)))
seg_axi (axis.clk, axis.rst);
assign seg_axi.tlast = 1'b1;
logic [NUM_SEG:0] valid;
assign valid[NUM_SEG] = 1'b0;
genvar b;
genvar s;
generate begin : lbus_gen
for (s=0; s < NUM_SEG; s=s+1) begin : segment_loop
// Reverse data byte ordering on each segment
for (b = 0; b < DATA_WIDTH/32; b=b+1) begin : byte_loop
assign lbus_d[s].data[b*8 +: 8] = axis.tdata[((s+1)*(DATA_WIDTH/NUM_SEG)-8-(b*8)) +: 8];
end : byte_loop
// valid if tkeep is set for any bytes in the segment
assign valid[s] = (| axis.tkeep[s*SEG_BYTES +: SEG_BYTES]) & axis.tvalid;
// enable when valid and transfering
assign lbus_d[s].ena = valid[s] & axis.tready;
// eop on last valid byte if last is set
// we init an extra valid bit to 0 so if all valid bits for all segments are set we trigger an eop on the final segment
assign lbus_d[s].eop = (valid[s] ^ valid[s+1]) & axis.tlast;
// set error on all segmetns if tuser is set
assign lbus_d[s].err = valid[s] & axis.tuser;
// translate keep to trailing bytes and invert sign
always_comb begin
if (lbus_d[s].eop) begin
lbus_d[s].mty = SEG_BYTES - seg_axi.keep2trailing(axis.tkeep[s*SEG_BYTES+: SEG_BYTES]);
end else begin
lbus_d[s].mty = 'b0;
end
end
//SOP can only occur on segment 0, so init all the bits to zero, then assign segment 0
if (s==0) begin
assign lbus_d[s].sop = found_last & axis.tvalid & axis.tready;
end else begin
assign lbus_d[s].sop = 1'b0;
end
// assign the output DFF's
always_ff @(posedge axis.clk) begin
lbus_out[s].data <= lbus_d[s].data;
lbus_out[s].ena <= lbus_d[s].ena;
lbus_out[s].sop <= lbus_d[s].sop;
lbus_out[s].eop <= lbus_d[s].eop;
lbus_out[s].err <= lbus_d[s].err;
lbus_out[s].mty <= lbus_d[s].mty;
end
end : segment_loop
end : lbus_gen
endgenerate
// SOP Statemachine
always_ff @(posedge axis.clk) begin : sop_sm
if(axis.rst) begin
found_last <= 1'b1;
end else begin
if(axis.tvalid & axis.tlast & axis.tready) found_last <= 1'b1;
else if(axis.tvalid & axis.tready) found_last <= 1'b0;
end
end : sop_sm
endmodule
top/x400/ip/eth_100g_bd/eth_100g_bd.tcl
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################################################################
# This is a generated script based on design: eth_100g_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source eth_100g_bd_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name eth_100g_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:cmac_usplus:2.6\
xilinx.com:ip:xlconstant:1.1\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set core_drp [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:drp_rtl:1.0 core_drp ]
set eth100g_rx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_rx ]
set eth100g_tx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_tx ]
set gt_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_rx ]
set gt_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_tx ]
set refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 refclk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {156250000} \
] $refclk
set s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi ]
set_property -dict [ list \
CONFIG.ADDR_WIDTH {32} \
CONFIG.ARUSER_WIDTH {0} \
CONFIG.AWUSER_WIDTH {0} \
CONFIG.BUSER_WIDTH {0} \
CONFIG.DATA_WIDTH {32} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_BURST {0} \
CONFIG.HAS_CACHE {0} \
CONFIG.HAS_LOCK {0} \
CONFIG.HAS_PROT {0} \
CONFIG.HAS_QOS {0} \
CONFIG.HAS_REGION {0} \
CONFIG.HAS_RRESP {1} \
CONFIG.HAS_WSTRB {1} \
CONFIG.ID_WIDTH {0} \
CONFIG.MAX_BURST_LENGTH {1} \
CONFIG.NUM_READ_OUTSTANDING {1} \
CONFIG.NUM_READ_THREADS {1} \
CONFIG.NUM_WRITE_OUTSTANDING {1} \
CONFIG.NUM_WRITE_THREADS {1} \
CONFIG.PROTOCOL {AXI4LITE} \
CONFIG.READ_WRITE_MODE {READ_WRITE} \
CONFIG.RUSER_BITS_PER_BYTE {0} \
CONFIG.RUSER_WIDTH {0} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.WUSER_BITS_PER_BYTE {0} \
CONFIG.WUSER_WIDTH {0} \
] $s_axi
# Create ports
set ctl_tx_pause_req [ create_bd_port -dir I -from 8 -to 0 ctl_tx_pause_req ]
set ctl_tx_resend_pause [ create_bd_port -dir I ctl_tx_resend_pause ]
set drp_clk [ create_bd_port -dir I -type clk drp_clk ]
set gt_txusrclk2 [ create_bd_port -dir O -type clk gt_txusrclk2 ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {eth100g_rx:eth100g_tx} \
CONFIG.FREQ_HZ {322265625} \
] $gt_txusrclk2
set init_clk [ create_bd_port -dir I -type clk init_clk ]
set pm_tick [ create_bd_port -dir I pm_tick ]
set rx_clk [ create_bd_port -dir I -type clk rx_clk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {322265625} \
] $rx_clk
set s_axi_aclk [ create_bd_port -dir I -type clk s_axi_aclk ]
set s_axi_sreset [ create_bd_port -dir I -type rst s_axi_sreset ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_HIGH} \
] $s_axi_sreset
set stat_rx_aligned [ create_bd_port -dir O stat_rx_aligned ]
set stat_rx_pause_req [ create_bd_port -dir O -from 8 -to 0 stat_rx_pause_req ]
set sys_reset [ create_bd_port -dir I -type rst sys_reset ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_HIGH} \
] $sys_reset
set tx_ovfout [ create_bd_port -dir O tx_ovfout ]
set tx_unfout [ create_bd_port -dir O tx_unfout ]
set usr_rx_reset [ create_bd_port -dir O -type rst usr_rx_reset ]
set usr_tx_reset [ create_bd_port -dir O -type rst usr_tx_reset ]
# Create instance: cmac_usplus_0, and set properties
set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:2.6 cmac_usplus_0 ]
set_property -dict [ list \
CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \
CONFIG.ENABLE_AXI_INTERFACE {1} \
CONFIG.GT_DRP_CLK {100} \
CONFIG.GT_GROUP_SELECT {X0Y4~X0Y7} \
CONFIG.GT_REF_CLK_FREQ {156.25} \
CONFIG.INCLUDE_AUTO_NEG_LT_LOGIC {0} \
CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.INCLUDE_SHARED_LOGIC {2} \
CONFIG.INCLUDE_STATISTICS_COUNTERS {1} \
CONFIG.LANE10_GT_LOC {NA} \
CONFIG.LANE1_GT_LOC {X0Y4} \
CONFIG.LANE2_GT_LOC {X0Y5} \
CONFIG.LANE3_GT_LOC {X0Y6} \
CONFIG.LANE4_GT_LOC {X0Y7} \
CONFIG.LANE5_GT_LOC {NA} \
CONFIG.LANE6_GT_LOC {NA} \
CONFIG.LANE7_GT_LOC {NA} \
CONFIG.LANE8_GT_LOC {NA} \
CONFIG.LANE9_GT_LOC {NA} \
CONFIG.NUM_LANES {4} \
CONFIG.RX_CHECK_ACK {0} \
CONFIG.RX_EQ_MODE {AUTO} \
CONFIG.RX_FLOW_CONTROL {1} \
CONFIG.TX_FLOW_CONTROL {1} \
CONFIG.USER_INTERFACE {LBUS} \
] $cmac_usplus_0
# Create instance: tie_loopback, and set properties
set tie_loopback [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 tie_loopback ]
set_property -dict [ list \
CONFIG.CONST_VAL {0} \
CONFIG.CONST_WIDTH {12} \
] $tie_loopback
# Create instance: tie_zero, and set properties
set tie_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 tie_zero ]
set_property -dict [ list \
CONFIG.CONST_VAL {0} \
] $tie_zero
# Create interface connections
connect_bd_intf_net -intf_net RefClk_1 [get_bd_intf_ports refclk] [get_bd_intf_pins cmac_usplus_0/gt_ref_clk]
connect_bd_intf_net -intf_net Rx_1 [get_bd_intf_ports gt_rx] [get_bd_intf_pins cmac_usplus_0/gt_rx]
connect_bd_intf_net -intf_net cmac_usplus_0_gt_tx [get_bd_intf_ports gt_tx] [get_bd_intf_pins cmac_usplus_0/gt_tx]
connect_bd_intf_net -intf_net cmac_usplus_0_lbus_rx [get_bd_intf_ports eth100g_rx] [get_bd_intf_pins cmac_usplus_0/lbus_rx]
connect_bd_intf_net -intf_net eth_100g_tx_1 [get_bd_intf_ports eth100g_tx] [get_bd_intf_pins cmac_usplus_0/lbus_tx]
connect_bd_intf_net -intf_net sDrp_1 [get_bd_intf_ports core_drp] [get_bd_intf_pins cmac_usplus_0/core_drp]
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_ports s_axi] [get_bd_intf_pins cmac_usplus_0/s_axi]
# Create port connections
connect_bd_net -net SysClk_1 [get_bd_ports init_clk] [get_bd_pins cmac_usplus_0/init_clk]
connect_bd_net -net aResetIn_1 [get_bd_ports sys_reset] [get_bd_pins cmac_usplus_0/sys_reset]
connect_bd_net -net cmac_usplus_0_gt_txusrclk2 [get_bd_ports gt_txusrclk2] [get_bd_pins cmac_usplus_0/gt_txusrclk2]
connect_bd_net -net cmac_usplus_0_stat_rx_aligned [get_bd_ports stat_rx_aligned] [get_bd_pins cmac_usplus_0/stat_rx_aligned]
connect_bd_net -net cmac_usplus_0_stat_rx_pause_req [get_bd_ports stat_rx_pause_req] [get_bd_pins cmac_usplus_0/stat_rx_pause_req]
connect_bd_net -net cmac_usplus_0_tx_ovfout [get_bd_ports tx_ovfout] [get_bd_pins cmac_usplus_0/tx_ovfout]
connect_bd_net -net cmac_usplus_0_tx_unfout [get_bd_ports tx_unfout] [get_bd_pins cmac_usplus_0/tx_unfout]
connect_bd_net -net cmac_usplus_0_usr_rx_reset [get_bd_ports usr_rx_reset] [get_bd_pins cmac_usplus_0/usr_rx_reset]
connect_bd_net -net cmac_usplus_0_usr_tx_reset [get_bd_ports usr_tx_reset] [get_bd_pins cmac_usplus_0/usr_tx_reset]
connect_bd_net -net ctl_tx_pause_req_1 [get_bd_ports ctl_tx_pause_req] [get_bd_pins cmac_usplus_0/ctl_tx_pause_req]
connect_bd_net -net ctl_tx_resend_pause_1 [get_bd_ports ctl_tx_resend_pause] [get_bd_pins cmac_usplus_0/ctl_tx_resend_pause]
connect_bd_net -net drp_clk_1 [get_bd_ports drp_clk] [get_bd_pins cmac_usplus_0/drp_clk]
connect_bd_net -net pm_tick_1 [get_bd_ports pm_tick] [get_bd_pins cmac_usplus_0/pm_tick]
connect_bd_net -net rx_clk_1 [get_bd_ports rx_clk] [get_bd_pins cmac_usplus_0/rx_clk]
connect_bd_net -net s_axi_aclk_1 [get_bd_ports s_axi_aclk] [get_bd_pins cmac_usplus_0/s_axi_aclk]
connect_bd_net -net s_axi_sreset_1 [get_bd_ports s_axi_sreset] [get_bd_pins cmac_usplus_0/s_axi_sreset]
connect_bd_net -net tie_loopback_dout [get_bd_pins cmac_usplus_0/gt_loopback_in] [get_bd_pins tie_loopback/dout]
connect_bd_net -net tie_zero_dout [get_bd_pins cmac_usplus_0/gtwiz_reset_rx_datapath] [get_bd_pins cmac_usplus_0/gtwiz_reset_tx_datapath] [get_bd_pins tie_zero/dout]
# Create address segments
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] SEG_cmac_usplus_0_Reg
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/eth_100g_bd/eth_100g_lbus2axis.sv
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: eth_100g_lbus2axi
//
// Description:
// Translate from lbus (xilinx segmented ifc) to
// AXI4S.
//
// Built using example provided from Xilinx
//
// Parameters:
// - FIFO_DEPTH - FIFO will be 2** deep
// - NUM_SEG - Number of lbus segments coming in
//
// Notes on timing difficulty
// The path back to pop is challenged
// -LBUS is popped out of the FIFO (SRL read can be slow)
// -LBUS is rotated N to 1 Mux (N= number of segments) For 100g N=4
// -Find where EOP is (search for the first 1)
// -Unrotate the number of words and use that to calculate pop
//
// Fifo Output
// Data starts from the SRL and is indexed by the read pointer
// Data_Valid comes from a comparison on fullness
// Invalid control is forced to zero (necessary for algorithm)
// It's not necessary to force all the data to zero just the control plane.
//
// Fifo output data is rotated (4 to 1) mux then reinterpreted as lbus data
//
// The rotated control signals are analyzed to determine
// no_eop, no_sop, some_empty, no_ena
//
// eop is specifically inspected in a 4in,4out function to find a pseudo
// one hot. this is unrotated along with enable, and combined with
// datavalid to determine the next pop, which controls incrementing of the
// rd_pointer.
//
import PkgEth100gLbus::*;
module eth_100g_lbus2axi #(
parameter FIFO_DEPTH = 5,
parameter NUM_SEG = 4
)
(
// AXIS IF
AxiStreamIf.master axis,
// Lbus Segments
input lbus_t lbus_in [NUM_SEG-1:0]
);
localparam SEG_BYTES = SEG_DATA_WIDTH/8;
localparam SEG_MTY_WIDTH = $clog2(SEG_BYTES);
localparam SEG_SHMEAR_WIDTH = SEG_DATA_WIDTH + SEG_MTY_WIDTH + 4;
//////////////////////////////////////////////////////////////////////////////////
////////////////// Data Input to FIFO ///////////
//////////////////////////////////////////////////////////////////////////////////
lbus_t lbus_fout_p[NUM_SEG-1:0]; //{ena,err,eop,sop,mty,data}
lbus_t lbus_fout[NUM_SEG-1:0]; //{ena,err,eop,sop,mty,data}
//FIFO Logic
logic push;
logic [NUM_SEG-1:0] pop;
logic [NUM_SEG-1:0] full;
logic [NUM_SEG-1:0] empty;
// always push the fifo on all lanes
assign push = lbus_in[0].ena;
// For each lane of incoming data place it into a separate FIFO
generate
genvar b1,gseg1;
begin : gen_seg_fifo
for(gseg1 = 0; gseg1 < NUM_SEG; gseg1=gseg1+1) begin
//////////////////////////////////////////////////////////////////////////////////
// INLINE FIFO
//////////////////////////////////////////////////////////////////////////////////
// simulation error if we push a full fifo
always_comb begin
if (push) begin
assert (!full[gseg1]) else $error("Pushing full fifo!");
end
end
// limit fanout to improve timing
(* max_fanout = 75 *) logic [4:0] a;
for (b1=0;b1<SEG_DATA_WIDTH;b1=b1+1) begin : gen_srl_data
SRLC32E srl_data(
.Q(lbus_fout_p[gseg1].data[b1]), .Q31(),
.A(a),
.CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].data[b1])
);
end
for (b1=0;b1<SEG_MTY_WIDTH;b1=b1+1) begin : gen_srl_mty
SRLC32E srl_mty(
.Q(lbus_fout_p[gseg1].mty[b1]), .Q31(),
.A(a),
.CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].mty[b1])
);
end
SRLC32E srl_err(
.Q(lbus_fout_p[gseg1].err), .Q31(),
.A(a),
.CE(push),.CLK(axis.clk),.D(lbus_in[gseg1].err)
);
// empty on prebuffer and SRL
logic my_empty;
always @(posedge axis.clk)
begin
if(axis.rst) begin
a <= 0;
my_empty <= 1;
full[gseg1] <= 0;
end else if(pop[gseg1] & ~push) begin
full[gseg1] <= 0;
if(a==0) begin
my_empty <= 1;
end else begin
a <= a - 1;
end
end else if(push & ~pop[gseg1]) begin
my_empty <= 0;
if(~my_empty) begin
a <= a + 1;
end
if(a == 30) begin
full[gseg1] <= 1;
end
end
end
// FIFO for time sensitive control signals. This creates a separate 31 deep fifo from
// DFF's on just 3 signals. The data signals continue to use an SRL to save space.
// The design bellow is a FIFO followed by a single DFF regsiter that is automatically
// prefilled when the FIFO has data.
logic [4:0] w_ptr,r_ptr,r_ptr_d,fullness;
logic [31:0] ena_mem, sop_mem, eop_mem;
// Final fifo stage after memory to remove address muxing from timing path
// this adds one clock of latency to empty flag as it will take 2 clocks to propagate
// into fifo.
//push critical timing signals to final flop. This adds 1 clock of latency on
// the final empty flag, but removes muxing of the memory elements
logic push_dff;
//using r_ptr_d to avoid extra latency in fullness change
always_comb begin
if (pop[gseg1]) begin
r_ptr_d = r_ptr+1;
end else begin
r_ptr_d = r_ptr;
end
fullness = w_ptr-r_ptr_d;
push_dff = (fullness != 0) & (pop[gseg1] | empty[gseg1]);
end
// speedier fifo implementation on these three control signals
// THE goal of this complexity is to have the outputs be a direct FF output
// instead of a muxed memory output.
always @(posedge axis.clk)
begin
if(axis.rst) begin
ena_mem <= '0;
sop_mem <= '0;
eop_mem <= '0;
lbus_fout_p[gseg1].ena <= 1'b0;
lbus_fout_p[gseg1].sop <= 1'b0;
lbus_fout_p[gseg1].eop <= 1'b0;
w_ptr <= 0;
r_ptr <= 0;
empty[gseg1] <= 1'b1;
end else begin
if(push) begin
ena_mem[w_ptr] <= lbus_in[gseg1].ena;
sop_mem[w_ptr] <= lbus_in[gseg1].sop;
eop_mem[w_ptr] <= lbus_in[gseg1].eop;
w_ptr <= w_ptr+1;
end
r_ptr <= r_ptr_d;
if (push_dff) begin
empty[gseg1] <= 1'b0;
lbus_fout_p[gseg1].ena <= ena_mem[r_ptr_d];
lbus_fout_p[gseg1].sop <= sop_mem[r_ptr_d];
lbus_fout_p[gseg1].eop <= eop_mem[r_ptr_d];
end else if (pop[gseg1]) begin
empty[gseg1] <= 1'b1;
end
end
end
// clear the enables if this fifo segment is not valid
always_comb begin
//default assignment
lbus_fout[gseg1] = lbus_fout_p[gseg1];
if (empty[gseg1]) begin
// clear ena,err,eop,sop,mty (But not data - saves fanout!)
lbus_fout[gseg1].ena = 0;
lbus_fout[gseg1].err = 0;
lbus_fout[gseg1].eop = 0;
lbus_fout[gseg1].sop = 0;
lbus_fout[gseg1].mty = '0;
end else begin
// clear bits if the segment isn't enabled
lbus_fout[gseg1].eop = lbus_fout_p[gseg1].eop && lbus_fout_p[gseg1].ena;
lbus_fout[gseg1].sop = lbus_fout_p[gseg1].sop && lbus_fout_p[gseg1].ena;
lbus_fout[gseg1].err = lbus_fout_p[gseg1].err && lbus_fout_p[gseg1].ena;
end
end
end
end : gen_seg_fifo
endgenerate
// post rotation lbus signals
lbus_t lbus_rot [NUM_SEG-1:0];
// rotated signals as vectors for decision making
logic [NUM_SEG-1:0] ena;
logic [NUM_SEG-1:0] sop;
logic [NUM_SEG-1:0] eop;
logic [NUM_SEG-1:0] rot_ena;
logic [NUM_SEG-1:0] rot_sop;
logic [NUM_SEG-1:0] rot_eop;
logic [NUM_SEG-1:0] rot_empty;
always_comb begin
foreach (rot_ena[s]) begin
ena[s] = lbus_fout[s].ena;
sop[s] = lbus_fout[s].sop;
eop[s] = lbus_fout[s].eop;
rot_ena[s] = lbus_rot[s].ena;
rot_sop[s] = lbus_rot[s].sop;
rot_eop[s] = lbus_rot[s].eop;
end
end
logic [$clog2(NUM_SEG)-1:0] rot;
//////////////////////////////////////////////////////////////////////////////////
////////////////// Generate Decision Information ///////////
//////////////////////////////////////////////////////////////////////////////////
logic no_sop;
logic no_eop;
logic no_ena;
logic some_empty;
logic send_idle;
always_comb begin
no_sop = sop == 0;
no_eop = eop == 0;
no_ena = ena == 0;
// check for an empy byte
some_empty = 1'b0;
foreach (ena[seg]) begin : segment_loop
if (ena[seg] == 0) begin
some_empty = 1'b1;
end
end : segment_loop;
end
always_comb begin
if (no_ena) begin
send_idle = 1'b0;
end else begin
// generally either there is an EOP with some empty segments
// or all empty segments on an unrotated bus. I'm not sure
// what this implies on an rotated bus
send_idle = no_eop & some_empty;
end
end
//////////////////////////////////////////////////////////////////////////////////
////////////////// Calculate Pop ///////////
//////////////////////////////////////////////////////////////////////////////////
// After rotation figure out how far till eop
//==========================================================================
// one-hot to thermometer code
// The goal is to find how far down till we reach the first eop
// This represents the bytes we will trasnfer this clock
//==========================================================================
// Xilinx example
// case (in_reqs)
// 4'b1000: onehot2thermo = 4'b1111;
//
// 4'b1100: onehot2thermo = 4'b0111;
// 4'b0100: onehot2thermo = 4'b0111;
//
// 4'b1110: onehot2thermo = 4'b0011;
// 4'b0110: onehot2thermo = 4'b0011;
// 4'b0010: onehot2thermo = 4'b0011;
//
// 4'b1111: onehot2thermo = 4'b0001;
// 4'b0111: onehot2thermo = 4'b0001;
// 4'b0011: onehot2thermo = 4'b0001;
// 4'b0001: onehot2thermo = 4'b0001;
//
// default: onehot2thermo = 4'b0000;
// endcase
logic [NUM_SEG-1:0] rot_xfer_now;
logic [NUM_SEG-1:0] mask [NUM_SEG-1:0];
logic [NUM_SEG-1:0] m1hot [NUM_SEG-1:0];
logic [NUM_SEG-1:0] meop [NUM_SEG-1:0];
logic [NUM_SEG-1:0] match;
always_comb begin
rot_xfer_now = '0;
foreach (rot_eop[s]) begin
// The function
// XXX1=>0001
// XX10=>0011
// X100=>0111
// 1000=>1111
// MASK
// 2**(0+1)-1 = 0001
// 2**(1+1)-1 = 0011
// 2**(2+1)-1 = 0111
// 2**(3+1)-1 = 1111
mask[s] = 2**(s+1)-1; // Constant
// MASK
// 2**0 = 0001
// 2**1 = 0010
// 2**2 = 0100
// 2**3 = 1000
m1hot[s] = 2**s; // Constant
// Mask valid_eop
meop[s] = rot_eop & mask[s];
// compare against 1hot
match[s] = meop[s] == m1hot[s];
if (match[s]) begin
rot_xfer_now = mask[s];
end
end
end
// unrotate the values and calculate pop
logic [NUM_SEG-1:0] xfer_now;
logic [NUM_SEG-1:0] filler_seg;
always_comb begin
if (send_idle)
xfer_now = '0;
else if (no_eop | no_sop)
xfer_now = '1;
else
// rotate left
xfer_now = {rot_xfer_now,rot_xfer_now} >> (NUM_SEG - rot);
end
// Flush out valid segments with no enable
assign filler_seg = ~ena & ~empty;
assign pop = (xfer_now | filler_seg) & ~empty;
//////////////////////////////////////////////////////////////////////////////////
////////////////// Calculate Rotate for the next clock ///////////
//////////////////////////////////////////////////////////////////////////////////
logic [$clog2(NUM_SEG)-1:0] next_rot;
always_comb begin
next_rot = 0;
foreach (rot_empty[s]) begin
if (~rot_empty[s] & lbus_rot[s].sop) begin
next_rot = s;
end
end
end
always @(posedge axis.clk)
begin
if(axis.rst) begin
rot <= '0;
//no valid data on any segment
end else if( no_ena ) begin
rot <= '0;
// If EOP, but no SoP
end else if( no_sop & ~no_eop & some_empty) begin
rot <= '0;
// If SOP, accumulate rotation to push to seg 0
end else if( ~no_sop ) begin
rot <= rot+next_rot;
end
end
//////////////////////////////////////////////////////////////////////////////////
////////////////// Rotation of segments from fifo output ///////////
//////////////////////////////////////////////////////////////////////////////////
generate
genvar b2,gseg2;
begin : rotate_lbus
//perform a bitwise rotation.
for(b2 = 0; b2 < SEG_SHMEAR_WIDTH; b2=b2+1) begin
logic [NUM_SEG-1:0] slice, slice_rotated;
//copy a horizontal slice across the segments
for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin
assign slice[gseg2] = lbus_fout[gseg2][b2];
end
// rotate the slice (should make SEG_SHMEAR_WIDTH copies of NUM_SEG to 1 mux)
assign slice_rotated = {slice,slice} >> rot; //rotate_right
// Copy slice back to the struct
for(gseg2 = 0; gseg2 < NUM_SEG; gseg2=gseg2+1) begin
assign lbus_rot[gseg2][b2] = slice_rotated[gseg2];
end
end
end : rotate_lbus
endgenerate
always_comb begin : rotate_data_valid
rot_empty = {empty,empty} >> rot; //rotate_right
end : rotate_data_valid
//////////////////////////////////////////////////////////////////////////////////
////////////////// LBUS out DFF /////////////////////
//////////////////////////////////////////////////////////////////////////////////
// This pipe stage is mainly to allow suming MTY bits and to add space for
// Vivado to try to pipeline the output
// post rotation lbus signals
lbus_t lbus_out [NUM_SEG-1:0];
logic [NUM_SEG-1:0] axi_seg_valid;
always_ff @(posedge axis.clk)
begin
if (axis.rst) begin
foreach (lbus_out[seg]) begin : segment_loop
lbus_out[seg] <= '0;
end
axi_seg_valid <= '0;
end else begin
lbus_out <= lbus_rot;
if (send_idle)
axi_seg_valid <= '0;
else if (no_eop)
axi_seg_valid <= '1;
else
axi_seg_valid <= rot_xfer_now;
end
end
////////////////////////////////////////////////////////////////////////////
// Generate AXI
////////////////////////////////////////////////////////////////////////////
logic [axis.DATA_WIDTH - 1:0] axis_tdata_w;
logic [$clog2(axis.DATA_WIDTH/8) - 1:0] axis_tuser_bytes_w;
logic [axis.DATA_WIDTH/8 - 1:0] axis_tkeep_w;
logic [NUM_SEG-1:0] axis_tlast_w;
logic [NUM_SEG-1:0] axis_tvalid_w;
logic [NUM_SEG-1:0] axis_tuser_err_w;
always_comb begin : axis_translate
axis_tuser_bytes_w = 'd0; // init to zero before summing
foreach (axis_tvalid_w[seg]) begin : segment_loop
axis_tvalid_w[seg] = lbus_out[seg].ena & axi_seg_valid[seg];
axis_tlast_w[seg] = lbus_out[seg].eop;
axis_tuser_err_w[seg] = lbus_out[seg].err;
// sum all the segment mty vectors
if (lbus_out[seg].ena && axi_seg_valid[seg]) begin
axis_tuser_bytes_w += SEG_DATA_WIDTH/8 - lbus_out[seg].mty;
end
// 512 bit word = 64 bytes = 4 X 128 bit(16 byte) segments
// assign bytes : LbusOrder
// S0 : S0B0..S0B15
// S1 : S1B0..S1B15
// S2 : S2B0..S2B15
// S3 : S3B0..S3B15
// AXI (swap Endianess on each segment)
// AXI = S3B15..S3B0, S2B15..S2B0, S1B15..S1B0, S0B15..S0B0
for(int b = 0; b < SEG_BYTES; b=b+1) begin : tdata_loop
// ( 1 * 128 )-8- 0*8) 120+:8 = S0B0
// ( 1 * 128 )-8- 1*8) 112+:8 = S0B1
// ...
// ( 1 * 128 )-8-14*8) 8+:8 = S0B14
// ( 1 * 128 )-8-15*8) 0+:8 = S0B15
////////////////////////////////////
// ( 2 * 128 )-8- 0*8) 248+:8 = S1B0
// ( 2 * 128 )-8- 1*8) 240+:8 = S1B1
// ...
// ( 2 * 128 )-8-14*8) 136+:8 = S1B14
// ( 2 * 128 )-8-15*8) 128+:8 = S1B15
////////////////////////////////////
// ...
////////////////////////////////////
// ( 4 * 128 )-8- 0*8) 504+:8 = S3B0
// ( 4 * 128 )-8- 1*8) 496+:8 = S3B1
// ...
// ( 4 * 128 )-8-14*8) 136+:8 = S3B14
// ( 4 * 128 )-8-15*8) 384+:8 = S3B15
axis_tdata_w[((seg+1)*axis.DATA_WIDTH/NUM_SEG-8-b*8) +: 8] = lbus_out[seg].data[b*8 +: 8];
end : tdata_loop
end : segment_loop
end : axis_translate
// convert bytes to keep
always_comb begin
axis_tkeep_w = '1;
if (axis_tlast_w != 0 && axis_tuser_bytes_w != 0) begin
foreach(axis_tkeep_w[b]) begin
axis_tkeep_w[b] = axis_tuser_bytes_w > b;
end
end
end
//////////////////////////////////////////////////////////////////////////////////
////////////////// AXIS output flop /////////////////////
//////////////////////////////////////////////////////////////////////////////////
localparam AXIS_MTY_WIDTH = $clog2(axis.BYTES_PER_WORD);
always_ff @(posedge axis.clk)
begin
if (axis.rst) begin
axis.tdata <= '0;
axis.tvalid <= 1'b0;
axis.tlast <= 1'b0;
axis.tuser <= '0;
axis.tkeep <= '0;
end else begin
axis.tdata <= axis_tdata_w;
axis.tvalid <= |axis_tvalid_w;
axis.tlast <= |axis_tlast_w;
if (axis.TKEEP == 1) begin
axis.tkeep <= axis_tkeep_w;
end else begin
axis.tkeep <= 'X;
end
// trailing bytes in last word
axis.tuser[AXIS_MTY_WIDTH-1:0] <= axis_tuser_bytes_w;
// MSB is error
axis.tuser[AXIS_MTY_WIDTH] <= |axis_tuser_err_w;
end
end
endmodule
top/x400/ip/eth_100g_bd/lbus_tb/Makefile
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../../../../top)
# Include viv_sim_preamble after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
include $(BASE_DIR)/../lib/fifo/Makefile.srcs
# If you generate the Xilinx CORE with an AXI interface you can find Xilinx's LBUS translators here
#$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_lbus2axis_segmented_top.v) \
#$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top.v) \
DESIGN_SRCS = $(abspath \
$(abspath ../eth_100g_axis2lbus.sv) \
$(abspath ../eth_100g_lbus2axis.sv) \
$(FIFO_SRCS) \
$(AXI4S_SV_SRCS) \
)
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4
MODELSIM_ARGS += glbl -t 1fs
# Define toplevel module
TB_TOP_MODULE ?= lbus_all_tb
SIM_TOP = $(TB_TOP_MODULE)
SIM_SRCS = \
$(abspath ../PkgEth100gLbus.sv) \
$(abspath axi_lbus_tb.sv) \
$(abspath lbus_axi_tb.sv) \
$(abspath $(TB_TOP_MODULE).sv) \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
# Suppressing the following worthless reminder.
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
SVLOG_ARGS = -suppress 2583 -keep_delta
VLOG_ARGS = -keep_delta
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak
top/x400/ip/eth_100g_bd/lbus_tb/axi_lbus_tb.sv
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: axi_lbus_tb
//
// Description:
//
// Testbench for eth_interface
//
module axi_lbus_tb #(
parameter TEST_NAME = ""
)(
/* no IO */
);
// Include macros and time declarations for use with PkgTestExec
`define TEST_EXEC_OBJ test
`include "test_exec.svh"
import PkgAxiStreamBfm::*;
import PkgEthernet::*;
import PkgTestExec::*;
import PkgEth100gLbus::*;
localparam DATA_WIDTH = 512;
localparam USER_WIDTH = $clog2(DATA_WIDTH/8)+1;
localparam NUM_SEG = 4;
localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG;
localparam SEG_BYTES = SEG_DATA_WIDTH/8;
//----------------------------------------------------
// clocks
//----------------------------------------------------
logic clk;
logic rst;
sim_clock_gen #(.PERIOD(5), .AUTOSTART(1))
clk_gen (.clk(clk), .rst(rst));
//----------------------------------------------------
//interfaces
//----------------------------------------------------
AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
axis (clk, rst);
//----------------------------------------------------
// DUT
//----------------------------------------------------
lbus_t lbus_out [NUM_SEG-1:0];
lbus_t lbus_g [NUM_SEG-1:0];
logic lbus_rdy = 1;
eth_100g_axi2lbus #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT (
.axis(axis),
.lbus_rdy(lbus_rdy),
.lbus_out(lbus_out)
);
//----------------------------------------------------
// Xilinx golden model
// When Xilinx is generated with an AXI interface xilinx prints
// an axi2lbus converter that has trouble meeting timing
// this is preserved to allow comparison to that
// TODO: remove when timing is passing and refactor is done
//----------------------------------------------------
/*
eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top GOLD (
.core_clk(clk),
.core_rst(rst),
// AXIS IF
.axis_tvalid(axis.tvalid),
.axis_tready(),
.axis_tdata(axis.tdata),
.axis_tlast(axis.tlast),
.axis_tkeep(axis.tkeep),
.axis_tuser(1'b0),
// LBUS IF
.lbus_rdyout(lbus_rdy),
.lbus_ovfout(1'b0),
.lbus_unfout(1'b0),
// Segment 0
.lbus_ena0(lbus_g[0].ena),
.lbus_data0(lbus_g[0].data),
.lbus_sop0(lbus_g[0].sop),
.lbus_eop0(lbus_g[0].eop),
.lbus_mty0(lbus_g[0].mty),
.lbus_err0(lbus_g[0].err),
// Segment 1
.lbus_ena1(lbus_g[1].ena),
.lbus_data1(lbus_g[1].data),
.lbus_sop1(lbus_g[1].sop),
.lbus_eop1(lbus_g[1].eop),
.lbus_mty1(lbus_g[1].mty),
.lbus_err1(lbus_g[1].err),
// Segment 2
.lbus_ena2(lbus_g[2].ena),
.lbus_data2(lbus_g[2].data),
.lbus_sop2(lbus_g[2].sop),
.lbus_eop2(lbus_g[2].eop),
.lbus_mty2(lbus_g[2].mty),
.lbus_err2(lbus_g[2].err),
// Segment 3
.lbus_ena3(lbus_g[3].ena),
.lbus_data3(lbus_g[3].data),
.lbus_sop3(lbus_g[3].sop),
.lbus_eop3(lbus_g[3].eop),
.lbus_mty3(lbus_g[3].mty),
.lbus_err3(lbus_g[3].err)
);
*/
//----------------------------------------------------
//BFMS
//----------------------------------------------------
TestExec test = new();
AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =
new(.slave(null),.master(axis));
//---------------------------------------------------------------------------
// Tests
//---------------------------------------------------------------------------
// use Test timeout to check reset goes away
task test_reset();
test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
wait(!rst);
repeat (10) @(posedge clk);
test.end_test();
endtask : test_reset
typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;
typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;
task automatic check_lbus(AxisPacket_t packets[$]);
int idle_insert = 0;
int byte_count = 0;
int first_clk = 1;
// loop over packets
foreach(packets[i]) begin
automatic raw_pkt_t pay;
pay = packets[i].dump_bytes;
first_clk=1;
while (pay.size() > 0) begin
@(posedge clk);
if (lbus_rdy) begin
if (lbus_out[0].ena) begin
for (int s=0; s < NUM_SEG; s++) begin
byte_count = 0;
for (int b = SEG_DATA_WIDTH/8-1; b >= 0; b--) begin
if (pay.size() > 0) begin
assert (lbus_out[s].data[b*8 +: 8] == pay.pop_front()) else $error("Data Mismatch");
byte_count++;
end
end
assert (lbus_out[s].ena == (byte_count > 0) ) else $error("Ena Mismatch");
if (lbus_out[s].ena) begin
if (first_clk && s==0) begin
assert (lbus_out[s].sop == 1) else $error("Sop not set");
end else begin
assert (lbus_out[s].sop == 0) else $error("Sop Set");
end
assert (lbus_out[s].mty == (SEG_BYTES-byte_count) % SEG_BYTES) else $error("Mty Mismatch");
assert (lbus_out[s].eop != (pay.size() > 0) ) else $error("Eop Mismatch");
assert (lbus_out[s].err == 0) else $error("Err Mismatch"); // not checking error yet
end else begin
assert (lbus_out[s].sop == 0) else $error("Sop Set while disabled");
assert (lbus_out[s].mty == 0) else $error("Mty set while disabled");
assert (lbus_out[s].eop == 0) else $error("Eop set while disabled");
assert (lbus_out[s].err == 0) else $error("Err set while disabled");
end
end // segment loop
first_clk=0;
end // first segment is enabled
end else begin //not lbus_rdy
for (int s=0; s < NUM_SEG; s++) begin
assert (lbus_out[s].ena == 0) else $error("Idle Ena set");
assert (lbus_out[s].err == 0) else $error("Idle Err set");
assert (lbus_out[s].sop == 0) else $error("Idle Sop set");
assert (lbus_out[s].eop == 0) else $error("Idle Eop set");
assert (lbus_out[s].mty == 0) else $error("Idle Mty non zero");
end
end
end // while pay.size > 0
end // foreach packet
endtask : check_lbus;
task automatic test_transfers(int num_samples[$]);
automatic AxisPacket_t send[$];
automatic AxisPacket_t expected[$];
automatic int sample_sum = 0;
test.start_test({TEST_NAME,"Test Transfer"}, 200us);
foreach (num_samples[i]) begin
automatic raw_pkt_t pay;
expected[i] = new;
send[i] = new;
get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256),
.ramp_inc(1),.pkt(pay),.SWIDTH(8));
sample_sum += num_samples[i];
send[i].push_bytes(pay);
// rebuild the expected packet for comparison without the preamble
expected[i].push_bytes(pay);
end
fork
begin // tx_thread
foreach (send[i]) begin
axi.put(send[i]);
end
end
begin //rx_thread
check_lbus(expected);
end
join
test.end_test();
endtask : test_transfers
//----------------------------------------------------
// Main test loop
//----------------------------------------------------
initial begin : tb_main
automatic int num_samples[$];
automatic int random_value;
clk_gen.reset();
// stalling is not allowed by whoever is reading the MAC
// i.e. ready is ignored
axi.set_master_stall_prob(0);
axi.run();
test_reset();
$display("Fixed Sequences");
num_samples = {64,65,66,67,68,69,70,71};
test_transfers(num_samples);
num_samples = {64,128,256,512,256,64,64,64};
test_transfers(num_samples);
num_samples = {65,64,64,64,64,64,64,64};
test_transfers(num_samples);
num_samples = {65,64,80,80,80,80,80,80};
test_transfers(num_samples);
num_samples = {64,64,96,80,96,80,96,80};
test_transfers(num_samples);
$display("Tons of 64");
num_samples.delete();
repeat(1000) begin
num_samples.push_back(64);
end
test_transfers(num_samples);
$display("Tons of 65");
num_samples.delete();
repeat(1000) begin
num_samples.push_back(65);
end
test_transfers(num_samples);
$display("Tons of Random");
num_samples.delete();
repeat(1000) begin
random_value = $urandom_range(64,512);
num_samples.push_back(random_value);
end
test_transfers(num_samples);
// End the TB, but don't $finish, since we don't want to kill other
// instances of this testbench that may be running.
test.end_tb(0);
// Kill the clocks to end this instance of the testbench
clk_gen.kill();
end // initial begin
endmodule
top/x400/ip/eth_100g_bd/lbus_tb/lbus_all_tb.sv
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: lbus_all_tb
//
// Description:
//
// Testbench for LBU<->AXI
//
module lbus_all_tb #(
/* no PARAM */
)(
/* no IO */
);
lbus_axi_tb #(.TEST_NAME("L2A")) L2A ();
axi_lbus_tb #(.TEST_NAME("A2L")) A2L ();
endmodule
top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: lbus_axi_tb
//
// Description:
//
// Testbench for eth_interface
//
module lbus_axi_tb #(
parameter TEST_NAME = ""
)(
/* no IO */
);
// Include macros and time declarations for use with PkgTestExec
`define TEST_EXEC_OBJ test
`include "test_exec.svh"
import PkgAxiStreamBfm::*;
import PkgEthernet::*;
import PkgTestExec::*;
import PkgEth100gLbus::*;
localparam DATA_WIDTH = 512;
localparam USER_WIDTH = $clog2(DATA_WIDTH/8)+1;
localparam NUM_SEG = 4;
localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG;
localparam SEG_BYTES = SEG_DATA_WIDTH/8;
//----------------------------------------------------
// clocks
//----------------------------------------------------
logic clk;
logic rst;
sim_clock_gen #(.PERIOD(5), .AUTOSTART(1))
clk_gen (.clk(clk), .rst(rst));
//----------------------------------------------------
//interfaces
//----------------------------------------------------
AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
axis (clk, rst);
AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
axig (clk, rst);
//----------------------------------------------------
// DUT
//----------------------------------------------------
lbus_t lbus_in [NUM_SEG-1:0];
eth_100g_lbus2axi #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT (
.axis(axis),
.lbus_in(lbus_in)
);
//----------------------------------------------------
// Xilinx golden model
// When Xilinx is generated with an AXI interface xilinx prints
// a lbus2axis converter that has trouble meeting timing
// this is preserved to allow comparison to that
// TODO: remove when timing is passing and refactor is done
//----------------------------------------------------
/*
eth_100g_bd_cmac_usplus_0_0_lbus2axis_segmented_top GOLD (
.core_clk(clk),
.core_rst(rst),
// AXIS IF
.axis_tvalid(axig.tvalid),
.axis_tdata(axig.tdata),
.axis_tlast(axig.tlast),
.axis_tkeep(axig.tkeep),
.axis_tuser(),
// Segment 0
.lbus_ena0(lbus_in[0].ena),
.lbus_data0(lbus_in[0].data),
.lbus_sop0(lbus_in[0].sop),
.lbus_eop0(lbus_in[0].eop),
.lbus_mty0(lbus_in[0].mty),
.lbus_err0(lbus_in[0].err),
// Segment 1
.lbus_ena1(lbus_in[1].ena),
.lbus_data1(lbus_in[1].data),
.lbus_sop1(lbus_in[1].sop),
.lbus_eop1(lbus_in[1].eop),
.lbus_mty1(lbus_in[1].mty),
.lbus_err1(lbus_in[1].err),
// Segment 2
.lbus_ena2(lbus_in[2].ena),
.lbus_data2(lbus_in[2].data),
.lbus_sop2(lbus_in[2].sop),
.lbus_eop2(lbus_in[2].eop),
.lbus_mty2(lbus_in[2].mty),
.lbus_err2(lbus_in[2].err),
// Segment 3
.lbus_ena3(lbus_in[3].ena),
.lbus_data3(lbus_in[3].data),
.lbus_sop3(lbus_in[3].sop),
.lbus_eop3(lbus_in[3].eop),
.lbus_mty3(lbus_in[3].mty),
.lbus_err3(lbus_in[3].err)
);
*/
//----------------------------------------------------
//BFMS
//----------------------------------------------------
TestExec test = new();
AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =
new(.slave(axis),.master(null));
//---------------------------------------------------------------------------
// Tests
//---------------------------------------------------------------------------
// use Test timeout to check reset goes away
task test_reset();
test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
wait(!rst);
repeat (10) @(posedge clk);
test.end_test();
endtask : test_reset
typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;
typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;
task automatic clear_lbus_in();
for (int i=0 ; i < NUM_SEG ; ++i) begin
lbus_in[i].data = 'b0;
lbus_in[i].mty = 'b0;
lbus_in[i].sop = 1'b0;
lbus_in[i].eop = 1'b0;
lbus_in[i].err = 1'b0;
lbus_in[i].ena = 1'b0;
end
endtask : clear_lbus_in;
task automatic send_lbus(AxisPacket_t packets[$]);
int seg = 0;
int b = 0;
int idle_insert = 0;
// loop over packets
foreach(packets[i]) begin
automatic raw_pkt_t pay;
pay = packets[i].dump_bytes;
// set for the first segment
lbus_in[seg].sop = 1;
// empty this packets payload
while (pay.size() > 0) begin
lbus_in[seg].ena = 1;
lbus_in[seg].data |= pay.pop_front()<<(SEG_DATA_WIDTH-b*8-8);
if (pay.size() == 0) begin
lbus_in[seg].eop = 1;
lbus_in[seg].mty = SEG_DATA_WIDTH-1-b;
end
if (seg == NUM_SEG-1 && b == SEG_DATA_WIDTH/8-1) begin
@(posedge clk);
clear_lbus_in();
idle_insert++;
// insert period idle period
if (idle_insert > 2) begin
@(posedge clk);
idle_insert =0;
end
end
b = (b+1) % (SEG_DATA_WIDTH/8);
if (b==0) begin
seg = (seg+1) % NUM_SEG;
end
end // pay.size > 0
if (b != 0) begin
seg = (seg+1) % NUM_SEG;
if (seg == 0) begin
@(posedge clk);
clear_lbus_in();
idle_insert++;
// insert period idle period
if (idle_insert > 2) begin
@(posedge clk);
idle_insert =0;
end
end
b = 0;
end
// 25% of the time we start a new packet
if ($urandom_range(99) < 25) begin
b = 0;
seg = 0;
// 25% of the time add an idle cycle
if ($urandom_range(99) < 25) begin
@(posedge clk);
clear_lbus_in();
idle_insert++;
// insert period idle period
if (idle_insert > 2) begin
idle_insert =0;
@(posedge clk);
end
@(posedge clk);
end else begin
@(posedge clk);
clear_lbus_in();
idle_insert++;
// insert period idle period
if (idle_insert > 2) begin
idle_insert =0;
@(posedge clk);
end
end
end
end // foreach packet
@(posedge clk);
clear_lbus_in();
endtask : send_lbus;
task automatic compare_packet(AxisPacket_t actual, expected);
automatic XportPacket_t actual_copy = new();
automatic XportPacket_t expected_copy = new();
actual_copy.import_axis(actual);
expected_copy.import_axis(expected);
expected_copy.tkeep_to_tuser();
actual_copy.clear_unused_bytes();
if (!expected_copy.equal(actual_copy)) begin
$display("Expected");
expected_copy.print();
$display("Actual");
actual_copy.print();
if (!expected_copy.equal(actual_copy))
$error("ERROR :: packet mismatch");
end
endtask : compare_packet;
task automatic test_transfers(int num_samples[$]);
automatic AxisPacket_t send[$];
automatic AxisPacket_t expected[$];
automatic int sample_sum = 0;
test.start_test({TEST_NAME,"Test Transfer"}, 200us);
foreach (num_samples[i]) begin
automatic raw_pkt_t pay;
expected[i] = new;
send[i] = new;
get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256),
.ramp_inc(1),.pkt(pay),.SWIDTH(8));
sample_sum += num_samples[i];
send[i].push_bytes(pay);
// rebuild the expected packet for comparison without the preamble
expected[i].push_bytes(pay);
end
fork
begin // tx_thread
send_lbus(send);
end
begin //rx_thread
foreach(expected[i]) begin
automatic AxisPacket_t actual;
axi.get(actual);
compare_packet(actual,expected[i]);
end
end
join
test.end_test();
endtask : test_transfers
//----------------------------------------------------
// Main test loop
//----------------------------------------------------
initial begin : tb_main
automatic int num_samples[$];
automatic int random_value;
clk_gen.reset();
// stalling is not allowed by whoever is reading the MAC
// i.e. ready is ignored
axi.slave_tready_init = 1'b1;
axi.set_master_stall_prob(0);
axi.set_slave_stall_prob(0);
axi.run();
clear_lbus_in();
test_reset();
$display("Fixed Sequences");
num_samples = {64,65,66,67,68,69,70,71};
test_transfers(num_samples);
num_samples = {64,128,256,512,256,64,64,64};
test_transfers(num_samples);
num_samples = {65,64,64,64,64,64,64,64};
test_transfers(num_samples);
num_samples = {65,64,80,80,80,80,80,80};
test_transfers(num_samples);
num_samples = {64,64,96,80,96,80,96,80};
test_transfers(num_samples);
$display("Tons of 64");
num_samples.delete();
repeat(1000) begin
num_samples.push_back(64);
end
test_transfers(num_samples);
$display("Tons of 65");
num_samples.delete();
repeat(1000) begin
num_samples.push_back(65);
end
test_transfers(num_samples);
$display("Tons of Random");
num_samples.delete();
repeat(1000) begin
random_value = $urandom_range(64,512);
num_samples.push_back(random_value);
end
test_transfers(num_samples);
// End the TB, but don't $finish, since we don't want to kill other
// instances of this testbench that may be running.
test.end_tb(0);
// Kill the clocks to end this instance of the testbench
clk_gen.kill();
end // initial begin
endmodule

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