61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
30 lines
1.0 KiB
Tcl
30 lines
1.0 KiB
Tcl
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# QSFP28 Port 1 (Lane 0) pin constraints for X410.
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#
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###############################################################################
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# Pin constraints for the MGTs (QSFP28 ports)
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###############################################################################
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# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
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# Lane 0 (X0Y4)
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set_property PACKAGE_PIN AA38 [get_ports {QSFP1_0_RX_P}]
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set_property PACKAGE_PIN AA39 [get_ports {QSFP1_0_RX_N}]
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set_property PACKAGE_PIN Y35 [get_ports {QSFP1_0_TX_P}]
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set_property PACKAGE_PIN Y36 [get_ports {QSFP1_0_TX_N}]
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###############################################################################
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# GTY_RCV_CLK_P can only be used with QSFP1
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###############################################################################
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set_property PACKAGE_PIN Y31 [get_ports {GTY_RCV_CLK_P}]
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set_property PACKAGE_PIN Y32 [get_ports {GTY_RCV_CLK_N}]
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set_property IOSTANDARD DIFF_SSTL12 [get_ports {GTY_RCV_CLK_*}]
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