61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
37 lines
958 B
Systemverilog
37 lines
958 B
Systemverilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: PkgEth100gLbus
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//
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// Description:
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//
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// Package to define an Lbus record
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//
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//-----------------------------------------------------------------------------
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// Lbus interface
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//
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// This is the segmented local bus interface on the Xilinx CMAC IP
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// see Xilinx CMAC documentation for detail
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// https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
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//-----------------------------------------------------------------------------
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package PkgEth100gLbus;
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localparam DATA_WIDTH = 512;
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localparam NUM_SEG = 4;
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localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG;
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typedef struct packed {
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logic [SEG_DATA_WIDTH-1:0] data;
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logic [$clog2(SEG_DATA_WIDTH/8)-1:0] mty;
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logic sop;
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logic eop;
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logic err;
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logic ena;
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} lbus_t;
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endpackage : PkgEth100gLbus
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