61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
51 lines
994 B
Devicetree
51 lines
994 B
Devicetree
/*
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* Copyright 2021 Ettus Research, a National Instruments Brand
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*
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* SPDX-License-Identifier: LGPL-3.0-or-later
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*/
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&fpga_full {
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#address-cells = <2>;
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#size-cells = <2>;
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misc_clk_3: misc_clk_3 {
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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compatible = "fixed-clock";
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};
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// AXI DMA engine + control
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nixge_internal: ethernet@10000A4000 {
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compatible = "ni,xge-enet-3.00";
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reg = <0x10 0x000A4000 0x0 0x4000
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0x10 0x000A8000 0x0 0x2000>;
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reg-names = "dma", "ctrl";
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clocks = <&misc_clk_3>;
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clock-names = "bus_clk";
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interrupts = <0 104 4 0 105 4>;
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interrupt-names = "tx", "rx";
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interrupt-parent = <&gic>;
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status = "okay";
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phy-mode = "internal";
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local-mac-address = <0x00 0x01 0x02 0x03 0x04 0x05>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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// Misc internal Ethernet registers
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uio@10000AA000 {
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compatible = "usrp-uio";
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reg = <0x10 0x000AA000 0x0 0x2000>;
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reg-names = "misc-enet-int-regs";
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status = "okay";
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};
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};
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