61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
18 lines
548 B
Plaintext
18 lines
548 B
Plaintext
# This file contains all testbenches to exlcude from the filter
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# list discovered by run_testbenches.py
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# NOTE: Lines containing "#" are treated as a comment
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top/e31x/sim/dram_test
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top/n3xx/sim/arm_to_sfp_loopback
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top/n3xx/sim/aurora_loopback
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top/n3xx/sim/one_gig_eth_loopback
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top/n3xx/sim/ten_gig_eth_loopback
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top/x300/sim/x300_pcie_int
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# These testbenches only work in ModelSim
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lib/axi4s_sv/axi4s_remove_bytes_tb
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lib/axi4s_sv/axi4s_add_bytes_tb
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lib/rfnoc/xport_sv/eth_interface_tb
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top/x400/sim/x4xx_qsfp_wrapper
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top/x400/ip/eth_100g_bd/lbus_tb
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