Wade Fife 3a6961a3f4 fpga: lib: Clean up and document lib files ...

Clean-up and document axi_tag_time, dds_freq_tune, and axi_sync.


Original-commit: 8edd13e6eba61ef2bfd96c7dc88b2642decbaa7a

2021-08-08 14:59:26 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Clean up and document lib files

2021-08-08 14:59:26 -05:00

sim

fpga: sim: Check for empty packet in clear_unused_bytes

2021-06-17 08:16:59 -05:00

tools

fpga: x400: Add makefiles for RF testbenches

2021-06-17 08:16:59 -05:00

top

N3xx: Fix White Rabbit

2021-08-04 15:19:58 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%