miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
207 Commits 1 Branch 0 Tags
3b15237d6bef83b0496cdc2eae330ae9e397723a
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Wade Fife 3b15237d6b x300: Fix sfpp_io_core tuser width 
Original-commit: 34b51b40f59412ae42e99246a60dd70de53ee180
2021-08-27 08:24:07 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
sim: Update chdr_16sc_to_sc12 testbench
2021-08-10 15:19:32 -05:00
sim
fpga: sim: Add PkgComplex, PkgMath, and PkgRandom
2021-08-08 14:59:26 -05:00
tools
fpga: Fix Xilinx bitfile parser for Python 3
2021-08-24 09:45:36 -05:00
top
x300: Fix sfpp_io_core tuser width
2021-08-27 08:24:07 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
S
Description
No description provided
84 MiB
Languages
Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%