Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ab93cb0929b9536b6d6cbfdc4813e6ba169053ae
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
Enable USE_AS_BUFF on packet gate to allow many packets to be buffered.
This reduces latency when several small packets are sent out close
together.
Original-commit: 32d348efe482d40c7090d8203a3c1374dfcb4a68
Fix the TUSER width for some buses in eth_ipv4_chdr_adapter. This
allows wider CHDR widths to be used with 10 GbE.
Original-commit: f0ed58f7518410fc174a6356c072dfb21e3de253
Moves X4C_100, X4C_200, C1_100, and C1_200 from experimental to
available targets and makes the needed changes to allow them to build
successfully.
Adds support for "UC" FPGA variant. U indicates that QSFP0 is unused
and C indicates that QSFP1 is 100 GbE.
Adds experimental CG_200 variant.
Original-commit: cb9609c886b156e22ae9d879fffad8d060f2ca2d
Removes the CPU_W parameter from x4xx.v and the qsfp_wrapper files. The
value of this parameter depends on the axi_eth_dma IP and therefore
should not be changed.
Original-commit: 84c49f40adc980e2968a6a844b4bdbb2d2d38c9c
This means that the stream endpoint's crossbar connection can be wider
and therefore support a higher bandwidth than the RFNoC block to which
the endpoint is connected. This improves host streaming performance.
Original-commit: 6e15e8bdb668163d51ff9e4099f587fde404ec63
Both the chdr_stream_output and chdr_xb_ingress_buff have a packet
gate, making one of them somewhat redundant. Removing one of them
reduces latency and frees up FPGA resources.
Original-commit: 9533bd025d74787d25b135d3092bffa1b51f6731
This adds a parameter to chdr_xb_ingress_buff and to chdr_stream_output
to make their packet gates optional. They are included by default.
Having the packet gate in chdr_xb_ingress_buff can reduce contention in
the crossbar. Having the packet gate in chdr_stream_output can reduce
the latency for non-data packets (e.g., stream status updates).
Original-commit: 67e0a5a340c14cb0c6ee170fb17be2c09737d723
This adds support for different widths on each port and adds the
ability to disable routes within the crossbar. Both of these features
allow for FPGA resource savings.
These features are controlled by the new parameters PORT_WIDTHS and
ENABLED_PATHS. Unused routes will have the associated logic removed.
A new testbench adds support for testing different port widths and
disabled routes. It also adds more rigrous testing of the crossbar.
Original-commit: 18bf81d91055b68765c44ca86a2cbcfa9704c749
Adds a BUILD_BASE_DIR makefile variable that allows you to specify the
base directory for FPGA build outputs. This allows you to put the
output from each run of make into a unique directory, or to run
multiple instances of make in parallel with each build's output being
put in a different directory. For example:
make X310_XG BUILD_BASE_DIR=/path/to/builds
Original-commit: bc6db8409ba756bbad0d0c158ffb00c614b58fd9
Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.
For example, you could run the following to produce an FPGA build with
different timing results from the default build:
make X310_XG BUILD_SEED=123
Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
This fixes recognition of $error and $fatal statements in the output of
XSim when running run_testbenches.py. XSim apparently prints a "shift
in" character (0x15) as part of its error statements, so the regular
expression was not matching.
Original-commit: ee36d7fabcf73f773edae00fbb1604a600db992d
This adds time alignment to the radio, so that the first transmitted or
received sample gets shifted into the position corresponding to its
timestamp. The applies only to configurations in which SPC > 1.
For example, if the radio time is incrementing by 4 samples per cycle
(SPC = 4) starting at time 0, and a packet is supposed to be
transmitted at time 201, then the data must be left-shifted by one
sample (201 % 4 = 1), so that the first sample of the packet correctly
aligns with the radio sample corresponding to time 201. Things get more
complicated if the radio time is not a multiple of the SPC (i.e., the
radio time started at time 1, 2, or 3 instead of 0).
Original-commit: 9afa6be7b270047cb03cbd5a16482e5d19edc3dd
This module supports timed sample alignment by shifting radio words
with multiple samples per cycle to put the first sample into the
correct position for the required timestamp.
Original-commit: 0a13db4afaaf88dda3bd194bbf20271c690d5c7f
Patch AR76780 was already listed as a requirement for X4xx and N3xx,
but was not listed as a requirement for X3xx and E3xx. This change
makes it required for all Vivado-based USRPs.
Original-commit: 5aa6bc4418a30d6e6fde80b80632f9f9115ea5c4
- Fix NODE_INST
- Fix RFNOC_PROTOVER
- Add option to use SystemVerilog transport adapter for raw UDP
Original-commit: 0114e108af63d9ac785649c8099a042299624943
- Fix NODE_INST
- Fix RFNOC_PROTOVER
- Add option to use SystemVerilog transport adapter for raw UDP
Original-commit: 693ec2c896306bcba3686385e5861593040d4cbd
This adds several features to the SystemVerilog Eth/IPv4/UDP transport
adaptor including:
- Compat register
- NODE_INST register
- Capabilities register
- KV map access for custom routing on RX data paths
- CHDR header removal for raw payloads to be sent over UDP
Also adds xport_adapter_ctrl.py, which allows controlling the new
registers.
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3
Set the NODE_INST parameter for each transport adapter on X4xx so that
each adapter has a unique node instance number.
Original-commit: 8e87a4d24aeeb77a9528ff67a36d8a0ae12e7137
The NODE_INST parameter was set to 0. This adds it as a parameter so
that each transport adapter can have a unique node instance number.
Original-commit: c6bfd2e7f8313d727c2e557958f1b1ac2f674d98
The NET_CHDR_W parameter tells the transport adapter what CHDR width
is used in transport packets, such as Ethernet packets. By default the
CHDR width used by the transport and RFNoC core will be the same. The
NET_CHDR_W parameter can be used in situations where the RFNoC core
expects a CHDR width from the transport adapter that is different from
that used over the network. In this situation, the transport adapter
will rewrite the CHDR packets so that each side gets the expected CHDR
width.
Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
In Vivado 2021.1, it is no longer allowed to use "default: 0" to
initialize an enum within a packed struct. So we must initalize enum
data members explicitly now.
Original-commit: 8007b6b4dff5b64d476b2e3ccb68a777c2f02c8b
This fixes some issues with the 2021.1 version of the 10 GbE IP. In the
new version, link status is sporadically detected by the Xilinx IP when
nothing is connected to the port. Also, when the SFP is inserted, the
link status goes up and down multiple times. This change fixes this by
adding a counter and only considering it "linked" when the link has
been stable for some amount of time.
Original-commit: 846c7be2e42f1db6d7c7cc0b1128e014f83e3bae
This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.
Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.
New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.
For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:
make -j4 X310_IP
Or, build two X310 bitstreams simultaneously:
make -j2 X310_XG X310_HG
Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".
Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a
This causes the latest RFNoC protocol version to be used by default
and avoids the need to update YAML files every time the RFNoC
protocol version gets bumped.
Original-commit: 92016a585a5223a9a7678134e318e412875b64c2
Update USRP RFNoC iamge core YAML files to use the more consistent
device port names. Clean up the formatting and make the files more
consistent.
Original-commit: 6318eaeff548f760056af7c8172937a296409d25
This updates all RFNoC devices so that they get the RFNoC protocol
version and CHDR width in the same way, from the output generated by
the RFNoC image builder.
Original-commit: 6f038dc2f69b38e715206b2e700fdd3a1bbc638e
Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to
IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.
Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3
Before this change, the packet size output by the Replay block during
playback was limited to length of a full memory burst transaction.
This led to relatively small packets during playback (typically
2 KiB) and had other side effects, such as simultaneous playback from
two different memory locations using different packet sizes because of
differences in memory alignment.
With this change, the configured packet size, as set by the register
REG_PLAY_WORDS_PER_PKT, is used for all packets except the last
packet of playback, which can of course be smaller.
Original-commit: 082a733c326d6332d581d5b7bf9ee86a503ba502
This sets the Replay block's counter width so that memory bursts are
up to 2 KiB. Previously, the counter width was fixed, which meant
that wide memories would require especially large buffers and could
exceed the 4 KiB limit imposed by AXI.
Original-commit: 08d03f881e2767f45ab7fc18c8003c9739b0ffb2
Change the width of the crossbar in the AXI Interconnect IP from
256-bit to 512-bit to match the DRAM memory controller width and to
give better performance.
Original-commit: 822cd03c8cd686f8b0554774adcbdd3803128bc2
Wade Fife