Wade Fife c09489b6b0 fpga: sim: Support unused tkeep in AxiStreamPacket::dump_bytes() ...

Original-commit: 0af84329a7d0f8c97131e14a522a2e0939dbb951

2022-08-29 17:01:45 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add compat to Verilog transport adapter

2022-08-29 17:01:45 -05:00

sim

fpga: sim: Support unused tkeep in AxiStreamPacket::dump_bytes()

2022-08-29 17:01:45 -05:00

tools

fpga: tools: Fix HLS IP builder for Vivado 2021.1

2022-08-25 13:55:30 -05:00

top

fpga: n3xx: Bump FPGA compat to 8.1

2022-08-29 17:01:45 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%