fpga: x400: Use x410_200 image core for x410_100 images
Original-commit: 23c856d4d9152153e34699e7507c4363c99b6124
This commit is contained in:
Wade Fife
+3
-4
@@ -71,7 +71,6 @@ BUILD_SEED ?= 0
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DEFS += BUILD_SEED=$(BUILD_SEED)
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# Defaults specific to the various targets:
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X410_100_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
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X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
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X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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X410_400_128_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_128_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_128_static_router.hex)
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@@ -125,15 +124,15 @@ endif
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##* Note: Not all targets are shipped with UHD
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X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X1_100)
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X410_XG_100: X410_IP build/usrp_x410_fpga_XG_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,XG_100)
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X410_X4_100: X410_IP build/usrp_x410_fpga_X4_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X4_100)
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X410_X1_200: X410_IP build/usrp_x410_fpga_X1_200.dts
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File diff suppressed because it is too large
Load Diff
@@ -1,21 +0,0 @@
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//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for x410)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2022-04-05T20:50:53.089049
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// Source: ./x410_100_rfnoc_image_core.yml
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// Source SHA256: 73ccfd5525b2438c74beb7694091d456ae10bff92ceaab68946dd8b00a052ea0
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//
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`define CHDR_WIDTH 64
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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@@ -1,154 +0,0 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'x410' # USRP type
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image_core_name: 'x410_100' # Name to use for the RFNoC Image Core files
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default_target: 'X410_XG_100' # Default make target
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size_bytes: 262144 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep2:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep3:
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ctrl: False
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data: True
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buff_size_bytes: 262144
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ep4:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep5:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep6:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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ep7:
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ctrl: False
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data: True
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buff_size_bytes: 32768
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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duc0: # NoC block name
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block_desc: 'duc.yml' # Block device descriptor file
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parameters:
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NUM_PORTS: 2
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ddc0:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio0:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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NIPC: RADIO_NIPC
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duc1:
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block_desc: 'duc.yml'
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parameters:
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NUM_PORTS: 2
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ddc1:
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block_desc: 'ddc.yml'
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parameters:
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NUM_PORTS: 2
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radio1:
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block_desc: 'radio.yml'
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parameters:
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NUM_PORTS: 2
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NIPC: RADIO_NIPC
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replay0:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 4
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MEM_DATA_W: 64
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MEM_ADDR_W: 32
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# RF A:0 TX
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- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
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- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
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# RF A:0 RX
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- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
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- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
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# RF A:1 TX
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- { srcblk: ep1, srcport: out0, dstblk: duc0, dstport: in_1 }
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- { srcblk: duc0, srcport: out_1, dstblk: radio0, dstport: in_1 }
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# RF A:1 RX
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- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
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- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
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#
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# RF B:0 TX
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- { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
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- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
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# RF B:0 RX
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- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
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- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
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# RF B:1 TX
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- { srcblk: ep3, srcport: out0, dstblk: duc1, dstport: in_1 }
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- { srcblk: duc1, srcport: out_1, dstblk: radio1, dstport: in_1 }
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# RF B:1 RX
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- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
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- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
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#
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# Replay Connections
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- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
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- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
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- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
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- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
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- { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 }
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- { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 }
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- { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 }
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- { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
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- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
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- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
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- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
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- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce }
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- { srcblk: _device_, srcport: radio, dstblk: ddc0, dstport: ce }
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- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: radio, dstblk: duc1, dstport: ce }
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- { srcblk: _device_, srcport: radio, dstblk: ddc1, dstport: ce }
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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@@ -1,25 +0,0 @@
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00000018
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00400240
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024002c0
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02c00280
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02800040
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00800241
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024102c1
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02c10281
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02810080
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00c00300
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03000380
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03800340
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034000c0
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01000301
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03010381
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03810341
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03410100
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014003c0
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03c00140
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018003c1
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03c10180
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01c003c2
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03c201c0
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020003c3
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03c30200
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