fpga: x400: Add CE clock
Adds a 266.667 MHz compute engine clock and uses it instead of the radio clock for the DDC and DUC. Using a faster clock than the radio allows the DDC and DUC to drain after a stall in the data flow. Original-commit: ab93cb0929b9536b6d6cbfdc4813e6ba169053ae
This commit is contained in:
Wade Fife
@@ -52,6 +52,7 @@ create_clock -name clk166 -period 6.000 \
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create_clock -name clk200 -period 5.000 \
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[get_pins -of_objects [get_cells -hierarchical {*PS8_i}] -filter {NAME =~ *PLCLK[3]}]
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create_generated_clock -name ce_clk [get_pins {ce_clk_gen_i/CLKOUT0}]
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###############################################################################
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# Sync to DB synthesizer sync CPLD input
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@@ -39,6 +39,7 @@ module rfnoc_image_core #(
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input wire radio_clk,
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input wire radio_2x_clk,
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input wire dram_clk,
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input wire ce_clk,
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// Basic
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input wire [ 15:0] device_id,
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@@ -69,65 +70,65 @@ module rfnoc_image_core #(
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// time
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input wire [ 63:0] radio_time,
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// radio0
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input wire [ 255:0] radio_rx_data_radio0,
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input wire [ 7:0] radio_rx_stb_radio0,
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output wire [ 7:0] radio_rx_running_radio0,
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output wire [ 255:0] radio_tx_data_radio0,
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input wire [ 7:0] radio_tx_stb_radio0,
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output wire [ 7:0] radio_tx_running_radio0,
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input wire [1023:0] radio_rx_data_radio0,
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input wire [ 31:0] radio_rx_stb_radio0,
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output wire [ 31:0] radio_rx_running_radio0,
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output wire [1023:0] radio_tx_data_radio0,
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input wire [ 31:0] radio_tx_stb_radio0,
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output wire [ 31:0] radio_tx_running_radio0,
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// radio1
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input wire [ 255:0] radio_rx_data_radio1,
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input wire [ 7:0] radio_rx_stb_radio1,
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output wire [ 7:0] radio_rx_running_radio1,
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output wire [ 255:0] radio_tx_data_radio1,
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input wire [ 7:0] radio_tx_stb_radio1,
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output wire [ 7:0] radio_tx_running_radio1,
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input wire [1023:0] radio_rx_data_radio1,
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input wire [ 31:0] radio_rx_stb_radio1,
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output wire [ 31:0] radio_rx_running_radio1,
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output wire [1023:0] radio_tx_data_radio1,
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input wire [ 31:0] radio_tx_stb_radio1,
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output wire [ 31:0] radio_tx_running_radio1,
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// dram
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input wire [ 0:0] axi_rst,
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output wire [ 3:0] m_axi_awid,
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output wire [ 191:0] m_axi_awaddr,
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output wire [ 31:0] m_axi_awlen,
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output wire [ 11:0] m_axi_awsize,
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output wire [ 7:0] m_axi_awburst,
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output wire [ 3:0] m_axi_awlock,
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output wire [ 15:0] m_axi_awcache,
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output wire [ 11:0] m_axi_awprot,
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output wire [ 15:0] m_axi_awqos,
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output wire [ 15:0] m_axi_awregion,
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output wire [ 3:0] m_axi_awuser,
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output wire [ 3:0] m_axi_awvalid,
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input wire [ 3:0] m_axi_awready,
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output wire [2047:0] m_axi_wdata,
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output wire [ 255:0] m_axi_wstrb,
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output wire [ 3:0] m_axi_wlast,
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output wire [ 3:0] m_axi_wuser,
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output wire [ 3:0] m_axi_wvalid,
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input wire [ 3:0] m_axi_wready,
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input wire [ 3:0] m_axi_bid,
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input wire [ 7:0] m_axi_bresp,
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input wire [ 3:0] m_axi_buser,
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input wire [ 3:0] m_axi_bvalid,
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output wire [ 3:0] m_axi_bready,
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output wire [ 3:0] m_axi_arid,
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output wire [ 191:0] m_axi_araddr,
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output wire [ 31:0] m_axi_arlen,
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output wire [ 11:0] m_axi_arsize,
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output wire [ 7:0] m_axi_arburst,
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output wire [ 3:0] m_axi_arlock,
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output wire [ 15:0] m_axi_arcache,
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output wire [ 11:0] m_axi_arprot,
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output wire [ 15:0] m_axi_arqos,
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output wire [ 15:0] m_axi_arregion,
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output wire [ 3:0] m_axi_aruser,
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output wire [ 3:0] m_axi_arvalid,
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input wire [ 3:0] m_axi_arready,
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input wire [ 3:0] m_axi_rid,
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input wire [2047:0] m_axi_rdata,
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input wire [ 7:0] m_axi_rresp,
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input wire [ 3:0] m_axi_rlast,
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input wire [ 3:0] m_axi_ruser,
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input wire [ 3:0] m_axi_rvalid,
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output wire [ 3:0] m_axi_rready,
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output wire [ 7:0] m_axi_awid,
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output wire [ 383:0] m_axi_awaddr,
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output wire [ 63:0] m_axi_awlen,
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output wire [ 23:0] m_axi_awsize,
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output wire [ 15:0] m_axi_awburst,
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output wire [ 7:0] m_axi_awlock,
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output wire [ 31:0] m_axi_awcache,
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output wire [ 23:0] m_axi_awprot,
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output wire [ 31:0] m_axi_awqos,
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output wire [ 31:0] m_axi_awregion,
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output wire [ 7:0] m_axi_awuser,
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output wire [ 7:0] m_axi_awvalid,
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input wire [ 7:0] m_axi_awready,
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output wire [4191:0] m_axi_wdata,
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output wire [ 511:0] m_axi_wstrb,
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output wire [ 7:0] m_axi_wlast,
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output wire [ 7:0] m_axi_wuser,
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output wire [ 7:0] m_axi_wvalid,
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input wire [ 7:0] m_axi_wready,
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input wire [ 7:0] m_axi_bid,
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input wire [ 15:0] m_axi_bresp,
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input wire [ 7:0] m_axi_buser,
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input wire [ 7:0] m_axi_bvalid,
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output wire [ 7:0] m_axi_bready,
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output wire [ 7:0] m_axi_arid,
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output wire [ 383:0] m_axi_araddr,
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output wire [ 63:0] m_axi_arlen,
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output wire [ 23:0] m_axi_arsize,
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output wire [ 15:0] m_axi_arburst,
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output wire [ 7:0] m_axi_arlock,
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output wire [ 31:0] m_axi_arcache,
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output wire [ 31:0] m_axi_arprot,
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output wire [ 31:0] m_axi_arqos,
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output wire [ 31:0] m_axi_arregion,
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output wire [ 7:0] m_axi_aruser,
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output wire [ 7:0] m_axi_arvalid,
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input wire [ 7:0] m_axi_arready,
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input wire [ 7:0] m_axi_rid,
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input wire [4191:0] m_axi_rdata,
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input wire [ 15:0] m_axi_rresp,
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input wire [ 7:0] m_axi_rlast,
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input wire [ 7:0] m_axi_ruser,
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input wire [ 7:0] m_axi_rvalid,
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output wire [ 7:0] m_axi_rready,
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// Transport Adapters ///////////////
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@@ -1123,12 +1124,12 @@ module rfnoc_image_core #(
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// time
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wire [ 63:0] radio0_radio_time;
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// radio
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wire [ 255:0] radio0_radio_rx_data;
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wire [ 7:0] radio0_radio_rx_stb;
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wire [ 7:0] radio0_radio_rx_running;
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wire [ 255:0] radio0_radio_tx_data;
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wire [ 7:0] radio0_radio_tx_stb;
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wire [ 7:0] radio0_radio_tx_running;
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wire [1023:0] radio0_radio_rx_data;
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wire [ 31:0] radio0_radio_rx_stb;
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wire [ 31:0] radio0_radio_rx_running;
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wire [1023:0] radio0_radio_tx_data;
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wire [ 31:0] radio0_radio_tx_stb;
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wire [ 31:0] radio0_radio_tx_running;
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rfnoc_block_radio #(
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.THIS_PORTID (4),
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@@ -1296,12 +1297,12 @@ module rfnoc_image_core #(
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// time
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wire [ 63:0] radio1_radio_time;
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// radio
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wire [ 255:0] radio1_radio_rx_data;
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wire [ 7:0] radio1_radio_rx_stb;
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wire [ 7:0] radio1_radio_rx_running;
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wire [ 255:0] radio1_radio_tx_data;
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wire [ 7:0] radio1_radio_tx_stb;
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wire [ 7:0] radio1_radio_tx_running;
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wire [1023:0] radio1_radio_rx_data;
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wire [ 31:0] radio1_radio_rx_stb;
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wire [ 31:0] radio1_radio_rx_running;
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wire [1023:0] radio1_radio_tx_data;
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wire [ 31:0] radio1_radio_tx_stb;
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wire [ 31:0] radio1_radio_tx_running;
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rfnoc_block_radio #(
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.THIS_PORTID (7),
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@@ -1367,50 +1368,50 @@ module rfnoc_image_core #(
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// axi_ram
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wire [ 0:0] replay0_axi_rst;
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wire [ 3:0] replay0_m_axi_awid;
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wire [ 191:0] replay0_m_axi_awaddr;
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wire [ 31:0] replay0_m_axi_awlen;
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wire [ 11:0] replay0_m_axi_awsize;
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wire [ 7:0] replay0_m_axi_awburst;
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wire [ 3:0] replay0_m_axi_awlock;
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wire [ 15:0] replay0_m_axi_awcache;
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wire [ 11:0] replay0_m_axi_awprot;
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wire [ 15:0] replay0_m_axi_awqos;
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wire [ 15:0] replay0_m_axi_awregion;
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wire [ 3:0] replay0_m_axi_awuser;
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wire [ 3:0] replay0_m_axi_awvalid;
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wire [ 3:0] replay0_m_axi_awready;
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wire [2047:0] replay0_m_axi_wdata;
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wire [ 255:0] replay0_m_axi_wstrb;
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wire [ 3:0] replay0_m_axi_wlast;
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wire [ 3:0] replay0_m_axi_wuser;
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wire [ 3:0] replay0_m_axi_wvalid;
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wire [ 3:0] replay0_m_axi_wready;
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wire [ 3:0] replay0_m_axi_bid;
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wire [ 7:0] replay0_m_axi_bresp;
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wire [ 3:0] replay0_m_axi_buser;
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wire [ 3:0] replay0_m_axi_bvalid;
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wire [ 3:0] replay0_m_axi_bready;
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wire [ 3:0] replay0_m_axi_arid;
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wire [ 191:0] replay0_m_axi_araddr;
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wire [ 31:0] replay0_m_axi_arlen;
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wire [ 11:0] replay0_m_axi_arsize;
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wire [ 7:0] replay0_m_axi_arburst;
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wire [ 3:0] replay0_m_axi_arlock;
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wire [ 15:0] replay0_m_axi_arcache;
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wire [ 11:0] replay0_m_axi_arprot;
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wire [ 15:0] replay0_m_axi_arqos;
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wire [ 15:0] replay0_m_axi_arregion;
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wire [ 3:0] replay0_m_axi_aruser;
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wire [ 3:0] replay0_m_axi_arvalid;
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wire [ 3:0] replay0_m_axi_arready;
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wire [ 3:0] replay0_m_axi_rid;
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wire [2047:0] replay0_m_axi_rdata;
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wire [ 7:0] replay0_m_axi_rresp;
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wire [ 3:0] replay0_m_axi_rlast;
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wire [ 3:0] replay0_m_axi_ruser;
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wire [ 3:0] replay0_m_axi_rvalid;
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wire [ 3:0] replay0_m_axi_rready;
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wire [ 7:0] replay0_m_axi_awid;
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wire [ 383:0] replay0_m_axi_awaddr;
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wire [ 63:0] replay0_m_axi_awlen;
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wire [ 23:0] replay0_m_axi_awsize;
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wire [ 15:0] replay0_m_axi_awburst;
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wire [ 7:0] replay0_m_axi_awlock;
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wire [ 31:0] replay0_m_axi_awcache;
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wire [ 23:0] replay0_m_axi_awprot;
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wire [ 31:0] replay0_m_axi_awqos;
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wire [ 31:0] replay0_m_axi_awregion;
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wire [ 7:0] replay0_m_axi_awuser;
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wire [ 7:0] replay0_m_axi_awvalid;
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wire [ 7:0] replay0_m_axi_awready;
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wire [4191:0] replay0_m_axi_wdata;
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wire [ 511:0] replay0_m_axi_wstrb;
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wire [ 7:0] replay0_m_axi_wlast;
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wire [ 7:0] replay0_m_axi_wuser;
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wire [ 7:0] replay0_m_axi_wvalid;
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wire [ 7:0] replay0_m_axi_wready;
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wire [ 7:0] replay0_m_axi_bid;
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wire [ 15:0] replay0_m_axi_bresp;
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wire [ 7:0] replay0_m_axi_buser;
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wire [ 7:0] replay0_m_axi_bvalid;
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wire [ 7:0] replay0_m_axi_bready;
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wire [ 7:0] replay0_m_axi_arid;
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wire [ 383:0] replay0_m_axi_araddr;
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wire [ 63:0] replay0_m_axi_arlen;
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wire [ 23:0] replay0_m_axi_arsize;
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wire [ 15:0] replay0_m_axi_arburst;
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wire [ 7:0] replay0_m_axi_arlock;
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wire [ 31:0] replay0_m_axi_arcache;
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wire [ 31:0] replay0_m_axi_arprot;
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wire [ 31:0] replay0_m_axi_arqos;
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wire [ 31:0] replay0_m_axi_arregion;
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wire [ 7:0] replay0_m_axi_aruser;
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wire [ 7:0] replay0_m_axi_arvalid;
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wire [ 7:0] replay0_m_axi_arready;
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wire [ 7:0] replay0_m_axi_rid;
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wire [4191:0] replay0_m_axi_rdata;
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wire [ 15:0] replay0_m_axi_rresp;
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wire [ 7:0] replay0_m_axi_rlast;
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wire [ 7:0] replay0_m_axi_ruser;
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wire [ 7:0] replay0_m_axi_rvalid;
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wire [ 7:0] replay0_m_axi_rready;
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rfnoc_block_replay #(
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.THIS_PORTID (8),
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@@ -1624,11 +1625,11 @@ module rfnoc_image_core #(
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//---------------------------------------------------------------------------
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assign radio0_radio_clk = radio_clk;
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assign duc0_ce_clk = radio_2x_clk;
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assign ddc0_ce_clk = radio_2x_clk;
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assign duc0_ce_clk = ce_clk;
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assign ddc0_ce_clk = ce_clk;
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assign radio1_radio_clk = radio_clk;
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assign duc1_ce_clk = radio_2x_clk;
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assign ddc1_ce_clk = radio_2x_clk;
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assign duc1_ce_clk = ce_clk;
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assign ddc1_ce_clk = ce_clk;
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assign replay0_mem_clk = dram_clk;
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@@ -145,9 +145,9 @@ connections:
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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- { srcblk: _device_, srcport: radio_2x, dstblk: duc0, dstport: ce }
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- { srcblk: _device_, srcport: radio_2x, dstblk: ddc0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
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- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
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- { srcblk: _device_, srcport: radio_2x, dstblk: duc1, dstport: ce }
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- { srcblk: _device_, srcport: radio_2x, dstblk: ddc1, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
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- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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@@ -39,6 +39,7 @@ module rfnoc_image_core #(
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input wire radio_clk,
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input wire radio_2x_clk,
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input wire dram_clk,
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input wire ce_clk,
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// Basic
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input wire [ 15:0] device_id,
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@@ -39,6 +39,7 @@ module rfnoc_image_core #(
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input wire radio_clk,
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input wire radio_2x_clk,
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input wire dram_clk,
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input wire ce_clk,
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// Basic
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input wire [ 15:0] device_id,
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@@ -69,65 +70,65 @@ module rfnoc_image_core #(
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// time
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input wire [ 63:0] radio_time,
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// radio0
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input wire [ 255:0] radio_rx_data_radio0,
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input wire [ 7:0] radio_rx_stb_radio0,
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output wire [ 7:0] radio_rx_running_radio0,
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output wire [ 255:0] radio_tx_data_radio0,
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input wire [ 7:0] radio_tx_stb_radio0,
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output wire [ 7:0] radio_tx_running_radio0,
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input wire [1023:0] radio_rx_data_radio0,
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input wire [ 31:0] radio_rx_stb_radio0,
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output wire [ 31:0] radio_rx_running_radio0,
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output wire [1023:0] radio_tx_data_radio0,
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input wire [ 31:0] radio_tx_stb_radio0,
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output wire [ 31:0] radio_tx_running_radio0,
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// radio1
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input wire [ 255:0] radio_rx_data_radio1,
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input wire [ 7:0] radio_rx_stb_radio1,
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output wire [ 7:0] radio_rx_running_radio1,
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output wire [ 255:0] radio_tx_data_radio1,
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input wire [ 7:0] radio_tx_stb_radio1,
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output wire [ 7:0] radio_tx_running_radio1,
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input wire [1023:0] radio_rx_data_radio1,
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input wire [ 31:0] radio_rx_stb_radio1,
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output wire [ 31:0] radio_rx_running_radio1,
|
||||
output wire [1023:0] radio_tx_data_radio1,
|
||||
input wire [ 31:0] radio_tx_stb_radio1,
|
||||
output wire [ 31:0] radio_tx_running_radio1,
|
||||
// dram
|
||||
input wire [ 0:0] axi_rst,
|
||||
output wire [ 3:0] m_axi_awid,
|
||||
output wire [ 191:0] m_axi_awaddr,
|
||||
output wire [ 31:0] m_axi_awlen,
|
||||
output wire [ 11:0] m_axi_awsize,
|
||||
output wire [ 7:0] m_axi_awburst,
|
||||
output wire [ 3:0] m_axi_awlock,
|
||||
output wire [ 15:0] m_axi_awcache,
|
||||
output wire [ 11:0] m_axi_awprot,
|
||||
output wire [ 15:0] m_axi_awqos,
|
||||
output wire [ 15:0] m_axi_awregion,
|
||||
output wire [ 3:0] m_axi_awuser,
|
||||
output wire [ 3:0] m_axi_awvalid,
|
||||
input wire [ 3:0] m_axi_awready,
|
||||
output wire [2047:0] m_axi_wdata,
|
||||
output wire [ 255:0] m_axi_wstrb,
|
||||
output wire [ 3:0] m_axi_wlast,
|
||||
output wire [ 3:0] m_axi_wuser,
|
||||
output wire [ 3:0] m_axi_wvalid,
|
||||
input wire [ 3:0] m_axi_wready,
|
||||
input wire [ 3:0] m_axi_bid,
|
||||
input wire [ 7:0] m_axi_bresp,
|
||||
input wire [ 3:0] m_axi_buser,
|
||||
input wire [ 3:0] m_axi_bvalid,
|
||||
output wire [ 3:0] m_axi_bready,
|
||||
output wire [ 3:0] m_axi_arid,
|
||||
output wire [ 191:0] m_axi_araddr,
|
||||
output wire [ 31:0] m_axi_arlen,
|
||||
output wire [ 11:0] m_axi_arsize,
|
||||
output wire [ 7:0] m_axi_arburst,
|
||||
output wire [ 3:0] m_axi_arlock,
|
||||
output wire [ 15:0] m_axi_arcache,
|
||||
output wire [ 11:0] m_axi_arprot,
|
||||
output wire [ 15:0] m_axi_arqos,
|
||||
output wire [ 15:0] m_axi_arregion,
|
||||
output wire [ 3:0] m_axi_aruser,
|
||||
output wire [ 3:0] m_axi_arvalid,
|
||||
input wire [ 3:0] m_axi_arready,
|
||||
input wire [ 3:0] m_axi_rid,
|
||||
input wire [2047:0] m_axi_rdata,
|
||||
input wire [ 7:0] m_axi_rresp,
|
||||
input wire [ 3:0] m_axi_rlast,
|
||||
input wire [ 3:0] m_axi_ruser,
|
||||
input wire [ 3:0] m_axi_rvalid,
|
||||
output wire [ 3:0] m_axi_rready,
|
||||
output wire [ 7:0] m_axi_awid,
|
||||
output wire [ 383:0] m_axi_awaddr,
|
||||
output wire [ 63:0] m_axi_awlen,
|
||||
output wire [ 23:0] m_axi_awsize,
|
||||
output wire [ 15:0] m_axi_awburst,
|
||||
output wire [ 7:0] m_axi_awlock,
|
||||
output wire [ 31:0] m_axi_awcache,
|
||||
output wire [ 23:0] m_axi_awprot,
|
||||
output wire [ 31:0] m_axi_awqos,
|
||||
output wire [ 31:0] m_axi_awregion,
|
||||
output wire [ 7:0] m_axi_awuser,
|
||||
output wire [ 7:0] m_axi_awvalid,
|
||||
input wire [ 7:0] m_axi_awready,
|
||||
output wire [4191:0] m_axi_wdata,
|
||||
output wire [ 511:0] m_axi_wstrb,
|
||||
output wire [ 7:0] m_axi_wlast,
|
||||
output wire [ 7:0] m_axi_wuser,
|
||||
output wire [ 7:0] m_axi_wvalid,
|
||||
input wire [ 7:0] m_axi_wready,
|
||||
input wire [ 7:0] m_axi_bid,
|
||||
input wire [ 15:0] m_axi_bresp,
|
||||
input wire [ 7:0] m_axi_buser,
|
||||
input wire [ 7:0] m_axi_bvalid,
|
||||
output wire [ 7:0] m_axi_bready,
|
||||
output wire [ 7:0] m_axi_arid,
|
||||
output wire [ 383:0] m_axi_araddr,
|
||||
output wire [ 63:0] m_axi_arlen,
|
||||
output wire [ 23:0] m_axi_arsize,
|
||||
output wire [ 15:0] m_axi_arburst,
|
||||
output wire [ 7:0] m_axi_arlock,
|
||||
output wire [ 31:0] m_axi_arcache,
|
||||
output wire [ 31:0] m_axi_arprot,
|
||||
output wire [ 31:0] m_axi_arqos,
|
||||
output wire [ 31:0] m_axi_arregion,
|
||||
output wire [ 7:0] m_axi_aruser,
|
||||
output wire [ 7:0] m_axi_arvalid,
|
||||
input wire [ 7:0] m_axi_arready,
|
||||
input wire [ 7:0] m_axi_rid,
|
||||
input wire [4191:0] m_axi_rdata,
|
||||
input wire [ 15:0] m_axi_rresp,
|
||||
input wire [ 7:0] m_axi_rlast,
|
||||
input wire [ 7:0] m_axi_ruser,
|
||||
input wire [ 7:0] m_axi_rvalid,
|
||||
output wire [ 7:0] m_axi_rready,
|
||||
|
||||
// Transport Adapters ///////////////
|
||||
|
||||
@@ -685,12 +686,12 @@ module rfnoc_image_core #(
|
||||
// time
|
||||
wire [ 63:0] radio0_radio_time;
|
||||
// radio
|
||||
wire [ 255:0] radio0_radio_rx_data;
|
||||
wire [ 7:0] radio0_radio_rx_stb;
|
||||
wire [ 7:0] radio0_radio_rx_running;
|
||||
wire [ 255:0] radio0_radio_tx_data;
|
||||
wire [ 7:0] radio0_radio_tx_stb;
|
||||
wire [ 7:0] radio0_radio_tx_running;
|
||||
wire [1023:0] radio0_radio_rx_data;
|
||||
wire [ 31:0] radio0_radio_rx_stb;
|
||||
wire [ 31:0] radio0_radio_rx_running;
|
||||
wire [1023:0] radio0_radio_tx_data;
|
||||
wire [ 31:0] radio0_radio_tx_stb;
|
||||
wire [ 31:0] radio0_radio_tx_running;
|
||||
|
||||
rfnoc_block_radio #(
|
||||
.THIS_PORTID (2),
|
||||
@@ -768,12 +769,12 @@ module rfnoc_image_core #(
|
||||
// time
|
||||
wire [ 63:0] radio1_radio_time;
|
||||
// radio
|
||||
wire [ 255:0] radio1_radio_rx_data;
|
||||
wire [ 7:0] radio1_radio_rx_stb;
|
||||
wire [ 7:0] radio1_radio_rx_running;
|
||||
wire [ 255:0] radio1_radio_tx_data;
|
||||
wire [ 7:0] radio1_radio_tx_stb;
|
||||
wire [ 7:0] radio1_radio_tx_running;
|
||||
wire [1023:0] radio1_radio_rx_data;
|
||||
wire [ 31:0] radio1_radio_rx_stb;
|
||||
wire [ 31:0] radio1_radio_rx_running;
|
||||
wire [1023:0] radio1_radio_tx_data;
|
||||
wire [ 31:0] radio1_radio_tx_stb;
|
||||
wire [ 31:0] radio1_radio_tx_running;
|
||||
|
||||
rfnoc_block_radio #(
|
||||
.THIS_PORTID (3),
|
||||
|
||||
@@ -39,6 +39,7 @@ module rfnoc_image_core #(
|
||||
input wire radio_clk,
|
||||
input wire radio_2x_clk,
|
||||
input wire dram_clk,
|
||||
input wire ce_clk,
|
||||
// Basic
|
||||
input wire [ 15:0] device_id,
|
||||
|
||||
@@ -69,65 +70,65 @@ module rfnoc_image_core #(
|
||||
// time
|
||||
input wire [ 63:0] radio_time,
|
||||
// radio0
|
||||
input wire [ 255:0] radio_rx_data_radio0,
|
||||
input wire [ 7:0] radio_rx_stb_radio0,
|
||||
output wire [ 7:0] radio_rx_running_radio0,
|
||||
output wire [ 255:0] radio_tx_data_radio0,
|
||||
input wire [ 7:0] radio_tx_stb_radio0,
|
||||
output wire [ 7:0] radio_tx_running_radio0,
|
||||
input wire [1023:0] radio_rx_data_radio0,
|
||||
input wire [ 31:0] radio_rx_stb_radio0,
|
||||
output wire [ 31:0] radio_rx_running_radio0,
|
||||
output wire [1023:0] radio_tx_data_radio0,
|
||||
input wire [ 31:0] radio_tx_stb_radio0,
|
||||
output wire [ 31:0] radio_tx_running_radio0,
|
||||
// radio1
|
||||
input wire [ 255:0] radio_rx_data_radio1,
|
||||
input wire [ 7:0] radio_rx_stb_radio1,
|
||||
output wire [ 7:0] radio_rx_running_radio1,
|
||||
output wire [ 255:0] radio_tx_data_radio1,
|
||||
input wire [ 7:0] radio_tx_stb_radio1,
|
||||
output wire [ 7:0] radio_tx_running_radio1,
|
||||
input wire [1023:0] radio_rx_data_radio1,
|
||||
input wire [ 31:0] radio_rx_stb_radio1,
|
||||
output wire [ 31:0] radio_rx_running_radio1,
|
||||
output wire [1023:0] radio_tx_data_radio1,
|
||||
input wire [ 31:0] radio_tx_stb_radio1,
|
||||
output wire [ 31:0] radio_tx_running_radio1,
|
||||
// dram
|
||||
input wire [ 0:0] axi_rst,
|
||||
output wire [ 3:0] m_axi_awid,
|
||||
output wire [ 191:0] m_axi_awaddr,
|
||||
output wire [ 31:0] m_axi_awlen,
|
||||
output wire [ 11:0] m_axi_awsize,
|
||||
output wire [ 7:0] m_axi_awburst,
|
||||
output wire [ 3:0] m_axi_awlock,
|
||||
output wire [ 15:0] m_axi_awcache,
|
||||
output wire [ 11:0] m_axi_awprot,
|
||||
output wire [ 15:0] m_axi_awqos,
|
||||
output wire [ 15:0] m_axi_awregion,
|
||||
output wire [ 3:0] m_axi_awuser,
|
||||
output wire [ 3:0] m_axi_awvalid,
|
||||
input wire [ 3:0] m_axi_awready,
|
||||
output wire [2047:0] m_axi_wdata,
|
||||
output wire [ 255:0] m_axi_wstrb,
|
||||
output wire [ 3:0] m_axi_wlast,
|
||||
output wire [ 3:0] m_axi_wuser,
|
||||
output wire [ 3:0] m_axi_wvalid,
|
||||
input wire [ 3:0] m_axi_wready,
|
||||
input wire [ 3:0] m_axi_bid,
|
||||
input wire [ 7:0] m_axi_bresp,
|
||||
input wire [ 3:0] m_axi_buser,
|
||||
input wire [ 3:0] m_axi_bvalid,
|
||||
output wire [ 3:0] m_axi_bready,
|
||||
output wire [ 3:0] m_axi_arid,
|
||||
output wire [ 191:0] m_axi_araddr,
|
||||
output wire [ 31:0] m_axi_arlen,
|
||||
output wire [ 11:0] m_axi_arsize,
|
||||
output wire [ 7:0] m_axi_arburst,
|
||||
output wire [ 3:0] m_axi_arlock,
|
||||
output wire [ 15:0] m_axi_arcache,
|
||||
output wire [ 11:0] m_axi_arprot,
|
||||
output wire [ 15:0] m_axi_arqos,
|
||||
output wire [ 15:0] m_axi_arregion,
|
||||
output wire [ 3:0] m_axi_aruser,
|
||||
output wire [ 3:0] m_axi_arvalid,
|
||||
input wire [ 3:0] m_axi_arready,
|
||||
input wire [ 3:0] m_axi_rid,
|
||||
input wire [2047:0] m_axi_rdata,
|
||||
input wire [ 7:0] m_axi_rresp,
|
||||
input wire [ 3:0] m_axi_rlast,
|
||||
input wire [ 3:0] m_axi_ruser,
|
||||
input wire [ 3:0] m_axi_rvalid,
|
||||
output wire [ 3:0] m_axi_rready,
|
||||
output wire [ 7:0] m_axi_awid,
|
||||
output wire [ 383:0] m_axi_awaddr,
|
||||
output wire [ 63:0] m_axi_awlen,
|
||||
output wire [ 23:0] m_axi_awsize,
|
||||
output wire [ 15:0] m_axi_awburst,
|
||||
output wire [ 7:0] m_axi_awlock,
|
||||
output wire [ 31:0] m_axi_awcache,
|
||||
output wire [ 23:0] m_axi_awprot,
|
||||
output wire [ 31:0] m_axi_awqos,
|
||||
output wire [ 31:0] m_axi_awregion,
|
||||
output wire [ 7:0] m_axi_awuser,
|
||||
output wire [ 7:0] m_axi_awvalid,
|
||||
input wire [ 7:0] m_axi_awready,
|
||||
output wire [4191:0] m_axi_wdata,
|
||||
output wire [ 511:0] m_axi_wstrb,
|
||||
output wire [ 7:0] m_axi_wlast,
|
||||
output wire [ 7:0] m_axi_wuser,
|
||||
output wire [ 7:0] m_axi_wvalid,
|
||||
input wire [ 7:0] m_axi_wready,
|
||||
input wire [ 7:0] m_axi_bid,
|
||||
input wire [ 15:0] m_axi_bresp,
|
||||
input wire [ 7:0] m_axi_buser,
|
||||
input wire [ 7:0] m_axi_bvalid,
|
||||
output wire [ 7:0] m_axi_bready,
|
||||
output wire [ 7:0] m_axi_arid,
|
||||
output wire [ 383:0] m_axi_araddr,
|
||||
output wire [ 63:0] m_axi_arlen,
|
||||
output wire [ 23:0] m_axi_arsize,
|
||||
output wire [ 15:0] m_axi_arburst,
|
||||
output wire [ 7:0] m_axi_arlock,
|
||||
output wire [ 31:0] m_axi_arcache,
|
||||
output wire [ 31:0] m_axi_arprot,
|
||||
output wire [ 31:0] m_axi_arqos,
|
||||
output wire [ 31:0] m_axi_arregion,
|
||||
output wire [ 7:0] m_axi_aruser,
|
||||
output wire [ 7:0] m_axi_arvalid,
|
||||
input wire [ 7:0] m_axi_arready,
|
||||
input wire [ 7:0] m_axi_rid,
|
||||
input wire [4191:0] m_axi_rdata,
|
||||
input wire [ 15:0] m_axi_rresp,
|
||||
input wire [ 7:0] m_axi_rlast,
|
||||
input wire [ 7:0] m_axi_ruser,
|
||||
input wire [ 7:0] m_axi_rvalid,
|
||||
output wire [ 7:0] m_axi_rready,
|
||||
|
||||
// Transport Adapters ///////////////
|
||||
|
||||
@@ -1123,12 +1124,12 @@ module rfnoc_image_core #(
|
||||
// time
|
||||
wire [ 63:0] radio0_radio_time;
|
||||
// radio
|
||||
wire [ 255:0] radio0_radio_rx_data;
|
||||
wire [ 7:0] radio0_radio_rx_stb;
|
||||
wire [ 7:0] radio0_radio_rx_running;
|
||||
wire [ 255:0] radio0_radio_tx_data;
|
||||
wire [ 7:0] radio0_radio_tx_stb;
|
||||
wire [ 7:0] radio0_radio_tx_running;
|
||||
wire [1023:0] radio0_radio_rx_data;
|
||||
wire [ 31:0] radio0_radio_rx_stb;
|
||||
wire [ 31:0] radio0_radio_rx_running;
|
||||
wire [1023:0] radio0_radio_tx_data;
|
||||
wire [ 31:0] radio0_radio_tx_stb;
|
||||
wire [ 31:0] radio0_radio_tx_running;
|
||||
|
||||
rfnoc_block_radio #(
|
||||
.THIS_PORTID (4),
|
||||
@@ -1296,12 +1297,12 @@ module rfnoc_image_core #(
|
||||
// time
|
||||
wire [ 63:0] radio1_radio_time;
|
||||
// radio
|
||||
wire [ 255:0] radio1_radio_rx_data;
|
||||
wire [ 7:0] radio1_radio_rx_stb;
|
||||
wire [ 7:0] radio1_radio_rx_running;
|
||||
wire [ 255:0] radio1_radio_tx_data;
|
||||
wire [ 7:0] radio1_radio_tx_stb;
|
||||
wire [ 7:0] radio1_radio_tx_running;
|
||||
wire [1023:0] radio1_radio_rx_data;
|
||||
wire [ 31:0] radio1_radio_rx_stb;
|
||||
wire [ 31:0] radio1_radio_rx_running;
|
||||
wire [1023:0] radio1_radio_tx_data;
|
||||
wire [ 31:0] radio1_radio_tx_stb;
|
||||
wire [ 31:0] radio1_radio_tx_running;
|
||||
|
||||
rfnoc_block_radio #(
|
||||
.THIS_PORTID (7),
|
||||
@@ -1367,50 +1368,50 @@ module rfnoc_image_core #(
|
||||
|
||||
// axi_ram
|
||||
wire [ 0:0] replay0_axi_rst;
|
||||
wire [ 3:0] replay0_m_axi_awid;
|
||||
wire [ 191:0] replay0_m_axi_awaddr;
|
||||
wire [ 31:0] replay0_m_axi_awlen;
|
||||
wire [ 11:0] replay0_m_axi_awsize;
|
||||
wire [ 7:0] replay0_m_axi_awburst;
|
||||
wire [ 3:0] replay0_m_axi_awlock;
|
||||
wire [ 15:0] replay0_m_axi_awcache;
|
||||
wire [ 11:0] replay0_m_axi_awprot;
|
||||
wire [ 15:0] replay0_m_axi_awqos;
|
||||
wire [ 15:0] replay0_m_axi_awregion;
|
||||
wire [ 3:0] replay0_m_axi_awuser;
|
||||
wire [ 3:0] replay0_m_axi_awvalid;
|
||||
wire [ 3:0] replay0_m_axi_awready;
|
||||
wire [2047:0] replay0_m_axi_wdata;
|
||||
wire [ 255:0] replay0_m_axi_wstrb;
|
||||
wire [ 3:0] replay0_m_axi_wlast;
|
||||
wire [ 3:0] replay0_m_axi_wuser;
|
||||
wire [ 3:0] replay0_m_axi_wvalid;
|
||||
wire [ 3:0] replay0_m_axi_wready;
|
||||
wire [ 3:0] replay0_m_axi_bid;
|
||||
wire [ 7:0] replay0_m_axi_bresp;
|
||||
wire [ 3:0] replay0_m_axi_buser;
|
||||
wire [ 3:0] replay0_m_axi_bvalid;
|
||||
wire [ 3:0] replay0_m_axi_bready;
|
||||
wire [ 3:0] replay0_m_axi_arid;
|
||||
wire [ 191:0] replay0_m_axi_araddr;
|
||||
wire [ 31:0] replay0_m_axi_arlen;
|
||||
wire [ 11:0] replay0_m_axi_arsize;
|
||||
wire [ 7:0] replay0_m_axi_arburst;
|
||||
wire [ 3:0] replay0_m_axi_arlock;
|
||||
wire [ 15:0] replay0_m_axi_arcache;
|
||||
wire [ 11:0] replay0_m_axi_arprot;
|
||||
wire [ 15:0] replay0_m_axi_arqos;
|
||||
wire [ 15:0] replay0_m_axi_arregion;
|
||||
wire [ 3:0] replay0_m_axi_aruser;
|
||||
wire [ 3:0] replay0_m_axi_arvalid;
|
||||
wire [ 3:0] replay0_m_axi_arready;
|
||||
wire [ 3:0] replay0_m_axi_rid;
|
||||
wire [2047:0] replay0_m_axi_rdata;
|
||||
wire [ 7:0] replay0_m_axi_rresp;
|
||||
wire [ 3:0] replay0_m_axi_rlast;
|
||||
wire [ 3:0] replay0_m_axi_ruser;
|
||||
wire [ 3:0] replay0_m_axi_rvalid;
|
||||
wire [ 3:0] replay0_m_axi_rready;
|
||||
wire [ 7:0] replay0_m_axi_awid;
|
||||
wire [ 383:0] replay0_m_axi_awaddr;
|
||||
wire [ 63:0] replay0_m_axi_awlen;
|
||||
wire [ 23:0] replay0_m_axi_awsize;
|
||||
wire [ 15:0] replay0_m_axi_awburst;
|
||||
wire [ 7:0] replay0_m_axi_awlock;
|
||||
wire [ 31:0] replay0_m_axi_awcache;
|
||||
wire [ 23:0] replay0_m_axi_awprot;
|
||||
wire [ 31:0] replay0_m_axi_awqos;
|
||||
wire [ 31:0] replay0_m_axi_awregion;
|
||||
wire [ 7:0] replay0_m_axi_awuser;
|
||||
wire [ 7:0] replay0_m_axi_awvalid;
|
||||
wire [ 7:0] replay0_m_axi_awready;
|
||||
wire [4191:0] replay0_m_axi_wdata;
|
||||
wire [ 511:0] replay0_m_axi_wstrb;
|
||||
wire [ 7:0] replay0_m_axi_wlast;
|
||||
wire [ 7:0] replay0_m_axi_wuser;
|
||||
wire [ 7:0] replay0_m_axi_wvalid;
|
||||
wire [ 7:0] replay0_m_axi_wready;
|
||||
wire [ 7:0] replay0_m_axi_bid;
|
||||
wire [ 15:0] replay0_m_axi_bresp;
|
||||
wire [ 7:0] replay0_m_axi_buser;
|
||||
wire [ 7:0] replay0_m_axi_bvalid;
|
||||
wire [ 7:0] replay0_m_axi_bready;
|
||||
wire [ 7:0] replay0_m_axi_arid;
|
||||
wire [ 383:0] replay0_m_axi_araddr;
|
||||
wire [ 63:0] replay0_m_axi_arlen;
|
||||
wire [ 23:0] replay0_m_axi_arsize;
|
||||
wire [ 15:0] replay0_m_axi_arburst;
|
||||
wire [ 7:0] replay0_m_axi_arlock;
|
||||
wire [ 31:0] replay0_m_axi_arcache;
|
||||
wire [ 31:0] replay0_m_axi_arprot;
|
||||
wire [ 31:0] replay0_m_axi_arqos;
|
||||
wire [ 31:0] replay0_m_axi_arregion;
|
||||
wire [ 7:0] replay0_m_axi_aruser;
|
||||
wire [ 7:0] replay0_m_axi_arvalid;
|
||||
wire [ 7:0] replay0_m_axi_arready;
|
||||
wire [ 7:0] replay0_m_axi_rid;
|
||||
wire [4191:0] replay0_m_axi_rdata;
|
||||
wire [ 15:0] replay0_m_axi_rresp;
|
||||
wire [ 7:0] replay0_m_axi_rlast;
|
||||
wire [ 7:0] replay0_m_axi_ruser;
|
||||
wire [ 7:0] replay0_m_axi_rvalid;
|
||||
wire [ 7:0] replay0_m_axi_rready;
|
||||
|
||||
rfnoc_block_replay #(
|
||||
.THIS_PORTID (8),
|
||||
@@ -1624,11 +1625,11 @@ module rfnoc_image_core #(
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
assign radio0_radio_clk = radio_clk;
|
||||
assign duc0_ce_clk = radio_2x_clk;
|
||||
assign ddc0_ce_clk = radio_2x_clk;
|
||||
assign duc0_ce_clk = ce_clk;
|
||||
assign ddc0_ce_clk = ce_clk;
|
||||
assign radio1_radio_clk = radio_clk;
|
||||
assign duc1_ce_clk = radio_2x_clk;
|
||||
assign ddc1_ce_clk = radio_2x_clk;
|
||||
assign duc1_ce_clk = ce_clk;
|
||||
assign ddc1_ce_clk = ce_clk;
|
||||
assign replay0_mem_clk = dram_clk;
|
||||
|
||||
|
||||
|
||||
@@ -154,9 +154,9 @@ connections:
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio_2x, dstblk: duc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: radio_2x, dstblk: ddc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio_2x, dstblk: duc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: radio_2x, dstblk: ddc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||
|
||||
@@ -39,6 +39,7 @@ module rfnoc_image_core #(
|
||||
input wire radio_clk,
|
||||
input wire radio_2x_clk,
|
||||
input wire dram_clk,
|
||||
input wire ce_clk,
|
||||
// Basic
|
||||
input wire [ 15:0] device_id,
|
||||
|
||||
@@ -69,65 +70,65 @@ module rfnoc_image_core #(
|
||||
// time
|
||||
input wire [ 63:0] radio_time,
|
||||
// radio0
|
||||
input wire [ 255:0] radio_rx_data_radio0,
|
||||
input wire [ 7:0] radio_rx_stb_radio0,
|
||||
output wire [ 7:0] radio_rx_running_radio0,
|
||||
output wire [ 255:0] radio_tx_data_radio0,
|
||||
input wire [ 7:0] radio_tx_stb_radio0,
|
||||
output wire [ 7:0] radio_tx_running_radio0,
|
||||
input wire [1023:0] radio_rx_data_radio0,
|
||||
input wire [ 31:0] radio_rx_stb_radio0,
|
||||
output wire [ 31:0] radio_rx_running_radio0,
|
||||
output wire [1023:0] radio_tx_data_radio0,
|
||||
input wire [ 31:0] radio_tx_stb_radio0,
|
||||
output wire [ 31:0] radio_tx_running_radio0,
|
||||
// radio1
|
||||
input wire [ 255:0] radio_rx_data_radio1,
|
||||
input wire [ 7:0] radio_rx_stb_radio1,
|
||||
output wire [ 7:0] radio_rx_running_radio1,
|
||||
output wire [ 255:0] radio_tx_data_radio1,
|
||||
input wire [ 7:0] radio_tx_stb_radio1,
|
||||
output wire [ 7:0] radio_tx_running_radio1,
|
||||
input wire [1023:0] radio_rx_data_radio1,
|
||||
input wire [ 31:0] radio_rx_stb_radio1,
|
||||
output wire [ 31:0] radio_rx_running_radio1,
|
||||
output wire [1023:0] radio_tx_data_radio1,
|
||||
input wire [ 31:0] radio_tx_stb_radio1,
|
||||
output wire [ 31:0] radio_tx_running_radio1,
|
||||
// dram
|
||||
input wire [ 0:0] axi_rst,
|
||||
output wire [ 3:0] m_axi_awid,
|
||||
output wire [ 191:0] m_axi_awaddr,
|
||||
output wire [ 31:0] m_axi_awlen,
|
||||
output wire [ 11:0] m_axi_awsize,
|
||||
output wire [ 7:0] m_axi_awburst,
|
||||
output wire [ 3:0] m_axi_awlock,
|
||||
output wire [ 15:0] m_axi_awcache,
|
||||
output wire [ 11:0] m_axi_awprot,
|
||||
output wire [ 15:0] m_axi_awqos,
|
||||
output wire [ 15:0] m_axi_awregion,
|
||||
output wire [ 3:0] m_axi_awuser,
|
||||
output wire [ 3:0] m_axi_awvalid,
|
||||
input wire [ 3:0] m_axi_awready,
|
||||
output wire [2047:0] m_axi_wdata,
|
||||
output wire [ 255:0] m_axi_wstrb,
|
||||
output wire [ 3:0] m_axi_wlast,
|
||||
output wire [ 3:0] m_axi_wuser,
|
||||
output wire [ 3:0] m_axi_wvalid,
|
||||
input wire [ 3:0] m_axi_wready,
|
||||
input wire [ 3:0] m_axi_bid,
|
||||
input wire [ 7:0] m_axi_bresp,
|
||||
input wire [ 3:0] m_axi_buser,
|
||||
input wire [ 3:0] m_axi_bvalid,
|
||||
output wire [ 3:0] m_axi_bready,
|
||||
output wire [ 3:0] m_axi_arid,
|
||||
output wire [ 191:0] m_axi_araddr,
|
||||
output wire [ 31:0] m_axi_arlen,
|
||||
output wire [ 11:0] m_axi_arsize,
|
||||
output wire [ 7:0] m_axi_arburst,
|
||||
output wire [ 3:0] m_axi_arlock,
|
||||
output wire [ 15:0] m_axi_arcache,
|
||||
output wire [ 11:0] m_axi_arprot,
|
||||
output wire [ 15:0] m_axi_arqos,
|
||||
output wire [ 15:0] m_axi_arregion,
|
||||
output wire [ 3:0] m_axi_aruser,
|
||||
output wire [ 3:0] m_axi_arvalid,
|
||||
input wire [ 3:0] m_axi_arready,
|
||||
input wire [ 3:0] m_axi_rid,
|
||||
input wire [2047:0] m_axi_rdata,
|
||||
input wire [ 7:0] m_axi_rresp,
|
||||
input wire [ 3:0] m_axi_rlast,
|
||||
input wire [ 3:0] m_axi_ruser,
|
||||
input wire [ 3:0] m_axi_rvalid,
|
||||
output wire [ 3:0] m_axi_rready,
|
||||
output wire [ 7:0] m_axi_awid,
|
||||
output wire [ 383:0] m_axi_awaddr,
|
||||
output wire [ 63:0] m_axi_awlen,
|
||||
output wire [ 23:0] m_axi_awsize,
|
||||
output wire [ 15:0] m_axi_awburst,
|
||||
output wire [ 7:0] m_axi_awlock,
|
||||
output wire [ 31:0] m_axi_awcache,
|
||||
output wire [ 23:0] m_axi_awprot,
|
||||
output wire [ 31:0] m_axi_awqos,
|
||||
output wire [ 31:0] m_axi_awregion,
|
||||
output wire [ 7:0] m_axi_awuser,
|
||||
output wire [ 7:0] m_axi_awvalid,
|
||||
input wire [ 7:0] m_axi_awready,
|
||||
output wire [4191:0] m_axi_wdata,
|
||||
output wire [ 511:0] m_axi_wstrb,
|
||||
output wire [ 7:0] m_axi_wlast,
|
||||
output wire [ 7:0] m_axi_wuser,
|
||||
output wire [ 7:0] m_axi_wvalid,
|
||||
input wire [ 7:0] m_axi_wready,
|
||||
input wire [ 7:0] m_axi_bid,
|
||||
input wire [ 15:0] m_axi_bresp,
|
||||
input wire [ 7:0] m_axi_buser,
|
||||
input wire [ 7:0] m_axi_bvalid,
|
||||
output wire [ 7:0] m_axi_bready,
|
||||
output wire [ 7:0] m_axi_arid,
|
||||
output wire [ 383:0] m_axi_araddr,
|
||||
output wire [ 63:0] m_axi_arlen,
|
||||
output wire [ 23:0] m_axi_arsize,
|
||||
output wire [ 15:0] m_axi_arburst,
|
||||
output wire [ 7:0] m_axi_arlock,
|
||||
output wire [ 31:0] m_axi_arcache,
|
||||
output wire [ 31:0] m_axi_arprot,
|
||||
output wire [ 31:0] m_axi_arqos,
|
||||
output wire [ 31:0] m_axi_arregion,
|
||||
output wire [ 7:0] m_axi_aruser,
|
||||
output wire [ 7:0] m_axi_arvalid,
|
||||
input wire [ 7:0] m_axi_arready,
|
||||
input wire [ 7:0] m_axi_rid,
|
||||
input wire [4191:0] m_axi_rdata,
|
||||
input wire [ 15:0] m_axi_rresp,
|
||||
input wire [ 7:0] m_axi_rlast,
|
||||
input wire [ 7:0] m_axi_ruser,
|
||||
input wire [ 7:0] m_axi_rvalid,
|
||||
output wire [ 7:0] m_axi_rready,
|
||||
|
||||
// Transport Adapters ///////////////
|
||||
|
||||
@@ -791,12 +792,12 @@ module rfnoc_image_core #(
|
||||
// time
|
||||
wire [ 63:0] radio0_radio_time;
|
||||
// radio
|
||||
wire [ 255:0] radio0_radio_rx_data;
|
||||
wire [ 7:0] radio0_radio_rx_stb;
|
||||
wire [ 7:0] radio0_radio_rx_running;
|
||||
wire [ 255:0] radio0_radio_tx_data;
|
||||
wire [ 7:0] radio0_radio_tx_stb;
|
||||
wire [ 7:0] radio0_radio_tx_running;
|
||||
wire [1023:0] radio0_radio_rx_data;
|
||||
wire [ 31:0] radio0_radio_rx_stb;
|
||||
wire [ 31:0] radio0_radio_rx_running;
|
||||
wire [1023:0] radio0_radio_tx_data;
|
||||
wire [ 31:0] radio0_radio_tx_stb;
|
||||
wire [ 31:0] radio0_radio_tx_running;
|
||||
|
||||
rfnoc_block_radio #(
|
||||
.THIS_PORTID (4),
|
||||
@@ -964,12 +965,12 @@ module rfnoc_image_core #(
|
||||
// time
|
||||
wire [ 63:0] radio1_radio_time;
|
||||
// radio
|
||||
wire [ 255:0] radio1_radio_rx_data;
|
||||
wire [ 7:0] radio1_radio_rx_stb;
|
||||
wire [ 7:0] radio1_radio_rx_running;
|
||||
wire [ 255:0] radio1_radio_tx_data;
|
||||
wire [ 7:0] radio1_radio_tx_stb;
|
||||
wire [ 7:0] radio1_radio_tx_running;
|
||||
wire [1023:0] radio1_radio_rx_data;
|
||||
wire [ 31:0] radio1_radio_rx_stb;
|
||||
wire [ 31:0] radio1_radio_rx_running;
|
||||
wire [1023:0] radio1_radio_tx_data;
|
||||
wire [ 31:0] radio1_radio_tx_stb;
|
||||
wire [ 31:0] radio1_radio_tx_running;
|
||||
|
||||
rfnoc_block_radio #(
|
||||
.THIS_PORTID (7),
|
||||
@@ -1115,11 +1116,11 @@ module rfnoc_image_core #(
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
assign radio0_radio_clk = radio_clk;
|
||||
assign duc0_ce_clk = radio_2x_clk;
|
||||
assign ddc0_ce_clk = radio_2x_clk;
|
||||
assign duc0_ce_clk = ce_clk;
|
||||
assign ddc0_ce_clk = ce_clk;
|
||||
assign radio1_radio_clk = radio_clk;
|
||||
assign duc1_ce_clk = radio_2x_clk;
|
||||
assign ddc1_ce_clk = radio_2x_clk;
|
||||
assign duc1_ce_clk = ce_clk;
|
||||
assign ddc1_ce_clk = ce_clk;
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
@@ -117,8 +117,8 @@ connections:
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio_2x, dstblk: duc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: radio_2x, dstblk: ddc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio_2x, dstblk: duc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: radio_2x, dstblk: ddc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
|
||||
|
||||
@@ -41,6 +41,7 @@ module rfnoc_image_core #(
|
||||
input wire radio0_2x_clk,
|
||||
input wire radio1_2x_clk,
|
||||
input wire dram_clk,
|
||||
input wire ce_clk,
|
||||
// Basic
|
||||
input wire [ 15:0] device_id,
|
||||
|
||||
|
||||
@@ -41,6 +41,7 @@ module rfnoc_image_core #(
|
||||
input wire radio0_2x_clk,
|
||||
input wire radio1_2x_clk,
|
||||
input wire dram_clk,
|
||||
input wire ce_clk,
|
||||
// Basic
|
||||
input wire [ 15:0] device_id,
|
||||
|
||||
|
||||
@@ -41,6 +41,7 @@ module rfnoc_image_core #(
|
||||
input wire radio0_2x_clk,
|
||||
input wire radio1_2x_clk,
|
||||
input wire dram_clk,
|
||||
input wire ce_clk,
|
||||
// Basic
|
||||
input wire [ 15:0] device_id,
|
||||
|
||||
|
||||
@@ -41,6 +41,7 @@ module rfnoc_image_core #(
|
||||
input wire radio0_2x_clk,
|
||||
input wire radio1_2x_clk,
|
||||
input wire dram_clk,
|
||||
input wire ce_clk,
|
||||
// Basic
|
||||
input wire [ 15:0] device_id,
|
||||
|
||||
|
||||
@@ -482,6 +482,61 @@ module x4xx (
|
||||
);
|
||||
`endif
|
||||
|
||||
// Compute Engine Clock
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// __ce_clk__266.66667______0.000______50.0_______94.562_____97.786
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________200____________0.010
|
||||
|
||||
wire ce_gen_clkfbout;
|
||||
wire ce_gen_clkout0;
|
||||
wire ce_clk;
|
||||
|
||||
PLLE4_ADV #(
|
||||
.COMPENSATION ("AUTO" ),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1 ),
|
||||
.CLKFBOUT_MULT (4 ),
|
||||
.CLKFBOUT_PHASE (0.000 ),
|
||||
.CLKOUT0_DIVIDE (3 ),
|
||||
.CLKOUT0_PHASE (0.000 ),
|
||||
.CLKOUT0_DUTY_CYCLE(0.500 ),
|
||||
.CLKIN_PERIOD (5.000 )
|
||||
) ce_clk_gen_i (
|
||||
.CLKFBOUT (ce_gen_clkfbout),
|
||||
.CLKOUT0 (ce_gen_clkout0 ),
|
||||
.CLKOUT0B ( ),
|
||||
.CLKOUT1 ( ),
|
||||
.CLKOUT1B ( ),
|
||||
.CLKFBIN (ce_gen_clkfbout),
|
||||
.CLKIN (clk200 ),
|
||||
.DADDR (7'h0 ),
|
||||
.DCLK (1'b0 ),
|
||||
.DEN (1'b0 ),
|
||||
.DI (16'h0 ),
|
||||
.DO ( ),
|
||||
.DRDY ( ),
|
||||
.DWE (1'b0 ),
|
||||
.CLKOUTPHYEN(1'b0 ),
|
||||
.CLKOUTPHY ( ),
|
||||
.LOCKED ( ),
|
||||
.PWRDWN (1'b0 ),
|
||||
.RST (areset )
|
||||
);
|
||||
|
||||
BUFG bufg_ce_i (
|
||||
.O(ce_clk ),
|
||||
.I(ce_gen_clkout0)
|
||||
);
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// PPS Handling
|
||||
//---------------------------------------------------------------------------
|
||||
@@ -2973,6 +3028,7 @@ module x4xx (
|
||||
.rfnoc_chdr_rst (bus_clk_rst),
|
||||
.rfnoc_ctrl_clk (clk40),
|
||||
.rfnoc_ctrl_rst (clk40_rst),
|
||||
.ce_clk (ce_clk),
|
||||
.dram0_sys_clk_p (DRAM0_REFCLK_P),
|
||||
.dram0_sys_clk_n (DRAM0_REFCLK_N),
|
||||
.dram0_ck_t (DRAM0_CLK_P),
|
||||
|
||||
@@ -62,6 +62,8 @@ module x4xx_core #(
|
||||
input wire rfnoc_ctrl_clk,
|
||||
input wire rfnoc_ctrl_rst,
|
||||
|
||||
input wire ce_clk,
|
||||
|
||||
// DRAM Bank 0
|
||||
input wire dram0_sys_clk_p,
|
||||
input wire dram0_sys_clk_n,
|
||||
@@ -620,6 +622,7 @@ module x4xx_core #(
|
||||
.radio_2x_clk (radio_clk_2x[0]),
|
||||
`endif
|
||||
.dram_clk (dram_clk),
|
||||
.ce_clk (ce_clk),
|
||||
.device_id (device_id),
|
||||
.m_ctrlport_radio0_req_wr (ctrlport_radio_req_wr [0* 1+: 1]),
|
||||
.m_ctrlport_radio0_req_rd (ctrlport_radio_req_rd [0* 1+: 1]),
|
||||
|
||||
Reference in New Issue
Block a user