a405111ce7e91a359fe559840ede677880344b8f
Adds simulation coverage for 10 GbE with 512-bit CHDR bus. Original-commit: 0e50a37b5ec6039ed4e8947421dd333047e24408
Description
No description provided
84 MiB
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%