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fpga: Add BUILD_SEED variable

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Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.

For example, you could run the following to produce an FPGA build with
different timing results from the default build:

make X310_XG BUILD_SEED=123


Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
This commit is contained in:
Wade Fife
2023-02-07 23:04:12 -06:00
parent 2c0fea5d1e
commit ab63d78a6c
15 changed files with 221 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/e31x/Makefile
+15 -10
View File
@@ -14,6 +14,10 @@
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
DEFS += BUILD_SEED=$(BUILD_SEED)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
ifdef CHECK
@@ -62,22 +66,22 @@ E310_SG3_IP:
##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
E310_SG1_IDLE E3XX_idle: E310_SG1_IP build/usrp_e310_sg1_idle_fpga.dts
$(call vivado_build,E310_SG1, E310_IDLE_IMAGE=1 E310_SG1=1)
$(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1)
$(call post_build,$@,E310_SG1_IDLE)
##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP build/usrp_e310_sg3_idle_fpga.dts
$(call vivado_build,E310_SG3, E310_IDLE_IMAGE=1 E310_SG3=1)
$(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1)
$(call post_build,$@,E310_SG3_IDLE)
##E310_SG1: Build USRP E3XX (Speed Grade 1).
E310_SG1 E310: E310_SG1_IP build/usrp_e310_sg1_fpga.dts
$(call vivado_build,E310_SG1, E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
$(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
$(call post_build,$@,E310_SG1)
##E310_SG3: Build USRP E3XX (Speed Grade 3).
E310_SG3 E310_sg3: E310_SG3_IP build/usrp_e310_sg3_fpga.dts
$(call vivado_build,E310_SG3, E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
$(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
$(call post_build,$@,E310_SG3)
@@ -102,11 +106,12 @@ help: ##Show this help message.
##
##Supported Options
##-----------------
##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build.
## Note: The RFNoC image core must also be configured to use DRAM.
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build.
## Note: The RFNoC image core must also be configured to use DRAM.
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
.PHONY: all clean cleanall help
top/e31x/e31x_core.v
+9 -1
View File
@@ -150,7 +150,7 @@ module e31x_core #(
/////////////////////////////////////////////////////////////////////////////////
localparam [15:0] COMPAT_MAJOR = 16'd6;
localparam [15:0] COMPAT_MINOR = 16'd0;
localparam [15:0] COMPAT_MINOR = 16'd1;
/////////////////////////////////////////////////////////////////////////////////
@@ -186,6 +186,7 @@ module e31x_core #(
localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40;
localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44;
localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48;
localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C;
localparam NUM_TIMEKEEPERS = 1;
@@ -469,6 +470,13 @@ module e31x_core #(
REG_NUM_TIMEKEEPERS:
cp_glob_resp_data <= NUM_TIMEKEEPERS;
REG_BUILD_SEED: begin
`ifndef BUILD_SEED
`define BUILD_SEED 32'b0
`endif
cp_glob_resp_data <= `BUILD_SEED;
end
default: begin
// Don't acknowledge if the address doesn't match
cp_glob_resp_ack <= 1'b0;
top/e320/Makefile
+11 -7
View File
@@ -14,9 +14,12 @@
## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS)
XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS)
AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS)
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
@@ -97,9 +100,10 @@ help: ##Show this help message.
##
##Supported Options
##-----------------
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
.PHONY: all clean cleanall help
top/e320/e320_core.v
+12 -3
View File
@@ -193,7 +193,7 @@ module e320_core #(
/////////////////////////////////////////////////////////////////////////////////
localparam [15:0] COMPAT_MAJOR = 16'd6;
localparam [15:0] COMPAT_MINOR = 16'd1;
localparam [15:0] COMPAT_MINOR = 16'd2;
/////////////////////////////////////////////////////////////////////////////////
@@ -231,6 +231,7 @@ module e320_core #(
localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40;
localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44;
localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48;
localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C;
localparam NUM_TIMEKEEPERS = 1;
@@ -486,11 +487,12 @@ module e320_core #(
REG_DATESTAMP:
cp_glob_resp_data <= build_datestamp;
REG_GIT_HASH:
REG_GIT_HASH: begin
`ifndef GIT_HASH
`define GIT_HASH 32'h0BADC0DE
`define GIT_HASH 32'h0BADC0DE
`endif
cp_glob_resp_data <= `GIT_HASH;
end
REG_SCRATCH:
cp_glob_resp_data <= scratch_reg;
@@ -529,6 +531,13 @@ module e320_core #(
REG_NUM_TIMEKEEPERS:
cp_glob_resp_data <= NUM_TIMEKEEPERS;
REG_BUILD_SEED: begin
`ifndef BUILD_SEED
`define BUILD_SEED 32'b0
`endif
cp_glob_resp_data <= `BUILD_SEED;
end
default: begin
// Don't acknowledge if the address doesn't match
cp_glob_resp_ack <= 1'b0;
top/n3xx/Makefile
+16 -12
View File
@@ -23,15 +23,18 @@
# Uncomment this line to add four example Aurora loopback lanes on the QSFP NPIO bus.
# OPTIONS += QSFP_LANES=4
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
# Additional definitions specific to the various targets:
WX_DEFS=SFP0_WR=1 SFP1_10GBE=1 BUILD_WR=1 BUILD_10G=1 $(OPTIONS)
HG_DEFS=SFP0_1GBE=1 SFP1_10GBE=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS)
XG_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 BUILD_10G=1 $(OPTIONS)
HA_DEFS=SFP0_1GBE=1 SFP1_AURORA=1 BUILD_1G=1 BUILD_AURORA=1 $(OPTIONS)
XA_DEFS=SFP0_10GBE=1 SFP1_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 $(OPTIONS)
AA_DEFS=SFP0_AURORA=1 SFP1_AURORA=1 BUILD_AURORA=1 $(OPTIONS)
XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 BUILD_WR=1 BUILD_10G=1 QSFP_LANES=2 $(OPTIONS)
AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS)
WX_DEFS=SFP0_WR=1 SFP1_10GBE=1 BUILD_WR=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
HG_DEFS=SFP0_1GBE=1 SFP1_10GBE=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XG_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
HA_DEFS=SFP0_1GBE=1 SFP1_AURORA=1 BUILD_1G=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XA_DEFS=SFP0_10GBE=1 SFP1_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
AA_DEFS=SFP0_AURORA=1 SFP1_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 BUILD_WR=1 BUILD_10G=1 QSFP_LANES=2 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
# Defaults specific to the various targets:
N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex)
@@ -200,9 +203,10 @@ help: ##Show this help message.
##
##Supported Options
##-----------------
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
.PHONY: all clean cleanall help
top/n3xx/n3xx_core.v
+12 -3
View File
@@ -211,7 +211,7 @@ module n3xx_core #(
/////////////////////////////////////////////////////////////////////////////////
localparam [15:0] COMPAT_MAJOR = 16'd8;
localparam [15:0] COMPAT_MINOR = 16'd1;
localparam [15:0] COMPAT_MINOR = 16'd2;
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
@@ -244,6 +244,7 @@ module n3xx_core #(
localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30;
localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34;
localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48;
localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C;
localparam NUM_TIMEKEEPERS = 1;
@@ -543,11 +544,12 @@ module n3xx_core #(
REG_DATESTAMP:
cp_glob_resp_data <= build_datestamp;
REG_GIT_HASH:
REG_GIT_HASH: begin
`ifndef GIT_HASH
`define GIT_HASH 32'h0BADC0DE
`define GIT_HASH 32'h0BADC0DE
`endif
cp_glob_resp_data <= `GIT_HASH;
end
REG_FP_GPIO_MASTER:
cp_glob_resp_data <= fp_gpio_master_reg;
@@ -588,6 +590,13 @@ module n3xx_core #(
REG_NUM_TIMEKEEPERS:
cp_glob_resp_data <= NUM_TIMEKEEPERS;
REG_BUILD_SEED: begin
`ifndef BUILD_SEED
`define BUILD_SEED 32'b0
`endif
cp_glob_resp_data <= `BUILD_SEED;
end
default: begin
// Don't acknowledge if the address doesn't match
cp_glob_resp_ack <= 1'b0;
top/x300/Makefile
+13 -9
View File
@@ -21,11 +21,14 @@
CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py
GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS)
HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS)
XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS)
HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS)
XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS)
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
@@ -146,9 +149,10 @@ help: ##Show this help message.
##
##Supported Options
##-----------------
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
.PHONY: all clean cleanall help
top/x300/bus_int.v
+9 -1
View File
@@ -175,11 +175,12 @@ module bus_int #(
localparam RB_NUM_TIMEKEEPERS = 8'd12;
localparam RB_FP_GPIO_SRC = 8'd13;
localparam RB_DEVICE_ID = 8'd14;
localparam RB_BUILD_SEED = 8'd15;
localparam RB_TA_SFP0_BASE = SR_TA_SFP0_BASE;
localparam RB_TA_SFP1_BASE = SR_TA_SFP1_BASE;
localparam COMPAT_MAJOR = 16'h0027;
localparam COMPAT_MINOR = 16'h0001;
localparam COMPAT_MINOR = 16'h0002;
localparam NUM_TIMEKEEPERS = 1;
// Include the RFNoC image core header file
@@ -457,8 +458,15 @@ module bus_int #(
`else
RB_ETH_TYPE1: rb_data = {32'h0};
`endif
`endif
`ifndef GIT_HASH
`define GIT_HASH 32'h0BADC0DE
`endif
RB_GIT_HASH: rb_data = `GIT_HASH;
`ifndef BUILD_SEED
`define BUILD_SEED 32'b0
`endif
RB_BUILD_SEED: rb_data = `BUILD_SEED;
RB_XADC_VALS: rb_data = xadc_readback;
RB_FP_GPIO_SRC: rb_data = fp_gpio_src;
SR_BASE_TIME: begin
top/x400/Makefile
+10 -5
View File
@@ -65,6 +65,10 @@ DRAM ?= 1
DEFS += $(OPTIONS)
# Initialize a build seed. This can be changed to randomly affect build results.
BUILD_SEED ?= 0
DEFS += BUILD_SEED=$(BUILD_SEED)
# Defaults specific to the various targets:
X410_100_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
@@ -226,10 +230,11 @@ help: ##Show this help message.
##
##Supported Options
##-----------------
##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build.
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build.
##GUI=1 Launch the build in the Vivado GUI.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##SYNTH=1 Launch the build but stop after synthesis.
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
.PHONY: all clean cleanall help
top/x400/doc/X4XX_FPGA_left.htm
+1
View File
@@ -348,6 +348,7 @@
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|PPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|PPS_CTRL_REG');">PPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_RATE_REG');">CHDR_CLK_RATE_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG" onclick="a('GLOBAL_REGS_REGMAP|CHDR_CLK_COUNT_REG');">CHDR_CLK_COUNT_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|BUILD_SEED_REG" onclick="a('GLOBAL_REGS_REGMAP|BUILD_SEED_REG');">BUILD_SEED_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_CTRL_REG');">GPS_CTRL_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|GPS_STATUS_REG" onclick="a('GLOBAL_REGS_REGMAP|GPS_STATUS_REG');">GPS_STATUS_REG</span></p>
<p><span class="register" id="a_GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG" onclick="a('GLOBAL_REGS_REGMAP|DBOARD_CTRL_REG');">DBOARD_CTRL_REG</span></p>
top/x400/doc/X4XX_FPGA_right.htm
+88 -5
View File
@@ -716,7 +716,7 @@ Prism.languages.vhdl={comment:/--.+/,"vhdl-vectors":{pattern:/\b[oxb]"[\da-f_]+"
<p>The top is defined in HDL source file common_regs.v, x4xx.v.</p>
<div class="group"><a name="P5 Content"></a><h2 class="group">P5 Content</h2>
<div class="register"><h3 class="register">Register map supplied for open-source projects</h3>
<i><BR/><BR/>"All content provided is Copyright 2022 National Instruments Corporation.
<i><BR/><BR/>"All content provided is Copyright 2023 National Instruments Corporation.
For information on NI trademark guidelines, please see <a href="http://www.ni.com/legal/trademarks/">http://www.ni.com/legal/trademarks/</a>. For the NI Patent Notice, please see <a href="http://www.ni.com/legal/patents/">http://www.ni.com/legal/patents/</a>."
</i></div><BR/>
</div>
@@ -6830,6 +6830,89 @@ Returns the count value of a free-running counter driven by the RFNoC
</div>
</div>
<div class="register">
<a name="GLOBAL_REGS_REGMAP|BUILD_SEED_REG"></a>
<h3 class="register">Offset 0x0028: BUILD_SEED_REG Register (R)</h3>
<a class="sh_addrs" href="javascript:sa('GLOBAL_REGS_REGMAP|BUILD_SEED_REG_in')">(<span id="show_GLOBAL_REGS_REGMAP|BUILD_SEED_REG_in">show</span> extended info)</a>
<div class="sh_addrs" id="div_GLOBAL_REGS_REGMAP|BUILD_SEED_REG_in">
<table class="extended_info">
<tr>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">Port <a href="#X4XX_FPGA|ARM_M_AXI_HPM0">ARM_M_AXI_HPM0</a></td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#AXI_HPM0_REGMAP|CORE_REGS">AXI_HPM0_REGMAP|CORE_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x10000A0000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right"><a href="#CORE_REGS_REGMAP|GLOBAL_REGS">CORE_REGS_REGMAP|GLOBAL_REGS</a></td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;0x000000</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info" align="right">BUILD_SEED_REG</td></tr>
<tr><td class="offset_info" align="right">&nbsp;&nbsp;offset=0x0028</td></tr>
</table>
</td>
<td class="outercell" rowspan="1">
<table border="0" cellspacing="0" cellpadding="0">
<tr><td class="offset_info">
Total Offset =</td></tr>
<tr><td class="offset_info">&nbsp;&nbsp;0x10000A0028
</td></tr>
</table>
</td>
</tr>
</table><p/>
<p class="reg_info">Initial Value not specified
</p>
<p class="reg_info">This register is defined in HDL source file x4xx_global_regs.v.</p>
</div>
<div class="info">
Build seed used for this compilation. Making this value readable
ensures that compilation results are affected by the value in this
register.
</div>
</div>
<div class="register">
@@ -24241,9 +24324,9 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>9</td>
<td class='value'>10</td>
<td class='l'>0x00000009</td>
<td class='l'>0x0000000A</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
@@ -24254,9 +24337,9 @@ FPGA version.<BR/>
<tr valign="top">
<td class='value'>570827282</td>
<td class='value'>571610633</td>
<td class='l'>0x22062212</td>
<td class='l'>0x22121609</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>
top/x400/regmap/global_regs_regmap_utils.vh
+7 -1
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -21,6 +21,7 @@
// PPS_CTRL_REG : 0x1C (x4xx_global_regs.v)
// CHDR_CLK_RATE_REG : 0x20 (x4xx_global_regs.v)
// CHDR_CLK_COUNT_REG : 0x24 (x4xx_global_regs.v)
// BUILD_SEED_REG : 0x28 (x4xx_global_regs.v)
// GPS_CTRL_REG : 0x38 (x4xx_global_regs.v)
// GPS_STATUS_REG : 0x3C (x4xx_global_regs.v)
// DBOARD_CTRL_REG : 0x40 (x4xx_global_regs.v)
@@ -181,6 +182,11 @@
localparam CHDR_CLK_COUNT_REG_SIZE = 32; // register width in bits
localparam CHDR_CLK_COUNT_REG_MASK = 32'h0;
// BUILD_SEED_REG Register (from x4xx_global_regs.v)
localparam BUILD_SEED_REG = 'h28; // Register Offset
localparam BUILD_SEED_REG_SIZE = 32; // register width in bits
localparam BUILD_SEED_REG_MASK = 32'h0;
// GPS_CTRL_REG Register (from x4xx_global_regs.v)
localparam GPS_CTRL_REG = 'h38; // Register Offset
localparam GPS_CTRL_REG_SIZE = 32; // register width in bits
top/x400/regmap/versioning_regs_regmap_utils.vh
+2 -2
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@@ -84,8 +84,8 @@
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_CURRENT_VERSION_MINOR = 'h9; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22062212; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
localparam FPGA_CURRENT_VERSION_MINOR = 'hA; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22121609; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7;
top/x400/x4xx.v
+2 -2
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@@ -2280,12 +2280,12 @@ endmodule
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="FPGA_CURRENT_VERSION_MAJOR" integer="7"/>
// <value name="FPGA_CURRENT_VERSION_MINOR" integer="9"/>
// <value name="FPGA_CURRENT_VERSION_MINOR" integer="10"/>
// <value name="FPGA_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="7"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x22062212"/>
// <value name="FPGA_VERSION_LAST_MODIFIED_TIME" integer="0x22121609"/>
// </enumeratedtype>
// </group>
//</regmap>
top/x400/x4xx_global_regs.v
+14
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@@ -280,6 +280,13 @@ module x4xx_global_regs #(
s_ctrlport_resp_data <= CHDR_CLK_RATE[CHDR_CLK_RATE_REG_SIZE-1:0];
end
REG_BASE + BUILD_SEED_REG: begin
`ifndef BUILD_SEED
`define BUILD_SEED 32'b0
`endif
s_ctrlport_resp_data <= `BUILD_SEED;
end
REG_BASE + CHDR_CLK_COUNT_REG: begin
s_ctrlport_resp_data <= chdr_counter_reg;
end
@@ -601,6 +608,13 @@ endmodule
// CHDR bus clock.
// </info>
// </register>
// <register name="BUILD_SEED_REG" offset="0x28" size="32" writable="false">
// <info>
// Build seed used for this compilation. Making this value readable
// ensures that compilation results are affected by the value in this
// register.
// </info>
// </register>
// <register name="QSFP_PORT_0_0_INFO_REG" offset="0x60" size="32" writable="false">
// <info>
// Returns information from the QSFP0 Lane0.