diff --git a/top/e31x/Makefile b/top/e31x/Makefile index f4e744b..45b8dae 100644 --- a/top/e31x/Makefile +++ b/top/e31x/Makefile @@ -14,6 +14,10 @@ ## build/usrp__fpga_.dts: Device tree source file ## build/usrp__fpga_.rpt: Build report (includes utilization and timing summary) +# Initialize a build seed. This can be changed to randomly affect build results. +BUILD_SEED ?= 0 +DEFS += BUILD_SEED=$(BUILD_SEED) + # Set build option (check RTL, run synthesis, or do a full build) ifndef TARGET ifdef CHECK @@ -62,22 +66,22 @@ E310_SG3_IP: ##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1). E310_SG1_IDLE E3XX_idle: E310_SG1_IP build/usrp_e310_sg1_idle_fpga.dts - $(call vivado_build,E310_SG1, E310_IDLE_IMAGE=1 E310_SG1=1) + $(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1) $(call post_build,$@,E310_SG1_IDLE) ##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3). E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP build/usrp_e310_sg3_idle_fpga.dts - $(call vivado_build,E310_SG3, E310_IDLE_IMAGE=1 E310_SG3=1) + $(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1) $(call post_build,$@,E310_SG3_IDLE) ##E310_SG1: Build USRP E3XX (Speed Grade 1). E310_SG1 E310: E310_SG1_IP build/usrp_e310_sg1_fpga.dts - $(call vivado_build,E310_SG1, E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,)) + $(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,)) $(call post_build,$@,E310_SG1) ##E310_SG3: Build USRP E3XX (Speed Grade 3). E310_SG3 E310_sg3: E310_SG3_IP build/usrp_e310_sg3_fpga.dts - $(call vivado_build,E310_SG3, E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,)) + $(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,)) $(call post_build,$@,E310_SG3) @@ -102,11 +106,12 @@ help: ##Show this help message. ## ##Supported Options ##----------------- -##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build. -## Note: The RFNoC image core must also be configured to use DRAM. -##GUI=1 Launch the build in the Vivado GUI. -##CHECK=1 Launch the syntax checker instead of building a bitfile. -##SYNTH=1 Launch the build but stop after synthesis. -##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) +##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build. +## Note: The RFNoC image core must also be configured to use DRAM. +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##BUILD_SEED= Build seed to used to affect build results. (Default is 0) +##TOP= Specify a top module for syntax checking. (Default is the bitfile top) .PHONY: all clean cleanall help diff --git a/top/e31x/e31x_core.v b/top/e31x/e31x_core.v index 7a453a5..732534e 100644 --- a/top/e31x/e31x_core.v +++ b/top/e31x/e31x_core.v @@ -150,7 +150,7 @@ module e31x_core #( ///////////////////////////////////////////////////////////////////////////////// localparam [15:0] COMPAT_MAJOR = 16'd6; - localparam [15:0] COMPAT_MINOR = 16'd0; + localparam [15:0] COMPAT_MINOR = 16'd1; ///////////////////////////////////////////////////////////////////////////////// @@ -186,6 +186,7 @@ module e31x_core #( localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40; localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44; localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; + localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C; localparam NUM_TIMEKEEPERS = 1; @@ -469,6 +470,13 @@ module e31x_core #( REG_NUM_TIMEKEEPERS: cp_glob_resp_data <= NUM_TIMEKEEPERS; + REG_BUILD_SEED: begin + `ifndef BUILD_SEED + `define BUILD_SEED 32'b0 + `endif + cp_glob_resp_data <= `BUILD_SEED; + end + default: begin // Don't acknowledge if the address doesn't match cp_glob_resp_ack <= 1'b0; diff --git a/top/e320/Makefile b/top/e320/Makefile index 55fc8cd..ec555a4 100644 --- a/top/e320/Makefile +++ b/top/e320/Makefile @@ -14,9 +14,12 @@ ## build/usrp__fpga_.dts: Device tree source file ## build/usrp__fpga_.rpt: Build report (includes utilization and timing summary) -1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS) -XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS) -AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) +# Initialize a build seed. This can be changed to randomly affect build results. +BUILD_SEED ?= 0 + +1G_DEFS=SFP_1GBE=1 BUILD_1G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +XG_DEFS=SFP_10GBE=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) # Set build option (check RTL, run synthesis, or do a full build) ifndef TARGET @@ -97,9 +100,10 @@ help: ##Show this help message. ## ##Supported Options ##----------------- -##GUI=1 Launch the build in the Vivado GUI. -##CHECK=1 Launch the syntax checker instead of building a bitfile. -##SYNTH=1 Launch the build but stop after synthesis. -##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##BUILD_SEED= Build seed to used to affect build results. (Default is 0) +##TOP= Specify a top module for syntax checking. (Default is the bitfile top) .PHONY: all clean cleanall help diff --git a/top/e320/e320_core.v b/top/e320/e320_core.v index d9a3173..3d1c857 100644 --- a/top/e320/e320_core.v +++ b/top/e320/e320_core.v @@ -193,7 +193,7 @@ module e320_core #( ///////////////////////////////////////////////////////////////////////////////// localparam [15:0] COMPAT_MAJOR = 16'd6; - localparam [15:0] COMPAT_MINOR = 16'd1; + localparam [15:0] COMPAT_MINOR = 16'd2; ///////////////////////////////////////////////////////////////////////////////// @@ -231,6 +231,7 @@ module e320_core #( localparam REG_DBOARD_CTRL = REG_BASE_MISC + 14'h40; localparam REG_DBOARD_STATUS = REG_BASE_MISC + 14'h44; localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; + localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C; localparam NUM_TIMEKEEPERS = 1; @@ -486,11 +487,12 @@ module e320_core #( REG_DATESTAMP: cp_glob_resp_data <= build_datestamp; - REG_GIT_HASH: + REG_GIT_HASH: begin `ifndef GIT_HASH - `define GIT_HASH 32'h0BADC0DE + `define GIT_HASH 32'h0BADC0DE `endif cp_glob_resp_data <= `GIT_HASH; + end REG_SCRATCH: cp_glob_resp_data <= scratch_reg; @@ -529,6 +531,13 @@ module e320_core #( REG_NUM_TIMEKEEPERS: cp_glob_resp_data <= NUM_TIMEKEEPERS; + REG_BUILD_SEED: begin + `ifndef BUILD_SEED + `define BUILD_SEED 32'b0 + `endif + cp_glob_resp_data <= `BUILD_SEED; + end + default: begin // Don't acknowledge if the address doesn't match cp_glob_resp_ack <= 1'b0; diff --git a/top/n3xx/Makefile b/top/n3xx/Makefile index aac2670..1041545 100644 --- a/top/n3xx/Makefile +++ b/top/n3xx/Makefile @@ -23,15 +23,18 @@ # Uncomment this line to add four example Aurora loopback lanes on the QSFP NPIO bus. # OPTIONS += QSFP_LANES=4 +# Initialize a build seed. This can be changed to randomly affect build results. +BUILD_SEED ?= 0 + # Additional definitions specific to the various targets: -WX_DEFS=SFP0_WR=1 SFP1_10GBE=1 BUILD_WR=1 BUILD_10G=1 $(OPTIONS) -HG_DEFS=SFP0_1GBE=1 SFP1_10GBE=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS) -XG_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 BUILD_10G=1 $(OPTIONS) -HA_DEFS=SFP0_1GBE=1 SFP1_AURORA=1 BUILD_1G=1 BUILD_AURORA=1 $(OPTIONS) -XA_DEFS=SFP0_10GBE=1 SFP1_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 $(OPTIONS) -AA_DEFS=SFP0_AURORA=1 SFP1_AURORA=1 BUILD_AURORA=1 $(OPTIONS) -XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 BUILD_WR=1 BUILD_10G=1 QSFP_LANES=2 $(OPTIONS) -AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS) +WX_DEFS=SFP0_WR=1 SFP1_10GBE=1 BUILD_WR=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +HG_DEFS=SFP0_1GBE=1 SFP1_10GBE=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +XG_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 BUILD_10G=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +HA_DEFS=SFP0_1GBE=1 SFP1_AURORA=1 BUILD_1G=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +XA_DEFS=SFP0_10GBE=1 SFP1_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +AA_DEFS=SFP0_AURORA=1 SFP1_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 BUILD_WR=1 BUILD_10G=1 QSFP_LANES=2 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) # Defaults specific to the various targets: N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex) @@ -200,9 +203,10 @@ help: ##Show this help message. ## ##Supported Options ##----------------- -##GUI=1 Launch the build in the Vivado GUI. -##CHECK=1 Launch the syntax checker instead of building a bitfile. -##SYNTH=1 Launch the build but stop after synthesis. -##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##BUILD_SEED= Build seed to used to affect build results. (Default is 0) +##TOP= Specify a top module for syntax checking. (Default is the bitfile top) .PHONY: all clean cleanall help diff --git a/top/n3xx/n3xx_core.v b/top/n3xx/n3xx_core.v index 2d8f35e..98b4333 100644 --- a/top/n3xx/n3xx_core.v +++ b/top/n3xx/n3xx_core.v @@ -211,7 +211,7 @@ module n3xx_core #( ///////////////////////////////////////////////////////////////////////////////// localparam [15:0] COMPAT_MAJOR = 16'd8; - localparam [15:0] COMPAT_MINOR = 16'd1; + localparam [15:0] COMPAT_MINOR = 16'd2; ///////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////// @@ -244,6 +244,7 @@ module n3xx_core #( localparam REG_FP_GPIO_MASTER = REG_BASE_MISC + 14'h30; localparam REG_FP_GPIO_RADIO_SRC = REG_BASE_MISC + 14'h34; localparam REG_NUM_TIMEKEEPERS = REG_BASE_MISC + 14'h48; + localparam REG_BUILD_SEED = REG_BASE_MISC + 14'h4C; localparam NUM_TIMEKEEPERS = 1; @@ -543,11 +544,12 @@ module n3xx_core #( REG_DATESTAMP: cp_glob_resp_data <= build_datestamp; - REG_GIT_HASH: + REG_GIT_HASH: begin `ifndef GIT_HASH - `define GIT_HASH 32'h0BADC0DE + `define GIT_HASH 32'h0BADC0DE `endif cp_glob_resp_data <= `GIT_HASH; + end REG_FP_GPIO_MASTER: cp_glob_resp_data <= fp_gpio_master_reg; @@ -588,6 +590,13 @@ module n3xx_core #( REG_NUM_TIMEKEEPERS: cp_glob_resp_data <= NUM_TIMEKEEPERS; + REG_BUILD_SEED: begin + `ifndef BUILD_SEED + `define BUILD_SEED 32'b0 + `endif + cp_glob_resp_data <= `BUILD_SEED; + end + default: begin // Don't acknowledge if the address doesn't match cp_glob_resp_ack <= 1'b0; diff --git a/top/x300/Makefile b/top/x300/Makefile index 76dc23b..10f347e 100644 --- a/top/x300/Makefile +++ b/top/x300/Makefile @@ -21,11 +21,14 @@ CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py -GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS) -HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS) -XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS) -HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS) -XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS) +# Initialize a build seed. This can be changed to randomly affect build results. +BUILD_SEED ?= 0 + +GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +XG_DEFS=BUILD_10G=1 SFP0_10GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +HA_DEFS=BUILD_1G=1 BUILD_AURORA=1 SFP0_1GBE=1 SFP1_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) +XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) # Set build option (check RTL, run synthesis, or do a full build) ifndef TARGET @@ -146,9 +149,10 @@ help: ##Show this help message. ## ##Supported Options ##----------------- -##GUI=1 Launch the build in the Vivado GUI. -##CHECK=1 Launch the syntax checker instead of building a bitfile. -##SYNTH=1 Launch the build but stop after synthesis. -##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##BUILD_SEED= Build seed to used to affect build results. (Default is 0) +##TOP= Specify a top module for syntax checking. (Default is the bitfile top) .PHONY: all clean cleanall help diff --git a/top/x300/bus_int.v b/top/x300/bus_int.v index 1262853..e74b12e 100644 --- a/top/x300/bus_int.v +++ b/top/x300/bus_int.v @@ -175,11 +175,12 @@ module bus_int #( localparam RB_NUM_TIMEKEEPERS = 8'd12; localparam RB_FP_GPIO_SRC = 8'd13; localparam RB_DEVICE_ID = 8'd14; + localparam RB_BUILD_SEED = 8'd15; localparam RB_TA_SFP0_BASE = SR_TA_SFP0_BASE; localparam RB_TA_SFP1_BASE = SR_TA_SFP1_BASE; localparam COMPAT_MAJOR = 16'h0027; - localparam COMPAT_MINOR = 16'h0001; + localparam COMPAT_MINOR = 16'h0002; localparam NUM_TIMEKEEPERS = 1; // Include the RFNoC image core header file @@ -457,8 +458,15 @@ module bus_int #( `else RB_ETH_TYPE1: rb_data = {32'h0}; `endif +`endif +`ifndef GIT_HASH + `define GIT_HASH 32'h0BADC0DE `endif RB_GIT_HASH: rb_data = `GIT_HASH; +`ifndef BUILD_SEED + `define BUILD_SEED 32'b0 +`endif + RB_BUILD_SEED: rb_data = `BUILD_SEED; RB_XADC_VALS: rb_data = xadc_readback; RB_FP_GPIO_SRC: rb_data = fp_gpio_src; SR_BASE_TIME: begin diff --git a/top/x400/Makefile b/top/x400/Makefile index b0b1379..6b3a078 100644 --- a/top/x400/Makefile +++ b/top/x400/Makefile @@ -65,6 +65,10 @@ DRAM ?= 1 DEFS += $(OPTIONS) +# Initialize a build seed. This can be changed to randomly affect build results. +BUILD_SEED ?= 0 +DEFS += BUILD_SEED=$(BUILD_SEED) + # Defaults specific to the various targets: X410_100_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex) X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex) @@ -226,10 +230,11 @@ help: ##Show this help message. ## ##Supported Options ##----------------- -##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build. -##GUI=1 Launch the build in the Vivado GUI. -##CHECK=1 Launch the syntax checker instead of building a bitfile. -##SYNTH=1 Launch the build but stop after synthesis. -##TOP= Specify a top module for syntax checking. (Optional. Default is the bitfile top) +##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build. +##GUI=1 Launch the build in the Vivado GUI. +##CHECK=1 Launch the syntax checker instead of building a bitfile. +##SYNTH=1 Launch the build but stop after synthesis. +##BUILD_SEED= Build seed to used to affect build results. (Default is 0) +##TOP= Specify a top module for syntax checking. (Default is the bitfile top) .PHONY: all clean cleanall help diff --git a/top/x400/doc/X4XX_FPGA_left.htm b/top/x400/doc/X4XX_FPGA_left.htm index d53fc9e..528c529 100644 --- a/top/x400/doc/X4XX_FPGA_left.htm +++ b/top/x400/doc/X4XX_FPGA_left.htm @@ -348,6 +348,7 @@

PPS_CTRL_REG

CHDR_CLK_RATE_REG

CHDR_CLK_COUNT_REG

+

BUILD_SEED_REG

GPS_CTRL_REG

GPS_STATUS_REG

DBOARD_CTRL_REG

diff --git a/top/x400/doc/X4XX_FPGA_right.htm b/top/x400/doc/X4XX_FPGA_right.htm index 2f6a1e6..ae24ff2 100644 --- a/top/x400/doc/X4XX_FPGA_right.htm +++ b/top/x400/doc/X4XX_FPGA_right.htm @@ -716,7 +716,7 @@ Prism.languages.vhdl={comment:/--.+/,"vhdl-vectors":{pattern:/\b[oxb]"[\da-f_]+"

The top is defined in HDL source file common_regs.v, x4xx.v.

P5 Content

Register map supplied for open-source projects

-

"All content provided is Copyright 2022 National Instruments Corporation. +

"All content provided is Copyright 2023 National Instruments Corporation. For information on NI trademark guidelines, please see http://www.ni.com/legal/trademarks/. For the NI Patent Notice, please see http://www.ni.com/legal/patents/."

@@ -6830,6 +6830,89 @@ Returns the count value of a free-running counter driven by the RFNoC + + +
+ + +

Offset 0x0028: BUILD_SEED_REG Register (R)

+ + (show extended info) +
+ + + + + + + + + + + + + + + + + +
+ + + +
Port ARM_M_AXI_HPM0
+ +		 + + + + +
AXI_HPM0_REGMAP|CORE_REGS
  0x10000A0000
+ +		 + + + + +
CORE_REGS_REGMAP|GLOBAL_REGS
  0x000000
+ +		 + + + + +
BUILD_SEED_REG
  offset=0x0028
+ +		 + + + + + +
+ + +Total Offset =
  0x10000A0028 + +
+ +

+ +

Initial Value not specified +

+ +

This register is defined in HDL source file x4xx_global_regs.v.

+ +
+ +
+ +Build seed used for this compilation. Making this value readable + ensures that compilation results are affected by the value in this + register. + +
+
@@ -24241,9 +24324,9 @@ FPGA version.
- 9 + 10 - 0x00000009 + 0x0000000A

FPGA_CURRENT_VERSION_MINOR

@@ -24254,9 +24337,9 @@ FPGA version.
- 570827282 + 571610633 - 0x22062212 + 0x22121609

FPGA_VERSION_LAST_MODIFIED_TIME

diff --git a/top/x400/regmap/global_regs_regmap_utils.vh b/top/x400/regmap/global_regs_regmap_utils.vh index 0c04904..9f6627c 100644 --- a/top/x400/regmap/global_regs_regmap_utils.vh +++ b/top/x400/regmap/global_regs_regmap_utils.vh @@ -1,5 +1,5 @@ // -// Copyright 2022 Ettus Research, A National Instruments Company +// Copyright 2023 Ettus Research, A National Instruments Company // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -21,6 +21,7 @@ // PPS_CTRL_REG : 0x1C (x4xx_global_regs.v) // CHDR_CLK_RATE_REG : 0x20 (x4xx_global_regs.v) // CHDR_CLK_COUNT_REG : 0x24 (x4xx_global_regs.v) + // BUILD_SEED_REG : 0x28 (x4xx_global_regs.v) // GPS_CTRL_REG : 0x38 (x4xx_global_regs.v) // GPS_STATUS_REG : 0x3C (x4xx_global_regs.v) // DBOARD_CTRL_REG : 0x40 (x4xx_global_regs.v) @@ -181,6 +182,11 @@ localparam CHDR_CLK_COUNT_REG_SIZE = 32; // register width in bits localparam CHDR_CLK_COUNT_REG_MASK = 32'h0; + // BUILD_SEED_REG Register (from x4xx_global_regs.v) + localparam BUILD_SEED_REG = 'h28; // Register Offset + localparam BUILD_SEED_REG_SIZE = 32; // register width in bits + localparam BUILD_SEED_REG_MASK = 32'h0; + // GPS_CTRL_REG Register (from x4xx_global_regs.v) localparam GPS_CTRL_REG = 'h38; // Register Offset localparam GPS_CTRL_REG_SIZE = 32; // register width in bits diff --git a/top/x400/regmap/versioning_regs_regmap_utils.vh b/top/x400/regmap/versioning_regs_regmap_utils.vh index eb128e9..3ad83e1 100644 --- a/top/x400/regmap/versioning_regs_regmap_utils.vh +++ b/top/x400/regmap/versioning_regs_regmap_utils.vh @@ -84,8 +84,8 @@ localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_CURRENT_VERSION_MINOR = 'h9; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22062212; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_CURRENT_VERSION_MINOR = 'hA; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22121609; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_100M_VERSION localparam RF_CORE_100M_VERSION_SIZE = 7; diff --git a/top/x400/x4xx.v b/top/x400/x4xx.v index 4a9bbe9..9ff649a 100644 --- a/top/x400/x4xx.v +++ b/top/x400/x4xx.v @@ -2280,12 +2280,12 @@ endmodule //
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED // // -// +// // // // // -// +// // // // diff --git a/top/x400/x4xx_global_regs.v b/top/x400/x4xx_global_regs.v index 5373c0a..a12dbc1 100644 --- a/top/x400/x4xx_global_regs.v +++ b/top/x400/x4xx_global_regs.v @@ -280,6 +280,13 @@ module x4xx_global_regs #( s_ctrlport_resp_data <= CHDR_CLK_RATE[CHDR_CLK_RATE_REG_SIZE-1:0]; end + REG_BASE + BUILD_SEED_REG: begin + `ifndef BUILD_SEED + `define BUILD_SEED 32'b0 + `endif + s_ctrlport_resp_data <= `BUILD_SEED; + end + REG_BASE + CHDR_CLK_COUNT_REG: begin s_ctrlport_resp_data <= chdr_counter_reg; end @@ -601,6 +608,13 @@ endmodule // CHDR bus clock. // // +// +// +// Build seed used for this compilation. Making this value readable +// ensures that compilation results are affected by the value in this +// register. +// +// // // // Returns information from the QSFP0 Lane0.