Wade Fife 0e65ae3c86 fpga: x400: Add 1x64, 2x64, and 1x128 DRAM interconnect ...

Original-commit: daf1ed2ad2fbb72f16a9909fa75a0ba9e2879583

2023-02-24 08:07:17 -06:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: rfnoc: Add resize capability to chdr_stream_endpoint

2023-02-24 08:07:17 -06:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: Add BUILD_BASE_DIR option to makefiles

2023-02-09 07:38:49 -06:00

top

fpga: x400: Add 1x64, 2x64, and 1x128 DRAM interconnect

2023-02-24 08:07:17 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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