Wade Fife 2612487d43 fpga: n3xx: Add CE clock ...

Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.


Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1

2023-10-18 22:23:55 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Allow buffering in eth_ipv4_chdr_adapter

2023-10-18 22:23:55 -05:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: Add X440/FBX support

2023-06-12 10:27:29 -05:00

top

fpga: n3xx: Add CE clock

2023-10-18 22:23:55 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%