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fpga: Add X440/FBX support

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Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/sim_axi_ram.sv
+37 -27
View File
@@ -1,34 +1,44 @@
//
// Copyright 2019 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: sim_axi_ram
//
// Description:
// Description:
//
// Simulation model for a basic AXI4 memory mapped memory. A few notes on its
// Simulation model for a basic AXI4 memory mapped memory. A few notes on its
// behavior:
//
// - This model does not reorder requests (regardless of WID/RID). All
// - This model does not reorder requests (regardless of WID/RID). All
// requests are evaluated strictly in order.
// - The only supported response is OKAY
// - This model supports misaligned memory accesses, which cause a
// - This model supports misaligned memory accesses, which cause a
// simulation warning.
// - A reset does not clear the memory contents
// - The memory itself is implemented using an associative array (sparse
// - The memory itself is implemented using an associative array (sparse
// matrix) so that large memories can be supported.
// - This model is half duplex, meaning read and write data transfers won't
// happen at the same time. A new data transfer won't begin until the
// previous one has completed.
//
// Parameters:
//
// - AWIDTH : Address width of the memory to model
// - DWIDTH : Data width of the memory to model
// - IDWIDTH : Width of ID ports of the AXI bus
// - BIG_ENDIAN : Endianness of the memory model (0 = little, 1 = big)
// - STALL_PROB : Default probability of a channel stalling (0 to 99)
// - NO_4KB_LIMIT : Allow bursts to cross 4 KiB boundaries
//
module sim_axi_ram #(
parameter AWIDTH = 32,
parameter DWIDTH = 64,
parameter IDWIDTH = 2,
parameter BIG_ENDIAN = 0,
parameter STALL_PROB = 25
parameter AWIDTH = 32,
parameter DWIDTH = 64,
parameter IDWIDTH = 2,
parameter BIG_ENDIAN = 0,
parameter STALL_PROB = 25,
parameter NO_4KB_LIMIT = 0
) (
input logic s_aclk,
input logic s_aresetn,
@@ -82,7 +92,7 @@ module sim_axi_ram #(
//---------------------------------------------------------------------------
// Data Types
//---------------------------------------------------------------------------
typedef enum logic [1:0] { FIXED, INCR, WRAP } burst_t;
typedef enum logic [1:0] { OKAY, EXOKAY, SLVERR, DECERR } resp_t;
@@ -95,7 +105,7 @@ module sim_axi_ram #(
burst_t burst;
} req_t;
// Make the address type an extra bit wide so that we can detect
// Make the address type an extra bit wide so that we can detect
// out-of-bounds accesses easily.
typedef bit [AWIDTH:0] addr_t;
@@ -160,7 +170,7 @@ module sim_axi_ram #(
rdata_stall_prob = probability;
endfunction : set_read_stall_prob
// Set Write Address Channel stall probability
// Set Write Address Channel stall probability
function void set_waddr_stall_prob(int probability);
assert(probability >= 0 && probability <= 100) else begin
$error("Probability must be from 0 to 100");
@@ -200,7 +210,7 @@ module sim_axi_ram #(
rdata_stall_prob = probability;
endfunction : set_rdata_stall_prob
// Get Write Address Channel stall probability
// Get Write Address Channel stall probability
function int get_waddr_stall_prob();
return waddr_stall_prob;
endfunction : get_waddr_stall_prob
@@ -313,13 +323,13 @@ module sim_axi_ram #(
assert ($cast(burst, s_axi_awburst)) else begin
$fatal(1, "Invalid AWBURST value");
end
assert ((s_axi_awaddr & MASK_4K) ==
((s_axi_awaddr + (s_axi_awlen+1)*(2**s_axi_awsize) - 1) & MASK_4K)) else begin
assert (NO_4KB_LIMIT || ((s_axi_awaddr & MASK_4K) ==
((s_axi_awaddr + (s_axi_awlen+1)*(2**s_axi_awsize) - 1) & MASK_4K))) else begin
$fatal(1, "Memory write burst crosses 4 KiB boundary");
end
if (DEBUG) begin
$display("WRITE REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m",
$display("WRITE REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m",
req.id, req.addr, req.len, req.size, req.burst.name, $realtime);
end
@@ -370,13 +380,13 @@ module sim_axi_ram #(
assert ($cast(burst, s_axi_awburst)) else begin
$fatal(1, "Invalid ARBURST value");
end
assert ((s_axi_araddr & MASK_4K) ==
((s_axi_araddr + (s_axi_arlen+1)*(2**s_axi_arsize) - 1) & MASK_4K)) else begin
assert (NO_4KB_LIMIT || ((s_axi_araddr & MASK_4K) ==
((s_axi_araddr + (s_axi_arlen+1)*(2**s_axi_arsize) - 1) & MASK_4K))) else begin
$fatal(1, "Memory read burst crosses 4 KiB boundary");
end
if (DEBUG) begin
$display("READ REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m",
$display("READ REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m",
req.id, req.addr, req.len, req.size, req.burst.name, $realtime);
end
@@ -437,7 +447,7 @@ module sim_axi_ram #(
addr = req.addr;
end
INCR : begin
// If the address rolls over, we've reached the end of the
// If the address rolls over, we've reached the end of the
// memory and we should stop here.
addr = req.addr + i*req.size;
if (addr < req.addr) break;
@@ -451,7 +461,7 @@ module sim_axi_ram #(
write_mem(addr, req.size, s_axi_wdata, s_axi_wstrb);
if (DEBUG) begin
$display("WRITE: count=%3X, ADDR=%X, DATA=%X, SIZE=%X, STRB=%X, %t, %m",
$display("WRITE: count=%3X, ADDR=%X, DATA=%X, SIZE=%X, STRB=%X, %t, %m",
i, addr, s_axi_wdata, req.size, s_axi_wstrb, $realtime);
end
@@ -474,9 +484,9 @@ module sim_axi_ram #(
// Enqueue write response
write_resp.put(req);
// Make sure WLAST asserted for the last word. If not we report an error.
// Per the AXI4 standard, "a slave is not required to use the WLAST
// signal" because "a slave can calculate the last write data transfer
// Make sure WLAST asserted for the last word. If not we report an error.
// Per the AXI4 standard, "a slave is not required to use the WLAST
// signal" because "a slave can calculate the last write data transfer
// from the burst length AWLEN".
if (s_axi_wlast != 1'b1) begin
$error("WLAST not asserted on last word of burst");
@@ -598,7 +608,7 @@ module sim_axi_ram #(
addr = req.addr;
end
INCR : begin
// If the address rolls over, we've reached the end of the memory
// If the address rolls over, we've reached the end of the memory
// and we should stop here.
addr = req.addr + i*req.size;
if (addr < req.addr) break;
lib/rfnoc/blocks/rfnoc_block_replay/axis_replay.v
+6 -2
View File
@@ -168,8 +168,12 @@ module axis_replay #(
// The lower MEM_ALIGN bits for all memory byte addresses should be 0.
localparam MEM_ALIGN = $clog2(MEM_DATA_W / 8);
//
// AXI alignment requirement (4096 bytes) in MEM_DATA_W-bit words
localparam AXI_ALIGNMENT = 4096 / BYTES_PER_WORD;
// Burst length in bytes
localparam BURST_LENGTH = 2**MEM_COUNT_W * BYTES_PER_WORD;
//
// AXI alignment requirement (normally 4096 bytes) in MEM_DATA_W-bit words
localparam AXI_ALIGNMENT = (BURST_LENGTH <= 4096) ? 4096 / BYTES_PER_WORD :
BURST_LENGTH / BYTES_PER_WORD;
// Memory Buffering Parameters
//
lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay.v
+22 -19
View File
@@ -15,26 +15,30 @@
//
// Parameters:
//
// THIS_PORTID : Control crossbar port to which this block is connected
// CHDR_W : AXIS-CHDR data bus width
// MTU : Maximum transmission unit (i.e., maximum packet size in
// CHDR words is 2**MTU).
// NUM_PORTS : Number of replay instances to instantiate. Each one will
// have its own register set and memory interface.
// MEM_DATA_W : Data width to use for the memory interface.
// MEM_ADDR_W : Byte address width to use for the memory interface.
// THIS_PORTID : Control crossbar port to which this block is connected
// CHDR_W : AXIS-CHDR data bus width
// MTU : Maximum transmission unit (i.e., maximum packet size in
// CHDR words is 2**MTU).
// NUM_PORTS : Number of replay instances to instantiate. Each one will
// have its own register set and memory interface.
// MEM_DATA_W : Data width to use for the memory interface.
// MEM_ADDR_W : Byte address width to use for the memory interface.
// BURST_LENGTH : Burst length to use in bytes. Must not exceed 256 words. It
// can be larger than the 4096-byte limit of AXI, but this
// might not be compatible with all memories.
//
`default_nettype none
module rfnoc_block_replay #(
parameter [9:0] THIS_PORTID = 10'd0,
parameter CHDR_W = 64,
parameter [5:0] MTU = 10,
parameter NUM_PORTS = 1,
parameter MEM_DATA_W = 64,
parameter MEM_ADDR_W = 30
parameter [9:0] THIS_PORTID = 10'd0,
parameter CHDR_W = 64,
parameter [5:0] MTU = 10,
parameter NUM_PORTS = 1,
parameter MEM_DATA_W = 64,
parameter MEM_ADDR_W = 30,
parameter BURST_LENGTH = MEM_DATA_W/8 * 256
) (
//---------------------------------------------------------------------------
// AXIS-CHDR Port
@@ -323,11 +327,10 @@ module rfnoc_block_replay #(
//---------------------------------------------------------------------------
// Width of memory transfer count. This controls the maximum burst length
// supported by the Replay block. For AXI compatibility, it must be 8 or less
// and should not represent more than 4 KiB. Here we set it to 2 KiB by
// default.
localparam MEM_COUNT_W = (MEM_DATA_W <= 64) ? 8 : // Max width allowed
$clog2(2048 / (MEM_DATA_W/8)); // 2 KiB
// supported by the Replay block. For AXI, it must not exceed 8 and it should
// be no more than 4096 unless supported by the memory being used.
localparam DESIRED_MEM_COUNT_W = $clog2(BURST_LENGTH / (MEM_DATA_W/8));
localparam MEM_COUNT_W = (DESIRED_MEM_COUNT_W > 8) ? 8 : DESIRED_MEM_COUNT_W;
genvar i;
generate
lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_tb.sv
+2 -1
View File
@@ -209,7 +209,8 @@ module rfnoc_block_replay_tb#(
.DWIDTH (MEM_DATA_W),
.IDWIDTH (1),
.BIG_ENDIAN (0),
.STALL_PROB (STALL_PROB)
.STALL_PROB (STALL_PROB),
.NO_4KB_LIMIT(MEM_DATA_W/8 * 256 > 4096)
) sim_axi_ram_i (
.s_aclk (mem_clk),
.s_aresetn (~mem_rst),
tools/utils/image_package_mapping.py
+37
View File
@@ -95,6 +95,31 @@ PACKAGE_MAPPING = {
"usrp_x410_fpga_CG_400.rpt",
]
},
"x440": {
"type": "x4xx",
"package_name": "x4xx_x440_fpga_default-g{}.zip",
"files": ["usrp_x440_fpga_CG_400.bit",
"usrp_x440_fpga_CG_400.bit.md5",
"usrp_x440_fpga_CG_400.dts",
"usrp_x440_fpga_CG_400.dts.md5",
"usrp_x440_fpga_CG_400.rpt",
"usrp_x440_fpga_X4_400.bit",
"usrp_x440_fpga_X4_400.bit.md5",
"usrp_x440_fpga_X4_400.dts",
"usrp_x440_fpga_X4_400.dts.md5",
"usrp_x440_fpga_X4_400.rpt",
"usrp_x440_fpga_CG_1600.bit",
"usrp_x440_fpga_CG_1600.bit.md5",
"usrp_x440_fpga_CG_1600.dts",
"usrp_x440_fpga_CG_1600.dts.md5",
"usrp_x440_fpga_CG_1600.rpt",
"usrp_x440_fpga_X4_1600.bit",
"usrp_x440_fpga_X4_1600.bit.md5",
"usrp_x440_fpga_X4_1600.dts",
"usrp_x440_fpga_X4_1600.dts.md5",
"usrp_x440_fpga_X4_1600.rpt",
]
},
"x410_cpld": {
"type": "x4xx",
"package_name": "x4xx_x410_cpld_default-g{}.zip",
@@ -107,6 +132,18 @@ PACKAGE_MAPPING = {
"usrp_x410_cpld_10m08.svf",
"usrp_x410_cpld_10m08.svf.md5"]
},
"x440_cpld": {
"type": "x4xx",
"package_name": "x4xx_x440_cpld_default-g{}.zip",
"files": ["usrp_x440_cpld_10m04.rpd",
"usrp_x440_cpld_10m04.rpd.md5",
"usrp_x440_cpld_10m04.svf",
"usrp_x440_cpld_10m04.svf.md5",
"usrp_x440_cpld_10m08.rpd",
"usrp_x440_cpld_10m08.rpd.md5",
"usrp_x440_cpld_10m08.svf",
"usrp_x440_cpld_10m08.svf.md5"]
},
"zbx_cpld": {
"type": "x4xx",
"package_name": "x4xx_zbx_cpld_default-g{}.zip",
top/x400/Makefile
+65 -1
View File
@@ -62,6 +62,14 @@ X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_40
X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0
X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128
X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0
X440_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0
X440_X1_1600: DEFS += $(QSFP0_10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=2*$(DRAM) DRAM_W=512
X440_X4_1600: DEFS += $(QSFP0_4X10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=2*$(DRAM) DRAM_W=512
X440_C1_1600: DEFS += $(QSFP0_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=0
X440_CG_1600: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=0
# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
# exclude it. Note that some targets exclude it regardless of this setting.
@@ -79,6 +87,10 @@ X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_
X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex)
X440_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_static_router.hex)
X440_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_d_static_router.hex)
X440_1600_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_static_router.hex)
X440_1600_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_d_static_router.hex)
# Option to stop after RTL elaboration. Use this flag as a synthesis check.
ifndef TARGET
@@ -132,7 +144,15 @@ endif
##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused
##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused
##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
##* Note: Not all targets are shipped with UHD.
##X440_X1_400 | 400 MHz | 8 | 10 GbE (Lane 0) | Unused | 128b x 8 Ch
##X440_X4_400 | 400 MHz | 8 | 4 x 10 GbE | Unused | 128b x 8 Ch
##X440_C1_400 | 400 MHz | 8 | 100 GbE | Unused | Unused
##X440_CG_400 | 400 MHz | 8 | 100 GbE | 100 GbE | Unused
##X440_X1_1600 | 1.6 GHz | 2 | 10 GbE (Lane 0) | Unused | 512b x 2 Ch
##X440_X4_1600 | 1.6 GHz | 2 | 4 x 10 GbE | Unused | 512b x 2 Ch
##X440_C1_1600 | 1.6 GHz | 2 | 100 GbE | Unused | Unused
##X440_CG_1600 | 1.6 GHz | 2 | 100 GbE | 100 GbE | Unused
##* Note: Not all targets are shipped with UHD
##* Note: Some YAML configurations might not use all available DRAM channels.
X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts
@@ -207,6 +227,38 @@ X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,CG_400)
X440_X1_400: X440_IP build/usrp_x440_fpga_X1_400.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
$(call post_build,X440,X1_400)
X440_X4_400: X440_IP build/usrp_x440_fpga_X4_400.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
$(call post_build,X440,X4_400)
X440_C1_400: X440_IP build/usrp_x440_fpga_C1_400.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
$(call post_build,X440,C1_400)
X440_CG_400: X440_IP build/usrp_x440_fpga_CG_400.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
$(call post_build,X440,CG_400)
X440_X1_1600: X440_IP build/usrp_x440_fpga_X1_1600.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
$(call post_build,X440,X1_1600)
X440_X4_1600: X440_IP build/usrp_x440_fpga_X4_1600.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
$(call post_build,X440,X4_1600)
X440_C1_1600: X440_IP build/usrp_x440_fpga_C1_1600.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
$(call post_build,X440,C1_1600)
X440_CG_1600: X440_IP build/usrp_x440_fpga_CG_1600.dts
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
$(call post_build,X440,CG_1600)
##
##Experimental Targets
##-------------|-----------|----|-----------------|-----------------|------------
@@ -229,6 +281,9 @@ all: X410_X4_200 X410_CG_400 X410_UC_200 ##(Default targets)
X410_IP: ##Build IP only.
+$(call vivado_ip,X410,$(DEFS) X410=1)
X440_IP: ##Build IP only.
+$(call vivado_ip,X440,$(DEFS) X440=1)
build/usrp_x410%.dts: dts/*.dts dts/*.dtsi
-mkdir -p build
tools/parse_versions_for_dts.py \
@@ -238,6 +293,15 @@ build/usrp_x410%.dts: dts/*.dts dts/*.dtsi
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
$$(python3 tools/get_dts_input.py --target $@)
build/usrp_x440%.dts: dts/*.dts dts/*.dtsi
-mkdir -p build
tools/parse_versions_for_dts.py \
--input regmap/x440/versioning_regs_regmap_utils.vh \
--output dts/x440-version-info.dtsi \
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_full
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
$$(python3 tools/get_dts_input.py --target $@)
clean: ##Clean up all target build outputs.
@echo "Cleaning targets..."
@rm -rf build-X4*
top/x400/Makefile.x4xx.inc
+32
View File
@@ -100,11 +100,36 @@ rf/x410/x410_rf_reset_controller.vhd \
dboards/zbx/db_gpio_interface.v
endif
ifdef X440
TOP_SRCS += \
rf/100m/rf_core_100m.v \
rf/full/rf_core_full.v \
rf/x440/x440_rf_reset_controller.vhd \
dboards/fbx/db_gpio_interface.v \
dboards/fbx/ctrlport_to_i2c_sync_ctrl.v \
dboards/fbx/led_atr_control.v \
dboards/fbx/clock_en_control.v \
dboards/fbx/rf_atr_control.v
endif
ifdef X410
MB_XDC += \
constraints/timing/x410_clocks.xdc
endif
ifdef X440
ifeq ($(RF_BW), 400)
MB_XDC += \
constraints/timing/x440_clocks_400.xdc
endif
ifeq ($(RF_BW), 1600)
MB_XDC += \
constraints/timing/x440_clocks_1600.xdc
endif
MB_XDC += \
constraints/timing/x440_clocks.xdc
endif
MB_XDC += \
constraints/pins/common.xdc \
constraints/timing/shared_constants.sdc \
@@ -119,6 +144,13 @@ constraints/pins/x410/db_gpio.xdc \
constraints/timing/x410.xdc
endif
ifdef X440
MB_XDC += \
constraints/pins/rfdc_4x4.xdc \
constraints/pins/x440/db_gpio.xdc \
constraints/timing/x440.xdc
endif
# Definitions
# MGT Types from x4xx_mgt_type.vh
MGT_100GbE = 5
top/x400/constraints/pins/qsfp1_0.xdc
-1
View File
@@ -26,4 +26,3 @@ set_property PACKAGE_PIN Y36 [get_ports {QSFP1_0_TX_N}]
set_property PACKAGE_PIN Y31 [get_ports {GTY_RCV_CLK_P}]
set_property PACKAGE_PIN Y32 [get_ports {GTY_RCV_CLK_N}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {GTY_RCV_CLK_*}]
top/x400/constraints/pins/rfdc_4x4.xdc
+87
View File
@@ -0,0 +1,87 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# RF data converters pin constraints for X440.
# Converter pin mapping can be found at(redirected from UG1075):
# https://www.xilinx.com/support/packagefiles/zuppackages/xczu28drffvg1517pkg.txt
#
# SYSREF input for data converters.
set_property PACKAGE_PIN U4 [get_ports {SYSREF_RF_N}]
set_property PACKAGE_PIN U5 [get_ports {SYSREF_RF_P}]
###############################################################################
# Pin constraints for the ADCs
###############################################################################
# ADC Reference Clocks for Slot 0 (DBA)
set_property PACKAGE_PIN AF5 [get_ports {ADC_CLK_P[0]}]
set_property PACKAGE_PIN AF4 [get_ports {ADC_CLK_N[0]}]
set_property PACKAGE_PIN AD5 [get_ports {ADC_CLK_P[1]}]
set_property PACKAGE_PIN AD4 [get_ports {ADC_CLK_N[1]}]
# ADC Reference Clocks for Slot 1 (DBB)
set_property PACKAGE_PIN AB5 [get_ports {ADC_CLK_P[2]}]
set_property PACKAGE_PIN AB4 [get_ports {ADC_CLK_N[2]}]
set_property PACKAGE_PIN Y5 [get_ports {ADC_CLK_P[3]}]
set_property PACKAGE_PIN Y4 [get_ports {ADC_CLK_N[3]}]
# ADC Inputs for Slot 0 (DBA)
# Note: numbering here does NOT match schematic, but it is the right order
# according to RF BD Connection spec.
set_property PACKAGE_PIN AH2 [get_ports {DB0_RX_P[3]}]
set_property PACKAGE_PIN AH1 [get_ports {DB0_RX_N[3]}]
set_property PACKAGE_PIN AK2 [get_ports {DB0_RX_P[2]}]
set_property PACKAGE_PIN AK1 [get_ports {DB0_RX_N[2]}]
set_property PACKAGE_PIN AM2 [get_ports {DB0_RX_P[1]}]
set_property PACKAGE_PIN AM1 [get_ports {DB0_RX_N[1]}]
set_property PACKAGE_PIN AP2 [get_ports {DB0_RX_P[0]}]
set_property PACKAGE_PIN AP1 [get_ports {DB0_RX_N[0]}]
# ADC Inputs for Slot 1 (DBB)
# Note: numbering here does NOT match schematic, but it is the right order
# according to RF BD Connection spec.
set_property PACKAGE_PIN Y2 [get_ports {DB1_RX_P[3]}]
set_property PACKAGE_PIN Y1 [get_ports {DB1_RX_N[3]}]
set_property PACKAGE_PIN AB2 [get_ports {DB1_RX_P[2]}]
set_property PACKAGE_PIN AB1 [get_ports {DB1_RX_N[2]}]
set_property PACKAGE_PIN AD2 [get_ports {DB1_RX_P[1]}]
set_property PACKAGE_PIN AD1 [get_ports {DB1_RX_N[1]}]
set_property PACKAGE_PIN AF2 [get_ports {DB1_RX_P[0]}]
set_property PACKAGE_PIN AF1 [get_ports {DB1_RX_N[0]}]
###############################################################################
# Pin constraints for the DACs
###############################################################################
# DAC Reference Clock for Slot 0 (DBA)
set_property PACKAGE_PIN R5 [get_ports {DAC_CLK_P[0]}]
set_property PACKAGE_PIN R4 [get_ports {DAC_CLK_N[0]}]
# DAC Reference Clock for Slot 1 (DBB)
set_property PACKAGE_PIN N5 [get_ports {DAC_CLK_P[1]}]
set_property PACKAGE_PIN N4 [get_ports {DAC_CLK_N[1]}]
# DAC Outputs for Slot 0 (DBA)
set_property PACKAGE_PIN U2 [get_ports {DB0_TX_P[0]}]
set_property PACKAGE_PIN U1 [get_ports {DB0_TX_N[0]}]
set_property PACKAGE_PIN R2 [get_ports {DB0_TX_P[1]}]
set_property PACKAGE_PIN R1 [get_ports {DB0_TX_N[1]}]
set_property PACKAGE_PIN N2 [get_ports {DB0_TX_P[2]}]
set_property PACKAGE_PIN N1 [get_ports {DB0_TX_N[2]}]
set_property PACKAGE_PIN L2 [get_ports {DB0_TX_P[3]}]
set_property PACKAGE_PIN L1 [get_ports {DB0_TX_N[3]}]
# DAC Outputs for Slot 1 (DBB)
set_property PACKAGE_PIN J2 [get_ports {DB1_TX_P[0]}]
set_property PACKAGE_PIN J1 [get_ports {DB1_TX_N[0]}]
set_property PACKAGE_PIN G2 [get_ports {DB1_TX_P[1]}]
set_property PACKAGE_PIN G1 [get_ports {DB1_TX_N[1]}]
set_property PACKAGE_PIN E2 [get_ports {DB1_TX_P[2]}]
set_property PACKAGE_PIN E1 [get_ports {DB1_TX_N[2]}]
set_property PACKAGE_PIN C2 [get_ports {DB1_TX_P[3]}]
set_property PACKAGE_PIN C1 [get_ports {DB1_TX_N[3]}]
top/x400/constraints/pins/x440/db_gpio.xdc
+180
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# DB GPIO pin constraints for X440.
#
###############################################################################
# Pin constraints for the other PL pins (1.8 V)
###############################################################################
set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[0]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[0]}]
set_property IOB TRUE [get_ports {DB1_GPIO[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[1]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[1]}]
set_property IOB TRUE [get_ports {DB1_GPIO[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[2]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[2]}]
set_property IOB TRUE [get_ports {DB1_GPIO[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[3]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[3]}]
set_property IOB TRUE [get_ports {DB1_GPIO[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[4]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[4]}]
set_property IOB TRUE [get_ports {DB1_GPIO[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[5]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[5]}]
set_property IOB TRUE [get_ports {DB1_GPIO[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[6]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[6]}]
set_property IOB TRUE [get_ports {DB1_GPIO[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[7]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[7]}]
set_property IOB TRUE [get_ports {DB1_GPIO[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[8]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[8]}]
set_property IOB TRUE [get_ports {DB1_GPIO[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[9]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[9]}]
set_property IOB TRUE [get_ports {DB1_GPIO[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[10]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[10]}]
set_property IOB TRUE [get_ports {DB1_GPIO[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[11]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[11]}]
set_property IOB TRUE [get_ports {DB1_GPIO[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[12]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[12]}]
set_property IOB TRUE [get_ports {DB1_GPIO[12]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[13]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[13]}]
set_property IOB TRUE [get_ports {DB1_GPIO[13]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[14]}]
set_property PULLUP TRUE [get_ports {DB1_GPIO[14]}]
set_property IOB TRUE [get_ports {DB1_GPIO[14]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[15]}]
set_property PULLUP TRUE [get_ports {DB1_GPIO[15]}]
set_property IOB TRUE [get_ports {DB1_GPIO[15]}]
# DB1_GPIO[17] connects to D, DB1_GPIO[16] connects to D#
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[16]}]
set_property PULLDOWN FALSE [get_ports {DB1_GPIO[16]}]
set_property SLEW SLOW [get_ports {DB1_GPIO[16]}]
set_property DRIVE 16 [get_ports {DB1_GPIO[16]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[17]}]
set_property PULLDOWN FALSE [get_ports {DB1_GPIO[17]}]
set_property SLEW SLOW [get_ports {DB1_GPIO[17]}]
set_property DRIVE 16 [get_ports {DB1_GPIO[17]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[18]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[18]}]
set_property IOB TRUE [get_ports {DB1_GPIO[18]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[19]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[19]}]
set_property IOB TRUE [get_ports {DB1_GPIO[19]}]
set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[0]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[0]}]
set_property IOB TRUE [get_ports {DB0_GPIO[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[1]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[1]}]
set_property IOB TRUE [get_ports {DB0_GPIO[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[2]}]
set_property PULLUP TRUE [get_ports {DB0_GPIO[2]}]
set_property IOB TRUE [get_ports {DB0_GPIO[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[3]}]
set_property PULLUP TRUE [get_ports {DB0_GPIO[3]}]
set_property IOB TRUE [get_ports {DB0_GPIO[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[4]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[4]}]
set_property IOB TRUE [get_ports {DB0_GPIO[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[5]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[5]}]
set_property IOB TRUE [get_ports {DB0_GPIO[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[6]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[6]}]
set_property IOB TRUE [get_ports {DB0_GPIO[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[7]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[7]}]
set_property IOB TRUE [get_ports {DB0_GPIO[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[8]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[8]}]
set_property IOB TRUE [get_ports {DB0_GPIO[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[9]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[9]}]
set_property IOB TRUE [get_ports {DB0_GPIO[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[10]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[10]}]
set_property IOB TRUE [get_ports {DB0_GPIO[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[11]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[11]}]
set_property IOB TRUE [get_ports {DB0_GPIO[11]}]
# DB0_GPIO[13] connects to D, DB0_GPIO[12] connects to D#
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[12]}]
set_property PULLDOWN FALSE [get_ports {DB0_GPIO[12]}]
set_property SLEW SLOW [get_ports {DB0_GPIO[12]}]
set_property DRIVE 16 [get_ports {DB0_GPIO[12]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[13]}]
set_property PULLDOWN FALSE [get_ports {DB0_GPIO[13]}]
set_property SLEW SLOW [get_ports {DB0_GPIO[13]}]
set_property DRIVE 16 [get_ports {DB0_GPIO[13]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[14]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[14]}]
set_property IOB TRUE [get_ports {DB0_GPIO[14]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[15]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[15]}]
set_property IOB TRUE [get_ports {DB0_GPIO[15]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[16]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[16]}]
set_property IOB TRUE [get_ports {DB0_GPIO[16]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[17]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[17]}]
set_property IOB TRUE [get_ports {DB0_GPIO[17]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[18]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[18]}]
set_property IOB TRUE [get_ports {DB0_GPIO[18]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[19]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[19]}]
set_property IOB TRUE [get_ports {DB0_GPIO[19]}]
top/x400/constraints/timing/x440.xdc
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Timing constraints exclusive to X440. These should be used
# in conjunction with ./common.xdc
#
###############################################################################
# DB GPIO
# This interface is defined as system synchronous to pll_ref_clk.
# Some timing constants in this section are declared in
# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
###############################################################################
# In the current db_gpio_interface implementation, all GPIOs are received asynchronously
# by the DB, so we add a very relax constraint for these signals.
set db_gpio_min 0
set db_gpio_max [expr {$pll_ref_clk_period/2}]
set db_gpio_sync_max 3.500
# Set constraints for all ports.
set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
set db_gpio_sync_ports [get_ports {DB0_GPIO[12] DB0_GPIO[13] DB1_GPIO[16] DB1_GPIO[17]}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_min $db_gpio_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_max $db_gpio_ports
# Should just overwrite the setting for the sync clock ports that are also in db_gpio_ports
set_output_delay -clock [get_clocks ref_clk] -max $db_gpio_sync_max $db_gpio_sync_ports
set_input_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_min $db_gpio_ports
set_input_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_max $db_gpio_ports
# Use multi cycle path constraint to relax timing on these pins.
set_multicycle_path -setup 2 -from [get_pins db_gpio_gen[*].db_gpio_interface_i/ctrlport_to_i2c_inst/i2c_master/byte_controller/bit_controller/*_oen_reg/C]
set_multicycle_path -end -hold 7 -from [get_pins db_gpio_gen[*].db_gpio_interface_i/ctrlport_to_i2c_inst/i2c_master/byte_controller/bit_controller/*_oen_reg/C]
###############################################################################
# x440_ps_rfdc_bd
###############################################################################
# This property tells Vivado that we require these clocks to be well aligned.
# We have synchronous clock domain crossings between these clocks that can have
# large hold violations after placement due to uneven clock loading.
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk_2x \
}]
# We treat rfdc_clk buffers as asynchronous, with knowledge that
# code clocked in this domain will be reset after this clocked is enabled. This
# will make timing easier to meet on these clock domains.
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_2x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_2x_buf/*BUFGCE*/CE}]
###############################################################################
# SPLL SYSREF Capture
###############################################################################
# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
# SYSREF and PLL reference clock are directly fed into the RFSoC.
# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
# output) with a double synchronizer and then transfered to the RFDC clock
# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
# sync. purposes.
# SYSREF is a continuous signal intentionally shifted in the LMK chip to align
# it closer to the PRC's falling edge.
# The highest PRC frequency supported in MPM (64 MHz) is used for
# timing constraints. Therefore, SYSREF LMK's delay = (1/64e6)/2.
set sysref_lmk_delay 7.8125
#
# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
#
# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
# which essentially over-constrains SYSREF.
#
# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
# calculated as follows:
# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
# - PRC prop. delay (min)
set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
#
# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
# is calculated as follows:
# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
# - PRC prop. delay (min)
set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
###############################################################################
# SPI to MB CPLD (PL)
# This interface is defined as system synchronous to pll_ref_clk.
###############################################################################
# The output delays are chosen to allow a large time window of valid data for
# the MB CPLD logic.
set spi_min_out_delay -1.500
set spi_max_out_delay 9.500
# Set output constraints for all ports.
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
top/x400/constraints/timing/x440_clocks.xdc
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Clock definition constraints for X440
#
###############################################################################
# MMCM-Related Clocks
#
# Note: Vivado will create generated clocks based on the default MMCM settings
# configured in the clocking wizard, but we are going to dynamically change
# those clocks, and so we need to provide worst-case values in here.
###############################################################################
# PLL Reference Clock (PRC) input. This goes from the LMK straight to the MMCM
# input, and is used to generate the internal PRC as well as RFDC/data clocks.
set pll_ref_clk_in_period 15.625
create_clock -name pll_ref_in_clk -period $pll_ref_clk_in_period [get_ports PLL_REFCLK_FPGA_P]
# Internal PLL Reference Clock (PRC). Used to derive data clocks. Constrain to
# the fastest possible clock rate supported in the driver.
set pll_ref_clk_period 15.625
create_clock -name pll_ref_clk \
-period $pll_ref_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT0]
###############################################################################
# Generated Clocks
###############################################################################
create_generated_clock -name sync_ref_clk \
-source [get_ports BASE_REFCLK_FPGA_P] \
-divide_by 2 [get_pins clock_div_5mhz/clk_out_reg/Q]
top/x400/constraints/timing/x440_clocks_1600.xdc
+20
View File
@@ -0,0 +1,20 @@
#
# Copyright 2023 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Clock definition constraints for X440 1600 type images
#
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
# and RFNoC. Maximum supported master clock rate is 2.048 Gsps @8SPC => 256 MHz.
set rfdc_data_clk_period 3.906
create_clock -name rfdc_r0_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
create_clock -name rfdc_r1_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
top/x400/constraints/timing/x440_clocks_400.xdc
+21
View File
@@ -0,0 +1,21 @@
#
# Copyright 2023 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Clock definition constraints for X440 400 type images
#
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
# and RFNoC. Maximum supported master clock rate is 500 Msps @8SPC => 62.5 MHz.
# Theoretical maximum converter rate is 4.096 GSps, so really, 512 Msps @ 8SPC => 64 MHz.
set rfdc_data_clk_period 15.625
create_clock -name rfdc_r0_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
create_clock -name rfdc_r1_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
top/x400/cpld/Makefile
+14 -1
View File
@@ -22,11 +22,14 @@
10M08_ID = "10M08SAU169I7G"
# Project directories
X440_DIR = $(abspath ./x440)
X410_DIR = $(abspath ./x410)
# Target specific variables
X410_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 PROJECT_DIR=$(X410_DIR) X410=1
X410_CPLD_10M08: DEFS = VARIANT_`echo $(10M08_ID) | cut -c1-5`=1 PROJECT_DIR=$(X410_DIR) X410=1
X440_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 PROJECT_DIR=$(X440_DIR) X440=1
X440_CPLD_10M08: DEFS = VARIANT_`echo $(10M08_ID) | cut -c1-5`=1 PROJECT_DIR=$(X440_DIR) X440=1
X410_CPLD_MFG_10M08: DEFS = VARIANT_`echo $(10M08_ID) | cut -c1-5`=1 MFG_SUPPORT=1 PROJECT_DIR=$(X410_DIR)
@@ -61,7 +64,7 @@ endif
##Supported Targets
##-----------------
all: X410_CPLD_10M04 X410_CPLD_10M08 ##(Default target)
all: X410_CPLD_10M04 X410_CPLD_10M08 X440_CPLD_10M04 X440_CPLD_10M08 ##(Default target)
##X410_CPLD_10M04: Motherboard CPLD targeted to 10M04SAU169I7G.
X410_CPLD_10M04:
@@ -73,6 +76,16 @@ X410_CPLD_10M08:
$(call quartus_build,$(10M08_ID),$(DEFS))
$(call post_build,"usrp_x410_cpld_`echo $(10M08_ID) | cut -c1-5 | tr A-Z a-z`")
##X440_CPLD_10M08: Motherboard CPLD targeted to 10M04SAU169I7G.
X440_CPLD_10M04:
$(call quartus_build,$(10M04_ID),$(DEFS))
$(call post_build,"usrp_x440_cpld_`echo $(10M04_ID) | cut -c1-5 | tr A-Z a-z`")
##X440_CPLD_10M08: Motherboard CPLD targeted to 10M08SAU169I7G.
X440_CPLD_10M08:
$(call quartus_build,$(10M08_ID),$(DEFS))
$(call post_build,"usrp_x440_cpld_`echo $(10M08_ID) | cut -c1-5 | tr A-Z a-z`")
X410_CPLD_IP: ##Build IPs only, needed for simulation.
@# Building only X410_CPLD_10M04 IP
$(call quartus_ip,$(10M04_ID),$(DEFS))
top/x400/cpld/common/pl_cpld_regs.v
+2
View File
@@ -47,6 +47,8 @@ module pl_cpld_regs #(
`ifdef X410
`include "../regmap/x410/constants_regmap_utils.vh"
`else
`include "../regmap/x440/constants_regmap_utils.vh"
`endif
`include "../regmap/pl_cpld_base_regmap_utils.vh"
`include "../../../../lib/rfnoc/core/ctrlport.vh"
top/x400/cpld/common/ps_cpld_regs.v
+2
View File
@@ -47,6 +47,8 @@ module ps_cpld_regs #(
);
`ifdef X410
`include "../regmap/x410/constants_regmap_utils.vh"
`else
`include "../regmap/x440/constants_regmap_utils.vh"
`endif
`include "../regmap/ps_cpld_base_regmap_utils.vh"
`include "../../../../lib/rfnoc/core/ctrlport.vh"
top/x400/cpld/ctrlport_to_jtag.v
-275
View File
@@ -1,275 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_to_jtag
//
// Description:
//
// This module wraps a JTAG master and provides a ControlPort slave
// interface.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers
// DEFAULT_PRESCALAR : Default clock divider to use
//
`default_nettype none
module ctrlport_to_jtag #(
parameter BASE_ADDRESS = 0,
parameter DEFAULT_PRESCALAR = 0
) (
//---------------------------------------------------------------------------
// ControlPort Slave
//---------------------------------------------------------------------------
input wire ctrlport_clk,
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status = 0,
output reg [31:0] s_ctrlport_resp_data = 0,
//---------------------------------------------------------------------------
// JTAG Signals
//---------------------------------------------------------------------------
output wire tck,
output wire tdi,
input wire tdo,
output wire tms
);
`include "../../../lib/rfnoc/core/ctrlport.vh"
`include "./regmap/jtag_regmap_utils.vh"
//---------------------------------------------------------------------------
// Local Registers
//---------------------------------------------------------------------------
reg [ TX_DATA_SIZE-1:0] tx_data_reg;
reg [ STB_DATA_SIZE-1:0] stb_data_reg;
reg [PRESCALAR_SIZE-1:0] prescalar_reg = DEFAULT_PRESCALAR;
reg [ LENGTH_SIZE-1:0] length_reg;
reg start_reg;
reg soft_rst_stb_reg;
//---------------------------------------------------------------------------
// Readback Signals from JTAG Master
//---------------------------------------------------------------------------
wire [31:0] rd_data;
wire ready;
//---------------------------------------------------------------------------
// Handling of CtrlPort
//---------------------------------------------------------------------------
localparam NUM_ADDRESSES = 32;
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
wire soft_rst_requested = (s_ctrlport_req_addr == BASE_ADDRESS + CONTROL) &&
(s_ctrlport_req_data[RESET] == 1'b1);
always @(posedge ctrlport_clk) begin
// Reset internal registers and responses
if (ctrlport_rst) begin
tx_data_reg <= {TX_DATA_SIZE {1'b0}};
stb_data_reg <= {STB_DATA_SIZE {1'b0}};
prescalar_reg <= DEFAULT_PRESCALAR;
length_reg <= {LENGTH_SIZE {1'b0}};
start_reg <= 1'b0;
soft_rst_stb_reg <= 1'b0;
s_ctrlport_resp_ack <= 1'b0;
end else begin
// Request independent default assignments
start_reg <= 1'b0;
soft_rst_stb_reg <= 1'b0; // self-clearing strobe
// Write requests
if (s_ctrlport_req_wr) begin
// Always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {CTRLPORT_DATA_W{1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
// Process write requests only in case ready is asserted because JTAG
// module requires these values to be stable when it is not ready.
//
// The one exception is when a soft-reset is requested to reset the
// bitq_fsm, in that case that is a valid write.
if (soft_rst_requested) begin
soft_rst_stb_reg <= 1'b1;
end else if (ready) begin
case (s_ctrlport_req_addr)
BASE_ADDRESS + TX_DATA: begin
tx_data_reg <= s_ctrlport_req_data;
end
BASE_ADDRESS + STB_DATA: begin
stb_data_reg <= s_ctrlport_req_data;
end
BASE_ADDRESS + CONTROL: begin
length_reg <= s_ctrlport_req_data[LENGTH_MSB:LENGTH];
prescalar_reg <= s_ctrlport_req_data[PRESCALAR_MSB:PRESCALAR];
// When the RESET bit is high, a soft-reset (i.e. no start strobe)
// must take place, which is handled by the default assignment.
// Otherwise, if the RESET bit is low, a start strobe should be
// issued, triggering a transaction.
start_reg <= (s_ctrlport_req_data[RESET] == 1'b0);
end
// Error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// Error in case ready is not asserted
end else begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
end
// Read requests
end else if (s_ctrlport_req_rd) begin
// Default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + RX_DATA: begin
s_ctrlport_resp_data <= rd_data;
end
BASE_ADDRESS + CONTROL: begin
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
s_ctrlport_resp_data[LENGTH_MSB:LENGTH] <= length_reg;
s_ctrlport_resp_data[PRESCALAR_MSB:PRESCALAR] <= prescalar_reg;
s_ctrlport_resp_data[READY] <= ready;
end
// Error on undefined address
default: begin
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// No request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
//---------------------------------------------------------------------------
// JTAG Master
//---------------------------------------------------------------------------
// bitq_fsm reset is asserted by either the ctrlport_rst or the soft-reset
// strobe triggered through software.
wire bitq_resetn = ~(ctrlport_rst | soft_rst_stb_reg);
bitq_fsm #(
.IDLE_VALUE (1'b0)
) jtag_master (
.clk (ctrlport_clk),
.rstn (bitq_resetn),
.prescalar (prescalar_reg),
.bit_clk (tck),
.bit_in (tdo),
.bit_out (tdi),
.bit_stb (tms),
.start (start_reg),
.ready (ready),
.len (length_reg),
.wr_data (tx_data_reg),
.stb_data (stb_data_reg),
.rd_data (rd_data)
);
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="JTAG_REGMAP" readablestrobes="false" markdown="true" generatevhdl="true" ettusguidelines="true">
//
// <group name="JTAG_REGS">
// <info>
// This register map is present for each JTAG module.
//
// Basic operation would be:
//
// - poll @.ready until asserted
// - write / read data
// - write @.CONTROL register along with @.reset deasserted to start a transaction
//
// For resetting the BITQ FSM, simply assert @.reset.
//
// This operation seems a little strange, but it is what the axi_bitq driver
// expects. This behavior has been implemented in previous products.
//
// </info>
//
// <register name="TX_DATA" readable="false" offset="0x00" size="32">
// <info>Data to be transmitted (TDI)</info>
// </register>
//
// <register name="STB_DATA" readable="false" offset="0x04" size="32">
// <info>Data to be transmitted (TMS)</info>
// </register>
//
// <register name="CONTROL" offset="0x08" size="32">
// <info>JTAG module status and control</info>
// <bitfield name="prescalar" range="7..0" initialvalue="true">
// <info>Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value.</info>
// </bitfield>
// <bitfield name="length" range="12..8">
// <info>(Number of bits - 1) to be transferred</info>
// </bitfield>
// <bitfield name="reset" readable="false" range="31">
// <info>When asserted ('1') a soft-reset for the bitq FSM is triggered,
// preventing any transactions to take place.
//
// Deassert this bit, along with values for @.prescalar and @.length
// to trigger a new transaction (start strobe).</info>
// </bitfield>
// <bitfield name="ready" writable="false" range="31">
// <info>Bitq FSM is ready for input (no data transmission in progress).</info>
// </bitfield>
// </register>
//
// <register name="RX_DATA" offset="0x0C" writable="false" size="32">
// <info>Received data (TDO)</info>
// </register>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/ctrlport_to_spi.v
-276
View File
@@ -1,276 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_to_spi
//
// Description:
//
// This module wraps a SPI master and provides a ControlPort interface.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers.
//
`default_nettype none
module ctrlport_to_spi #(
parameter BASE_ADDRESS = 0
) (
//---------------------------------------------------------------
// ControlPort Slave
//---------------------------------------------------------------
input wire ctrlport_clk,
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status = 0,
output reg [31:0] s_ctrlport_resp_data = 0,
//---------------------------------------------------------------
// SPI Signals
//---------------------------------------------------------------
output wire sclk,
output wire mosi,
output wire [15:0] ss,
input wire miso
);
`include "../../../lib/rfnoc/core/ctrlport.vh"
`include "./regmap/spi_regmap_utils.vh"
//---------------------------------------------------------------
// Translating CtrlPort <-> Wishbone
//---------------------------------------------------------------
reg wb_cyc_i; // Active bus cycle
reg wb_we_i = 1'b0; // Write access
reg [ 4:0] wb_adr_i = 5'b0;
reg [31:0] wb_dat_i = 32'b0;
wire wb_ack_o;
wire [31:0] wb_dat_o;
wire wb_err_o;
// Check for address to be in range [base_addr..base_addr+32)
localparam NUM_ADDRESSES = 32;
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
// Following chapter 3.2.3 (classic standard SINGLE WRITE cycle) of
// https://cdn.opencores.org/downloads/wbspec_b4.pdf
always @(posedge ctrlport_clk) begin
// Reset internal registers and responses
if (ctrlport_rst) begin
wb_cyc_i <= 1'b0;
s_ctrlport_resp_ack <= 1'b0;
end else begin
// Request independent default assignments
s_ctrlport_resp_ack <= 1'b0;
// Wait for ack on active bus transactions
if (wb_cyc_i) begin
if (wb_ack_o) begin
// End bus cycle and generate response
wb_cyc_i <= 1'b0;
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= wb_dat_o;
if (wb_err_o) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
end else begin
s_ctrlport_resp_status <= CTRL_STS_OKAY;
end
end
// Write requests
end else if (s_ctrlport_req_wr) begin
// Assume there is a valid address
wb_cyc_i <= 1'b1;
wb_we_i <= 1'b1;
wb_dat_i <= s_ctrlport_req_data;
case (s_ctrlport_req_addr)
BASE_ADDRESS + TX_DATA_LOW: begin
wb_adr_i <= 5'h00;
end
BASE_ADDRESS + TX_DATA_HIGH: begin
wb_adr_i <= 5'h04;
end
BASE_ADDRESS + CONTROL: begin
wb_adr_i <= 5'h10;
end
BASE_ADDRESS + CLOCK_DIVIDER: begin
wb_adr_i <= 5'h14;
end
BASE_ADDRESS + SLAVE_SELECT: begin
wb_adr_i <= 5'h18;
end
// Error on undefined address
default: begin
wb_cyc_i <= 1'b0;
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// Read requests
end else if (s_ctrlport_req_rd) begin
// Assume there is a valid address
wb_cyc_i <= 1'b1;
wb_we_i <= 1'b0;
case (s_ctrlport_req_addr)
BASE_ADDRESS + RX_DATA_LOW: begin
wb_adr_i <= 5'h00;
end
BASE_ADDRESS + RX_DATA_HIGH: begin
wb_adr_i <= 5'h04;
end
BASE_ADDRESS + CONTROL: begin
wb_adr_i <= 5'h10;
end
BASE_ADDRESS + CLOCK_DIVIDER: begin
wb_adr_i <= 5'h14;
end
BASE_ADDRESS + SLAVE_SELECT: begin
wb_adr_i <= 5'h18;
end
// Error on undefined address
default: begin
wb_cyc_i <= 1'b0;
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// No request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
//---------------------------------------------------------------
// SPI Master
//---------------------------------------------------------------
spi_top spi_master (
.wb_clk_i (ctrlport_clk),
.wb_rst_i (ctrlport_rst),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_sel_i (4'hF),
.wb_we_i (wb_we_i),
.wb_stb_i (wb_cyc_i),
.wb_cyc_i (wb_cyc_i),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.wb_int_o (),
.ss_pad_o (ss),
.sclk_pad_o (sclk),
.mosi_pad_o (mosi),
.miso_pad_i (miso)
);
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="SPI_REGMAP" readablestrobes="false" markdown="true" generatevhdl="true" ettusguidelines="true">
//
// <group name="SPI_REGS">
// <info>
// This register map is present for each SPI master.
//
// For information about the register content and the way to interact with the core see the
// <a href="https://opencores.org/websvn/filedetails?repname=spi&path=%2Fspi%2Ftrunk%2Fdoc%2Fspi.pdf" target="_blank">documentation</a>
// of the SPI master from opencores used internally.
//
// The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider.
// Only 64 bits of data are available via this register interface.
//
// For the different SPI modes use the following table to derive the bits in @.CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested.
//
//| CPOL | CPHA | TX_NEG | RX_NEG |
//| ------- | -------- | -------- | ------- |
//| 0 | 0 | 1 | 0 |
//| 0 | 1 | 0 | 1 |
//| 1 | 0 | 0 | 1 |
//| 1 | 1 | 1 | 0 |
// </info>
//
// <register name="RX_DATA_LOW" offset="0x00" writable="false" size="32">
// <info>Lower 32 bits of the received word. (RxWord[31:0])</info>
// </register>
//
// <register name="RX_DATA_HIGH" offset="0x04" writable="false" size="32">
// <info>Higher 32 bits of the received word. (RxWord[63:32])</info>
// </register>
//
// <register name="TX_DATA_LOW" offset="0x08" readable="false" size="32">
// <info>Lower 32 bits of the received word. (TxWord[31:0])</info>
// </register>
//
// <register name="TX_DATA_HIGH" offset="0x0C" readable="false" size="32">
// <info>Higher 32 bits of the received word. (TxWord[63:32])</info>
// </register>
//
// <register name="CONTROL" offset="0x10" size="32">
// <info>Control register</info>
// </register>
// <register name="CLOCK_DIVIDER" offset="0x14" size="8">
// <bitfield name="Divider" range="7..0">
// <info>
// Clock Divider.
// </info>
// </bitfield>
// </register>
// <register name="SLAVE_SELECT" offset="0x18" size="16">
// <bitfield name="SS" range="15..0">
// <info>
// Slave select.
// </info>
// </bitfield>
// </register>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/db_spi_shared_constants.sdc
-20
View File
@@ -1,20 +0,0 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
# Timing constants for the MB CPLD <-> DB CPLD SPI interface
#
# Delays are rounded to integer values which leave a slack of >1ns on each setup
# and hold path without requirement for adding hold delays (as reported
# by Quartus fitter report).
# The signal might change before the SCLK edge as the internal
# registers are driven by PLL reference clock rather than the SPI clock used
# for the port timing constaints.
set db_cpld_spi_max_out 14.000
set db_cpld_spi_min_out 2.000
set db_cpld_spi_max_in 2.000
set db_cpld_spi_min_in -2.000
top/x400/cpld/mb_cpld.sdc
-689
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@@ -1,689 +0,0 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
# Timing constraints for the X4xx's motherboard CPLD.
#
set_time_format -unit ns -decimal_places 3
#####################################################################
# General
#####################################################################
# For a couple of 3.3V interfaces the buffer SN74AVC4T774RSVR is used to
# increase the drive strength. For reuse we define the timings constants here.
# For direction A to B and B to A the maximum timing varies by 0.1 ns. Taking
# the maximum of both.
set buffer_prop_min 0.100
set buffer_prop_max 2.400
#####################################################################
# Main Clocks
#####################################################################
## Input clocks.
# Reliable clock: 100.0 MHz
set CLK_100_period 10.000
create_clock -name CLK_100 -period $CLK_100_period [get_ports CLK_100]
# internal PLL derived clock
derive_pll_clocks
# provide name for derived clocks
set CLK_250 [get_clocks {*clk[1]}]
# PLL output pins of the generated 50 MHz clock for internal processing
set clk50_period 20.000
set pll_clk_out_pin [get_pins {pll_inst|altpll_component|auto_generated|pll1|clk[0]}]
set clk250_period 4.000
# PLL reference clock: 64 MHz (maximum)
set prc_clock_period 15.625
create_clock -name PLL_REF_CLK -period $prc_clock_period [get_ports PLL_REF_CLK]
#####################################################################
# Timing exceptions
#####################################################################
## SPI slaves
# Delay path for all synchronizers is based on the period of the
# faster clock domain (50 MHz derived by the PLL from 100 MHz reliable clock).
set clk50_period [expr {$CLK_100_period * 2}]
set_max_delay -to [get_registers *synchronizer_false_path\|value\[0\]\[*\]] \
$clk50_period
# sclk data to CLK_100
set_max_delay -from [get_registers *spi_slave_async\|received_word\[*\]] \
-to [get_registers *spi_slave_async\|data_out\[*\]] \
$clk50_period
# PLL driven data to sclk
set_max_delay -from [get_clocks {pll_inst*}] \
-to [get_registers *spi_slave_async\|transmit_bits\[*\]] \
$clk50_period
#####################################################################
# JTAG to daughterboards
#####################################################################
# Use the worst-case board propagation delays.
# Assuming 170.0 ps/in and usage of X410 DB.
# Longest trace | Trace length | Trace delay
# TDI to DB 0 | 7.625 in | 1.296 ns
# --------------------------------------------
# JTAG parameters
# see https://www.intel.com/content/www/us/en/programmable/documentation/mcn1397700832153.html#mcn1399899915639
set db_jtag_board_delay 1.296
set db_jtag_setup 3.000
set db_jtag_hold 10.000
set db_jtag_clk_to_out 20.000
set db0_jtag_outputs [get_ports {DB_JTAG_TDI[0] DB_JTAG_TMS[0]}]
set db0_jtag_inputs [get_ports {DB_JTAG_TDO[0]}]
set db1_jtag_outputs [get_ports {DB_JTAG_TDI[1] DB_JTAG_TMS[1]}]
set db1_jtag_inputs [get_ports {DB_JTAG_TDO[1]}]
##### DB 0 #####
# generated jtag clock is at least divided by 4
# max JTAG clock rate = 20 MHz
# source clock rate = 50 MHz
# only even dividers -> minimum value = 4
set db0_jtag_clk_register [get_registers {ctrlport_to_jtag:db0_jtag|bitq_fsm:jtag_master|bitq_state.HIGH}]
create_generated_clock -source $pll_clk_out_pin \
-name db0_jtag_clk $db0_jtag_clk_register \
-divide_by 4
# see White Rabbit DAC for futher explanation
set_false_path -from $db0_jtag_clk_register -to $db0_jtag_clk_register
create_generated_clock \
-source $db0_jtag_clk_register \
-name db0_jtag_out_clk [get_ports {DB_JTAG_TCK[0]}]
set_output_delay -clock db0_jtag_out_clk \
-max [expr {$db_jtag_setup + $db_jtag_board_delay + $buffer_prop_max}] \
$db0_jtag_outputs
set_output_delay -clock db0_jtag_out_clk \
-min [expr {-$db_jtag_hold - $db_jtag_board_delay - $buffer_prop_min}] \
$db0_jtag_outputs
# data is driven on CPLD on falling edge, which is 2 clock cycles ahead
# of the latch edge
set_multicycle_path -setup -start -to $db0_jtag_outputs 2
set_multicycle_path -hold -start -to $db0_jtag_outputs 3
# maximum delay accounts for slow clock and data propagation as
# well as clock to out time
set_input_delay -clock_fall -clock db0_jtag_out_clk \
-max [expr {$db_jtag_clk_to_out + 2*$db_jtag_board_delay + 2*$buffer_prop_max}] \
$db0_jtag_inputs
# worst-case everything changes immediatelly
set_input_delay -clock_fall -clock db0_jtag_out_clk \
-min [expr {2*$buffer_prop_min}] \
$db0_jtag_inputs
set_multicycle_path -setup -end -from $db0_jtag_inputs 2
set_multicycle_path -hold -end -from $db0_jtag_inputs 3
##### DB 1 #####
# generated jtag clock is at least divided by 4
set db1_jtag_clk_register [get_registers {ctrlport_to_jtag:db1_jtag|bitq_fsm:jtag_master|bitq_state.HIGH}]
create_generated_clock -source $pll_clk_out_pin \
-name db1_jtag_clk $db1_jtag_clk_register \
-divide_by 4
# see White Rabbit DAC for futher explanation
set_false_path -from $db1_jtag_clk_register -to $db1_jtag_clk_register
create_generated_clock \
-source $db1_jtag_clk_register \
-name db1_jtag_out_clk [get_ports {DB_JTAG_TCK[1]}]
set_output_delay -clock db1_jtag_out_clk \
-max [expr {$db_jtag_setup + $db_jtag_board_delay + $buffer_prop_max}] \
$db1_jtag_outputs
set_output_delay -clock db1_jtag_out_clk \
-min [expr {-$db_jtag_hold - $db_jtag_board_delay - $buffer_prop_min}] \
$db1_jtag_outputs
set_multicycle_path -setup -start -to $db1_jtag_outputs 2
set_multicycle_path -hold -start -to $db1_jtag_outputs 3
# maximum delay accounts for slow clock and data propagation as
# well as clock to out time
set_input_delay -clock_fall -clock db1_jtag_out_clk \
-max [expr {$db_jtag_clk_to_out + 2*$db_jtag_board_delay + 2*$buffer_prop_max}] \
$db1_jtag_inputs
# ideally everything changes immediatelly
set_input_delay -clock_fall -clock db1_jtag_out_clk \
-min [expr {2*$buffer_prop_min}] \
$db1_jtag_inputs
set_multicycle_path -setup -end -from $db1_jtag_inputs 2
set_multicycle_path -hold -end -from $db1_jtag_inputs 3
#####################################################################
# FPGA <-> MB CPLD PL SPI interface
#####################################################################
# Create clock for the PL's SPI interface.
# PRC at least divided by 2 by the SPI Master on FPGA
set pl_sclk_period [expr {2 * $prc_clock_period}]
create_clock -name pl_sclk -period $pl_sclk_period [get_registers mb_cpld_sclk]
# The SPI PL master (on the FPGA) is designed as a system synchronous
# interface using PLL_REF_CLK.
# The FPGA output constraints are required to calculate the windows
# at CPLD of valid data
# They are derived iteratively from the FPGA design ensuring a large
# valid data period.
set pl_spi_fpga_min_out 0.000
set pl_spi_fpga_max_out 11.000
# The longest trace on the PL SPI interface is (sssuming 170.0 ps/in)
# Longest trace | Trace length | Trace delay
# CS_0 | 7.143 in | 1.215 ns
set pl_spi_board_delay 1.215
# This path also contains a level translator which has a typical
# switching time of 2.7 ns. Let's add a margin of 1 ns as worst
# case estimation
set pl_level_trans_delay 3.700
# CPLD and FPGA both use PLL reference clock from a common clock chip.
# The traces from that clock chip to the ICs are not length matched
# Assume a worst case clock difference of 0.5 ns at the IC inputs.
# There is no direction defined. The clock can arrive faster or slower
# on one IC.
set pl_clock_diff 0.500
set pl_slave_inputs [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS_N[*]}]
# calculate output delays back from capturing edge, add board delay, level translator and clock difference
set_input_delay -clock PLL_REF_CLK \
-max [expr {$prc_clock_period - $pl_spi_fpga_max_out + $pl_spi_board_delay + $pl_level_trans_delay + $pl_clock_diff}] \
$pl_slave_inputs
# Assuming data is going without any delay, clock is arriving early at CPLD.
# Negate minimum output delay as it is defined from the change to the start clock edge.
set_input_delay -clock PLL_REF_CLK \
-min [expr {- $pl_spi_fpga_min_out - $pl_clock_diff}] \
$pl_slave_inputs
# ensure large data valid window for the FPGA
# those values are used in the FPGA / DB CPLDs
# to calculate the input delay
# those values are maximum integer values to still meet timing
set pl_spi_cpld_min_out -1.000
set pl_spi_cpld_max_out 8.000
set pl_slave_outputs [get_ports {PL_CPLD_MISO}]
set_output_delay -clock PLL_REF_CLK -max $pl_spi_cpld_max_out $pl_slave_outputs
set_output_delay -clock PLL_REF_CLK -min $pl_spi_cpld_min_out $pl_slave_outputs
#####################################################################
# DB clock and reset
#####################################################################
# Output clocks for the daughterboards (SPI control)
create_generated_clock -source $pll_clk_out_pin \
-name db0_ref_clk [get_ports {DB_REF_CLK[0]}]
create_generated_clock -source $pll_clk_out_pin \
-name db1_ref_clk [get_ports {DB_REF_CLK[1]}]
# output reset within one clock period
set_max_delay -to [get_ports {DB_ARST[0] DB_ARST[1]}] $CLK_100_period
set_min_delay -to [get_ports {DB_ARST[0] DB_ARST[1]}] 0
#####################################################################
# DB SPI interfaces
#####################################################################
# --------- ----------------- -----------------
# FPGA | CS/SCLK/ | MB CPLD | | DB |
# |-- MOSI ->|--------> R1 ->|--------->| |
# SPI | | | | SPI |
# master |<- MISO --|<- R2 <--------|<---------| slave |
# --------- ----------------- -----------------
#
# The output clocks are derived from the PLL reference clock (PRC). The SCLK
# edges are aligned with the rising edge of PLL reference clock. There are two
# registers R1 and R2 in the SPI path between FPGA and DB.
# For the transmission of data from master to slave those registers are
# transparent. The overall reception is just delayed by 1 PLL reference clock
# cycle. In the other direction the MISO timing is different. The falling edge
# of SCLK is used for changing the data signals. The propagation of this signal
# to the DB is delayed by 1 PLL reference clock period because of register R1.
# The MISO signal is captured on the rising edge of SCLK on the FPGA. Register
# R2 in the MB CPLD changes the timing in a way that MISO has to be stable on
# the rising edge of PLL reference clock before the SCLK rising edge.
# Additionally a minimum of two PLL reference clock cycles are required for
# processing in the SPI slave. The number of processing cycles is denoted by n.
# Here is an example for n=2 and SPI bus with CPHA=0 and CPOL=0.
# Data is driven on the falling edge and captured on the rising edge of the
# clock signal. The falling edge of the SCLK@DB is delayed by a clock cycle
# because of R1. The FPGA as SPI master is capturing the data on the rising edge
# of SCLK. The register R2 on the MB CPLD is capturing the data one clock cycle
# earlier. Therefore MISO has to be stable one clock cycle earlier then the
# original SCLK at the MB CPLD input. The effective SCLK signal to use for the
# timing constraints of the DB therefore has a low period which is reduced by 2
# clock cycles (R1 + R2) of PLL reference clock. It still has the same period as
# SCLK. In this example the low period would be 2 PRC cycles and the high period
# would be 6 PRC cycles.
# The following waveform illustrates the timing for n=2. Based on the defined
# delays <XXXX> denotes the time when the signal is not stable.
#
# <--- R1 --->|<-------- n=2 -------->|<--- R2 --->
# PRC ___/-----\_____/-----\_____/-----\_____/-----\_____/----
# SCLK ---\_______________________________________________/----
# SCLK @ DB (ideal) ---------------\________________________________________
# SCLK @ DB (effective) ---------------\_______________________/----------------
# MOSI output @ MB CPLD --------------<XXXX>------------------------------------
# MISO input @ MB CPLD -------------------------<XXXX>-------------------------
# DB propagation and processing <--------->
# MOSI change @ FPGA ^
# MOSI change @ MB CPLD ^
# MISO capture @ MB CPLD ^
# MISO capture @ FPGA ^
#
# Although the delays are defined based on PLL reference clock the SPI bus clock
# must be divided by at least n+2, where n>1 to be functional. Increase n in
# case the DB propagation and processing time does not fit into n PLL reference
# clock cycles taking the delays from below into account (see waveform above).
# Make sure you defined the SPI bus clock frequency for the slave to n*PLL clock
# period (effective SPI clock). Set the required SPI DB clock divider on the
# FPGA before starting data transfer.
#
# The constants for this interface are defined in db_spi_shared_constants.sdc
#### DB 0 ####
create_generated_clock -source [get_ports {PLL_REF_CLK}] \
-name db0_ctrl_clk_int [get_registers {DB_CTRL_SCLK[0]~reg0}]
create_generated_clock -source [get_registers {DB_CTRL_SCLK[0]~reg0}] \
-name db0_ctrl_clk [get_ports {DB_CTRL_SCLK[0]}]
set db0_ctrl_outputs [get_ports {DB_CTRL_MOSI[0] DB_CTRL_CS_N[0]}]
set_output_delay -clock db0_ctrl_clk -max $db_cpld_spi_max_out $db0_ctrl_outputs
set_output_delay -clock db0_ctrl_clk -min $db_cpld_spi_min_out $db0_ctrl_outputs
set db0_ctrl_inputs [get_ports {DB_CTRL_MISO[0]}]
set_input_delay -clock db0_ctrl_clk -max $db_cpld_spi_max_in $db0_ctrl_inputs
set_input_delay -clock db0_ctrl_clk -min $db_cpld_spi_min_in $db0_ctrl_inputs
#### DB 1 ####
create_generated_clock -source [get_ports {PLL_REF_CLK}] \
-name db1_ctrl_clk_int [get_registers {DB_CTRL_SCLK[1]~reg0}]
create_generated_clock -source [get_registers {DB_CTRL_SCLK[1]~reg0}] \
-name db1_ctrl_clk [get_ports DB_CTRL_SCLK[1]]
set db1_ctrl_outputs [get_ports {DB_CTRL_MOSI[1] DB_CTRL_CS_N[1]}]
set_output_delay -clock db1_ctrl_clk -max $db_cpld_spi_max_out $db1_ctrl_outputs
set_output_delay -clock db1_ctrl_clk -min $db_cpld_spi_min_out $db1_ctrl_outputs
set db1_ctrl_inputs [get_ports {DB_CTRL_MISO[1]}]
set_input_delay -clock db1_ctrl_clk -max $db_cpld_spi_max_in $db1_ctrl_inputs
set_input_delay -clock db1_ctrl_clk -min $db_cpld_spi_min_in $db1_ctrl_inputs
#####################################################################
# Power supply clocks, LEDs, DIO direction
#####################################################################
# Change all output signals in this section within one clock period of the
# driving clocks.
# Power supply clocks
set power_supply_clocks_outputs [get_ports {PWR_SUPPLY_CLK_*}]
set_min_delay -to $power_supply_clocks_outputs 0
set_max_delay -to $power_supply_clocks_outputs $CLK_100_period
# LED signals
set led_outputs [get_ports {QSFP0_LED_ACTIVE[*] QSFP0_LED_LINK[*] \
QSFP1_LED_ACTIVE[*] QSFP1_LED_LINK[*]}]
set_min_delay -to $led_outputs 0
set_max_delay -to $led_outputs $prc_clock_period
# DIO direction
set dio_outputs [get_ports {DIO_DIRECTION_A[*] DIO_DIRECTION_B[*]}]
set_min_delay -to $dio_outputs 0
set_max_delay -to $dio_outputs $clk50_period
# Power control
set pwr_ctrl_outputs [get_ports {IPASS_POWER_DISABLE PWR_EN_5V_OSC_100 PWR_EN_5V_OSC_122_88}]
set_min_delay -to $pwr_ctrl_outputs 0
set_max_delay -to $pwr_ctrl_outputs $clk50_period
# Power fault inputs
# Virtual clocks for constraining inputs. Using an odd clock period to
# make sure any uncovered paths will result in timing errors due to short setup
# or hold path.
set power_fault_inputs [get_ports {IPASS_POWER_EN_FAULT[*]}]
create_clock -name virtual_async_in_clk -period 4.567
set_input_delay -clock virtual_async_in_clk 0 $power_fault_inputs
#####################################################################
# FPGA <-> MB CPLD PS SPI interface
#####################################################################
# Assume the PS SPI clock is maximum 5 MHz.
# It is driven from another source and provided with the data.
set ps_sclk_period 200.000
create_clock -name ps_sclk -period $ps_sclk_period [get_ports PS_CPLD_SCLK]
# The SPI PS master (on the FPGA) is wired through the MIO (Multiplexed I/O)
# pins, meaning that the timing characteristics of the interface come from
# the controller itself (i.e. no timed routing through PL).
# Based on the SPI master controller specification (DS925: Table 48),
# one may define the min/max input/output delay constraints.
set ps_spi_tco_min -2.000
set ps_spi_tco_max 5.000
set ps_spi_miso_setup -2.000
set ps_spi_miso_hold [expr {0.3 * $ps_sclk_period}]
# Use the worst-case board propagation delays.
# Assuming 170.0 ps/in.
# Longest trace | Trace length | Trace delay
# CS0_n | 4.735 in | 0.805 ns
# --------------------------------------------
set ps_spi_board_delay 0.805
set ps_slave_inputs [get_ports {PS_CPLD_MOSI PS_CPLD_CS_N[*]}]
# clock is immediately available, data is taking maximum time
# SPI data in CPOL=CPHA=1 is driven on the falling sclk edge
set ps_sclk_max_in_delay [expr {$ps_spi_tco_max + $ps_spi_board_delay}]
set_input_delay -clock ps_sclk -clock_fall \
-max $ps_sclk_max_in_delay \
$ps_slave_inputs
# fast data and clock delayed (reducing data delay)
set_input_delay -clock ps_sclk -clock_fall \
-min [expr {$ps_spi_tco_min - $ps_spi_board_delay}] \
$ps_slave_inputs
set ps_slave_outputs [get_ports {PS_CPLD_MISO}]
# use only half the frequency because falling edge is driving data
set_output_delay -clock ps_sclk \
-max [expr {$ps_spi_miso_setup + 2*$ps_spi_board_delay}] \
$ps_slave_outputs
# use hold requirement only as clock and data propagation further
# delay the signal
set_output_delay -clock ps_sclk \
-min [expr {-$ps_spi_miso_hold}] \
$ps_slave_outputs
# Chip select signals are captured for binary decoding in 250 MHz clock domain.
# To be able to specify a maximum delay for the data path only a second set of
# input delays is added to the root clock of the 250 MHz domain.
set_input_delay -add_delay -clock CLK_100 0 [get_ports {PS_CPLD_CS_N[*]}]
# Declare paths between the 2 clock domains as false paths
set_false_path -from [get_clocks {CLK_100}] -to [get_ports {PS_CPLD_MISO}]
set_false_path -from [get_clocks {ps_sclk}] -to [get_registers {synchronizer:ps_spi_input_sync_inst*}]
# Specify maximum data path delay
set_max_delay -from [get_ports {PS_CPLD_CS_N[*]}] -to $CLK_250 $clk250_period
#####################################################################
# MB CPLD PS SPI passthrough
#####################################################################
###### Binary CS decoding ######
# The CS outputs for the external SPI slaves are driven from a 250 MHz clock to
# ensure glitch free switching after binary encoding. Additionally those signals
# have to meet the setup and hold requirements of the SPI slaves operating at
# ps_sclk (5 MHz). CS lines typically are asserted half a clock period of sclk
# before any active edge of sclk. The constraints below are using multi-cycle
# paths to provide the placer with information about the clock multiplier from
# ps_sclk to 250 MHz. Furthermore they incorporate the time required for
# decoding by lowering the clock multiplier as shown in the waveform below
# (multiplier is not shown correctly).
#
# ps_sclk -\__________________________________________________/--------
# 250 MHz _/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\-
# CS @ CPLD input X>--------------- stable ------------------------------------
# CS @ CPLD output ---------<XXXXXXX>-------------- stable ---------------------
# |<----->| min decoding delay
# |<----->| change window
# --------------->| SPI slave hold requirement
# SPI slave setup requirement |<-------------------------------->|
#
# Get port to apply the multi-cycle constraint.
set binary_cs_ports [get_ports {LMK32_CS_N TPM_CS_N PHASE_DAC_CS_N DB_CALEEPROM_CS_N[*] CLK_DB_CS_N}]
# Determine number of full 250 MHz periods within half a period of ps_sclk.
set ps_spi_clock_divider [expr {int($ps_sclk_period/$clk250_period/2)}]
# Setup multi-cycle accounts for
# - one clock cycle data path delay from port to first register stage
# - one clock cycle to resolve meta-stability
# - up to 3 register stages internally (port to ps_cpld_cs_n_shift3)
# - one output register stage (registers on each $binary_cs_ports)
# Static timing analysis will take the data path from register to output port
# into account.
# The number of 250 MHz periods is reduced by a total of 7 clock cycles (listed
# above) to match the SPI slave setup requirement time shown in the waveform
# above. The slave's setup time in ps_sclk domain is specified below for each
# individual slave.
set ps_spi_setup_multicycle [expr {$ps_spi_clock_divider - 7}]
set_multicycle_path -setup -start -to $binary_cs_ports $ps_spi_setup_multicycle
# Hold multicycle accounts for
# - min 2 synchronization register stages internally (ps_cpld_cs_n_shift2)
# (= min one clock cycle delay as data could arrive just before setup
# requirement of first register stages assuming no data delay)
# - one output register stage
# Static timing analysis will take the data path from register to output port
# into account.
# As the clock edge for hold analysis is shifted with the setup edge the number
# of multi cycles has to be increased by this amount of cycles to get back to
# the falling edge of ps_sclk. Furthermore CS lines are released one half
# ps_sclk period after the last data transfer. So hold delay is increased by an
# additional half clock cycle.
set ps_spi_hold_multicycle [expr {$ps_spi_clock_divider + $ps_spi_setup_multicycle - 2}]
set_multicycle_path -hold -start -to $binary_cs_ports $ps_spi_hold_multicycle
###### local SPI slave ######
# The chip select path for the MB CPLD itself is driven in the 250 MHz clock
# domain and captured by registers operating at ps_sclk. Therefore setting the
# path as false path preventing the placer from adding additional routing delay
# to ensure hold timing. The setup path is limited to a maximum extend of one
# clock period. As this path crosses clock domains clock propagation is included
# in this path during static timing analysis. The TCL analysis in
# scripts/ps_cs_analysis.tcl ensures a maximum value for data excluding the
# clocking network.
set_false_path -from [get_registers {ps_spi_cs_n_decoded[0]}] -hold
set_max_delay -from [get_registers {ps_spi_cs_n_decoded[0]}] $clk250_period
###### LMK04832 ######
create_generated_clock -source [get_ports PS_CPLD_SCLK] \
-name lmk_spi_sclk [get_ports LMK32_SCLK]
# Use the worst-case board propagation delays.
# Assuming 170.0 ps/in.
# Longest trace | Trace length | Trace delay
# LMK32_SCLK | 8.259 in | 1.404 ns
# --------------------------------------------
set lmk_board_delay 1.404
# setup and hold dominated by CS <-> SCK relationship
set lmk_setup 20.000
set lmk_hold 20.000
set lmk_tco_max 60.000
set lmk_outputs [get_ports {LMK32_MOSI LMK32_CS_N}]
set_output_delay -clock lmk_spi_sclk \
-max [expr {$lmk_setup + $lmk_board_delay + $buffer_prop_max}] \
$lmk_outputs
set_output_delay -clock lmk_spi_sclk \
-min [expr {-$lmk_hold - $lmk_board_delay - $buffer_prop_min}] \
$lmk_outputs
set lmk_inputs [get_ports {LMK32_MISO}]
set_input_delay -clock lmk_spi_sclk -clock_fall \
-max [expr {$lmk_tco_max + 2*$lmk_board_delay + 2*$buffer_prop_max}] \
$lmk_inputs
set_input_delay -clock lmk_spi_sclk -clock_fall \
-min [expr {2*$buffer_prop_min}] \
$lmk_inputs
###### Phase DAC ######
create_generated_clock -source [get_ports PS_CPLD_SCLK] \
-name phase_dac_spi_sclk [get_ports PHASE_DAC_SCLK]
# Use the worst-case board propagation delays.
# Assuming 170.0 ps/in.
# Longest trace | Trace length | Trace delay
# SpiDCs3v3_n | 8.322 in | 1.415 ns
# --------------------------------------------
set phase_dac_board_delay 1.415
#setup dominated by SYNC signal
set phase_dac_setup 13.000
set phase_dac_hold 5.000
# device captures data on falling clock edge (CPOL = 1)
# constraining it as it would be like all the other SPI modules
# PS SPI master is responsible for changing SPI mode when talking
# to this device
set phase_dac_outputs [get_ports {PHASE_DAC_MOSI PHASE_DAC_CS_N}]
set_output_delay -clock phase_dac_spi_sclk -clock_fall \
-max [expr {$phase_dac_setup + $phase_dac_board_delay}] \
$phase_dac_outputs
set_output_delay -clock phase_dac_spi_sclk -clock_fall \
-min [expr {-$phase_dac_hold - $phase_dac_board_delay}] \
$phase_dac_outputs
###### TPM ######
create_generated_clock -source [get_ports PS_CPLD_SCLK] \
-name tpm_spi_sclk [get_ports TPM_SCLK]
# Use the worst-case board propagation delays.
# Assuming 170.0 ps/in.
# Longest trace | Trace length | Trace delay
# TPM_CS_n | 1.128 in | 0.196 ns
# --------------------------------------------
set tpm_board_delay 0.196
#tco dominated by NSS signal
set tpm_setup 5.000
set tpm_hold 5.000
set tpm_tco_max 25.000
set tpm_outputs [get_ports {TPM_MOSI TPM_CS_N}]
set_output_delay -clock tpm_spi_sclk \
-max [expr {$tpm_setup + $tpm_board_delay}] \
$tpm_outputs
set_output_delay -clock tpm_spi_sclk \
-min [expr {-$tpm_hold - $tpm_board_delay}] \
$tpm_outputs
set tpm_inputs [get_ports {TPM_MISO}]
set_input_delay -clock tpm_spi_sclk -clock_fall \
-max [expr {$tpm_tco_max + 2*$tpm_board_delay}] \
$tpm_inputs
set_input_delay -clock tpm_spi_sclk -clock_fall \
-min 0 \
$tpm_inputs
###### DB Calibration EEPROM ######
# Use worst case board propagation delays to estimate input and output
# timing. The longest path assuming 170 ps/in is:
# db0_caleeprom_spi_cs_n | 4.387 in | 0.746 ns
set eeprom_board_prop_delay 0.746
# Within the path to the EEPROM on the DB there is a level-transistor.
# The maximum propagation delays are 0.1..3.3 ns to the DB and 3.7 ns from the DB.
set eeprom_lvl_trans_to_db_delay_min 0.1
set eeprom_lvl_trans_to_db_delay_max 3.3
set eeprom_lvl_trans_from_db_delay_max 3.7
# Data in setup and hold times of the EEPROM are 5ns (based on the
# CS_N setup and hold times).
set db_eeprom_setup 5
set db_eeprom_hold 5
# Ouput valid from SCK is min 0 ns and max 8 ns.
set db_eeprom_output_valid 8
# max out path assuming clock delay is 0 and data delay is maximum value
set eeprom_max_out [expr {$eeprom_board_prop_delay + $eeprom_lvl_trans_to_db_delay_max + $db_eeprom_setup}]
# min out path assuming clock delay is maximal and data delay is 0
set eeprom_min_out [expr {-($eeprom_board_prop_delay + $eeprom_lvl_trans_to_db_delay_min + $db_eeprom_hold)}]
# board propagation to eeprom and back + lvl_translator back and forth + clock to data on eeprom
set eeprom_max_in [expr {$eeprom_board_prop_delay*2 + $eeprom_lvl_trans_to_db_delay_max + $eeprom_lvl_trans_from_db_delay_max + $db_eeprom_output_valid}]
# assuming no delay for everything
set eeprom_min_in 0
### DB 0
create_generated_clock -source [get_ports PS_CPLD_SCLK] \
-name db0_eeprom_clk [get_ports {DB_CALEEPROM_SCLK[0]}]
set db0_eeprom_outputs [get_ports {DB_CALEEPROM_MOSI[0] DB_CALEEPROM_CS_N[0]}]
set_output_delay -clock db0_eeprom_clk -max $eeprom_max_out $db0_eeprom_outputs
set_output_delay -clock db0_eeprom_clk -min $eeprom_min_out $db0_eeprom_outputs
set db0_eeprom_inputs [get_ports {DB_CALEEPROM_MISO[0]}]
# data is changed on the falling edge
set_input_delay -clock db0_eeprom_clk -clock_fall -max $eeprom_max_in $db0_eeprom_inputs
set_input_delay -clock db0_eeprom_clk -clock_fall -min $eeprom_min_in $db0_eeprom_inputs
### DB 1
create_generated_clock -source [get_ports PS_CPLD_SCLK] \
-name db1_eeprom_clk [get_ports {DB_CALEEPROM_SCLK[1]}]
set db1_eeprom_outputs [get_ports {DB_CALEEPROM_MOSI[1] DB_CALEEPROM_CS_N[1]}]
set_output_delay -clock db1_eeprom_clk -max $eeprom_max_out $db1_eeprom_outputs
set_output_delay -clock db1_eeprom_clk -min $eeprom_min_out $db1_eeprom_outputs
set db1_eeprom_inputs [get_ports {DB_CALEEPROM_MISO[1]}]
# data is changed on the falling edge
set_input_delay -clock db1_eeprom_clk -clock_fall -max $eeprom_max_in $db1_eeprom_inputs
set_input_delay -clock db1_eeprom_clk -clock_fall -min $eeprom_min_in $db1_eeprom_inputs
#### Clocking AUX board SPI interface ####
# Rev B clocking aux board uses a LMK05318 connected to this interface
# Using its timing for this interface.
create_generated_clock -source [get_ports PS_CPLD_SCLK] \
-name clk_db_clk_out [get_ports CLK_DB_SCLK]
set clk_db_setup 10.000
set clk_db_hold 10.000
set clk_db_tco_max 20.000
# Just a worst case assumption based on 2 times the MB trace length CLK_DB_MOSI.
# The multiplier 2 accounts for any traces on the CLK AUX board.
set clk_db_board_delay 4.000
set clk_db_outputs [get_ports {CLK_DB_CS_N CLK_DB_MOSI}]
# Output signals have to stable for max setup and propagation time. Clock delay
# to device is expected to be 0 in this equation.
set_output_delay -clock clk_db_clk_out \
-max [expr {$clk_db_setup + $clk_db_board_delay + $buffer_prop_max}] $clk_db_outputs
# The min output delay is comprised of:
# - device required hold time ($clk_db_hold)
# - max clock propagation delay ($clk_db_board_delay)
# - min data propagation time (0)
# All terms have to be negated as min output delay is defined in opposite
# direction (positive into the past).
set_output_delay -clock clk_db_clk_out \
-min [expr {-$clk_db_hold - $clk_db_board_delay - $buffer_prop_min}] $clk_db_outputs
set clk_db_inputs [get_ports {CLK_DB_MISO}]
# Max delay calculated is based on
# - max clock delay ($clk_db_board_delay)
# - max clock to out LMK ($clk_db_tco_max)
# - max data path delay ($clk_db_board_delay)
set_input_delay -clock clk_db_clk_out -clock_fall \
-max [expr {$clk_db_tco_max + $clk_db_board_delay*2 + 2*$buffer_prop_max}] $clk_db_inputs
# Min delay assumes clock propagates to device and data propagates to CPLD
# without any delays.
set_input_delay -clock clk_db_clk_out -clock_fall \
-min [expr {2*$buffer_prop_min}] $clk_db_inputs
#####################################################################
# PCIe signals
#####################################################################
# I²C bus is operated at 100kHz. Constraints would not improve timing
# significantly (typically in the order of nanoseconds, which is negligible
# given the SCL period of 10 us).
# PCI-Express reset signal is not timing critical as it is received
# asynchronously by the FPGA.
set_false_path -to [get_ports {IPASS_SDA[0] IPASS_SCL[0] PCIE_RESET}]
# I²C inputs are only consumed by synchronizers.
# Add exceptions for all known consumers.
set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|I2cTop:CableI2cx|I2cMonitor:I2cMonitorx|I2cFilter:I2cFilterx|I2cSigFilter:SclFilterx|fSig_ms}]
set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|I2cTop:CableI2cx|I2cMonitor:I2cMonitorx|I2cFilter:I2cFilterx|I2cSigFilter:SdaFilterx|fSig_ms}]
set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|StuckBusFixer:StuckBusFixerx|DoubleSyncSlAsyncIn:DoubleSclkx|DoubleSyncAsyncInBase:DoubleSyncAsyncInBasex|DFlopAsync:oSig_msx|lpm_ff:LPM_FFx|dffs[0]}]
set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|StuckBusFixer:StuckBusFixerx|DoubleSyncSlAsyncIn:DoubleSdax|DoubleSyncAsyncInBase:DoubleSyncAsyncInBasex|DFlopAsync:oSig_msx|lpm_ff:LPM_FFx|dffs[0]}]
#####################################################################
# Known Issue of On-Chip Flash
#####################################################################
# see https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2016/warning--332060---node---alteraonchipflash-onchipflash-alteraonc.html
create_generated_clock -name flash_se_neg_reg \
-source [get_pins { on_chip_flash:flash_inst|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk }] \
-divide_by 2 [get_pins { on_chip_flash:flash_inst|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q } ]
#####################################################################
# Clock uncertainty
#####################################################################
# Assign some uncertainty to all clocks
set clock_uncertainty 0.150
set_clock_uncertainty -to [get_clocks *] $clock_uncertainty
derive_clock_uncertainty
top/x400/cpld/pl_cpld_regs.v
-297
View File
@@ -1,297 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: pl_cpld_regs
//
// Description:
//
// Basic Registers to inform software about version and capabilities.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers
//
`default_nettype none
module pl_cpld_regs #(
parameter BASE_ADDRESS = 0
) (
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
// QSFP LEDs
// Port 0
output wire [ 3:0] qsfp0_led_active,
output wire [ 3:0] qsfp0_led_link,
// Port 1
output wire [ 3:0] qsfp1_led_active,
output wire [ 3:0] qsfp1_led_link,
// iPass status
output wire [ 1:0] ipass_cable_present
);
`include "regmap/constants_regmap_utils.vh"
`include "regmap/pl_cpld_base_regmap_utils.vh"
`include "../../../lib/rfnoc/core/ctrlport.vh"
//---------------------------------------------------------------------------
// Address Calculation
//---------------------------------------------------------------------------
localparam NUM_ADDRESSES = 64;
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
//---------------------------------------------------------------------------
// Internal Registers
//---------------------------------------------------------------------------
reg [SCRATCH_REGISTER_SIZE-1:0] scratch_reg;
reg [LED_REGISTER_SIZE-1:0] led_reg;
reg [CABLE_PRESENT_REG_SIZE-1:0] ipass_reg;
//---------------------------------------------------------------------------
// Assign Outputs
//---------------------------------------------------------------------------
assign qsfp0_led_active = led_reg[QSFP0_LED_ACTIVE+:QSFP0_LED_ACTIVE_SIZE];
assign qsfp0_led_link = led_reg[QSFP0_LED_LINK+:QSFP0_LED_LINK_SIZE];
assign qsfp1_led_active = led_reg[QSFP1_LED_ACTIVE+:QSFP1_LED_ACTIVE_SIZE];
assign qsfp1_led_link = led_reg[QSFP1_LED_LINK+:QSFP1_LED_LINK_SIZE];
assign ipass_cable_present = ipass_reg;
//---------------------------------------------------------------------------
// Handling of ControlPort Requests
//---------------------------------------------------------------------------
always @(posedge ctrlport_clk) begin
// Reset internal registers and responses
if (ctrlport_rst) begin
scratch_reg <= 0;
led_reg <= 0;
ipass_reg <= 0;
s_ctrlport_resp_ack <= 1'b0;
// Write requests
end else if (s_ctrlport_req_wr) begin
// Always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + SCRATCH_REGISTER:
scratch_reg <= s_ctrlport_req_data;
BASE_ADDRESS + LED_REGISTER:
led_reg <= s_ctrlport_req_data[LED_REGISTER_SIZE-1:0];
BASE_ADDRESS + CABLE_PRESENT_REG: begin
ipass_reg[0] <= s_ctrlport_req_data[IPASS0_CABLE_PRESENT];
ipass_reg[1] <= s_ctrlport_req_data[IPASS1_CABLE_PRESENT];
end
// Error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// Read request
end else if (s_ctrlport_req_rd) begin
// Default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + SIGNATURE_REGISTER:
s_ctrlport_resp_data <= PL_CPLD_SIGNATURE;
BASE_ADDRESS + REVISION_REGISTER:
s_ctrlport_resp_data <= CPLD_REVISION;
BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER:
s_ctrlport_resp_data <= OLDEST_CPLD_REVISION;
BASE_ADDRESS + SCRATCH_REGISTER:
s_ctrlport_resp_data <= scratch_reg;
BASE_ADDRESS + GIT_HASH_REGISTER:
`ifdef GIT_HASH
s_ctrlport_resp_data <= `GIT_HASH;
`else
s_ctrlport_resp_data <= 32'hDEADBEEF;
`endif
BASE_ADDRESS + LED_REGISTER:
s_ctrlport_resp_data <= {{(CTRLPORT_DATA_W - LED_REGISTER_SIZE){1'b0}}, led_reg};
BASE_ADDRESS + CABLE_PRESENT_REG: begin
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
s_ctrlport_resp_data[IPASS0_CABLE_PRESENT] <= ipass_reg[0];
s_ctrlport_resp_data[IPASS1_CABLE_PRESENT] <= ipass_reg[1];
end
// Error on undefined address
default: begin
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// No request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="PL_CPLD_BASE_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="PL_CPLD_BASE_REGS">
// <info>
// Basic registers containing version and capabilities information.
// </info>
//
// <register name="SIGNATURE_REGISTER" offset="0x00" writable="false" size="32">
// <info>Contains the product's signature.</info>
// <bitfield name="PRODUCT_SIGNATURE" range="31..0">
// <info>Fixed value PL_CPLD_SIGNATURE of @.CONSTANTS_REGMAP</info>
// </bitfield>
// </register>
//
// <register name="REVISION_REGISTER" offset="0x04" writable="false" size="32">
// <info>Contains the CPLD revision (see CPLD_REVISION of @.CONSTANTS_REGMAP)</info>
// <bitfield name="REVISION_HH" range="7..0">
// <info>Contains revision hour code.</info>
// </bitfield>
// <bitfield name="REVISION_DD" range="15..8">
// <info>Contains revision day code.</info>
// </bitfield>
// <bitfield name="REVISION_MM" range="23..16">
// <info>Contains revision month code.</info>
// </bitfield>
// <bitfield name="REVISION_YY" range="31..24">
// <info>Contains revision year code.</info>
// </bitfield>
// </register>
//
// <register name="OLDEST_COMPATIBLE_REVISION_REGISTER" offset="0x08" writable="false" size="32">
// <info>
// This register returns (in YYMMDDHH format) the oldest revision
// that is still compatible with this one. Compatible means that
// registers or register bits may have been added, but not
// modified or deleted (see OLDEST_CPLD_REVISION of @.CONSTANTS_REGMAP).
// </info>
// <bitfield name="OLD_REVISION_HH" range="7..0">
// <info>Contains revision hour code.</info>
// </bitfield>
// <bitfield name="OLD_REVISION_DD" range="15..8">
// <info>Contains revision day code.</info>
// </bitfield>
// <bitfield name="OLD_REVISION_MM" range="23..16">
// <info>Contains revision month code.</info>
// </bitfield>
// <bitfield name="OLD_REVISION_YY" range="31..24">
// <info>Contains revision year code.</info>
// </bitfield>
// </register>
//
// <register name="SCRATCH_REGISTER" offset="0x0C" size="32">
// <info>Read/write register for general software use.</info>
// </register>
//
// <register name="GIT_HASH_REGISTER" offset="0x10" size="32" writable="false">
// <info>
// Git hash of commit used to build this image.{br}
// Value equals 0xDEADBEEF if the git hash was not used during synthesis.
// </info>
// <bitfield name="GIT_CLEAN" range="31..28">
// <info>
// 0x0 in case the git status was clean{br}
// 0xF in case there were uncommitted changes
// </info>
// </bitfield>
// <bitfield name="GIT_HASH" range="27..0">
// <info>7 hex digit hash code of the commit</info>
// </bitfield>
// </register>
// </group>
//
// <group name="MB_CPLD_LED_REGS">
// <info>
// Register Map to control QSFP LEDs.
// </info>
// <register name="LED_REGISTER" offset="0x20" size="16">
// <info>
// Provides to the LEDs of the QSFP ports.
// Write access will directly change the LED status.
// The LED lights up if the corresponding bit is set.
// </info>
// <bitfield name="QSFP0_LED_LINK" range="3..0">
// <info>Link LEDs of QSFP port 0</info>
// </bitfield>
// <bitfield name="QSFP0_LED_ACTIVE" range="7..4">
// <info>Active LEDs of QSFP port 0</info>
// </bitfield>
// <bitfield name="QSFP1_LED_LINK" range="11..8">
// <info>Link LEDs of QSFP port 1</info>
// </bitfield>
// <bitfield name="QSFP1_LED_ACTIVE" range="15..12">
// <info>Active LEDs of QSFP port 1</info>
// </bitfield>
// </register>
// </group>
//
// <group name="PL_CMI_REGS">
// <info>
// Cable present status register.
// </info>
// <register name="CABLE_PRESENT_REG" offset="0x30" size="2">
// <info>
// Information from FPGA about the cable present status.
// </info>
// <bitfield name="IPASS0_CABLE_PRESENT" range="0">
// <info>Set to 1 if cable present in iPass 0 connector.</info>
// </bitfield>
// <bitfield name="IPASS1_CABLE_PRESENT" range="1">
// <info>Set to 1 if cable present in iPass 1 connector.</info>
// </bitfield>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/ps_cpld_regs.v
-404
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@@ -1,404 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ps_cpld_regs
//
// Description:
//
// Basic registers to inform software about version and capabilities.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers
//
`default_nettype none
module ps_cpld_regs #(
parameter BASE_ADDRESS = 0
) (
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
// Configuration outputs
output reg [ 1:0] db_clk_enable = 2'b00,
output reg [ 1:0] db_reset = 2'b11,
output reg pll_ref_clk_enable = 1'b0,
output reg [11:0] dio_direction_a = 12'b0,
output reg [11:0] dio_direction_b = 12'b0,
output reg [39:0] serial_num = 40'b0,
output reg cmi_ready = 1'b0,
input wire cmi_other_side_detected
);
`include "regmap/constants_regmap_utils.vh"
`include "regmap/ps_cpld_base_regmap_utils.vh"
`include "../../../lib/rfnoc/core/ctrlport.vh"
//-----------------------------------------------------------------------------
// Address Calculation
//-----------------------------------------------------------------------------
localparam NUM_ADDRESSES = 64;
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
//-----------------------------------------------------------------------------
// Internal Registers
//-----------------------------------------------------------------------------
reg [SCRATCH_REGISTER_SIZE-1:0] scratch_reg;
//-----------------------------------------------------------------------------
// Handling of ControlPort Requests
//-----------------------------------------------------------------------------
always @(posedge ctrlport_clk) begin
// Reset internal registers and responses
if (ctrlport_rst) begin
scratch_reg <= 0;
db_clk_enable <= 2'b00;
db_reset <= 2'b11;
pll_ref_clk_enable <= 1'b0;
dio_direction_a <= {DIO_DIRECTION_A_SIZE{1'b0}};
dio_direction_b <= {DIO_DIRECTION_B_SIZE{1'b0}};
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
// Write requests
end else begin
if (s_ctrlport_req_wr) begin
// Always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + SCRATCH_REGISTER:
scratch_reg <= s_ctrlport_req_data;
BASE_ADDRESS + PL_DB_REGISTER: begin
if (s_ctrlport_req_data[DISABLE_CLOCK_DB0]) begin
db_clk_enable[0] <= 1'b0;
end else if (s_ctrlport_req_data[ENABLE_CLOCK_DB0]) begin
db_clk_enable[0] <= 1'b1;
end
if (s_ctrlport_req_data[DISABLE_CLOCK_DB1]) begin
db_clk_enable[1] <= 1'b0;
end else if (s_ctrlport_req_data[ENABLE_CLOCK_DB1]) begin
db_clk_enable[1] <= 1'b1;
end
if (s_ctrlport_req_data[DISABLE_PLL_REF_CLOCK]) begin
pll_ref_clk_enable <= 1'b0;
end else if (s_ctrlport_req_data[ENABLE_PLL_REF_CLOCK]) begin
pll_ref_clk_enable <= 1'b1;
end
if (s_ctrlport_req_data[ASSERT_RESET_DB0]) begin
db_reset[0] <= 1'b1;
end else if (s_ctrlport_req_data[RELEASE_RESET_DB0]) begin
db_reset[0] <= 1'b0;
end
if (s_ctrlport_req_data[ASSERT_RESET_DB1]) begin
db_reset[1] <= 1'b1;
end else if (s_ctrlport_req_data[RELEASE_RESET_DB1]) begin
db_reset[1] <= 1'b0;
end
end
BASE_ADDRESS + DIO_DIRECTION_REGISTER: begin
dio_direction_a <= s_ctrlport_req_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A];
dio_direction_b <= s_ctrlport_req_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B];
end
BASE_ADDRESS + SERIAL_NUM_LOW_REG: begin
serial_num[31:0] <= s_ctrlport_req_data;
end
BASE_ADDRESS + SERIAL_NUM_HIGH_REG: begin
serial_num[39:32] <= s_ctrlport_req_data[SERIAL_NUM_HIGH_REG_SIZE-1:0];
end
BASE_ADDRESS + CMI_CONTROL_STATUS: begin
cmi_ready <= s_ctrlport_req_data[CMI_READY];
end
// Error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// Read request
end else if (s_ctrlport_req_rd) begin
// Default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
case (s_ctrlport_req_addr)
BASE_ADDRESS + SIGNATURE_REGISTER:
s_ctrlport_resp_data <= PS_CPLD_SIGNATURE;
BASE_ADDRESS + REVISION_REGISTER:
s_ctrlport_resp_data <= CPLD_REVISION;
BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER:
s_ctrlport_resp_data <= OLDEST_CPLD_REVISION;
BASE_ADDRESS + SCRATCH_REGISTER:
s_ctrlport_resp_data <= scratch_reg;
BASE_ADDRESS + GIT_HASH_REGISTER:
`ifdef GIT_HASH
s_ctrlport_resp_data <= `GIT_HASH;
`else
s_ctrlport_resp_data <= 32'hDEADBEEF;
`endif
BASE_ADDRESS + PL_DB_REGISTER: begin
s_ctrlport_resp_data[DB0_CLOCK_ENABLED] <= db_clk_enable[0];
s_ctrlport_resp_data[DB1_CLOCK_ENABLED] <= db_clk_enable[1];
s_ctrlport_resp_data[PLL_REF_CLOCK_ENABLED] <= pll_ref_clk_enable;
s_ctrlport_resp_data[DB0_RESET_ASSERTED] <= db_reset[0];
s_ctrlport_resp_data[DB1_RESET_ASSERTED] <= db_reset[1];
end
BASE_ADDRESS + DIO_DIRECTION_REGISTER: begin
s_ctrlport_resp_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A] <= dio_direction_a;
s_ctrlport_resp_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B] <= dio_direction_b;
end
BASE_ADDRESS + SERIAL_NUM_LOW_REG: begin
s_ctrlport_resp_data <= serial_num[31:0];
end
BASE_ADDRESS + SERIAL_NUM_HIGH_REG: begin
s_ctrlport_resp_data[SERIAL_NUM_HIGH_REG_SIZE-1:0] <= serial_num[39:32];
end
BASE_ADDRESS + CMI_CONTROL_STATUS: begin
s_ctrlport_resp_data[CMI_READY] <= cmi_ready;
s_ctrlport_resp_data[OTHER_SIDE_DETECTED] <= cmi_other_side_detected;
end
// Error on undefined address
default: begin
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// No request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="PS_CPLD_BASE_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="PS_CPLD_BASE_REGS">
// <info>
// Basic registers containing version and capabilites information.
// </info>
//
// <register name="SIGNATURE_REGISTER" offset="0x00" writable="false" size="32">
// <info>Contains the product's signature.</info>
// <bitfield name="PRODUCT_SIGNATURE" range="31..0">
// <info>Fixed value PS_CPLD_SIGNATURE of @.CONSTANTS_REGMAP</info>
// </bitfield>
// </register>
//
// <register name="REVISION_REGISTER" offset="0x04" writable="false" size="32">
// <info>Contains the CPLD revision (see CPLD_REVISION of @.CONSTANTS_REGMAP).</info>
// <bitfield name="REVISION_HH" range="7..0">
// <info>Contains revision hour code.</info>
// </bitfield>
// <bitfield name="REVISION_DD" range="15..8">
// <info>Contains revision day code.</info>
// </bitfield>
// <bitfield name="REVISION_MM" range="23..16">
// <info>Contains revision month code.</info>
// </bitfield>
// <bitfield name="REVISION_YY" range="31..24">
// <info>Contains revision year code.</info>
// </bitfield>
// </register>
//
// <register name="OLDEST_COMPATIBLE_REVISION_REGISTER" offset="0x08" writable="false" size="32">
// <info>
// This register returns (in YYMMDDHH format) the oldest revision
// that is still compatible with this one. Compatible means that
// registers or register bits may have been added, but not
// modified or deleted (see OLDEST_CPLD_REVISION of @.CONSTANTS_REGMAP).
// </info>
// <bitfield name="OLD_REVISION_HH" range="7..0">
// <info>Contains revision hour code.</info>
// </bitfield>
// <bitfield name="OLD_REVISION_DD" range="15..8">
// <info>Contains revision day code.</info>
// </bitfield>
// <bitfield name="OLD_REVISION_MM" range="23..16">
// <info>Contains revision month code.</info>
// </bitfield>
// <bitfield name="OLD_REVISION_YY" range="31..24">
// <info>Contains revision year code.</info>
// </bitfield>
// </register>
//
// <register name="SCRATCH_REGISTER" offset="0x0C" size="32">
// <info>Read/write register for general software use.</info>
// </register>
//
// <register name="GIT_HASH_REGISTER" offset="0x10" size="32" writable="false">
// <info>
// Git hash of commit used to build this image.{br}
// Value equals 0xDEADBEEF if the git hash was not used during synthesis.
// </info>
// <bitfield name="GIT_CLEAN" range="31..28">
// <info>
// 0x0 in case the git status was clean{br}
// 0xF in case there were uncommitted changes
// </info>
// </bitfield>
// <bitfield name="GIT_HASH" range="27..0">
// <info>7 hex digit hash code of the commit</info>
// </bitfield>
// </register>
// </group>
//
// <group name="PS_CONTROL_REGS">
// <info>
// Register Map to control MB CPLD functions.
// </info>
// <register name="PL_DB_REGISTER" offset="0x20" size="32">
// <info>
// Register to control the PL part DB SPI connection and reset generation.
// The DB connection is clocked with PLL reference clock. Ensure this clock is stable
// and enabled before starting any SPI request.
// The PLL reference clock can be disabled if both DB connections are disabled or inactive.
// To enable the DB connection, enable clock with one write access and release
// reset with the next write access.
// To disable the DB connection, assert reset with one write access and
// disable clocks with the next write access.
// </info>
// <bitfield name="DB0_CLOCK_ENABLED" range="0" writable="false">
// <info>Indicates if a clock is forwarded to DB 0.</info>
// </bitfield>
// <bitfield name="DB1_CLOCK_ENABLED" range="1" writable="false">
// <info>Indicates if a clock is forwarded to DB 1.</info>
// </bitfield>
// <bitfield name="PLL_REF_CLOCK_ENABLED" range="2" writable="false">
// <info>Indicates if the PLL reference clock for the PL interface is enabled.</info>
// </bitfield>
// <bitfield name="DB0_RESET_ASSERTED" range="4" writable="false">
// <info>Indicates that reset is asserted for DB 0.</info>
// </bitfield>
// <bitfield name="DB1_RESET_ASSERTED" range="5" writable="false">
// <info>Indicates that reset is asserted for DB 1.</info>
// </bitfield>
// <bitfield name="ENABLE_CLOCK_DB0" range="8" readable="false">
// <info>Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by @.DISABLE_CLOCK_DB0)</info>
// </bitfield>
// <bitfield name="ENABLE_CLOCK_DB1" range="9" readable="false">
// <info>Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by @.DISABLE_CLOCK_DB1)</info>
// </bitfield>
// <bitfield name="ENABLE_PLL_REF_CLOCK" range="10" readable="false">
// <info>Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by @.DISABLE_PLL_REF_CLOCK)</info>
// </bitfield>
// <bitfield name="DISABLE_CLOCK_DB0" range="12" readable="false">
// <info>Writing with this flag set disables DB 0 clock forwarding (overrides @.ENABLE_CLOCK_DB0)</info>
// </bitfield>
// <bitfield name="DISABLE_CLOCK_DB1" range="13" readable="false">
// <info>Writing with this flag set disables DB 1 clock forwarding (overrides @.ENABLE_CLOCK_DB1)</info>
// </bitfield>
// <bitfield name="DISABLE_PLL_REF_CLOCK" range="14" readable="false">
// <info>Writing with this flag set disables the PLL reference clock (overrides @.ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock.</info>
// </bitfield>
// <bitfield name="RELEASE_RESET_DB0" range="16" readable="false">
// <info>Writing with this flag set releases DB 0 reset. (may be overwritten by @.ASSERT_RESET_DB0)</info>
// </bitfield>
// <bitfield name="RELEASE_RESET_DB1" range="17" readable="false">
// <info>Writing with this flag set releases DB 1 reset. (may be overwritten by @.ASSERT_RESET_DB1)</info>
// </bitfield>
// <bitfield name="ASSERT_RESET_DB0" range="20" readable="false">
// <info>Writing with this flag set asserts reset for DB 0 (overrides @.RELEASE_RESET_DB0)</info>
// </bitfield>
// <bitfield name="ASSERT_RESET_DB1" range="21" readable="false">
// <info>Writing with this flag set asserts reset for DB 1 (overrides @.RELEASE_RESET_DB1)</info>
// </bitfield>
// </register>
// </group>
//
// <group name="DIO_REGS">
// <info>
// Registers to control the GPIO buffer direction on the DIO board connected to the FPGA.
// Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers.
// Set the direction in the FPGA's DIO register appropriately.
// </info>
// <register name="DIO_DIRECTION_REGISTER" offset="0x30" size="32">
// <info>
// Set the direction of FPGA buffer connected to DIO ports on the DIO board.{br/}
// Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA.
// </info>
// <bitfield name="DIO_DIRECTION_A" range="11..0" initialvalue="0"/>
// <bitfield name="DIO_DIRECTION_B" range="27..16" initialvalue="0"/>
// </register>
// </group>
//
// <group name="PS_CMI_REGS">
// <info>
// Cable present status register.
// </info>
// <register name="SERIAL_NUM_LOW_REG" offset="0x34" size="32">
// <info>Least significant bytes of 5 byte serial number.</info>
// </register>
// <register name="SERIAL_NUM_HIGH_REG" offset="0x38" size="8">
// <info>Most significant byte of 5 byte serial number.</info>
// </register>
// <register name="CMI_CONTROL_STATUS" offset="0x3C" size="32">
// <info>Control CMI communication and delivers information on the CMI link status.</info>
// <bitfield name="CMI_READY" range="0">
// <info>Set if the device is ready to establish a PCI-Express link (affects CMI_CLP_READY bit).</info>
// </bitfield>
// <bitfield name="OTHER_SIDE_DETECTED" range="31" writable="false">
// <info>1 if an upstream CMI device has been detected.</info>
// </bitfield>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/ps_power_regs.v
-231
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@@ -1,231 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ps_power_regs
//
// Description:
//
// Registers to control power supplies on the motherboard.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers.
// NUM_ADDRESSES : Number of bytes of address space to use.
//
`default_nettype none
module ps_power_regs #(
parameter BASE_ADDRESS = 0,
parameter NUM_ADDRESSES = 32
) (
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
// iPass
output reg ipass_power_disable = 1'b0,
input wire [ 1:0] ipass_power_fault_n,
// Oscillators
output reg osc_100_en,
output reg osc_122_88_en
);
`include "regmap/ps_power_regmap_utils.vh"
`include "../../../lib/rfnoc/core/ctrlport.vh"
//----------------------------------------------------------
// Address Calculation
//----------------------------------------------------------
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
//----------------------------------------------------------
// Internal Registers
//----------------------------------------------------------
reg [1:0] ipass_power_sticky = 2'b00;
reg [1:0] ipass_clear_sticky = 2'b00;
//----------------------------------------------------------
// Handling of ControlPort Requests
//----------------------------------------------------------
always @(posedge ctrlport_clk) begin
// Reset internal registers and responses
if (ctrlport_rst) begin
ipass_power_disable <= 1'b0;
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}};
osc_100_en <= 1'b0;
osc_122_88_en <= 1'b0;
end else begin
// Default assignments
ipass_clear_sticky <= 2'b00;
// Write requests
if (s_ctrlport_req_wr) begin
// Always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}};
case (s_ctrlport_req_addr)
BASE_ADDRESS + IPASS_POWER_REG: begin
ipass_power_disable <= s_ctrlport_req_data[IPASS_DISABLE_POWER_BIT];
ipass_clear_sticky[0] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT0];
ipass_clear_sticky[1] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT1];
end
BASE_ADDRESS + OSC_POWER_REG: begin
osc_100_en <= s_ctrlport_req_data[OSC_100];
osc_122_88_en <= s_ctrlport_req_data[OSC_122_88];
end
// Error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// Read request
end else if (s_ctrlport_req_rd) begin
// Default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}};
case (s_ctrlport_req_addr)
BASE_ADDRESS + IPASS_POWER_REG: begin
s_ctrlport_resp_data[IPASS_DISABLE_POWER_BIT] <= ipass_power_disable;
s_ctrlport_resp_data[IPASS_POWER_FAULT0] <= ipass_power_sticky[0];
s_ctrlport_resp_data[IPASS_POWER_FAULT1] <= ipass_power_sticky[1];
end
BASE_ADDRESS + OSC_POWER_REG: begin
s_ctrlport_resp_data[OSC_100] <= osc_100_en;
s_ctrlport_resp_data[OSC_122_88] <= osc_122_88_en;
end
// Error on undefined address
default: begin
s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// No request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
//----------------------------------------------------------
// Sticky Logic of Power Registers
//----------------------------------------------------------
// Synchronize asynchronous inputs
wire [1:0] ipass_power_fault_lcl_n;
synchronizer #(
.WIDTH (2),
.STAGES (2),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (1)
) power_fault_sync (
.clk (ctrlport_clk),
.rst (ctrlport_rst),
.in (ipass_power_fault_n),
.out (ipass_power_fault_lcl_n)
);
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
ipass_power_sticky <= 2'b00;
end else begin
// Keep value if not cleared or set in case of fault
ipass_power_sticky <= (ipass_power_sticky & ~ipass_clear_sticky) | ~ipass_power_fault_lcl_n;
end
end
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="PS_POWER_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="PS_POWER_REGS">
// <info>
// Registers to control power supplies on the motherboard.
// </info>
//
// <register name="IPASS_POWER_REG" offset="0x00" size="32">
// <info>Controls the power supplies for the iPass connectors.</info>
// <bitfield name="IPASS_DISABLE_POWER_BIT" range="0">
// <info>Set to 1 to disable power for both iPass connectors.</info>
// </bitfield>
// <bitfield name="IPASS_CLEAR_POWER_FAULT0" range="30" readable="false">
// <info>Clear @.IPASS_POWER_FAULT0.</info>
// </bitfield>
// <bitfield name="IPASS_CLEAR_POWER_FAULT1" range="31" readable="false">
// <info>Clear @.IPASS_POWER_FAULT1.</info>
// </bitfield>
// <bitfield name="IPASS_POWER_FAULT0" range="30" writable="false">
// <info>
// Asserted signal indicates a power fault in power switch for iPass
// connector 0. Sticky bit. Asserted on occurrence. Reset using
// @.IPASS_CLEAR_POWER_FAULT0.
// </info>
// </bitfield>
// <bitfield name="IPASS_POWER_FAULT1" range="31" writable="false">
// <info>
// Asserted signal indicates a power fault in power switch for iPass
// connector 1. Sticky bit. Asserted on occurrence. Reset using
// @.IPASS_CLEAR_POWER_FAULT1.
// </info>
// </bitfield>
// </register>
//
// <register name="OSC_POWER_REG" offset="0x04" size="32">
// <info>Controls the power supplies for the oscillators.</info>
// <bitfield name="OSC_100" range="0">
// <info>Enables 5V power switch for the 100 MHz oscillator.</info>
// </bitfield>
// <bitfield name="OSC_122_88" range="1">
// <info>Enables 5V power switch for the 122.88 MHz oscillator.</info>
// </bitfield>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/pwr_supply_clk_gen.v
-73
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@@ -1,73 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: pwr_supply_clk_gen
//
// Description:
//
// Generates a clock for one motherboard power supply.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers.
// NUM_ADDRESSES : Number of bytes of address space to use.
//
`default_nettype none
module pwr_supply_clk_gen#(
parameter SOURCE_CLK_FREQ = 100_000_000,
parameter TARGET_CLK_FREQ = 100_000
) (
// Base clock and reset
input wire clk,
input wire rst,
// Power supply clocks
output reg pwr_supply_clk
);
//-----------------------------------------------------------------------------
// Counter Calculation / Definition
//-----------------------------------------------------------------------------
// Counter to generate the power supply switching clock
// Assumption: the ratio between the generated clock and the source clock is
// even, therefore we can produce a 50% DC clock output.
localparam MAX_COUNT = SOURCE_CLK_FREQ / TARGET_CLK_FREQ / 2;
localparam COUNTER_W = $clog2(MAX_COUNT);
reg [COUNTER_W-1:0] counter = 0;
//-----------------------------------------------------------------------------
// Clock Generation
//-----------------------------------------------------------------------------
// This process implements a simple clock divider for the power supply
// switcher.
// SAFE COUNTER START! rst is a synchronous reset generated in the
// clk domain; therefore, inherently safe.
always @(posedge clk) begin
if (rst) begin
counter <= 0;
pwr_supply_clk <= 1'b0;
end
else begin
// Add one every cycle to the counter
counter <= counter + 1'b1;
// When the counter reaches its mid value, it is reset and the output clock
// output is toggled.
if (counter == MAX_COUNT-1) begin
counter <= 0;
pwr_supply_clk <= ~pwr_supply_clk;
end
end
end
endmodule
`default_nettype wire
top/x400/cpld/quartus/ps_cs_analysis.tcl
-32
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@@ -1,32 +0,0 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Module: ps_cs_analysis
#
# Description:
#
# Analyze false path in PS SPI logic to ensure an upper delay boundary.
#
# get project to a working state
project_open -force "mb_cpld.qpf"
create_timing_netlist
update_timing_netlist
# Determine data path delay from MB CPLD chip select signal to MB CPLD internal
# SPI slave
set paths [report_path -from [get_registers {ps_spi_cs_n_decoded[0]}] -multi_corner]
set spiSlaveCsPathDelay [lindex $paths 1]
# clock period at 250 MHz (clock driving the decoding registers)
set maxDelay 4
# compare path from above with maximum delay
if ([expr {$maxDelay < $spiSlaveCsPathDelay}]) {
puts "MB CPLD SPI CS line longer than expected."
exit 1
}
exit 0
top/x400/cpld/quartus/raw_conversion.cof
-39
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@@ -1,39 +0,0 @@
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<output_filename>output_files/mb_cpld_converted.pof</output_filename>
<n_pages>1</n_pages>
<width>1</width>
<mode>14</mode>
<sof_data>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>output_files/mb_cpld.sof<compress_bitstream>1</compress_bitstream></sof_filename>
</bit0>
</sof_data>
<version>10</version>
<create_cvp_file>0</create_cvp_file>
<create_hps_iocsr>0</create_hps_iocsr>
<auto_create_rpd>1</auto_create_rpd>
<rpd_little_endian>1</rpd_little_endian>
<options>
<map_file>1</map_file>
</options>
<MAX10_device_options>
<por>0</por>
<io_pullup>1</io_pullup>
<config_from_cfm0_only>0</config_from_cfm0_only>
<isp_source>0</isp_source>
<verify_protect>0</verify_protect>
<epof>0</epof>
<ufm_source>0</ufm_source>
</MAX10_device_options>
<advanced_options>
<ignore_epcs_id_check>1</ignore_epcs_id_check>
<ignore_condone_check>2</ignore_condone_check>
<plc_adjustment>0</plc_adjustment>
<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>
<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes>
<bitslice_pre_padding>1</bitslice_pre_padding>
</advanced_options>
</cof>
top/x400/cpld/reconfig_engine.v
-1065
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top/x400/cpld/regmap/mb_cpld_pl_regmap_utils.vh
-36
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@@ -1,36 +0,0 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: mb_cpld_pl_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// PL_REGISTERS : 0x0 (mb_cpld.v)
// JTAG_DB0 : 0x60 (mb_cpld.v)
// JTAG_DB1 : 0x80 (mb_cpld.v)
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group MB_CPLD_PL_WINDOWS
//===============================================================================
// PL_REGISTERS Window (from mb_cpld.v)
localparam PL_REGISTERS = 'h0; // Window Offset
localparam PL_REGISTERS_SIZE = 'h40; // size in bytes
// JTAG_DB0 Window (from mb_cpld.v)
localparam JTAG_DB0 = 'h60; // Window Offset
localparam JTAG_DB0_SIZE = 'h20; // size in bytes
// JTAG_DB1 Window (from mb_cpld.v)
localparam JTAG_DB1 = 'h80; // Window Offset
localparam JTAG_DB1_SIZE = 'h20; // size in bytes
top/x400/cpld/reset_generator.v
-93
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@@ -1,93 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: reset_generator
//
// Description:
//
// Generates a power-on reset signal that is asserted at startup and stays
// asserted for at least CYCLES_IN_RESET clock cycles.
//
// Internally, it generates a 1-bit synchronous signal (initialize) to safely
// initialize the power_on_reset_counter incremental counter to 0's.
//
// A delayed version of the initializing signal is also generated
// (counter_enable) to start counting.
//
// 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ 9_
// clk _| |_| |_| |_| |_| |_| |_| |_| |_|
// _____________________
// initialize _____________|
// _________
// counter_enable _________________________|
//
`default_nettype none
module reset_generator (
input wire clk,
output reg power_on_reset = 1'b1
);
wire [0:0] counter_enable;
wire [0:0] initialize;
synchronizer #(
.WIDTH (1),
.STAGES (3),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (0)
) init_sync_inst (
.clk (clk),
.rst (1'b0),
.in (1'b1),
.out (initialize)
);
synchronizer #(
.WIDTH (1),
.STAGES (3),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (0)
) counter_en_sync_inst (
.clk (clk),
.rst (1'b0),
.in (initialize),
.out (counter_enable)
);
// Internal synchronous reset generator.
localparam CYCLES_IN_RESET = 20;
reg [7:0] power_on_reset_counter = 8'b0;
// This block generates a synchronous reset in the clk domain that can be
// used by downstream logic.
//
// power_on_reset_counter is first initialized to 0's upon assertion of
// initialize. Some cycles later (3), upon assertion if counter_enable,
// power_on_reset_counter starts to increment.
//
// power_on_reset will remain asserted until power_on_reset_counter reaches
// cycles_in_reset, resulting in the deassertion of power_on_reset.
always @(posedge clk) begin : power_on_reset_gen
if (counter_enable) begin
if (power_on_reset_counter == CYCLES_IN_RESET-1) begin
power_on_reset <= 1'b0;
end else begin
power_on_reset_counter <= power_on_reset_counter + 1'b1;
power_on_reset <= 1'b1;
end
end
else if (initialize) begin
power_on_reset_counter <= 8'b0;
power_on_reset <= 1'b1;
end
end
endmodule
`default_nettype wire
top/x400/cpld/spi_slave.v
-288
View File
@@ -1,288 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: spi_slave
//
// Description:
//
// SPI slave for configuration CPOL = CPHA = 0.
// Transfers 8 bit = 1 byte MSB first. Parallel data has to be
// provided and consumed immediately when flags are asserted.
//
// Limitation: clk frequency <= 2*sclk frequency
//
// Data request from sclk domain is triggered towards the clk domain ahead of
// time. This is due to the clock domain crossing using the synchronizer and
// processing pipeline stages.
//
// The worst case propagation delay of the used synchronizer is:
//
// 4 'clk' clock cycles:
// 1 clock cycle of signal propagation to synchronizer
// (data_request_sclk assertion)
// 1 clock cycle to capture data with instability in first stage
// 1 clock cycle to stabilize first stage
// 1 clock cycle to capture data in second stage
// (data_request_clk available in 'clk' domain)
//
// Once synchronized in 'clk' domain, there is one additional clock cycle to
// derive data_out_valid and data_in_required. To ensure that transmit data
// is registered a 'clk' cycle ahead of the actual transmission we need 2
// more 'clk' clock cycles. This ensures that transmit_word has changed and
// is stable for at least one 'clk' cycle before 'sclk' asserts again. Any
// additional time required externally to respond to the control port
// requests should be considered in this crossing as well. This is a total of
// 7 clock cycles (+ctrlport response margin) @ clk domain. The minimum
// required time in sclk domain to issue the request is calculated based on
// the clock frequencies.
//
// Parameters:
//
// CLK_FREQUENCY : Frequency of "clk"
// SPI_FREQUENCY : Frequency of "sclk"
//
`default_nettype none
module spi_slave #(
parameter CLK_FREQUENCY = 50000000,
parameter SPI_FREQUENCY = 10000000
) (
//---------------------------------------------------------------
// SPI Interface
//---------------------------------------------------------------
input wire sclk,
input wire cs_n,
input wire mosi,
output wire miso,
//---------------------------------------------------------------
// Parallel Interface
//---------------------------------------------------------------
input wire clk,
input wire rst,
output reg data_in_required,
input wire data_in_valid,
input wire [7:0] data_in,
output reg data_out_valid,
output reg [7:0] data_out,
output wire active
);
wire [0:0] data_request_clk;
wire [0:0] reception_complete_clk;
//---------------------------------------------------------------
// SPI Receiver @ sclk
//---------------------------------------------------------------
reg [7:0] receiver_reg;
reg [2:0] current_bit_index;
reg reception_complete_sclk = 1'b0;
reg [7:0] received_word;
always @(posedge sclk or posedge cs_n) begin
// Reset logic on positive cs_n edge = slave idle
if (cs_n) begin
receiver_reg <= 8'b0;
end
// Rising edge of sclk
else begin
// Capture bits into shift register MSBs first
receiver_reg <= {receiver_reg[6:0], mosi};
end
end
// Reset with cs_n might occur too early during clk sync.
// Reset half way through the reception.
always @(posedge sclk) begin
// Complete word was received
if (current_bit_index == 7) begin
reception_complete_sclk <= 1'b1;
received_word <= {receiver_reg[6:0], mosi};
// Reset after half transaction
end else if (current_bit_index == 3) begin
reception_complete_sclk <= 1'b0;
end
end
//---------------------------------------------------------------
// Handover of data sclk -> clk
//---------------------------------------------------------------
synchronizer #(
.WIDTH (1),
.STAGES (2),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (1)
) data_sync_inst (
.clk (clk),
.rst (1'b0),
.in (reception_complete_sclk),
.out (reception_complete_clk)
);
//---------------------------------------------------------------
// Parallel interface data output @ clk
//---------------------------------------------------------------
reg reception_complete_clk_delayed = 1'b0;
// Propagate toggling signal without reset to ensure stability on reset
always @(posedge clk) begin
// Capture last state of reception
reception_complete_clk_delayed <= reception_complete_clk;
end
// Derive data and control signal
always @(posedge clk) begin
if (rst) begin
data_out_valid <= 1'b0;
data_out <= 8'b0;
end
else begin
// Default assignment
data_out_valid <= 1'b0;
// Provide data to output on rising_edge
if (reception_complete_clk & ~reception_complete_clk_delayed) begin
// Data can simply be captured as the reception complete signal
// indicates stable values in received_word.
data_out <= received_word;
data_out_valid <= 1'b1;
end
end
end
//---------------------------------------------------------------
// SPI Transmitter @ sclk
//---------------------------------------------------------------
// Data request calculation:
// SCLK_CYCLES_DURING_DATA_REQ = 8 clk period / sclk period
// Clock periods are expressed by reciprocal of frequencies.
// Term "+CLK_FREQUENCY-1" is used to round up the result in integer logic.
localparam SCLK_CYCLES_DURING_DATA_REQ = (8*SPI_FREQUENCY + CLK_FREQUENCY-1)/CLK_FREQUENCY;
// subtract from 8 bits per transfer to get target index
localparam DATA_REQ_BIT_INDEX = 8 - SCLK_CYCLES_DURING_DATA_REQ;
reg [7:0] transmit_bits;
reg [7:0] transmit_word;
reg data_request_sclk = 1'b0;
always @(negedge sclk or posedge cs_n) begin
// Reset logic on positive cs_n edge = slave idle
if (cs_n) begin
current_bit_index <= 3'b0;
data_request_sclk <= 1'b0;
transmit_bits <= 8'b0;
end
// Falling edge of sclk
else begin
// Fill or move shift register for byte transmissions
if (current_bit_index == 7) begin
transmit_bits <= transmit_word;
end else begin
transmit_bits <= {transmit_bits[6:0], 1'b0};
end
// Update bit index
current_bit_index <= current_bit_index + 1'b1;
// Trigger request for new word at start of calculated index
if (current_bit_index == DATA_REQ_BIT_INDEX-1) begin
data_request_sclk <= 1'b1;
// Reset after half the reception in case cs_n is not changed in between
// two transactions.
end else if (current_bit_index == (DATA_REQ_BIT_INDEX+4-1)%8) begin
data_request_sclk <= 1'b0;
end
end
end
// Drive miso output with data when cs_n low
assign miso = cs_n ? 1'bz : transmit_bits[7];
//---------------------------------------------------------------
// Handover of Data Request sclk -> clk
//---------------------------------------------------------------
synchronizer #(
.WIDTH (1),
.STAGES (2),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (1)
) request_sync_inst (
.clk (clk),
.rst (rst),
.in (data_request_sclk),
.out (data_request_clk)
);
//---------------------------------------------------------------
// Parallel Interface Data Input Control
//---------------------------------------------------------------
reg data_request_clk_delayed;
always @(posedge clk) begin
if (rst) begin
data_request_clk_delayed <= 1'b0;
data_in_required <= 1'b0;
transmit_word <= 8'b0;
end
else begin
// Default assignment
data_in_required <= 1'b0;
// Capture last state of data request
data_request_clk_delayed <= data_request_clk;
// Request data from input
if (~data_request_clk_delayed & data_request_clk) begin
data_in_required <= 1'b1;
end
// Capture new data if valid data available, 0 otherwise.
if (data_in_required) begin
if (data_in_valid) begin
transmit_word <= data_in;
end else begin
transmit_word <= 8'b0;
end
end
end
end
//---------------------------------------------------------------
// Chip Select
//---------------------------------------------------------------
// Driven as active signal in parallel clock domain
wire cs_n_clk;
assign active = ~cs_n_clk;
synchronizer #(
.WIDTH (1),
.STAGES (2),
.INITIAL_VAL (1'b1),
.FALSE_PATH_TO_IN (1)
) active_sync_inst (
.clk (clk),
.rst (rst),
.in (cs_n),
.out (cs_n_clk)
);
endmodule
`default_nettype wire
top/x400/cpld/spi_slave_to_ctrlport_master.v
-238
View File
@@ -1,238 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: spi_slave_to_ctrlport_master
//
// Description:
//
// SPI slave to ContolPort master conversion in order to tunnel control port
// request through an SPI bus.
//
// The request format on SPI is defined as:
//
// Write request:
// 1'b1 = write, 15 bit address, 32 bit data (MOSI), 8 bit processing gap,
// 5 bit padding, 1 bit ack, 2 bit status
//
// Read request:
// 1'b0 = read, 15 bit address, 8 bit processing gap, 32 bit data (MISO),
// 5 bit padding, 1 bit ack, 2 bit status
//
// Parameters:
//
// CLK_FREQUENCY : Frequency of "clk"
// SPI_FREQUENCY : Frequency of "sclk"
//
`default_nettype none
module spi_slave_to_ctrlport_master #(
parameter CLK_FREQUENCY = 50000000,
parameter SPI_FREQUENCY = 10000000
) (
//---------------------------------------------------------------
// ControlPort Master
//---------------------------------------------------------------
input wire ctrlport_clk,
input wire ctrlport_rst,
output wire m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [19:0] m_ctrlport_req_addr,
output wire [31:0] m_ctrlport_req_data,
input wire m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [31:0] m_ctrlport_resp_data,
//---------------------------------------------------------------
// SPI Slave
//---------------------------------------------------------------
input wire sclk,
input wire cs_n,
input wire mosi,
output wire miso
);
`include "../../../lib/rfnoc/core/ctrlport.vh"
//---------------------------------------------------------------
// SPI Slave
//---------------------------------------------------------------
wire [7:0] data_in;
wire [7:0] data_out;
wire data_in_valid;
wire data_out_valid;
wire data_in_required;
wire spi_slave_active;
spi_slave #(
.CLK_FREQUENCY (CLK_FREQUENCY),
.SPI_FREQUENCY (SPI_FREQUENCY)
) spi_slave_async (
.sclk (sclk),
.cs_n (cs_n),
.mosi (mosi),
.miso (miso),
.clk (ctrlport_clk),
.rst (ctrlport_rst),
.data_in_required (data_in_required),
.data_in_valid (data_in_valid),
.data_in (data_in),
.data_out_valid (data_out_valid),
.data_out (data_out),
.active (spi_slave_active)
);
//---------------------------------------------------------------
// Reset Generation from SPI Slave
//---------------------------------------------------------------
reg spi_slave_active_delayed = 1'b0;
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
spi_slave_active_delayed <= 1'b0;
end
else begin
spi_slave_active_delayed <= spi_slave_active;
end
end
// Trigger reset on falling edge of active signal (rising edge of cs_n)
wire spi_slave_reset;
assign spi_slave_reset = spi_slave_active_delayed & (~spi_slave_active);
//---------------------------------------------------------------
// Transfer Constants
//---------------------------------------------------------------
localparam NUM_BYTES_TRANSACTION = 8;
localparam NUM_BYTES_WRITE_REQUEST_PAYLOAD = 6;
localparam NUM_BYTES_READ_REQUEST_PAYLOAD = 2;
localparam MAX_BYTES_RESPONSE_PAYLOAD = 5;
//---------------------------------------------------------------
// Data Receiver
//---------------------------------------------------------------
reg [3:0] num_bytes_received;
reg request_received;
reg write_request;
reg provide_response;
reg [NUM_BYTES_WRITE_REQUEST_PAYLOAD*8-1:0] request_reg = {NUM_BYTES_WRITE_REQUEST_PAYLOAD*8 {1'b0}};
always @(posedge ctrlport_clk) begin
if (ctrlport_rst || spi_slave_reset) begin
num_bytes_received <= 4'b0;
request_received <= 1'b0;
write_request <= 1'b0;
provide_response <= 1'b0;
end
else begin
// Counter number of received bytes
if (data_out_valid) begin
// Increment counter
num_bytes_received <= num_bytes_received + 1'b1;
if (num_bytes_received == NUM_BYTES_TRANSACTION-1) begin
num_bytes_received <= 4'b0;
end
end
// Check for read / write on first received byte's MSB
if (data_out_valid && (num_bytes_received == 0)) begin
write_request <= data_out[7];
end
// Detect complete request
request_received <= 1'b0;
if (data_out_valid) begin
if (write_request && (num_bytes_received == NUM_BYTES_WRITE_REQUEST_PAYLOAD-1)) begin
request_received <= 1'b1;
provide_response <= 1'b1;
end else if (~write_request && (num_bytes_received == NUM_BYTES_READ_REQUEST_PAYLOAD-1)) begin
request_received <= 1'b1;
provide_response <= 1'b1;
end
end
// Detect end of response on last received byte
if (num_bytes_received == NUM_BYTES_TRANSACTION-1) begin
provide_response <= 1'b0;
end
// Capture data into shift register
if (data_out_valid) begin
request_reg <= {request_reg[NUM_BYTES_WRITE_REQUEST_PAYLOAD*8-8-1:0], data_out};
end
end
end
// Drive ControlPort
localparam SPI_TRANSFER_ADDRESS_WIDTH = 15;
assign m_ctrlport_req_wr = request_received && write_request;
assign m_ctrlport_req_rd = request_received && ~write_request;
assign m_ctrlport_req_data = request_reg[CTRLPORT_DATA_W-1:0];
assign m_ctrlport_req_addr = (write_request) ?
{5'b0, request_reg[CTRLPORT_DATA_W+:SPI_TRANSFER_ADDRESS_WIDTH]} :
{5'b0, request_reg[0+:SPI_TRANSFER_ADDRESS_WIDTH]};
//---------------------------------------------------------------
// Response Handling
//---------------------------------------------------------------
reg [MAX_BYTES_RESPONSE_PAYLOAD*8-1:0] response_reg;
reg ready_for_response; // active during processing gap
wire write_response_byte;
always @(posedge ctrlport_clk) begin
if (ctrlport_rst || spi_slave_reset) begin
response_reg <= {8*MAX_BYTES_RESPONSE_PAYLOAD {1'b0}};
ready_for_response <= 1'b0;
end
else begin
// Reset response on new request
if (request_received) begin
ready_for_response <= 1'b1;
if (write_request) begin
// Just last byte -> padding, ack flag, CMDERR, padding (data length)
response_reg <= {5'b0, 1'b1, CTRL_STS_CMDERR, {CTRLPORT_DATA_W{1'b0}}};
end else begin
// Last 5 bytes -> data = 0, Padding, ack flag, CMDERR
response_reg <= {{CTRLPORT_DATA_W{1'b0}}, 5'b0, 1'b1, CTRL_STS_CMDERR};
end
// Capture response within processing gap, leave default response from above otherwise
end else if (m_ctrlport_resp_ack && ready_for_response) begin
if (write_request) begin
response_reg <= {5'b0, m_ctrlport_resp_ack, m_ctrlport_resp_status, {CTRLPORT_DATA_W{1'b0}}};
end else begin
response_reg <= {m_ctrlport_resp_data, 5'b0, m_ctrlport_resp_ack, m_ctrlport_resp_status};
end
end
// Shift data after writing to slave
if (write_response_byte) begin
response_reg <= {response_reg[0+:(MAX_BYTES_RESPONSE_PAYLOAD-1)*8], 8'b0};
ready_for_response <= 1'b0;
end
end
end
// Response is written after request part has been transferred
assign write_response_byte = data_in_required && provide_response;
// Assign SPI slave inputs
assign data_in = response_reg[(MAX_BYTES_RESPONSE_PAYLOAD-1)*8+:8];
assign data_in_valid = write_response_byte;
endmodule
`default_nettype wire
top/x400/cpld/x440/led_control.v
+222
View File
@@ -0,0 +1,222 @@
//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: led_control
//
// Description:
// Implements control over LED state via CtrlPort. The default state
// has the LEDs disabled.
//
`default_nettype none
module led_control #(
parameter BASE_ADDRESS = 0,
parameter REGMAP_SIZE = 8'h1
) (
// Clock and reset
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
// LED Control (domain: ctrlport_clk)
output reg ch0_rx2_led,
output reg ch0_tx_led,
output reg ch0_rx_led,
output reg ch1_rx2_led,
output reg ch1_tx_led,
output reg ch1_rx_led,
output reg ch2_rx2_led,
output reg ch2_tx_led,
output reg ch2_rx_led,
output reg ch3_rx2_led,
output reg ch3_tx_led,
output reg ch3_rx_led
);
`include "../regmap/x440/led_setup_regmap_utils.vh"
`include "../../../../lib/rfnoc/core/ctrlport.vh"
//---------------------------------------------------------------
// ATR memory signals
//---------------------------------------------------------------
reg [31:0] led_ctrl_reg;
//---------------------------------------------------------------
// Handling of CtrlPort
//---------------------------------------------------------------
// Check of request address is targeted for this module.
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + REGMAP_SIZE);
always @(posedge ctrlport_clk) begin
// reset internal registers and responses
if (ctrlport_rst) begin
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_status <= 2'b0;
s_ctrlport_resp_data <= 32'b0;
end else begin
// write requests
if (s_ctrlport_req_wr) begin
// always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {32{1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + LED_CONTROL: begin
led_ctrl_reg <= s_ctrlport_req_data;
end
// error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// no response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
//req_rd not delayed
end else if (s_ctrlport_req_rd) begin
// default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
s_ctrlport_resp_data <= {32{1'b0}};
case (s_ctrlport_req_addr)
BASE_ADDRESS : begin
s_ctrlport_resp_data <= led_ctrl_reg & LED_CONTROL_MASK;
end
// error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// no response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// no request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
always @(posedge ctrlport_clk) begin
//outputs
ch0_rx2_led <= led_ctrl_reg[CH0_RX2_LED_EN];
ch0_tx_led <= led_ctrl_reg[CH0_TRX1_LED_RED_EN];
ch0_rx_led <= led_ctrl_reg[CH0_TRX1_LED_GR_EN];
ch1_rx2_led <= led_ctrl_reg[CH1_RX2_LED_EN];
ch1_tx_led <= led_ctrl_reg[CH1_TRX1_LED_RED_EN];
ch1_rx_led <= led_ctrl_reg[CH1_TRX1_LED_GR_EN];
ch2_rx2_led <= led_ctrl_reg[CH2_RX2_LED_EN];
ch2_tx_led <= led_ctrl_reg[CH2_TRX1_LED_RED_EN];
ch2_rx_led <= led_ctrl_reg[CH2_TRX1_LED_GR_EN];
ch3_rx2_led <= led_ctrl_reg[CH3_RX2_LED_EN];
ch3_tx_led <= led_ctrl_reg[CH3_TRX1_LED_RED_EN];
ch3_rx_led <= led_ctrl_reg[CH3_TRX1_LED_GR_EN];
end
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="LED_SETUP_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="LED_SETUP_REGISTERS">
// <info>
// Contains registers that control the LEDs.
// </info>
// <register name="LED_CONTROL" size="32" offset="0x0" attributes="Readable|Writable">
// <info>
// This register configures RF Frontend LEDs.
// </info>
// <bitfield name="CH0_RX2_LED_EN" range="0" initialvalue="0">
// <info>
// Enables the Ch0 Rx2 Green LED
// </info>
// </bitfield>
// <bitfield name="CH0_TRX1_LED_RED_EN" range="1" initialvalue="0">
// <info>
// Enables the Ch0 TRX (TX) Red LED
// </info>
// </bitfield>
// <bitfield name="CH0_TRX1_LED_GR_EN" range="2" initialvalue="0">
// <info>
// Enables the Ch0 TRX (RX) Green LED
// </info>
// </bitfield>
// <bitfield name="CH1_RX2_LED_EN" range="8" initialvalue="0">
// <info>
// Enables the Ch1 Rx2 Green LED
// </info>
// </bitfield>
// <bitfield name="CH1_TRX1_LED_RED_EN" range="9" initialvalue="0">
// <info>
// Enables the Ch1 TRX (TX) Red LED
// </info>
// </bitfield>
// <bitfield name="CH1_TRX1_LED_GR_EN" range="10" initialvalue="0">
// <info>
// Enables the Ch1 TRX (RX) Green LED
// </info>
// </bitfield>
// <bitfield name="CH2_RX2_LED_EN" range="16" initialvalue="0">
// <info>
// Enables the Ch2 Rx2 Green LED
// </info>
// </bitfield>
// <bitfield name="CH2_TRX1_LED_RED_EN" range="17" initialvalue="0">
// <info>
// Enables the Ch2 TRX (TX) Red LED
// </info>
// </bitfield>
// <bitfield name="CH2_TRX1_LED_GR_EN" range="18" initialvalue="0">
// <info>
// Enables the Ch2 TRX (RX) Green LED
// </info>
// </bitfield>
// <bitfield name="CH3_RX2_LED_EN" range="24" initialvalue="0">
// <info>
// Enables the Ch3 Rx2 Green LED
// </info>
// </bitfield>
// <bitfield name="CH3_TRX1_LED_RED_EN" range="25" initialvalue="0">
// <info>
// Enables the Ch3 TRX (TX) Red LED
// </info>
// </bitfield>
// <bitfield name="CH3_TRX1_LED_GR_EN" range="26" initialvalue="0">
// <info>
// Enables the Ch3 TRX (RX) Green LED
// </info>
// </bitfield>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/x440/mb_cpld.sdc
+21
View File
@@ -0,0 +1,21 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
# Timing constraints for the x440's motherboard CPLD.
#
#####################################################################
# DB specific LED constraints
#####################################################################
# LED signals
set led_outputs [get_ports {QSFP0_LED_ACTIVE[*] QSFP0_LED_LINK[*] \
QSFP1_LED_ACTIVE[*] QSFP1_LED_LINK[*] CH*_RX2_LED[*] CH*_TX_LED[*] CH*_RX_LED[*] } ]
set_min_delay -to $led_outputs 0
set_max_delay -to $led_outputs $prc_clock_period
top/x400/cpld/mb_cpld.v → top/x400/cpld/x440/mb_cpld.v
+99 -152
View File
@@ -1,5 +1,5 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -7,7 +7,7 @@
//
// Description:
//
// Top level file for the X4xx motherboard CPLD.
// Top level file for the X440 motherboard CPLD.
//
// Parameters:
//
@@ -90,22 +90,20 @@ module mb_cpld #(
output wire [3:0] QSFP1_LED_ACTIVE,
output wire [3:0] QSFP1_LED_LINK,
// Daughterboard control interface
// Daughterboard LED GPIO
// 1 -> DB1 / 0 -> DB0
output reg [1:0] DB_CTRL_SCLK,
output reg [1:0] DB_CTRL_MOSI,
input wire [1:0] DB_CTRL_MISO,
output reg [1:0] DB_CTRL_CS_N,
output wire [1:0] DB_REF_CLK,
output wire [1:0] DB_ARST,
// Daughterboards' JTAG master interfaces.
// 1 -> DB1 / 0 -> DB0
output wire [1:0] DB_JTAG_TCK,
output wire [1:0] DB_JTAG_TDI, // from CPLD to DB
input wire [1:0] DB_JTAG_TDO, // from DB to CPLD
output wire [1:0] DB_JTAG_TMS,
output wire [1:0] CH0_RX2_LED,
output wire [1:0] CH0_TX_LED,
output wire [1:0] CH0_RX_LED,
output wire [1:0] CH1_RX2_LED,
output wire [1:0] CH1_TX_LED,
output wire [1:0] CH1_RX_LED,
output wire [1:0] CH2_RX2_LED,
output wire [1:0] CH2_TX_LED,
output wire [1:0] CH2_RX_LED,
output wire [1:0] CH3_RX2_LED,
output wire [1:0] CH3_TX_LED,
output wire [1:0] CH3_RX_LED,
//---------------------------------------------------------------------------
// PS Interfaces to/from Motherboard
//---------------------------------------------------------------------------
@@ -132,13 +130,6 @@ module mb_cpld #(
output wire [11:0] DIO_DIRECTION_A,
output wire [11:0] DIO_DIRECTION_B,
// Daughterboard calibration EEPROM SPI
// 1 -> DB1 / 0 -> DB0
output wire [1:0] DB_CALEEPROM_SCLK,
output wire [1:0] DB_CALEEPROM_MOSI,
input wire [1:0] DB_CALEEPROM_MISO,
output wire [1:0] DB_CALEEPROM_CS_N,
//---------------------------------------------------------------------------
// Miscellaneous
//---------------------------------------------------------------------------
@@ -161,9 +152,9 @@ module mb_cpld #(
// SPI masters (spi_top) are limited to 64 bit transmission length
`define SPI_MAX_CHAR_64
`include "../../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/mb_cpld_ps_regmap_utils.vh"
`include "regmap/mb_cpld_pl_regmap_utils.vh"
`include "../../../../lib/rfnoc/core/ctrlport.vh"
`include "../regmap/mb_cpld_ps_regmap_utils.vh"
`include "../regmap/x440/mb_cpld_pl_regmap_utils.vh"
//---------------------------------------------------------------------------
// Clocks and Resets
@@ -346,24 +337,6 @@ module mb_cpld #(
wire [1:0] db_reset;
wire [1:0] ipass_cable_present;
// Clocks and reset
oddr db0_clk_out (
.outclock (clk50),
.din ({1'b0, db_clk_enable[0]}),
.pad_out (DB_REF_CLK[0]),
.aclr (reset_clk50)
);
oddr db1_clk_out (
.outclock (clk50),
.din ({1'b0, db_clk_enable[1]}),
.pad_out (DB_REF_CLK[1]),
.aclr (reset_clk50)
);
assign DB_ARST[0] = db_reset[0];
assign DB_ARST[1] = db_reset[1];
// PL SPI FPGA -> DB CPLD
reg mb_cpld_sclk, mb_cpld_mosi, mb_cpld_cs_n;
wire mb_cpld_miso;
@@ -378,24 +351,8 @@ module mb_cpld #(
// SW is expected to properly setup the DBs before issuing SPI transactions.
always @(posedge pll_ref_clk_int) begin : to_db
// Default chip selects
DB_CTRL_CS_N[0] <= 1'b1;
DB_CTRL_CS_N[1] <= 1'b1;
mb_cpld_cs_n <= 1'b1;
// DB 0
DB_CTRL_SCLK[0] <= PL_CPLD_SCLK;
DB_CTRL_MOSI[0] <= PL_CPLD_MOSI;
if (PL_CPLD_CS_N == PL_CS_DB0) begin
DB_CTRL_CS_N[0] <= 1'b0;
end
// DB 1
DB_CTRL_SCLK[1] <= PL_CPLD_SCLK;
DB_CTRL_MOSI[1] <= PL_CPLD_MOSI;
if (PL_CPLD_CS_N == PL_CS_DB1) begin
DB_CTRL_CS_N[1] <= 1'b0;
end
// MB CPLD
mb_cpld_sclk <= PL_CPLD_SCLK;
mb_cpld_mosi <= PL_CPLD_MOSI;
@@ -408,8 +365,6 @@ module mb_cpld #(
always @(posedge pll_ref_clk_int) begin : from_db
case (PL_CPLD_CS_N)
PL_CS_MB_CPLD : PL_CPLD_MISO <= mb_cpld_miso; // MB CPLD
PL_CS_DB1 : PL_CPLD_MISO <= DB_CTRL_MISO[1]; // DB 1
PL_CS_DB0 : PL_CPLD_MISO <= DB_CTRL_MISO[0]; // DB 0
PL_CS_IDLE : PL_CPLD_MISO <= 1'bz; // Inactive
endcase
end
@@ -450,6 +405,22 @@ module mb_cpld #(
wire [31:0] pl_regs_ctrlport_resp_data;
wire [ 1:0] pl_regs_ctrlport_resp_status;
wire [19:0] db0_led_ctrlport_req_addr;
wire [31:0] db0_led_ctrlport_req_data;
wire db0_led_ctrlport_req_rd;
wire db0_led_ctrlport_req_wr;
wire db0_led_ctrlport_resp_ack;
wire [31:0] db0_led_ctrlport_resp_data;
wire [ 1:0] db0_led_ctrlport_resp_status;
wire [19:0] db1_led_ctrlport_req_addr;
wire [31:0] db1_led_ctrlport_req_data;
wire db1_led_ctrlport_req_rd;
wire db1_led_ctrlport_req_wr;
wire db1_led_ctrlport_resp_ack;
wire [31:0] db1_led_ctrlport_resp_data;
wire [ 1:0] db1_led_ctrlport_resp_status;
wire [19:0] pl_term_ctrlport_req_addr;
wire [31:0] pl_term_ctrlport_req_data;
wire pl_term_ctrlport_req_rd;
@@ -458,22 +429,6 @@ module mb_cpld #(
wire [31:0] pl_term_ctrlport_resp_data;
wire [ 1:0] pl_term_ctrlport_resp_status;
wire pl_jtag0_ctrlport_req_rd;
wire pl_jtag0_ctrlport_req_wr;
wire pl_jtag0_ctrlport_resp_ack;
wire [31:0] pl_jtag0_ctrlport_resp_data;
wire [ 1:0] pl_jtag0_ctrlport_resp_status;
wire [19:0] pl_jtag0_ctrlport_req_addr;
wire [31:0] pl_jtag0_ctrlport_req_data;
wire [19:0] pl_jtag1_ctrlport_req_addr;
wire [31:0] pl_jtag1_ctrlport_req_data;
wire pl_jtag1_ctrlport_req_rd;
wire pl_jtag1_ctrlport_req_wr;
wire pl_jtag1_ctrlport_resp_ack;
wire [31:0] pl_jtag1_ctrlport_resp_data;
wire [1:0] pl_jtag1_ctrlport_resp_status;
ctrlport_splitter #(
.NUM_SLAVES (4)
) pl_ctrlport_splitter (
@@ -489,16 +444,16 @@ module mb_cpld #(
.s_ctrlport_resp_ack (pl_ctrlport_resp_ack),
.s_ctrlport_resp_status (pl_ctrlport_resp_status),
.s_ctrlport_resp_data (pl_ctrlport_resp_data),
.m_ctrlport_req_wr ({pl_regs_ctrlport_req_wr, pl_term_ctrlport_req_wr, pl_jtag0_ctrlport_req_wr, pl_jtag1_ctrlport_req_wr}),
.m_ctrlport_req_rd ({pl_regs_ctrlport_req_rd, pl_term_ctrlport_req_rd, pl_jtag0_ctrlport_req_rd, pl_jtag1_ctrlport_req_rd}),
.m_ctrlport_req_addr ({pl_regs_ctrlport_req_addr, pl_term_ctrlport_req_addr, pl_jtag0_ctrlport_req_addr, pl_jtag1_ctrlport_req_addr}),
.m_ctrlport_req_data ({pl_regs_ctrlport_req_data, pl_term_ctrlport_req_data, pl_jtag0_ctrlport_req_data, pl_jtag1_ctrlport_req_data}),
.m_ctrlport_req_wr ({pl_regs_ctrlport_req_wr, db0_led_ctrlport_req_wr, db1_led_ctrlport_req_wr, pl_term_ctrlport_req_wr}),
.m_ctrlport_req_rd ({pl_regs_ctrlport_req_rd, db0_led_ctrlport_req_rd, db1_led_ctrlport_req_rd, pl_term_ctrlport_req_rd}),
.m_ctrlport_req_addr ({pl_regs_ctrlport_req_addr, db0_led_ctrlport_req_addr, db1_led_ctrlport_req_addr, pl_term_ctrlport_req_addr}),
.m_ctrlport_req_data ({pl_regs_ctrlport_req_data, db0_led_ctrlport_req_data, db1_led_ctrlport_req_data, pl_term_ctrlport_req_data}),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack ({pl_regs_ctrlport_resp_ack, pl_term_ctrlport_resp_ack, pl_jtag0_ctrlport_resp_ack, pl_jtag1_ctrlport_resp_ack}),
.m_ctrlport_resp_status ({pl_regs_ctrlport_resp_status, pl_term_ctrlport_resp_status, pl_jtag0_ctrlport_resp_status, pl_jtag1_ctrlport_resp_status}),
.m_ctrlport_resp_data ({pl_regs_ctrlport_resp_data, pl_term_ctrlport_resp_data, pl_jtag0_ctrlport_resp_data, pl_jtag1_ctrlport_resp_data})
.m_ctrlport_resp_ack ({pl_regs_ctrlport_resp_ack, db0_led_ctrlport_resp_ack, db1_led_ctrlport_resp_ack, pl_term_ctrlport_resp_ack}),
.m_ctrlport_resp_status ({pl_regs_ctrlport_resp_status, db0_led_ctrlport_resp_status, db1_led_ctrlport_resp_status, pl_term_ctrlport_resp_status}),
.m_ctrlport_resp_data ({pl_regs_ctrlport_resp_data, db0_led_ctrlport_resp_data, db1_led_ctrlport_resp_data, pl_term_ctrlport_resp_data})
);
pl_cpld_regs #(
@@ -520,47 +475,63 @@ module mb_cpld #(
.ipass_cable_present (ipass_cable_present)
);
ctrlport_to_jtag #(
.BASE_ADDRESS (JTAG_DB0),
.DEFAULT_PRESCALAR (1)
) db0_jtag (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (pl_jtag0_ctrlport_req_wr),
.s_ctrlport_req_rd (pl_jtag0_ctrlport_req_rd),
.s_ctrlport_req_addr (pl_jtag0_ctrlport_req_addr),
.s_ctrlport_req_data (pl_jtag0_ctrlport_req_data),
.s_ctrlport_resp_ack (pl_jtag0_ctrlport_resp_ack),
.s_ctrlport_resp_status (pl_jtag0_ctrlport_resp_status),
.s_ctrlport_resp_data (pl_jtag0_ctrlport_resp_data),
.tck (DB_JTAG_TCK[0]),
.tdi (DB_JTAG_TDI[0]),
.tdo (DB_JTAG_TDO[0]),
.tms (DB_JTAG_TMS[0])
led_control #(
.BASE_ADDRESS (PL_DB0_LED_REGISTERS),
.REGMAP_SIZE (PL_DB0_LED_REGISTERS_SIZE)
) led_control_db0 (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (db0_led_ctrlport_req_wr),
.s_ctrlport_req_rd (db0_led_ctrlport_req_rd),
.s_ctrlport_req_addr (db0_led_ctrlport_req_addr),
.s_ctrlport_req_data (db0_led_ctrlport_req_data),
.s_ctrlport_resp_ack (db0_led_ctrlport_resp_ack),
.s_ctrlport_resp_status (db0_led_ctrlport_resp_status),
.s_ctrlport_resp_data (db0_led_ctrlport_resp_data),
.ch0_rx2_led (CH0_RX2_LED[0]),
.ch0_tx_led (CH0_TX_LED[0]),
.ch0_rx_led (CH0_RX_LED[0]),
.ch1_rx2_led (CH1_RX2_LED[0]),
.ch1_tx_led (CH1_TX_LED[0]),
.ch1_rx_led (CH1_RX_LED[0]),
.ch2_rx2_led (CH2_RX2_LED[0]),
.ch2_tx_led (CH2_TX_LED[0]),
.ch2_rx_led (CH2_RX_LED[0]),
.ch3_rx2_led (CH3_RX2_LED[0]),
.ch3_tx_led (CH3_TX_LED[0]),
.ch3_rx_led (CH3_RX_LED[0])
);
ctrlport_to_jtag #(
.BASE_ADDRESS (JTAG_DB1),
.DEFAULT_PRESCALAR (1)
) db1_jtag (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (pl_jtag1_ctrlport_req_wr),
.s_ctrlport_req_rd (pl_jtag1_ctrlport_req_rd),
.s_ctrlport_req_addr (pl_jtag1_ctrlport_req_addr),
.s_ctrlport_req_data (pl_jtag1_ctrlport_req_data),
.s_ctrlport_resp_ack (pl_jtag1_ctrlport_resp_ack),
.s_ctrlport_resp_status (pl_jtag1_ctrlport_resp_status),
.s_ctrlport_resp_data (pl_jtag1_ctrlport_resp_data),
.tck (DB_JTAG_TCK[1]),
.tdi (DB_JTAG_TDI[1]),
.tdo (DB_JTAG_TDO[1]),
.tms (DB_JTAG_TMS[1])
led_control #(
.BASE_ADDRESS (PL_DB1_LED_REGISTERS),
.REGMAP_SIZE (PL_DB1_LED_REGISTERS_SIZE)
) led_control_db1 (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (db1_led_ctrlport_req_wr),
.s_ctrlport_req_rd (db1_led_ctrlport_req_rd),
.s_ctrlport_req_addr (db1_led_ctrlport_req_addr),
.s_ctrlport_req_data (db1_led_ctrlport_req_data),
.s_ctrlport_resp_ack (db1_led_ctrlport_resp_ack),
.s_ctrlport_resp_status (db1_led_ctrlport_resp_status),
.s_ctrlport_resp_data (db1_led_ctrlport_resp_data),
.ch0_rx2_led (CH0_RX2_LED[1]),
.ch0_tx_led (CH0_TX_LED[1]),
.ch0_rx_led (CH0_RX_LED[1]),
.ch1_rx2_led (CH1_RX2_LED[1]),
.ch1_tx_led (CH1_TX_LED[1]),
.ch1_rx_led (CH1_RX_LED[1]),
.ch2_rx2_led (CH2_RX2_LED[1]),
.ch2_tx_led (CH2_TX_LED[1]),
.ch2_rx_led (CH2_RX_LED[1]),
.ch3_rx2_led (CH3_RX2_LED[1]),
.ch3_tx_led (CH3_TX_LED[1]),
.ch3_rx_led (CH3_RX_LED[1])
);
// Termination of ctrlport request
ctrlport_terminator #(
.START_ADDRESS (JTAG_DB1 + JTAG_DB1_SIZE),
.START_ADDRESS (PL_DB1_LED_REGISTERS + PL_DB1_LED_REGISTERS_SIZE),
.LAST_ADDRESS (2**CTRLPORT_ADDR_W-1)
) pl_terminator (
.ctrlport_clk (clk50),
@@ -682,16 +653,6 @@ module mb_cpld #(
assign PHASE_DAC_MOSI = PS_CPLD_MOSI;
assign PHASE_DAC_CS_N = ps_spi_cs_n_decoded[PS_CS_PHASE_DAC];
// DB EEPROM 0 SPI signals
assign DB_CALEEPROM_SCLK[0] = PS_CPLD_SCLK;
assign DB_CALEEPROM_MOSI[0] = PS_CPLD_MOSI;
assign DB_CALEEPROM_CS_N[0] = ps_spi_cs_n_decoded[PS_CS_DB0_CAL_EEPROM];
// DB EEPROM 1 SPI signals
assign DB_CALEEPROM_SCLK[1] = PS_CPLD_SCLK;
assign DB_CALEEPROM_MOSI[1] = PS_CPLD_MOSI;
assign DB_CALEEPROM_CS_N[1] = ps_spi_cs_n_decoded[PS_CS_DB1_CAL_EEPROM];
// CLK AUX DB SPI signals
assign CLK_DB_SCLK = PS_CPLD_SCLK;
assign CLK_DB_MOSI = PS_CPLD_MOSI;
@@ -702,8 +663,6 @@ module mb_cpld #(
assign PS_CPLD_MISO = (PS_CPLD_CS_N[2:0] == PS_CS_MB_CPLD) ? ps_spi_endpoint_miso :
(PS_CPLD_CS_N[2:0] == PS_CS_LMK32) ? LMK32_MISO :
(PS_CPLD_CS_N[2:0] == PS_CS_TPM) ? TPM_MISO :
(PS_CPLD_CS_N[2:0] == PS_CS_DB0_CAL_EEPROM) ? DB_CALEEPROM_MISO[0] :
(PS_CPLD_CS_N[2:0] == PS_CS_DB1_CAL_EEPROM) ? DB_CALEEPROM_MISO[1] :
(PS_CPLD_CS_N[2:0] == PS_CS_CLK_AUX_DB) ? CLK_DB_MISO :
1'bz; // Default case and PHASE_DAC
@@ -977,7 +936,7 @@ endmodule
//XmlParse xml_on
//<top name="X4XX_MB_CPLD">
//<top name="X440_MB_CPLD">
// <regmapcfg readablestrobes="false">
// <map name="MB_CPLD_PS_REGMAP"/>
// <map name="MB_CPLD_PL_REGMAP"/>
@@ -1011,21 +970,9 @@ endmodule
// All protocol masters controller by this register map are running with a clock frequency of 50 MHz.
// </info>
// <group name="MB_CPLD_PL_WINDOWS">
// <window name="PL_REGISTERS" offset="0x0" size="0x40" targetregmap="PL_CPLD_BASE_REGMAP"/>
// <window name="JTAG_DB0" offset="0x60" size="0x20" targetregmap="JTAG_REGMAP">
// <info>
// JTAG Master connected to first daugherboard's CPLD JTAG interface.
//
// **Use minimum value of 1 for @.JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.**
// </info>
// </window>
// <window name="JTAG_DB1" offset="0x80" size="0x20" targetregmap="JTAG_REGMAP">
// <info>
// JTAG Master connected to second daugherboard's CPLD JTAG interface.
//
// **Use minimum value of 1 for @.JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.**
// </info>
// </window>
// <window name="PL_REGISTERS" offset="0x0" size="0x40" targetregmap="PL_CPLD_BASE_REGMAP"/>
// <window name="PL_DB0_LED_REGISTERS" offset="0x50" size="0x10" targetregmap="LED_SETUP_REGMAP"/>
// <window name="PL_DB1_LED_REGISTERS" offset="0x60" size="0x10" targetregmap="LED_SETUP_REGMAP"/>
// </group>
//</regmap>
//<regmap name="CONSTANTS_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
@@ -1038,10 +985,10 @@ endmodule
// <info>
// This enumeration is used to create the constants held in the basic registers.
// </info>
// <value name="PS_CPLD_SIGNATURE" integer="0x0A522D27"/>
// <value name="PS_CPLD_SIGNATURE" integer="0x0A522D28"/>
// <value name="PL_CPLD_SIGNATURE" integer="0x3FDC5C47"/>
// <value name="CPLD_REVISION" integer="0x21111615"/>
// <value name="OLDEST_CPLD_REVISION" integer="0x20122114"/>
// <value name="CPLD_REVISION" integer="0x22080414"/>
// <value name="OLDEST_CPLD_REVISION" integer="0x22080414"/>
// </enumeratedtype>
// </group>
//</regmap>
top/x400/cpld/quartus/mb_cpld.qpf → top/x400/cpld/x440/quartus/mb_cpld.qpf
View File
top/x400/cpld/quartus/mb_cpld.qsf → top/x400/cpld/x440/quartus/mb_cpld.qsf
+67 -83
View File
@@ -293,74 +293,59 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_CS_N
# Daughterboards' JTAG master interfaces.
set_location_assignment PIN_J12 -to DB_JTAG_TCK[0]
set_location_assignment PIN_G9 -to DB_JTAG_TCK[1]
set_location_assignment PIN_K12 -to DB_JTAG_TDI[0]
set_location_assignment PIN_E13 -to DB_JTAG_TDI[1]
set_location_assignment PIN_H10 -to DB_JTAG_TDO[0]
set_location_assignment PIN_F13 -to DB_JTAG_TDO[1]
set_location_assignment PIN_K11 -to DB_JTAG_TMS[0]
set_location_assignment PIN_G10 -to DB_JTAG_TMS[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[1]
# Daughterboards' Calibration EEPROM SPI interfaces.
set_location_assignment PIN_C9 -to DB_CALEEPROM_CS_N[0]
set_location_assignment PIN_B9 -to DB_CALEEPROM_MISO[0]
set_location_assignment PIN_B10 -to DB_CALEEPROM_MOSI[0]
set_location_assignment PIN_A10 -to DB_CALEEPROM_SCLK[0]
set_location_assignment PIN_B5 -to DB_CALEEPROM_MOSI[1]
set_location_assignment PIN_B6 -to DB_CALEEPROM_SCLK[1]
set_location_assignment PIN_B4 -to DB_CALEEPROM_MISO[1]
set_location_assignment PIN_B3 -to DB_CALEEPROM_CS_N[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[1]
# Daughterboards' Control interfaces.
set_location_assignment PIN_C10 -to DB_CTRL_SCLK[0]
set_location_assignment PIN_A9 -to DB_CTRL_MISO[0]
set_location_assignment PIN_A8 -to DB_ARST[0]
set_location_assignment PIN_A11 -to DB_CTRL_CS_N[0]
set_location_assignment PIN_E8 -to DB_CTRL_MOSI[0]
set_location_assignment PIN_D8 -to DB_REF_CLK[0]
set_location_assignment PIN_A3 -to DB_REF_CLK[1]
set_location_assignment PIN_A4 -to DB_CTRL_MISO[1]
set_location_assignment PIN_D6 -to DB_CTRL_CS_N[1]
set_location_assignment PIN_E6 -to DB_CTRL_SCLK[1]
set_location_assignment PIN_A5 -to DB_CTRL_MOSI[1]
set_location_assignment PIN_B2 -to DB_ARST[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[1]
# DB0 TX/RX LEDS per chan
#-------------------------------------------
set_location_assignment PIN_A11 -to CH0_TX_LED[0]
set_location_assignment PIN_C10 -to CH0_RX_LED[0]
set_location_assignment PIN_A9 -to CH0_RX2_LED[0]
set_location_assignment PIN_E8 -to CH1_TX_LED[0]
set_location_assignment PIN_D8 -to CH1_RX_LED[0]
set_location_assignment PIN_A8 -to CH1_RX2_LED[0]
set_location_assignment PIN_C9 -to CH2_TX_LED[0]
set_location_assignment PIN_A10 -to CH2_RX_LED[0]
set_location_assignment PIN_B10 -to CH2_RX2_LED[0]
set_location_assignment PIN_K12 -to CH3_TX_LED[0]
set_location_assignment PIN_K11 -to CH3_RX_LED[0]
set_location_assignment PIN_J12 -to CH3_RX2_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_TX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX2_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_TX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX2_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_TX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX2_LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_TX_LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX_LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX2_LED[0]
# DB0 TX/RX LEDS per chan
#-------------------------------------------
set_location_assignment PIN_D6 -to CH0_TX_LED[1]
set_location_assignment PIN_E6 -to CH0_RX_LED[1]
set_location_assignment PIN_A4 -to CH0_RX2_LED[1]
set_location_assignment PIN_A5 -to CH1_TX_LED[1]
set_location_assignment PIN_A3 -to CH1_RX_LED[1]
set_location_assignment PIN_B2 -to CH1_RX2_LED[1]
set_location_assignment PIN_B3 -to CH2_TX_LED[1]
set_location_assignment PIN_B6 -to CH2_RX_LED[1]
set_location_assignment PIN_B5 -to CH2_RX2_LED[1]
set_location_assignment PIN_E13 -to CH3_TX_LED[1]
set_location_assignment PIN_G10 -to CH3_RX_LED[1]
set_location_assignment PIN_G9 -to CH3_RX2_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_TX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX2_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_TX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX2_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_TX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX2_LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_TX_LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX_LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX2_LED[1]
# Miscellaneous.
#------------------------------------------
@@ -395,19 +380,19 @@ set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmiWrapper.vhd
set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmi.vhd
set_global_assignment -name QSYS_FILE ../ip/clkctrl/clkctrl.qsys
set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys
set_global_assignment -name SDC_FILE ../db_spi_shared_constants.sdc
set_global_assignment -name SDC_FILE ../mb_cpld.sdc
set_global_assignment -name VERILOG_FILE ../reconfig_engine.v
set_global_assignment -name VERILOG_FILE ../mb_cpld.v
set_global_assignment -name VERILOG_FILE ../ctrlport_to_spi.v
set_global_assignment -name VERILOG_FILE ../ctrlport_to_jtag.v
set_global_assignment -name VERILOG_FILE ../pl_cpld_regs.v
set_global_assignment -name VERILOG_FILE ../pwr_supply_clk_gen.v
set_global_assignment -name VERILOG_FILE ../ps_cpld_regs.v
set_global_assignment -name VERILOG_FILE ../ps_power_regs.v
set_global_assignment -name VERILOG_FILE ../reset_generator.v
set_global_assignment -name VERILOG_FILE ../spi_slave_to_ctrlport_master.v
set_global_assignment -name VERILOG_FILE ../spi_slave.v
set_global_assignment -name SDC_FILE ../common/common.sdc
set_global_assignment -name SDC_FILE ../x440/mb_cpld.sdc
set_global_assignment -name VERILOG_FILE ../x440/mb_cpld.v
set_global_assignment -name VERILOG_FILE ../x440/led_control.v
set_global_assignment -name VERILOG_FILE ../common/reconfig_engine.v
set_global_assignment -name VERILOG_FILE ../common/ctrlport_to_spi.v
set_global_assignment -name VERILOG_FILE ../common/pl_cpld_regs.v
set_global_assignment -name VERILOG_FILE ../common/pwr_supply_clk_gen.v
set_global_assignment -name VERILOG_FILE ../common/ps_cpld_regs.v
set_global_assignment -name VERILOG_FILE ../common/ps_power_regs.v
set_global_assignment -name VERILOG_FILE ../common/reset_generator.v
set_global_assignment -name VERILOG_FILE ../common/spi_slave_to_ctrlport_master.v
set_global_assignment -name VERILOG_FILE ../common/spi_slave.v
set_global_assignment -name QIP_FILE ../ip/pll/pll.qip
set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer_impl.v
set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer.v
@@ -421,12 +406,11 @@ set_global_assignment -name VERILOG_FILE ../../../../lib/control/pulse_synchroni
set_global_assignment -name VERILOG_FILE ../../../../lib/control/handshake.v
set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/axi_bitq.vhd
set_global_assignment -name QIP_FILE ../ip/oddr/oddr.qip
set_global_assignment -name SOURCE_FILE db/mb_cpld.cmp.rdb
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_COLOR 52377 -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_IMPORT_FILE ../ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_IMPORT_FILE ../../ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_LAST_IMPORTED_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix"
set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix"
top/x400/cpld_interface.v
+5 -1
View File
@@ -85,7 +85,11 @@ module cpld_interface (
`include "../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/pl_cpld_regmap_utils.vh"
// Variant-dependent register map.
`include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh"
`ifdef X440
`include "cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh"
`else // Use X410 as the default variant for regmap.
`include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh"
`endif
`include "cpld/regmap/pl_cpld_base_regmap_utils.vh"
//---------------------------------------------------------------------------
top/x400/cpld_interface_regs.v
+5 -1
View File
@@ -46,7 +46,11 @@ module cpld_interface_regs #(
);
// Variant-dependent register map.
`include "regmap/x410/versioning_regs_regmap_utils.vh"
`ifdef X440
`include "regmap/x440/versioning_regs_regmap_utils.vh"
`else // Use X410 as the default variant for regmap.
`include "regmap/x410/versioning_regs_regmap_utils.vh"
`endif
`include "regmap/versioning_utils.vh"
`include "regmap/cpld_interface_regmap_utils.vh"
top/x400/dboards/db_gpio_interface.v
-275
View File
@@ -1,275 +0,0 @@
//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: db_gpio_interface
//
// Description:
// Interface for GPIO interface towards daughterboards.
//
// A ControlPort interface is serialized into bytes along with a valid signal.
// The ControlPort supports write requests only. Byte enables are not supported.
// There is support for timed commands.
// Furthermore there are 4 state wires towards the DB. Ensure an appropriate
// hold time on the states as the transmission happens in pll_ref_clk, which is
// slower than radio_clk. Pulses of e.g. just a single clock cycle may not get
// transferred to the DB.
//
// The 20 available GPIO lines are assigned with
// - 5x empty
// - bytestream direction
// - bytestream valid
// - bytestream data (8 bits)
// - 1x empty
// - db_state (4 bits)
//
`default_nettype none
module db_gpio_interface (
// Clocks and reset
input wire radio_clk,
input wire pll_ref_clk,
// DB state lines (domain: radio_clk)
input wire [ 3:0] db_state,
// Request (domain: radio_clk)
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response (domain: radio_clk)
output wire s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
// GPIO interface (domain: pll_ref_clk)
input wire [19:0] gpio_in,
output wire [19:0] gpio_out,
output wire [19:0] gpio_out_en,
// Version (Constant)
output wire [95:0] version_info
);
`include "../regmap/versioning_regs_regmap_utils.vh"
`include "../regmap/versioning_utils.vh"
//----------------------------------------------------------------------------
// Clock domain crossing (radio_clk -> pll_ref_clk)
//----------------------------------------------------------------------------
// Radio_clk is derived from pll_ref_clk by an integer multiplier and
// originate from the same PLL.
// Therefore the clock crossing can be achieved by using simple registers.
// Static timing analysis will be able to meet setup and hold requirements on
// them.
// holding read and write flags for multiple radio_clk cycles
reg ctrlport_req_wr_hold = 1'b0;
reg ctrlport_req_rd_hold = 1'b0;
reg [19:0] ctrlport_req_addr_prc = 20'b0;
reg [31:0] ctrlport_req_data_prc = 32'b0;
reg ctrlport_req_rd_prc = 1'b0;
reg ctrlport_req_wr_prc = 1'b0;
wire ctrlport_resp_ack_prc;
wire [31:0] ctrlport_resp_data_prc;
wire [ 1:0] ctrlport_resp_status_prc;
reg ctrlport_req_rd_fall = 1'b0;
reg ctrlport_req_wr_fall = 1'b0;
reg [31:0] ctrlport_resp_data_fall = 32'b0;
reg [ 1:0] ctrlport_resp_status_fall = 2'b0;
reg ctrlport_resp_ack_fall = 1'b0;
// Retime signals to falling edge of radio_clk.
// Because radio_clk is more heavily loaded than pll_ref_clk, it arrives at
// the FF's later, which leads to hold time violations when moving signals
// from pll_ref_clk to radio_clk. By sampling on the falling edge of
// radio_clk, we provide (nominally) half a radio_clk period of hold, while
// reducing setup time by half. The late arrival of radio_clk adds back some
// of the lost setup margin.
always @(negedge radio_clk) begin
ctrlport_req_rd_fall <= ctrlport_req_rd_prc;
ctrlport_req_wr_fall <= ctrlport_req_wr_prc;
ctrlport_resp_ack_fall <= ctrlport_resp_ack_prc;
ctrlport_resp_status_fall <= ctrlport_resp_status_prc;
ctrlport_resp_data_fall <= ctrlport_resp_data_prc;
end
always @(posedge radio_clk) begin
if (ctrlport_req_wr_fall) begin
ctrlport_req_wr_hold <= 1'b0;
end else if (s_ctrlport_req_wr) begin
ctrlport_req_wr_hold <= 1'b1;
end
if (ctrlport_req_rd_fall) begin
ctrlport_req_rd_hold <= 1'b0;
end else if (s_ctrlport_req_rd) begin
ctrlport_req_rd_hold <= 1'b1;
end
// capture request address and data
if (s_ctrlport_req_wr || s_ctrlport_req_rd) begin
ctrlport_req_addr_prc <= s_ctrlport_req_addr;
ctrlport_req_data_prc <= s_ctrlport_req_data;
end
end
// capture extended flags in pll_ref_clk domain
always @(posedge pll_ref_clk) begin
ctrlport_req_wr_prc <= ctrlport_req_wr_hold;
ctrlport_req_rd_prc <= ctrlport_req_rd_hold;
end
// search for rising edge in response
reg [1:0] ctrlport_resp_ack_reg = 2'b0;
always @(posedge radio_clk) begin
ctrlport_resp_ack_reg = {ctrlport_resp_ack_reg[0], ctrlport_resp_ack_fall};
end
assign s_ctrlport_resp_ack = ctrlport_resp_ack_reg[0] & ~ctrlport_resp_ack_reg[1];
// capture response data
always @(posedge radio_clk) begin
if (ctrlport_resp_ack_fall) begin
s_ctrlport_resp_status <= ctrlport_resp_status_fall;
s_ctrlport_resp_data <= ctrlport_resp_data_fall;
end
end
// transfer state lines
reg [3:0] db_state_prc = 4'b0;
reg [3:0] db_state_prc_fe = 4'b0;
always @(posedge pll_ref_clk) begin
db_state_prc <= db_state;
end
always @(negedge pll_ref_clk) begin
db_state_prc_fe <= db_state_prc;
end
// transfer reset
reg ctrlport_rst_hold = 1'b0;
reg ctrlport_rst_prc = 1'b0;
reg ctrlport_rst_fall = 1'b0;
always @(posedge radio_clk) begin
if (ctrlport_rst) begin
ctrlport_rst_hold <= 1'b1;
end else if (ctrlport_rst_fall) begin
ctrlport_rst_hold <= 1'b0;
end
end
always @(posedge pll_ref_clk) begin
ctrlport_rst_prc <= ctrlport_rst_hold;
end
always @(negedge radio_clk) begin
ctrlport_rst_fall <= ctrlport_rst_prc;
end
//----------------------------------------------------------------------------
// Ctrlport serializer
//----------------------------------------------------------------------------
wire [7:0] bytestream_data_in;
wire [7:0] bytestream_data_out;
wire bytestream_direction;
wire bytestream_output_enable;
wire bytestream_valid_in;
wire bytestream_valid_out;
ctrlport_byte_serializer serializer_i (
.ctrlport_clk (pll_ref_clk),
.ctrlport_rst (ctrlport_rst_prc),
.s_ctrlport_req_wr (ctrlport_req_wr_prc),
.s_ctrlport_req_rd (ctrlport_req_rd_prc),
.s_ctrlport_req_addr (ctrlport_req_addr_prc),
.s_ctrlport_req_data (ctrlport_req_data_prc),
.s_ctrlport_resp_ack (ctrlport_resp_ack_prc),
.s_ctrlport_resp_status (ctrlport_resp_status_prc),
.s_ctrlport_resp_data (ctrlport_resp_data_prc),
.bytestream_data_in (bytestream_data_in),
.bytestream_valid_in (bytestream_valid_in),
.bytestream_data_out (bytestream_data_out),
.bytestream_valid_out (bytestream_valid_out),
.bytestream_direction (bytestream_direction),
.bytestream_output_enable (bytestream_output_enable)
);
// IOB registers to drive data on the falling edge
reg [7:0] bytestream_data_out_fe;
reg bytestream_direction_fe;
reg bytestream_output_enable_fe;
reg bytestream_valid_out_fe;
// Signals are shifted into a falling edge domain to help meet
// hold requirements at CPLD
always @(negedge pll_ref_clk) begin
if (ctrlport_rst_prc) begin
bytestream_data_out_fe <= 8'b0;
bytestream_valid_out_fe <= 1'b0;
bytestream_direction_fe <= 1'b0;
bytestream_output_enable_fe <= 1'b1;
end else begin
bytestream_data_out_fe <= bytestream_data_out;
bytestream_valid_out_fe <= bytestream_valid_out;
bytestream_direction_fe <= bytestream_direction;
bytestream_output_enable_fe <= bytestream_output_enable;
end
end
//----------------------------------------------------------------------------
// wire assignment
//----------------------------------------------------------------------------
// 5 unused, 10 used, 1 unused and 4 used signals
assign gpio_out = {5'b0, bytestream_direction_fe, bytestream_valid_out_fe, bytestream_data_out_fe, 1'b0, db_state_prc_fe};
assign gpio_out_en = {5'b0, 1'b1, {9 {bytestream_output_enable_fe}}, 1'b0, {4 {1'b1}} };
assign bytestream_valid_in = gpio_in[13];
assign bytestream_data_in = gpio_in[12:5];
//----------------------------------------------------------------------------
// version_info
//----------------------------------------------------------------------------
// Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh
assign version_info = build_component_versions(
DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME,
build_version(
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR,
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR,
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD),
build_version(
DB_GPIO_IFC_CURRENT_VERSION_MAJOR,
DB_GPIO_IFC_CURRENT_VERSION_MINOR,
DB_GPIO_IFC_CURRENT_VERSION_BUILD));
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="VERSIONING_REGS_REGMAP">
// <group name="VERSIONING_CONSTANTS">
// <enumeratedtype name="DB_GPIO_IFC_VERSION" showhex="true">
// <info>
// Daughterboard GPIO interface.{BR/}
// For guidance on when to update these revision numbers,
// please refer to the register map documentation accordingly:
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MAJOR" integer="1"/>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MINOR" integer="0"/>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME" integer="0x20110616"/>
// </enumeratedtype>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/dboards/fbx/clock_en_control.v
+162
View File
@@ -0,0 +1,162 @@
//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: clock_en_control
//
// Description:
// Implements control over clock enable. clk_in is always active.
// The enable controls whether clk_out is active or not.
//
// Parameters:
//
// REG_BASE : Base address to use for registers.
// REG_SIZE : Register space size.
//
`default_nettype none
module clock_en_control #(
parameter BASE_ADDRESS = 0,
parameter REGMAP_SIZE = 8'h4
) (
// Clock and reset
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
// Clock Enable (domain: ctrlport_clk)
input wire clk_in,
output wire clk_out
);
`include "../../../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/clock_en_regmap_utils.vh"
//---------------------------------------------------------------
// ATR memory signals
//---------------------------------------------------------------
reg [31:0] clk_ctrl_reg;
//---------------------------------------------------------------
// Handling of CtrlPort
//---------------------------------------------------------------
// Check of request address is targeted for this module.
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + REGMAP_SIZE);
always @(posedge ctrlport_clk) begin
// reset internal registers and responses
if (ctrlport_rst) begin
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_status <= 2'b0;
s_ctrlport_resp_data <= 32'b0;
clk_ctrl_reg <= 32'b0;
end else begin
// write requests
if (s_ctrlport_req_wr) begin
// always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {32{1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + CLK_EN_CONTROL: begin
clk_ctrl_reg <= s_ctrlport_req_data;
end
// error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// no response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
//req_rd not delayed
end else if (s_ctrlport_req_rd) begin
// default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
s_ctrlport_resp_data <= {32{1'b0}};
case (s_ctrlport_req_addr)
BASE_ADDRESS + CLK_EN_CONTROL: begin
s_ctrlport_resp_data <= clk_ctrl_reg & CLK_EN_CONTROL_MASK;
end
// error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// no response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// no request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
//---------------------------------------------------------------
// Clock Enable
//---------------------------------------------------------------
wire clk_en;
synchronizer synchronizer_i (
.clk(clk_in ),
.rst(1'b0 ),
.in (clk_ctrl_reg[CLK_EN]),
.out(clk_en )
);
BUFGCE BUFGCE_i (
.O (clk_out),
.CE(clk_en ),
.I (clk_in )
);
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="CLK_EN_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="CLK_EN_REGISTERS">
// <info>
// Clock Enable Register
// </info>
// <register name="CLK_EN_CONTROL" size="32" offset="0x0" attributes="Readable|Writable">
// <info>
// This register configures Clock Enable.
// </info>
// <bitfield name="CLK_EN" range="0" initialvalue="0">
// <info>
// Enables the Clock.
// </info>
// </bitfield>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/dboards/fbx/ctrlport_to_i2c_sync_ctrl.v
+618
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@@ -0,0 +1,618 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_to_i2c_sync_ctrl
//
// Description:
//
// This module wraps a I2C WB master and provides a ControlPort interface
// specific to the SYNC IO expander peripheral.
// Sync switch control sequence is as follows:
// 1. Setup core and IO expander:
// a. Write to SETUP_REG
// b. Poll/read from SETUP_STATUS_REG until bit SETUP_STATUS == 1
// 2. Write sync switch configuration to SYNC_[1-5]_REG and RFS_EN_REG
// 3. Initiate io expander config
// a. Write to CONFIG_IO_REG
// b. Poll/read from CONFIG_IO_STATUS_REG until bit CONFIG_IO_STATUS == 1
// Step 1 only needs to happen once after power up or core reset.
// Repeat steps 2 and 3 as needed.
//
// Parameters:
//
// BASE_ADDRESS : Base address for CtrlPort registers.
// PRESCALE : Scaling factor to determine clock speed of I2C SCL.
// Must be divisible by 5.
//
`default_nettype wire
module ctrlport_to_i2c_sync_ctrl #(
parameter BASE_ADDRESS = 0,
parameter [15:0] PRESCALE = 'd500
) (
//---------------------------------------------------------------
// ControlPort Slave
//---------------------------------------------------------------
input wire ctrlport_clk,
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
output reg [31:0] s_ctrlport_resp_data = 32'b0,
//---------------------------------------------------------------
// I2C signals
//---------------------------------------------------------------
// i2c clock line
input wire scl_pad_i, // SCL-line input
output wire scl_pad_o, // SCL-line output
output wire scl_pad_en_o, // SCL-line output enable (active low)
// i2c data line
input wire sda_pad_i, // SDA-line input
output wire sda_pad_o, // SDA-line output
output wire sda_pad_en_o // SDA-line output enable (active low)
);
`include "../../../../lib/rfnoc/core/ctrlport.vh"
`include "../../../../lib/wishbone/i2c_master.vh"
`include "./regmap/rf_sync_regmap_utils.vh"
//---------------------------------------------------------------
// CtrlPort Interface Regs and Triggers to Initiate I2C
//---------------------------------------------------------------
reg [2:0] sync1, sync2, sync3, sync4, sync5;
reg rfs_en;
reg setup_trig; // initiate setup
reg config_io_trig; // configure IO
reg setup_finished;
reg setup_finished_hold;
reg config_io_finished;
reg config_io_finished_hold;
//---------------------------------------------------------------
// WishBone interface
//---------------------------------------------------------------
reg wb_cyc_i; // Active bus cycle
reg wb_we_i = 1'b0; // Write access
reg [2:0] wb_adr_i = 3'b0;
reg [7:0] wb_dat_i = 8'b0;
wire wb_ack_o;
wire [7:0] wb_dat_o;
// Check for address to be in range [base_addr..base_addr+32)
localparam NUM_ADDRESSES = 32;
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
(s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);
// The scaling factor (PRESCALE) of the input clock (ctrlport_clk) to SCL
// isn't direct but instead the relationship between the input clock and
// the state machine inside the i2c_master that controls SCL.
// This state machine has 5 repeated stages per SCL clock cycle so
// the scaling is divided by a factor of 5. The division here
// obscures a need for the user to do an extra step to calculate the
// PRESCALE parameter.
// For example, if a user wants to have an actual rescaling of 1:500
// (SCL to ctrlpor_clk), the PRESCALE parameter is divided by 5
// here so the i2c_master prescale value is set to 100.
if (PRESCALE % 5 != 0) begin : gen_assertion
ERROR_PRESCALE_must_be_div_by_5();
end
// constants to configure wb i2c master core
localparam PRESCALE_5 = PRESCALE/5;
localparam PRER_LO_CONST = PRESCALE_5[7:0];
localparam PRER_HI_CONST = PRESCALE_5[15:8];
//constants for interfacing with i2c master core
localparam I2C_WR = 1'b0;
localparam I2C_RD = 1'b1;
localparam SYNC_IO_SLV_ADR = 7'h20;
// CtrlPort Interface
// configure sync switch IO and trigger I2C transactions
always @(posedge ctrlport_clk) begin
// Reset internal registers and responses
if (ctrlport_rst) begin
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_status <= 2'b0;
s_ctrlport_resp_data <= 32'b0;
setup_trig <= 1'b0;
config_io_trig <= 1'b0;
setup_finished_hold <= 1'b0;
config_io_finished_hold <= 1'b0;
sync1 <= 3'b0;
sync2 <= 3'b0;
sync3 <= 3'b0;
sync4 <= 3'b0;
sync5 <= 3'b0;
rfs_en <= 1'b0;
end else begin
// Only ack under certain conditions
s_ctrlport_resp_ack <= 1'b0;
if (setup_finished) begin
setup_finished_hold <= 1'b1;
end
if (config_io_finished) begin
config_io_finished_hold <= 1'b1;
end
if (s_ctrlport_req_wr) begin // Write requests
// if address is normal ctrlport, immediately ack
if (address_in_range) begin
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
end
case (s_ctrlport_req_addr)
BASE_ADDRESS + SYNC_1_REG: begin
sync1 <= s_ctrlport_req_data[2:0];
end
BASE_ADDRESS + SYNC_2_REG: begin
sync2 <= s_ctrlport_req_data[2:0];
end
BASE_ADDRESS + SYNC_3_REG: begin
sync3 <= s_ctrlport_req_data[2:0];
end
BASE_ADDRESS + SYNC_4_REG: begin
sync4 <= s_ctrlport_req_data[2:0];
end
BASE_ADDRESS + SYNC_5_REG: begin
sync5 <= s_ctrlport_req_data[2:0];
end
BASE_ADDRESS + RFS_EN_REG: begin
rfs_en <= s_ctrlport_req_data[0];
end
//initialize SYNC_IO peripheral
BASE_ADDRESS + SETUP_REG: begin
setup_trig <= 1'b1;
setup_finished_hold <= 1'b0;
end
//configure IO
BASE_ADDRESS + CONFIG_IO_REG: begin
config_io_trig <= 1'b1;
config_io_finished_hold <= 1'b0;
end
endcase
// Read requests
end else if (s_ctrlport_req_rd) begin
// Acknowledge by default
if (address_in_range) begin
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
end
case (s_ctrlport_req_addr)
BASE_ADDRESS + SYNC_1_REG: begin
s_ctrlport_resp_data[2:0] <= sync1;
end
BASE_ADDRESS + SYNC_2_REG: begin
s_ctrlport_resp_data[2:0] <= sync2;
end
BASE_ADDRESS + SYNC_3_REG: begin
s_ctrlport_resp_data[2:0] <= sync3;
end
BASE_ADDRESS + SYNC_4_REG: begin
s_ctrlport_resp_data[2:0] <= sync4;
end
BASE_ADDRESS + SYNC_5_REG: begin
s_ctrlport_resp_data[2:0] <= sync5;
end
BASE_ADDRESS + RFS_EN_REG: begin
s_ctrlport_resp_data[2:0] <= {2'b00, rfs_en};
end
BASE_ADDRESS + SETUP_STATUS_REG: begin
s_ctrlport_resp_data[2:0] <= {2'b00, setup_finished_hold};
if(setup_finished_hold) begin
setup_trig <= 1'b0;
end
end
BASE_ADDRESS + CONFIG_IO_STATUS_REG: begin
s_ctrlport_resp_data[2:0] <= {2'b00, config_io_finished_hold};
if(config_io_finished_hold) begin
config_io_trig <= 1'b0;
end
end
// Respond with 0
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
end
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_data <= 32'b0;
end
endcase
// No request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end // always
// state machine for I2C Write Transactions and WB Controls
localparam I2C_IDLE = 0;
localparam I2C_PRE_LO = 1;
localparam I2C_PRE_HI = 2;
localparam I2C_EN = 3;
localparam I2C_TXR = 4;
localparam I2C_CR = 5;
localparam I2C_TIP_START = 6;
localparam I2C_TIP = 7;
localparam I2C_TIP_FIN = 8;
reg i2c_tip_fin; // indicates transfer is finished
reg i2c_master_en; // indicates i2c master setup and enabled
reg [3:0] i2c_state;
wire wb_cyc_valid; // determines what states wb_cyc_i should be high
reg i2c_wr; //trigger an i2c wr cmd
reg i2c_core_setup; //trigger i2c master setup
reg [7:0] wb_txr;
reg [7:0] wb_cr;
assign wb_cyc_valid = (i2c_state >= I2C_PRE_LO ) && (i2c_state < I2C_TIP_FIN);
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
i2c_state <= I2C_IDLE;
wb_cyc_i <= 1'b0;
wb_we_i <= 1'b0;
wb_adr_i <= 3'b0;
wb_dat_i <= 8'b0;
i2c_tip_fin <= 1'b0;
i2c_master_en <= 1'b0;
//more regs need to be set here.
end
else begin
//handle wb_cyc_i for all states. dependent on i2c transaction states
//and wb_ack_o
if (wb_cyc_i) begin
if (wb_ack_o) begin
wb_cyc_i <= 1'b0;
end
end else begin
if (wb_cyc_valid) begin
wb_cyc_i <= 1'b1;
end
end
case(i2c_state)
I2C_IDLE: begin
i2c_tip_fin <= 1'b0;
if (i2c_wr) begin
i2c_state <= I2C_TXR;
end
else if (i2c_core_setup) begin
i2c_state <= I2C_PRE_LO;
end
end //I2C_IDLE
//begin cases to setup i2c master core
I2C_PRE_LO: begin
wb_adr_i <= WB_PRER_LO;
wb_dat_i <= PRER_LO_CONST;
wb_we_i <= 1'b1;
if (wb_ack_o) begin
i2c_state <= I2C_PRE_HI;
end
end
I2C_PRE_HI: begin
wb_adr_i <= WB_PRER_HI;
wb_dat_i <= PRER_HI_CONST;
wb_we_i <= 1'b1;
if (wb_ack_o) begin
i2c_state <= I2C_EN;
end
end
I2C_EN: begin
wb_adr_i <= WB_CTR;
wb_dat_i <= WB_CORE_EN;
wb_we_i <= 1'b1;
i2c_master_en <= 1'b1;
if (wb_ack_o) begin
i2c_state <= I2C_IDLE;
end
end
//end cases to setup i2c master core
//begin cases to initiate i2c write transfer
I2C_TXR: begin
wb_adr_i <= WB_TXR;
wb_dat_i <= wb_txr;
wb_we_i <= 1'b1;
if (wb_ack_o) begin
i2c_state <= I2C_CR;
end
end
I2C_CR: begin
wb_adr_i <= WB_CR;
wb_dat_i <= wb_cr;
wb_we_i <= 1'b1;
if (wb_ack_o) begin
i2c_state <= I2C_TIP_START;
end
end
I2C_TIP_START: begin
wb_adr_i <= WB_SR;
wb_dat_i <= 8'b0;
wb_we_i <= 1'b0;
if (wb_ack_o && wb_dat_o[1]) begin
i2c_state <= I2C_TIP;
end
end
I2C_TIP: begin //TIP transfer in progress
wb_adr_i <= WB_SR;
wb_dat_i <= 8'b0;
wb_we_i <= 1'b0;
if (wb_ack_o && !wb_dat_o[1]) begin
i2c_state <= I2C_TIP_FIN;
i2c_tip_fin <= 1'b1; //pulse this as we transition to final state
end
end
I2C_TIP_FIN: begin
i2c_tip_fin <= 1'b0;
if (!i2c_wr) begin
i2c_state <= I2C_IDLE;
end
end
//end cases to initiate i2c write transfer
//default case, just go to I2C_IDLE
default : begin
i2c_state <= I2C_IDLE;
end
endcase
end
end //always
// i2c master top controller state machine
localparam IDLE = 0;
localparam EN = 1;
localparam IO_EXP_CONFIG_1 = 2;
localparam IO_EXP_CONFIG_2 = 3;
localparam IO_EXP_CONFIG_3 = 4;
localparam IO_EXP_CONFIG_4 = 5;
localparam IO_EXP_FIN = 6;
wire [15:0] io_config;
assign io_config = { rfs_en, sync5, sync4, sync3, sync2, sync1 };
reg [2:0] master_state;
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
master_state <= IDLE;
wb_txr <= 8'b0;
wb_cr <= 8'b0;
i2c_wr <= 1'b0;
setup_finished <= 1'b0;
config_io_finished <= 1'b0;
i2c_core_setup <= 1'b0;
end
else begin
case(master_state)
IDLE: begin
i2c_wr <= 1'b0;
setup_finished <= 1'b0;
config_io_finished <= 1'b0;
i2c_core_setup <= 1'b0;
if (setup_trig) begin
master_state <= EN;
end
else if (config_io_trig) begin
master_state <= IO_EXP_CONFIG_1;
end
end
EN: begin //all the prescale and enable setup happens in i2c_state machine
i2c_core_setup <= 1'b1; //triggers setup sequence in i2c state machine.
i2c_wr <= 1'b0;
if (i2c_master_en) begin //indicates setup sequence finished
master_state <= IO_EXP_CONFIG_1;
end
end
IO_EXP_CONFIG_1: begin //first stage of setting up IO EXP with startup configurations
wb_txr <= { SYNC_IO_SLV_ADR, I2C_WR};
wb_cr <= CR_START_AND_WRITE;
if (i2c_tip_fin) begin //when transfer is done, i2c_wr is disabled
i2c_wr <= 1'b0;
master_state <= IO_EXP_CONFIG_2;
end else begin
i2c_wr <= 1'b1;
end
end
IO_EXP_CONFIG_2: begin
if (setup_trig) begin
wb_txr <= IO_EXP_CONFIG0_REG; //CONFIG0 reg is what we set to configure I/O as output
end else if (config_io_trig) begin
wb_txr <= IO_EXP_OUTPUT_PORT0_REG;
end
wb_cr <= CR_WRITE;
if (i2c_tip_fin) begin //when transfer is done, i2c_wr is disabled
i2c_wr <= 1'b0;
master_state <= IO_EXP_CONFIG_3;
end else begin
i2c_wr <= 1'b1;
end
end
IO_EXP_CONFIG_3: begin
if (setup_trig) begin
wb_txr <= 1'b0;
end else if (config_io_trig) begin
wb_txr <= io_config[7:0];
end
wb_cr <= CR_WRITE;
if (i2c_tip_fin) begin //when transfer is done, i2c_wr is disabled
i2c_wr <= 1'b0;
master_state <= IO_EXP_CONFIG_4;
end else begin
i2c_wr <= 1'b1;
end
end
IO_EXP_CONFIG_4: begin
if (setup_trig) begin
wb_txr <= 1'b0;
end else if (config_io_trig) begin
wb_txr <= io_config[15:8];
end
wb_cr <= CR_WRITE_AND_STOP;
if (i2c_tip_fin) begin //when transfer is done, i2c_wr is disabled
i2c_wr <= 1'b0;
setup_finished <= setup_trig;
config_io_finished <= config_io_trig;
master_state <= IO_EXP_FIN;
end else begin
i2c_wr <= 1'b1;
end
end
IO_EXP_FIN : begin //final state to make sure triggers are unset before returning to IDLE;
i2c_wr <= 1'b0;
setup_finished <= 1'b0;
config_io_finished <= 1'b0;
if (!setup_trig && !config_io_trig) begin
master_state <= IDLE;
end
end
default : begin
master_state <= IDLE;
end
endcase
end
end //always
//wishbone-based i2c core
i2c_master_top #(
.ARST_LVL(1)
) i2c_master (
.wb_clk_i(ctrlport_clk),
.wb_rst_i(ctrlport_rst),
.arst_i(1'b0),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i),
.wb_stb_i(wb_cyc_i),
.wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o),
.wb_inta_o(),
.scl_pad_i(scl_pad_i),
.scl_pad_o(scl_pad_o),
.scl_padoen_o(scl_pad_en_o),
.sda_pad_i(sda_pad_i),
.sda_pad_o(sda_pad_o),
.sda_padoen_o(sda_pad_en_o)
);
endmodule
//XmlParse xml_on
//<regmap name="RF_SYNC_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="RF_SYNC_REGISTERS">
// <info>
// Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1
// switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for
// all four switches are not considered time critical controls, and are hence driven by a
// TCA6416A I/O expander controlled via I2C.
// This register map controls that I/O expander. The first 6 registers in
// this space set the values of the 5 3-pin sync switches and then an
// RFS enable bit. The 2 additional registers trigger a init sequence for
// the expander peripheral and configuring the I/O with the contents of
// the value registers both with a series of I2C commands.
// </info>
// <regtype name="SYNC_SWITCH" size="32" attributes="Readable|Writable">
// <info>
// Sets I/O to control Sync Switch.
// </info>
// <bitfield name="CONTROL_PIN_V1" range="0" initialvalue="0"/>
// <bitfield name="CONTROL_PIN_V2" range="1" initialvalue="0"/>
// <bitfield name="CONTROL_PIN_V3" range="2" initialvalue="0"/>
// </regtype>
// <register name="SYNC_1_REG" offset="0x00" typename="SYNC_SWITCH">
// <info>
// Sets I/O state to control Sync Switch 1.
// </info>
// </register>
// <register name="SYNC_2_REG" offset="0x04" typename="SYNC_SWITCH">
// <info>
// Sets I/O state to control Sync Switch 2.
// </info>
// </register>
// <register name="SYNC_3_REG" offset="0x08" typename="SYNC_SWITCH">
// <info>
// Sets I/O state to control Sync Switch 3.
// </info>
// </register>
// <register name="SYNC_4_REG" offset="0x0C" typename="SYNC_SWITCH">
// <info>
// Sets I/O state to control Sync Switch 4.
// </info>
// </register>
// <register name="SYNC_5_REG" offset="0x10" typename="SYNC_SWITCH">
// <info>
// Sets I/O state to control Sync Switch 5.
// </info>
// </register>
// <register name="RFS_EN_REG" offset="0x014" size="32" attributes="Readable|Writable">
// <info>
// Sets I/O state to control RFS Enable.
// </info>
// <bitfield name="RFS_EN_PIN" range="0" initialvalue="0" />
// </register>
// <register name="SETUP_REG" offset="0x18" size="32" attributes="Writable">
// <info>
// Write to this register to trigger initialization sequence of
// I2C Master core and TCA6416A I/O expander peripheral.
// </info>
// <bitfield name="SETUP_TRIG" range="0" initialvalue="0"/>
// </register>
// <register name="SETUP_STATUS_REG" offset="0x18" size="32" attributes="Readable">
// <info>
// Read from this register to check the status of setup.
// </info>
// <bitfield name="SETUP_STATUS" range="0" initialvalue="0"/>
// </register>
// <register name="CONFIG_IO_REG" offset="0x1C" size="32" attributes="Writable">
// <info>
// Write to this register to trigger I/O configuration I2C sequence of
// TCA6416A I/O expander peripheral.
// Read from this register to check the status of reconfiguring the setup.
// </info>
// <bitfield name="CONFIG_IO_TRIG" range="0" initialvalue="0"/>
// </register>
// <register name="CONFIG_IO_STATUS_REG" offset="0x1C" size="32" attributes="Readable">
// <info>
// Read from this register to check the status of reconfiguring the setup.
// </info>
// <bitfield name="CONFIG_IO_STATUS" range="0" initialvalue="0"/>
// </register>
//
// <enumeratedtype name="IO_EXPANDER_REGISTER_ADRS">
// <info>
// This is not a register spaces for this ctrlport interface but
// instead register addresses on the TCA6416A. Therefore, we will just
// define an enum with these addresses so there is no clash with the
// above ctrlport regmap.
// </info>
// <value name="IO_EXP_INPUT_PORT0_REG" integer="0"/>
// <value name="IO_EXP_INPUT_PORT1_REG" integer="1"/>
// <value name="IO_EXP_OUTPUT_PORT0_REG" integer="2"/>
// <value name="IO_EXP_OUTPUT_PORT1_REG" integer="3"/>
// <value name="IO_EXP_POLARITY_INV0_REG" integer="4"/>
// <value name="IO_EXP_POLARITY_INV1_REG" integer="5"/>
// <value name="IO_EXP_CONFIG0_REG" integer="6"/>
// <value name="IO_EXP_CONFIG1_REG" integer="7"/>
// </enumeratedtype>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/dboards/fbx/db_gpio_interface.v
+444
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@@ -0,0 +1,444 @@
//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: db_gpio_interface
//
// Description:
// Interface for GPIO interface towards FBX daughterboards.
//
//
// The 20 available GPIO lines are assigned with
// - 12x RF switches(3x per channel)
// - 2x I2C to Sync switches IO Expander
// - 6x empty
//
`default_nettype none
module db_gpio_interface #(
parameter LED_REGISTER_ADDRESS = 0
) (
// Clocks and reset
input wire radio_clk,
input wire pll_ref_clk,
input wire in_sync_clk,
output wire out_sync_clk,
// DB state lines (domain: radio_clk)
input wire [ 7:0] db_state,
// Request (domain: radio_clk)
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response (domain: radio_clk)
output wire s_ctrlport_resp_ack,
output wire [ 1:0] s_ctrlport_resp_status,
output wire [31:0] s_ctrlport_resp_data,
// ControlPort request to CPLD (domain: radio_clk)
output wire m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [19:0] m_ctrlport_req_addr,
output wire [31:0] m_ctrlport_req_data,
output wire [ 3:0] m_ctrlport_req_byte_en,
// ControlPort response from CPLD (domain: radio_clk)
input wire m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [31:0] m_ctrlport_resp_data,
// GPIO interface (domain: pll_ref_clk)
input wire [19:0] gpio_in,
output wire [19:0] gpio_out,
output wire [19:0] gpio_out_en,
// Version (Constant)
output wire [95:0] version_info
);
`include "../../regmap/x440/versioning_regs_regmap_utils.vh"
`include "regmap/fbx_ctrl_regmap_utils.vh"
`include "../../regmap/versioning_utils.vh"
//----------------------------------------------------------------------------
// Radio_clk -> pll_ref_clk clock crossing
//----------------------------------------------------------------------------
wire ctrlport_rst_prc;
wire ctrlport_req_wr_prc;
wire ctrlport_req_rd_prc;
wire [19:0] ctrlport_req_addr_prc;
wire [31:0] ctrlport_req_data_prc;
wire ctrlport_resp_ack_prc;
wire [ 1:0] ctrlport_resp_status_prc;
wire [31:0] ctrlport_resp_data_prc;
ctrlport_clk_cross core_clk_cross_slave (
.rst (ctrlport_rst),
.s_ctrlport_clk (radio_clk),
.s_ctrlport_req_wr (s_ctrlport_req_wr),
.s_ctrlport_req_rd (s_ctrlport_req_rd),
.s_ctrlport_req_addr (s_ctrlport_req_addr),
.s_ctrlport_req_portid (),
.s_ctrlport_req_rem_epid (),
.s_ctrlport_req_rem_portid (),
.s_ctrlport_req_data (s_ctrlport_req_data),
.s_ctrlport_req_byte_en (),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
.s_ctrlport_resp_status (s_ctrlport_resp_status),
.s_ctrlport_resp_data (s_ctrlport_resp_data),
.m_ctrlport_clk (pll_ref_clk),
.m_ctrlport_req_wr (ctrlport_req_wr_prc),
.m_ctrlport_req_rd (ctrlport_req_rd_prc),
.m_ctrlport_req_addr (ctrlport_req_addr_prc),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (ctrlport_req_data_prc),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (ctrlport_resp_ack_prc),
.m_ctrlport_resp_status (ctrlport_resp_status_prc),
.m_ctrlport_resp_data (ctrlport_resp_data_prc)
);
reset_sync reset_sync_prc (
.clk (pll_ref_clk),
.reset_in (ctrlport_rst),
.reset_out (ctrlport_rst_prc)
);
wire [7:0] db_state_prc;
handshake #(
.WIDTH (8)
) synchronizer_db_state (
.clk_a (radio_clk),
.rst_a (ctrlport_rst),
.valid_a (1'b1),
.data_a (db_state),
.busy_a (),
.clk_b (pll_ref_clk),
.valid_b (),
.data_b (db_state_prc)
);
//----------------------------------------------------------------------------
// CtrlPort Splitter
//----------------------------------------------------------------------------
wire [19:0] rf_atr_ctrlport_req_addr;
wire [31:0] rf_atr_ctrlport_req_data;
wire rf_atr_ctrlport_req_rd;
wire rf_atr_ctrlport_req_wr;
wire rf_atr_ctrlport_resp_ack;
wire [31:0] rf_atr_ctrlport_resp_data;
wire [ 1:0] rf_atr_ctrlport_resp_status;
wire [19:0] sync_ctrlport_req_addr;
wire [31:0] sync_ctrlport_req_data;
wire sync_ctrlport_req_rd;
wire sync_ctrlport_req_wr;
wire sync_ctrlport_resp_ack;
wire [31:0] sync_ctrlport_resp_data;
wire [ 1:0] sync_ctrlport_resp_status;
wire [19:0] led_atr_ctrlport_req_addr;
wire [31:0] led_atr_ctrlport_req_data;
wire led_atr_ctrlport_req_rd;
wire led_atr_ctrlport_req_wr;
wire led_atr_ctrlport_resp_ack;
wire [31:0] led_atr_ctrlport_resp_data;
wire [ 1:0] led_atr_ctrlport_resp_status;
wire [19:0] clk_en_ctrlport_req_addr;
wire [31:0] clk_en_ctrlport_req_data;
wire clk_en_ctrlport_req_rd;
wire clk_en_ctrlport_req_wr;
wire clk_en_ctrlport_resp_ack;
wire [31:0] clk_en_ctrlport_resp_data;
wire [ 1:0] clk_en_ctrlport_resp_status;
ctrlport_splitter #(
.NUM_SLAVES (4)
) fbx_ctrlport_splitter (
.ctrlport_clk (pll_ref_clk),
.ctrlport_rst (ctrlport_rst_prc),
.s_ctrlport_req_wr (ctrlport_req_wr_prc),
.s_ctrlport_req_rd (ctrlport_req_rd_prc),
.s_ctrlport_req_addr (ctrlport_req_addr_prc),
.s_ctrlport_req_data (ctrlport_req_data_prc),
.s_ctrlport_req_byte_en (4'hF),
.s_ctrlport_req_has_time (1'b0),
.s_ctrlport_req_time (64'b0),
.s_ctrlport_resp_ack (ctrlport_resp_ack_prc),
.s_ctrlport_resp_status (ctrlport_resp_status_prc),
.s_ctrlport_resp_data (ctrlport_resp_data_prc),
.m_ctrlport_req_wr ({ clk_en_ctrlport_req_wr, led_atr_ctrlport_req_wr, sync_ctrlport_req_wr, rf_atr_ctrlport_req_wr }),
.m_ctrlport_req_rd ({ clk_en_ctrlport_req_rd, led_atr_ctrlport_req_rd, sync_ctrlport_req_rd, rf_atr_ctrlport_req_rd }),
.m_ctrlport_req_addr ({ clk_en_ctrlport_req_addr, led_atr_ctrlport_req_addr, sync_ctrlport_req_addr, rf_atr_ctrlport_req_addr }),
.m_ctrlport_req_data ({ clk_en_ctrlport_req_data, led_atr_ctrlport_req_data, sync_ctrlport_req_data, rf_atr_ctrlport_req_data }),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack ({ clk_en_ctrlport_resp_ack, led_atr_ctrlport_resp_ack, sync_ctrlport_resp_ack, rf_atr_ctrlport_resp_ack }),
.m_ctrlport_resp_status ({ clk_en_ctrlport_resp_status, led_atr_ctrlport_resp_status, sync_ctrlport_resp_status, rf_atr_ctrlport_resp_status }),
.m_ctrlport_resp_data ({ clk_en_ctrlport_resp_data, led_atr_ctrlport_resp_data, sync_ctrlport_resp_data, rf_atr_ctrlport_resp_data })
);
//----------------------------------------------------------------------------
// Switch Control
//----------------------------------------------------------------------------
wire rf0_tx_rx_rfs, rf0_rx_rfs, rf0_tdds;
wire rf1_tx_rx_rfs, rf1_rx_rfs, rf1_tdds;
wire rf2_tx_rx_rfs, rf2_rx_rfs, rf2_tdds;
wire rf3_tx_rx_rfs, rf3_rx_rfs, rf3_tdds;
rf_atr_control #(
.REG_BASE (RF_ATR_REGS),
.REG_SIZE (RF_ATR_REGS_SIZE)
) rf_atr_control_i (
.ctrlport_clk (pll_ref_clk),
.ctrlport_rst (ctrlport_rst_prc),
.s_ctrlport_req_wr (rf_atr_ctrlport_req_wr),
.s_ctrlport_req_rd (rf_atr_ctrlport_req_rd),
.s_ctrlport_req_addr (rf_atr_ctrlport_req_addr),
.s_ctrlport_req_data (rf_atr_ctrlport_req_data),
.s_ctrlport_resp_ack (rf_atr_ctrlport_resp_ack),
.s_ctrlport_resp_status (rf_atr_ctrlport_resp_status),
.s_ctrlport_resp_data (rf_atr_ctrlport_resp_data),
.db_state (db_state_prc),
.rf0_tx_rx_rfs (rf0_tx_rx_rfs),
.rf0_rx_rfs (rf0_rx_rfs),
.rf0_tdds (rf0_tdds),
.rf1_tx_rx_rfs (rf1_tx_rx_rfs),
.rf1_rx_rfs (rf1_rx_rfs),
.rf1_tdds (rf1_tdds),
.rf2_tx_rx_rfs (rf2_tx_rx_rfs),
.rf2_rx_rfs (rf2_rx_rfs),
.rf2_tdds (rf2_tdds),
.rf3_tx_rx_rfs (rf3_tx_rx_rfs),
.rf3_rx_rfs (rf3_rx_rfs),
.rf3_tdds (rf3_tdds)
);
//----------------------------------------------------------------------------
// LED Control
//----------------------------------------------------------------------------
wire cpld_ctrlport_req_wr;
wire cpld_ctrlport_req_rd;
wire [19:0] cpld_ctrlport_req_addr;
wire [31:0] cpld_ctrlport_req_data;
wire [ 3:0] cpld_ctrlport_req_byte_en;
wire cpld_ctrlport_resp_ack;
wire [ 1:0] cpld_ctrlport_resp_status;
wire [31:0] cpld_ctrlport_resp_data;
led_atr_control #(
.LED_REGISTER_ADDRESS (LED_REGISTER_ADDRESS),
.REG_BASE (LED_ATR_REGS),
.REG_SIZE (LED_ATR_REGS_SIZE)
) led_atr_control_i (
.ctrlport_clk (pll_ref_clk),
.ctrlport_rst (ctrlport_rst_prc),
.s_ctrlport_req_wr (led_atr_ctrlport_req_wr),
.s_ctrlport_req_rd (led_atr_ctrlport_req_rd),
.s_ctrlport_req_addr (led_atr_ctrlport_req_addr),
.s_ctrlport_req_data (led_atr_ctrlport_req_data),
.s_ctrlport_resp_ack (led_atr_ctrlport_resp_ack),
.s_ctrlport_resp_status (led_atr_ctrlport_resp_status),
.s_ctrlport_resp_data (led_atr_ctrlport_resp_data),
.db_state (db_state_prc),
.m_ctrlport_req_wr (cpld_ctrlport_req_wr),
.m_ctrlport_req_rd (cpld_ctrlport_req_rd),
.m_ctrlport_req_addr (cpld_ctrlport_req_addr),
.m_ctrlport_req_data (cpld_ctrlport_req_data),
.m_ctrlport_req_byte_en (cpld_ctrlport_req_byte_en),
.m_ctrlport_resp_ack (cpld_ctrlport_resp_ack),
.m_ctrlport_resp_status (cpld_ctrlport_resp_status),
.m_ctrlport_resp_data (cpld_ctrlport_resp_data)
);
ctrlport_clk_cross core_clk_cross_cpld_master (
.rst (ctrlport_rst_prc),
.s_ctrlport_clk (pll_ref_clk),
.s_ctrlport_req_wr (cpld_ctrlport_req_wr),
.s_ctrlport_req_rd (cpld_ctrlport_req_rd),
.s_ctrlport_req_addr (cpld_ctrlport_req_addr),
.s_ctrlport_req_portid (),
.s_ctrlport_req_rem_epid (),
.s_ctrlport_req_rem_portid (),
.s_ctrlport_req_data (cpld_ctrlport_req_data),
.s_ctrlport_req_byte_en (cpld_ctrlport_req_byte_en),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_resp_ack (cpld_ctrlport_resp_ack),
.s_ctrlport_resp_status (cpld_ctrlport_resp_status),
.s_ctrlport_resp_data (cpld_ctrlport_resp_data),
.m_ctrlport_clk (radio_clk),
.m_ctrlport_req_wr (m_ctrlport_req_wr),
.m_ctrlport_req_rd (m_ctrlport_req_rd),
.m_ctrlport_req_addr (m_ctrlport_req_addr),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (m_ctrlport_req_data),
.m_ctrlport_req_byte_en (m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
.m_ctrlport_resp_status (m_ctrlport_resp_status),
.m_ctrlport_resp_data (m_ctrlport_resp_data)
);
//----------------------------------------------------------------------------
// I2C Control
//----------------------------------------------------------------------------
wire i2c_scl_i, i2c_scl_o, i2c_scl_en_o;
wire i2c_sda_i, i2c_sda_o, i2c_sda_en_o;
ctrlport_to_i2c_sync_ctrl #(
.BASE_ADDRESS(RF_SYNC_REGS),
.PRESCALE(1000)
) ctrlport_to_i2c_inst (
.ctrlport_clk (pll_ref_clk),
.ctrlport_rst (ctrlport_rst_prc),
.s_ctrlport_req_wr (sync_ctrlport_req_wr),
.s_ctrlport_req_rd (sync_ctrlport_req_rd),
.s_ctrlport_req_addr (sync_ctrlport_req_addr),
.s_ctrlport_req_data (sync_ctrlport_req_data),
.s_ctrlport_resp_ack (sync_ctrlport_resp_ack),
.s_ctrlport_resp_status (sync_ctrlport_resp_status),
.s_ctrlport_resp_data (sync_ctrlport_resp_data),
.scl_pad_i (i2c_scl_i),
.scl_pad_o (i2c_scl_o),
.scl_pad_en_o (i2c_scl_en_o),
.sda_pad_i (i2c_sda_i),
.sda_pad_o (i2c_sda_o),
.sda_pad_en_o (i2c_sda_en_o)
);
//----------------------------------------------------------------------------
// Sync Clock Enable
//----------------------------------------------------------------------------
clock_en_control #(
.BASE_ADDRESS(SYNC_CLK_EN_REGS)
) clock_en_control_inst (
.ctrlport_clk (pll_ref_clk),
.ctrlport_rst (ctrlport_rst_prc),
.s_ctrlport_req_wr (clk_en_ctrlport_req_wr),
.s_ctrlport_req_rd (clk_en_ctrlport_req_rd),
.s_ctrlport_req_addr (clk_en_ctrlport_req_addr),
.s_ctrlport_req_data (clk_en_ctrlport_req_data),
.s_ctrlport_resp_ack (clk_en_ctrlport_resp_ack),
.s_ctrlport_resp_status (clk_en_ctrlport_resp_status),
.s_ctrlport_resp_data (clk_en_ctrlport_resp_data),
.clk_in (in_sync_clk),
.clk_out (out_sync_clk)
);
//----------------------------------------------------------------------------
// wire assignment
//----------------------------------------------------------------------------
// RFS1, RFS2, RFS3, RFS4, RFS5, RFS6, RFS7, RFS8, TDDS1, TDDS2, TDDS3, TDDS4,
// 2 unused, 2 for I2C, 4 unused.
assign i2c_sda_i = gpio_in[4];
assign i2c_scl_i = gpio_in[5];
assign gpio_out = {rf0_tx_rx_rfs, rf0_rx_rfs,
rf1_tx_rx_rfs, rf1_rx_rfs,
rf2_tx_rx_rfs, rf2_rx_rfs,
rf3_tx_rx_rfs, rf3_rx_rfs,
rf0_tdds, rf1_tdds,
rf2_tdds, rf3_tdds,
2'b0, // Unused
i2c_scl_o, i2c_sda_o, // I2C
4'b0 // Unused
};
assign gpio_out_en = {12'hFFF, // Switches
2'b0, // Unused
~i2c_scl_en_o, ~i2c_sda_en_o, // I2C enables tri-state when HIGH
4'b0 // Unused
};
//----------------------------------------------------------------------------
// version_info
//----------------------------------------------------------------------------
// Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh
assign version_info = build_component_versions(
DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME,
build_version(
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR,
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR,
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD),
build_version(
DB_GPIO_IFC_CURRENT_VERSION_MAJOR,
DB_GPIO_IFC_CURRENT_VERSION_MINOR,
DB_GPIO_IFC_CURRENT_VERSION_BUILD));
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="VERSIONING_REGS_REGMAP">
// <group name="VERSIONING_CONSTANTS">
// <enumeratedtype name="DB_GPIO_IFC_VERSION" showhex="true">
// <info>
// Daughterboard GPIO interface.{BR/}
// For guidance on when to update these revision numbers,
// please refer to the register map documentation accordingly:
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MAJOR" integer="1"/>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MINOR" integer="0"/>
// <value name="DB_GPIO_IFC_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME" integer="0x22070116"/>
// </enumeratedtype>
// </group>
//</regmap>
//<regmap name="FBX_CTRL_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <info>
// This map contains register windows for controlling the different sources
// that drive the state of FBX control lines.
// </info>
// <group name="FBX_CONTROLS">
// <window name="RF_ATR_REGS" offset="0x0" size="0x2000" targetregmap="RF_ATR_REGMAP">
// <info>Control RF switches in FBX daughterboard based on the ATR state of the accessed radio</info>
// </window>
// <window name="RF_SYNC_REGS" offset="0x2000" size="0x2000" targetregmap="RF_SYNC_REGMAP">
// <info>I2C interface to FBX daughterboard IO Expander that controls SYNC switches and rfs en</info>
// </window>
// <window name="LED_ATR_REGS" offset="0x4000" size="0x2000" targetregmap="LED_ATR_REGMAP">
// <info>Control TX/RX LEDs based on the ATR state of the accessed radio</info>
// </window>
// <window name="SYNC_CLK_EN_REGS" offset="0x6000" size="0x2000" targetregmap="CLK_EN_REGMAP">
// <info>Clock enable register for SYNC INJECT 5 MHz clock</info>
// </window>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/dboards/fbx/led_atr_control.v
+569
View File
@@ -0,0 +1,569 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: led_atr_control
//
// Description:
// Translates db_status to implement control over RF LEDs via CtrlPort.
// Uses RAM to store multiple ATR configurations. Triggers CtrlPort
// requests to transfer changes to LEDs to MB CPLD.
// There are three supported control schemes for these switches:
// - ATR Disabled - Single persistent state.
// - Classic ATR - Each channel's LEDs depend on the transmission state
// of the respective channel.
// - DB State - Each channel's LEDs depend on the transmission state
// of all channels in this radio.
//
// Parameters:
//
// LED_REGISTER_ADDRESS : Address of LED register within CPLD.
// REG_BASE : Base address to use for registers.
// REG_SIZE : Register space size.
//
`default_nettype none
module led_atr_control #(
parameter LED_REGISTER_ADDRESS = 0,
parameter REG_BASE = 'h2000,
parameter REG_SIZE = 'h2000
) (
// Common ControlPort signals
input wire ctrlport_clk,
input wire ctrlport_rst,
// Slave ctrlport inteledace
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
output reg s_ctrlport_resp_ack = 1'b0,
output reg [ 1:0] s_ctrlport_resp_status = 2'b00,
output reg [31:0] s_ctrlport_resp_data = {32 {1'b0}},
// DB state lines
input wire [7:0] db_state,
// ControlPort request
output reg m_ctrlport_req_wr,
output wire m_ctrlport_req_rd,
output wire [19:0] m_ctrlport_req_addr,
output wire [31:0] m_ctrlport_req_data,
output wire [ 3:0] m_ctrlport_req_byte_en,
// ControlPort response
input wire m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [31:0] m_ctrlport_resp_data
);
`include "../../cpld/regmap/x440/led_setup_regmap_utils.vh"
`include "../../../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/led_atr_regmap_utils.vh"
//---------------------------------------------------------------
// ATR memory signals
//---------------------------------------------------------------
reg ram_led0_wea;
wire [LED_SIZE-1:0] ram_led0_doa;
wire [LED_SIZE-1:0] ram_led0_dob;
reg ram_led1_wea;
wire [LED_SIZE-1:0] ram_led1_doa;
wire [LED_SIZE-1:0] ram_led1_dob;
reg ram_led2_wea;
wire [LED_SIZE-1:0] ram_led2_doa;
wire [LED_SIZE-1:0] ram_led2_dob;
reg ram_led3_wea;
wire [LED_SIZE-1:0] ram_led3_doa;
wire [LED_SIZE-1:0] ram_led3_dob;
//---------------------------------------------------------------
// ATR Scheme signals
//---------------------------------------------------------------
reg [3:0] atr_disable = 4'b0;
// DB state/Classic ATR selector
reg [3:0] atr_mode = 4'b0;
//---------------------------------------------------------------------------
// Control inteledace handling
//---------------------------------------------------------------------------
// Check that address is within this module's range.
wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE);
// Check that address is targeting an ATR state.
wire address_is_atr = (s_ctrlport_req_addr >= REG_BASE + LED0_ATR_STATE(0)) && (s_ctrlport_req_addr <= REG_BASE + LED3_ATR_STATE(LED3_ATR_STATE_COUNT-1));
// Read request shift register to align memory read and response generation.
reg [ 1:0] read_req_shift_reg = 2'b0;
// Mask out 8 bits for ATR configurations to be able to compare all ATR
// configurations against the same base register address.
wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};
// Decode the ATR state being addressed.
wire [ 7:0] atr_address = s_ctrlport_req_addr[9:2];
always @ (posedge ctrlport_clk) begin
if (ctrlport_rst) begin
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_data <= 32'b0;
s_ctrlport_resp_status <= 2'b00;
atr_disable <= 4'b0;
atr_mode <= 4'b0;
ram_led0_wea <= 1'b0;
ram_led1_wea <= 1'b0;
ram_led2_wea <= 1'b0;
ram_led3_wea <= 1'b0;
end else begin
// default assignments
read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};
ram_led0_wea <= 1'b0;
ram_led1_wea <= 1'b0;
ram_led2_wea <= 1'b0;
ram_led3_wea <= 1'b0;
// Write registers
if (s_ctrlport_req_wr) begin
// Acknowledge by default
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
// Address ATR state writes
if(address_is_atr) begin
case (register_base_address)
REG_BASE + LED0_ATR_STATE(0): begin
ram_led0_wea <= 1'b1;
end
REG_BASE + LED1_ATR_STATE(0): begin
ram_led1_wea <= 1'b1;
end
REG_BASE + LED2_ATR_STATE(0): begin
ram_led2_wea <= 1'b1;
end
REG_BASE + LED3_ATR_STATE(0): begin
ram_led3_wea <= 1'b1;
end
// error on undefined address
default: begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
end
endcase
end else begin
// Address writes to the rest of the register space
case (s_ctrlport_req_addr)
REG_BASE + LED_ATR_OPTION_REGISTER: begin
atr_mode[0] <= s_ctrlport_req_data[LED0_ATR_OPTION];
atr_mode[1] <= s_ctrlport_req_data[LED1_ATR_OPTION];
atr_mode[2] <= s_ctrlport_req_data[LED2_ATR_OPTION];
atr_mode[3] <= s_ctrlport_req_data[LED3_ATR_OPTION];
end
REG_BASE + LED_ATR_DISABLED: begin
atr_disable[0] <= s_ctrlport_req_data[LED0_ATR_DISABLED];
atr_disable[1] <= s_ctrlport_req_data[LED1_ATR_DISABLED];
atr_disable[2] <= s_ctrlport_req_data[LED2_ATR_DISABLED];
atr_disable[3] <= s_ctrlport_req_data[LED3_ATR_DISABLED];
end
// No register implementation for provided address
default: begin
// Acknowledge and provide error status if address is in range
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
end
// Read registers
end else if (read_req_shift_reg[1]) begin
// Acknowledge by default
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
// Address ATR state reads
if(address_is_atr) begin
case (register_base_address)
REG_BASE + LED0_ATR_STATE(0): begin
s_ctrlport_resp_data <= ram_led0_doa & LED_ATR_STATE_MASK;
end
REG_BASE + LED1_ATR_STATE(0): begin
s_ctrlport_resp_data <= ram_led1_doa & LED_ATR_STATE_MASK;
end
REG_BASE + LED2_ATR_STATE(0): begin
s_ctrlport_resp_data <= ram_led2_doa & LED_ATR_STATE_MASK;
end
REG_BASE + LED3_ATR_STATE(0): begin
s_ctrlport_resp_data <= ram_led3_doa & LED_ATR_STATE_MASK;
end
default: begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
end
endcase
end else begin
// Address reads to the rest of the register space
case (s_ctrlport_req_addr)
REG_BASE + LED_ATR_OPTION_REGISTER: begin
s_ctrlport_resp_data[LED0_ATR_OPTION] <= atr_mode[0];
s_ctrlport_resp_data[LED1_ATR_OPTION] <= atr_mode[1];
s_ctrlport_resp_data[LED2_ATR_OPTION] <= atr_mode[2];
s_ctrlport_resp_data[LED3_ATR_OPTION] <= atr_mode[3];
end
REG_BASE + LED_ATR_DISABLED: begin
s_ctrlport_resp_data[LED0_ATR_DISABLED] <= atr_disable[0];
s_ctrlport_resp_data[LED1_ATR_DISABLED] <= atr_disable[1];
s_ctrlport_resp_data[LED2_ATR_DISABLED] <= atr_disable[2];
s_ctrlport_resp_data[LED3_ATR_DISABLED] <= atr_disable[3];
end
// No register implementation for provided address
default: begin
// Acknowledge and provide error status if address is in range
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
end
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
// register without reset
reg [ 7:0] ram_addr = 8'b0;
reg [LED_SIZE-1:0] ram_datain = {LED_SIZE{1'b0}};
always @(posedge ctrlport_clk) begin
// memories
ram_addr <= atr_address;
ram_datain <= s_ctrlport_req_data[LED_SIZE-1:0];
end
// ATR Scheme selection
reg [7:0] atr_config_led [3:0];
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin: read_address_gen
always @(posedge ctrlport_clk) begin
if (atr_disable[i]) begin
atr_config_led[i] <= 8'b0;
end else begin
if (atr_mode[i]) begin
atr_config_led[i] <= {6'b0, db_state[2*i+:2]};
end else begin
atr_config_led[i] <= db_state;
end
end
end
end
endgenerate
reg [31:0] led_combined = 32'b0;
always @(posedge ctrlport_clk) begin
led_combined[CH0_RX2_LED_EN] <= ram_led0_dob[RX2_LED];
led_combined[CH0_TRX1_LED_RED_EN] <= ram_led0_dob[TXRX_RED_LED];
led_combined[CH0_TRX1_LED_GR_EN] <= ram_led0_dob[TXRX_GR_LED];
led_combined[CH1_RX2_LED_EN] <= ram_led1_dob[RX2_LED];
led_combined[CH1_TRX1_LED_RED_EN] <= ram_led1_dob[TXRX_RED_LED];
led_combined[CH1_TRX1_LED_GR_EN] <= ram_led1_dob[TXRX_GR_LED];
led_combined[CH2_RX2_LED_EN] <= ram_led2_dob[RX2_LED];
led_combined[CH2_TRX1_LED_RED_EN] <= ram_led2_dob[TXRX_RED_LED];
led_combined[CH2_TRX1_LED_GR_EN] <= ram_led2_dob[TXRX_GR_LED];
led_combined[CH3_RX2_LED_EN] <= ram_led3_dob[RX2_LED];
led_combined[CH3_TRX1_LED_RED_EN] <= ram_led3_dob[TXRX_RED_LED];
led_combined[CH3_TRX1_LED_GR_EN] <= ram_led3_dob[TXRX_GR_LED];
end
//---------------------------------------------------------------
// ATR memory
//---------------------------------------------------------------
ram_2port #(
.DWIDTH (LED_SIZE),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0)
) ram_led0_i (
.clka (ctrlport_clk),
.ena (1'b1),
.wea (ram_led0_wea),
.addra (ram_addr),
.dia (ram_datain),
.doa (ram_led0_doa),
.clkb (ctrlport_clk),
.enb (1'b1),
.web (1'b0),
.addrb (atr_config_led[0]),
.dib ({LED_SIZE{1'b0}}),
.dob (ram_led0_dob));
ram_2port #(
.DWIDTH (LED_SIZE),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0)
) ram_led1_i (
.clka (ctrlport_clk),
.ena (1'b1),
.wea (ram_led1_wea),
.addra (ram_addr),
.dia (ram_datain),
.doa (ram_led1_doa),
.clkb (ctrlport_clk),
.enb (1'b1),
.web (1'b0),
.addrb (atr_config_led[1]),
.dib ({LED_SIZE{1'b0}}),
.dob (ram_led1_dob));
ram_2port #(
.DWIDTH (LED_SIZE),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0)
) ram_led2_i (
.clka (ctrlport_clk),
.ena (1'b1),
.wea (ram_led2_wea),
.addra (ram_addr),
.dia (ram_datain),
.doa (ram_led2_doa),
.clkb (ctrlport_clk),
.enb (1'b1),
.web (1'b0),
.addrb (atr_config_led[2]),
.dib ({LED_SIZE{1'b0}}),
.dob (ram_led2_dob));
ram_2port #(
.DWIDTH (LED_SIZE),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0)
) ram_led3_i (
.clka (ctrlport_clk),
.ena (1'b1),
.wea (ram_led3_wea),
.addra (ram_addr),
.dia (ram_datain),
.doa (ram_led3_doa),
.clkb (ctrlport_clk),
.enb (1'b1),
.web (1'b0),
.addrb (atr_config_led[3]),
.dib ({LED_SIZE{1'b0}}),
.dob (ram_led3_dob));
//----------------------------------------------------------
// Logic to wait for response after triggering request
//----------------------------------------------------------
reg transfer_in_progress;
reg [31:0] led_combined_delayed = 32'b0;
always @(posedge ctrlport_clk) begin
if (ctrlport_rst) begin
m_ctrlport_req_wr <= 1'b0;
transfer_in_progress <= 1'b0;
led_combined_delayed <= 16'b0;
end else begin
// Default assignment
m_ctrlport_req_wr <= 1'b0;
// Issue new request on change if no request is pending
if (led_combined != led_combined_delayed && ~transfer_in_progress) begin
transfer_in_progress <= 1'b1;
m_ctrlport_req_wr <= 1'b1;
led_combined_delayed <= led_combined;
end
// Reset pending request
if (m_ctrlport_resp_ack) begin
transfer_in_progress <= 1'b0;
end
end
end
//----------------------------------------------------------
// Static ControlPort assignments
//----------------------------------------------------------
assign m_ctrlport_req_rd = 0;
assign m_ctrlport_req_byte_en = 4'b1111;
assign m_ctrlport_req_addr = LED_REGISTER_ADDRESS;
assign m_ctrlport_req_data = {led_combined_delayed};
endmodule
//XmlParse xml_on
//<regmap name="LED_ATR_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="LED_ATR_REGISTERS">
// <info>
// Each channel in the FBX daughterboard has 3 LEDs. TXRX Red/Green LEDs and RX2 Green LED.
// This register map describes how to control the behavior of the 3 LEDs.
// There are three supported control schemes for these LEDs:</br>
// <ul>
// <li>ATR Disabled - Single persistent state.</li>
// <li>Classic ATR - Each channel's LEDs depend on the transmission state
// of the respective channel.</li>
// <li>DB State - Each channel's LEDs depend on the transmission state
// of all channels in this radio.</li>
// </ul>
// </info>
//
// <enumeratedtype name="LED_SIZE_TYPE">
// <value name="LED_SIZE" integer="3"/>
// </enumeratedtype>
//
// <regtype name="LED_ATR_STATE" size="32">
// <info>Holds the value for the control lines of each channel's LEDs
// for a particular ATR sate</info>
// <bitfield name="RX2_LED" range="0" initialvalue="0"/>
// <bitfield name="TXRX_RED_LED" range="1" initialvalue="0"/>
// <bitfield name="TXRX_GR_LED" range="2" initialvalue="0"/>
// </regtype>
//
// <register name="LED0_ATR_STATE" typename="LED_ATR_STATE" offset="0x00" count="256" options="--step 4">
// <info>
// Describes led behavior for the different ATR states. When @.LED0_ATR_OPTION
// is set to use the DB states, TX and RX states for LED0-LED3 are
// combined to create a single vector. This creates 256 different
// combinations, each with its own register. When @.LED0_ATR_OPTION is set to
// classic ATR, the first 4 offsets in this register group will be driven
// in accordance with the state of RF0.
// CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1,
// TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1]
// </info>
// </register>
//
// <register name="LED1_ATR_STATE" typename="LED_ATR_STATE" offset="0x400" count="256" options="--step 4">
// <info>
// Describes led behavior for the different ATR states. When @.LED1_ATR_OPTION
// is set to use the DB states, TX and RX states for LED0-LED3 are
// combined to create a single vector. This creates 256 different
// combinations, each with its own register. When @.LED1_ATR_OPTION is set to
// classic ATR, the first 4 offsets in this register group will be driven
// in accordance with the state of RF1.
// CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1,
// TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1]
// </info>
// </register>
//
// <register name="LED2_ATR_STATE" typename="LED_ATR_STATE" offset="0x800" count="256" options="--step 4">
// <info>
// Describes led behavior for the different ATR states. When @.LED2_ATR_OPTION
// is set to use the DB states, TX and RX states for LED0-LED3 are
// combined to create a single vector. This creates 256 different
// combinations, each with its own register. When @.LED2_ATR_OPTION is set to
// classic ATR, the first 4 offsets in this register group will be driven
// in accordance with the state of RF2.
// CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1,
// TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1]
// </info>
// </register>
//
// <register name="LED3_ATR_STATE" typename="LED_ATR_STATE" offset="0xC00" count="256" options="--step 4">
// <info>
// Describes led behavior for the different ATR states. When @.LED3_ATR_OPTION
// is set to use the DB states, TX and RX states for LED0-LED3 are
// combined to create a single vector. This creates 256 different
// combinations, each with its own register. When @.LED3_ATR_OPTION is set to
// classic ATR, the first 4 offsets in this register group will be driven
// in accordance with the state of RF3.
// CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1,
// TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1]
// </info>
// </register>
// <register name="LED_ATR_OPTION_REGISTER" offset="0x1000" size="32">
// <info>
// Controls whether switch control lines use the TX and RX state of
// their respective channel (Classic ATR) or the daughterboard state
// to select which state to use from values set in LED_ATR_STATE registers.
// For each particular bit:</br>
// 0: Use DB state for ATR</br>
// 1: Classic ATR mode.
// </info>
// <bitfield name="LED0_ATR_OPTION" range="0" initialvalue="0">
// <info>
// Control ATR scheme for RF0.
// </info>
// </bitfield>
// <bitfield name="LED1_ATR_OPTION" range="1" initialvalue="0">
// <info>
// Control ATR scheme for RF1.
// </info>
// </bitfield>
// <bitfield name="LED2_ATR_OPTION" range="2" initialvalue="0">
// <info>
// Control ATR scheme for RF2.
// </info>
// </bitfield>
// <bitfield name="LED3_ATR_OPTION" range="3" initialvalue="0">
// <info>
// Control ATR scheme for RF3.
// </info>
// </bitfield>
// </register>
// <register name="LED_ATR_DISABLED" offset="0x1004" size="32">
// <info>
// Disable ATR Control. DB state 0 will be reflected regardless of the ATR state.
// </info>
// <bitfield name="LED0_ATR_DISABLED" range="0" initialvalue="0"/>
// <bitfield name="LED1_ATR_DISABLED" range="1" initialvalue="0"/>
// <bitfield name="LED2_ATR_DISABLED" range="2" initialvalue="0"/>
// <bitfield name="LED3_ATR_DISABLED" range="3" initialvalue="0"/>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
`default_nettype wire
top/x400/cpld/regmap/constants_regmap_utils.vh → top/x400/dboards/fbx/regmap/clock_en_regmap_utils.vh
+10 -8
View File
@@ -3,7 +3,7 @@
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: constants_regmap_utils.vh
// Module: clock_en_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
@@ -11,18 +11,20 @@
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// CLK_EN_CONTROL : 0x0 (clock_en_control.v)
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group CONSTANTS_GROUP
// Register Group CLOCK_EN_REGISTERS
//===============================================================================
// Enumerated type CONSTANTS_ENUM
localparam CONSTANTS_ENUM_SIZE = 4;
localparam PS_CPLD_SIGNATURE = 'hA522D27; // CONSTANTS_ENUM:PS_CPLD_SIGNATURE
localparam OLDEST_CPLD_REVISION = 'h20122114; // CONSTANTS_ENUM:OLDEST_CPLD_REVISION
localparam CPLD_REVISION = 'h21111615; // CONSTANTS_ENUM:CPLD_REVISION
localparam PL_CPLD_SIGNATURE = 'h3FDC5C47; // CONSTANTS_ENUM:PL_CPLD_SIGNATURE
// CLK_EN_CONTROL Register (from clock_en_control.v)
localparam CLK_EN_CONTROL = 'h0; // Register Offset
localparam CLK_EN_CONTROL_SIZE = 32; // register width in bits
localparam CLK_EN_CONTROL_MASK = 32'h1;
localparam CLK_EN_SIZE = 1; //CLK_EN_CONTROL:CLK_EN
localparam CLK_EN_MSB = 0; //CLK_EN_CONTROL:CLK_EN
localparam CLK_EN = 0; //CLK_EN_CONTROL:CLK_EN
top/x400/dboards/fbx/regmap/fbx_ctrl_regmap_utils.vh
+41
View File
@@ -0,0 +1,41 @@
//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: fbx_ctrl_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// RF_ATR_REGS : 0x0 (db_gpio_interface.v)
// RF_SYNC_REGS : 0x2000 (db_gpio_interface.v)
// LED_ATR_REGS : 0x4000 (db_gpio_interface.v)
// SYNC_CLK_EN_REGS : 0x6000 (db_gpio_interface.v)
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group FBX_CONTROLS
//===============================================================================
// RF_ATR_REGS Window (from db_gpio_interface.v)
localparam RF_ATR_REGS = 'h0; // Window Offset
localparam RF_ATR_REGS_SIZE = 'h2000; // size in bytes
// RF_SYNC_REGS Window (from db_gpio_interface.v)
localparam RF_SYNC_REGS = 'h2000; // Window Offset
localparam RF_SYNC_REGS_SIZE = 'h2000; // size in bytes
// LED_ATR_REGS Window (from db_gpio_interface.v)
localparam LED_ATR_REGS = 'h4000; // Window Offset
localparam LED_ATR_REGS_SIZE = 'h2000; // size in bytes
// SYNC_CLK_EN_REGS Window (from db_gpio_interface.v)
localparam SYNC_CLK_EN_REGS = 'h6000; // Window Offset
localparam SYNC_CLK_EN_REGS_SIZE = 'h2000; // size in bytes
top/x400/dboards/fbx/regmap/led_atr_regmap_utils.vh
+110
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@@ -0,0 +1,110 @@
//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: led_atr_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// LED0_ATR_STATE : 0x0 (led_atr_control.v)
// LED1_ATR_STATE : 0x400 (led_atr_control.v)
// LED2_ATR_STATE : 0x800 (led_atr_control.v)
// LED3_ATR_STATE : 0xC00 (led_atr_control.v)
// LED_ATR_OPTION_REGISTER : 0x1000 (led_atr_control.v)
// LED_ATR_DISABLED : 0x1004 (led_atr_control.v)
//===============================================================================
// RegTypes
//===============================================================================
// LED_ATR_STATE Type (from led_atr_control.v)
localparam LED_ATR_STATE_SIZE = 32;
localparam LED_ATR_STATE_MASK = 32'h7;
localparam RX2_LED_SIZE = 1; //LED_ATR_STATE:RX2_LED
localparam RX2_LED_MSB = 0; //LED_ATR_STATE:RX2_LED
localparam RX2_LED = 0; //LED_ATR_STATE:RX2_LED
localparam TXRX_RED_LED_SIZE = 1; //LED_ATR_STATE:TXRX_RED_LED
localparam TXRX_RED_LED_MSB = 1; //LED_ATR_STATE:TXRX_RED_LED
localparam TXRX_RED_LED = 1; //LED_ATR_STATE:TXRX_RED_LED
localparam TXRX_GR_LED_SIZE = 1; //LED_ATR_STATE:TXRX_GR_LED
localparam TXRX_GR_LED_MSB = 2; //LED_ATR_STATE:TXRX_GR_LED
localparam TXRX_GR_LED = 2; //LED_ATR_STATE:TXRX_GR_LED
//===============================================================================
// Register Group LED_ATR_REGISTERS
//===============================================================================
// Enumerated type LED_SIZE_TYPE
localparam LED_SIZE_TYPE_SIZE = 1;
localparam LED_SIZE = 'h3; // LED_SIZE_TYPE:LED_SIZE
// LED0_ATR_STATE Register (from led_atr_control.v)
localparam LED0_ATR_STATE_COUNT = 256; // Number of elements in array
// LED1_ATR_STATE Register (from led_atr_control.v)
localparam LED1_ATR_STATE_COUNT = 256; // Number of elements in array
// LED2_ATR_STATE Register (from led_atr_control.v)
localparam LED2_ATR_STATE_COUNT = 256; // Number of elements in array
// LED3_ATR_STATE Register (from led_atr_control.v)
localparam LED3_ATR_STATE_COUNT = 256; // Number of elements in array
// LED_ATR_OPTION_REGISTER Register (from led_atr_control.v)
localparam LED_ATR_OPTION_REGISTER = 'h1000; // Register Offset
localparam LED_ATR_OPTION_REGISTER_SIZE = 32; // register width in bits
localparam LED_ATR_OPTION_REGISTER_MASK = 32'hF;
localparam LED0_ATR_OPTION_SIZE = 1; //LED_ATR_OPTION_REGISTER:LED0_ATR_OPTION
localparam LED0_ATR_OPTION_MSB = 0; //LED_ATR_OPTION_REGISTER:LED0_ATR_OPTION
localparam LED0_ATR_OPTION = 0; //LED_ATR_OPTION_REGISTER:LED0_ATR_OPTION
localparam LED1_ATR_OPTION_SIZE = 1; //LED_ATR_OPTION_REGISTER:LED1_ATR_OPTION
localparam LED1_ATR_OPTION_MSB = 1; //LED_ATR_OPTION_REGISTER:LED1_ATR_OPTION
localparam LED1_ATR_OPTION = 1; //LED_ATR_OPTION_REGISTER:LED1_ATR_OPTION
localparam LED2_ATR_OPTION_SIZE = 1; //LED_ATR_OPTION_REGISTER:LED2_ATR_OPTION
localparam LED2_ATR_OPTION_MSB = 2; //LED_ATR_OPTION_REGISTER:LED2_ATR_OPTION
localparam LED2_ATR_OPTION = 2; //LED_ATR_OPTION_REGISTER:LED2_ATR_OPTION
localparam LED3_ATR_OPTION_SIZE = 1; //LED_ATR_OPTION_REGISTER:LED3_ATR_OPTION
localparam LED3_ATR_OPTION_MSB = 3; //LED_ATR_OPTION_REGISTER:LED3_ATR_OPTION
localparam LED3_ATR_OPTION = 3; //LED_ATR_OPTION_REGISTER:LED3_ATR_OPTION
// LED_ATR_DISABLED Register (from led_atr_control.v)
localparam LED_ATR_DISABLED = 'h1004; // Register Offset
localparam LED_ATR_DISABLED_SIZE = 32; // register width in bits
localparam LED_ATR_DISABLED_MASK = 32'hF;
localparam LED0_ATR_DISABLED_SIZE = 1; //LED_ATR_DISABLED:LED0_ATR_DISABLED
localparam LED0_ATR_DISABLED_MSB = 0; //LED_ATR_DISABLED:LED0_ATR_DISABLED
localparam LED0_ATR_DISABLED = 0; //LED_ATR_DISABLED:LED0_ATR_DISABLED
localparam LED1_ATR_DISABLED_SIZE = 1; //LED_ATR_DISABLED:LED1_ATR_DISABLED
localparam LED1_ATR_DISABLED_MSB = 1; //LED_ATR_DISABLED:LED1_ATR_DISABLED
localparam LED1_ATR_DISABLED = 1; //LED_ATR_DISABLED:LED1_ATR_DISABLED
localparam LED2_ATR_DISABLED_SIZE = 1; //LED_ATR_DISABLED:LED2_ATR_DISABLED
localparam LED2_ATR_DISABLED_MSB = 2; //LED_ATR_DISABLED:LED2_ATR_DISABLED
localparam LED2_ATR_DISABLED = 2; //LED_ATR_DISABLED:LED2_ATR_DISABLED
localparam LED3_ATR_DISABLED_SIZE = 1; //LED_ATR_DISABLED:LED3_ATR_DISABLED
localparam LED3_ATR_DISABLED_MSB = 3; //LED_ATR_DISABLED:LED3_ATR_DISABLED
localparam LED3_ATR_DISABLED = 3; //LED_ATR_DISABLED:LED3_ATR_DISABLED
// Return the offset of an element of register array LED0_ATR_STATE
function integer LED0_ATR_STATE (input integer i);
LED0_ATR_STATE = (i * 'h4) + 'h0;
endfunction
// Return the offset of an element of register array LED1_ATR_STATE
function integer LED1_ATR_STATE (input integer i);
LED1_ATR_STATE = (i * 'h4) + 'h400;
endfunction
// Return the offset of an element of register array LED2_ATR_STATE
function integer LED2_ATR_STATE (input integer i);
LED2_ATR_STATE = (i * 'h4) + 'h800;
endfunction
// Return the offset of an element of register array LED3_ATR_STATE
function integer LED3_ATR_STATE (input integer i);
LED3_ATR_STATE = (i * 'h4) + 'hC00;
endfunction
top/x400/dboards/fbx/regmap/rf_atr_regmap_utils.vh
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rf_atr_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// RF0_ATR_STATE : 0x0 (rf_atr_control.v)
// RF1_ATR_STATE : 0x400 (rf_atr_control.v)
// RF2_ATR_STATE : 0x800 (rf_atr_control.v)
// RF3_ATR_STATE : 0xC00 (rf_atr_control.v)
// ATR_OPTION_REGISTER : 0x1000 (rf_atr_control.v)
// RF_ATR_DISABLED : 0x1004 (rf_atr_control.v)
//===============================================================================
// RegTypes
//===============================================================================
// RF_ATR_STATE Type (from rf_atr_control.v)
localparam RF_ATR_STATE_SIZE = 32;
localparam RF_ATR_STATE_MASK = 32'h7;
localparam TX_RX_RFS_SIZE = 1; //RF_ATR_STATE:TX_RX_RFS
localparam TX_RX_RFS_MSB = 0; //RF_ATR_STATE:TX_RX_RFS
localparam TX_RX_RFS = 0; //RF_ATR_STATE:TX_RX_RFS
localparam RX_RFS_SIZE = 1; //RF_ATR_STATE:RX_RFS
localparam RX_RFS_MSB = 1; //RF_ATR_STATE:RX_RFS
localparam RX_RFS = 1; //RF_ATR_STATE:RX_RFS
localparam TDDS_SIZE = 1; //RF_ATR_STATE:TDDS
localparam TDDS_MSB = 2; //RF_ATR_STATE:TDDS
localparam TDDS = 2; //RF_ATR_STATE:TDDS
//===============================================================================
// Register Group RF_ATR_REGISTERS
//===============================================================================
// Enumerated type RF_SWITCHES_SIZE_TYPE
localparam RF_SWITCHES_SIZE_TYPE_SIZE = 1;
localparam RFS_SIZE = 'h3; // RF_SWITCHES_SIZE_TYPE:RFS_SIZE
// RF0_ATR_STATE Register (from rf_atr_control.v)
localparam RF0_ATR_STATE_COUNT = 256; // Number of elements in array
// RF1_ATR_STATE Register (from rf_atr_control.v)
localparam RF1_ATR_STATE_COUNT = 256; // Number of elements in array
// RF2_ATR_STATE Register (from rf_atr_control.v)
localparam RF2_ATR_STATE_COUNT = 256; // Number of elements in array
// RF3_ATR_STATE Register (from rf_atr_control.v)
localparam RF3_ATR_STATE_COUNT = 256; // Number of elements in array
// ATR_OPTION_REGISTER Register (from rf_atr_control.v)
localparam ATR_OPTION_REGISTER = 'h1000; // Register Offset
localparam ATR_OPTION_REGISTER_SIZE = 32; // register width in bits
localparam ATR_OPTION_REGISTER_MASK = 32'hF;
localparam RF0_ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTER:RF0_ATR_OPTION
localparam RF0_ATR_OPTION_MSB = 0; //ATR_OPTION_REGISTER:RF0_ATR_OPTION
localparam RF0_ATR_OPTION = 0; //ATR_OPTION_REGISTER:RF0_ATR_OPTION
localparam RF1_ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTER:RF1_ATR_OPTION
localparam RF1_ATR_OPTION_MSB = 1; //ATR_OPTION_REGISTER:RF1_ATR_OPTION
localparam RF1_ATR_OPTION = 1; //ATR_OPTION_REGISTER:RF1_ATR_OPTION
localparam RF2_ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTER:RF2_ATR_OPTION
localparam RF2_ATR_OPTION_MSB = 2; //ATR_OPTION_REGISTER:RF2_ATR_OPTION
localparam RF2_ATR_OPTION = 2; //ATR_OPTION_REGISTER:RF2_ATR_OPTION
localparam RF3_ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTER:RF3_ATR_OPTION
localparam RF3_ATR_OPTION_MSB = 3; //ATR_OPTION_REGISTER:RF3_ATR_OPTION
localparam RF3_ATR_OPTION = 3; //ATR_OPTION_REGISTER:RF3_ATR_OPTION
// RF_ATR_DISABLED Register (from rf_atr_control.v)
localparam RF_ATR_DISABLED = 'h1004; // Register Offset
localparam RF_ATR_DISABLED_SIZE = 32; // register width in bits
localparam RF_ATR_DISABLED_MASK = 32'hF;
localparam RF0_ATR_DISABLED_SIZE = 1; //RF_ATR_DISABLED:RF0_ATR_DISABLED
localparam RF0_ATR_DISABLED_MSB = 0; //RF_ATR_DISABLED:RF0_ATR_DISABLED
localparam RF0_ATR_DISABLED = 0; //RF_ATR_DISABLED:RF0_ATR_DISABLED
localparam RF1_ATR_DISABLED_SIZE = 1; //RF_ATR_DISABLED:RF1_ATR_DISABLED
localparam RF1_ATR_DISABLED_MSB = 1; //RF_ATR_DISABLED:RF1_ATR_DISABLED
localparam RF1_ATR_DISABLED = 1; //RF_ATR_DISABLED:RF1_ATR_DISABLED
localparam RF2_ATR_DISABLED_SIZE = 1; //RF_ATR_DISABLED:RF2_ATR_DISABLED
localparam RF2_ATR_DISABLED_MSB = 2; //RF_ATR_DISABLED:RF2_ATR_DISABLED
localparam RF2_ATR_DISABLED = 2; //RF_ATR_DISABLED:RF2_ATR_DISABLED
localparam RF3_ATR_DISABLED_SIZE = 1; //RF_ATR_DISABLED:RF3_ATR_DISABLED
localparam RF3_ATR_DISABLED_MSB = 3; //RF_ATR_DISABLED:RF3_ATR_DISABLED
localparam RF3_ATR_DISABLED = 3; //RF_ATR_DISABLED:RF3_ATR_DISABLED
// Return the offset of an element of register array RF0_ATR_STATE
function integer RF0_ATR_STATE (input integer i);
RF0_ATR_STATE = (i * 'h4) + 'h0;
endfunction
// Return the offset of an element of register array RF1_ATR_STATE
function integer RF1_ATR_STATE (input integer i);
RF1_ATR_STATE = (i * 'h4) + 'h400;
endfunction
// Return the offset of an element of register array RF2_ATR_STATE
function integer RF2_ATR_STATE (input integer i);
RF2_ATR_STATE = (i * 'h4) + 'h800;
endfunction
// Return the offset of an element of register array RF3_ATR_STATE
function integer RF3_ATR_STATE (input integer i);
RF3_ATR_STATE = (i * 'h4) + 'hC00;
endfunction
top/x400/dboards/fbx/regmap/rf_sync_regmap_utils.vh
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rf_sync_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// SYNC_1_REG : 0x0 (ctrlport_to_i2c_sync_ctrl.v)
// SYNC_2_REG : 0x4 (ctrlport_to_i2c_sync_ctrl.v)
// SYNC_3_REG : 0x8 (ctrlport_to_i2c_sync_ctrl.v)
// SYNC_4_REG : 0xC (ctrlport_to_i2c_sync_ctrl.v)
// SYNC_5_REG : 0x10 (ctrlport_to_i2c_sync_ctrl.v)
// RFS_EN_REG : 0x14 (ctrlport_to_i2c_sync_ctrl.v)
// SETUP_REG/SETUP_STATUS_REG : 0x18 (ctrlport_to_i2c_sync_ctrl.v, ctrlport_to_i2c_sync_ctrl.v)
// CONFIG_IO_REG/CONFIG_IO_STATUS_REG : 0x1C (ctrlport_to_i2c_sync_ctrl.v, ctrlport_to_i2c_sync_ctrl.v)
//===============================================================================
// RegTypes
//===============================================================================
// SYNC_SWITCH Type (from ctrlport_to_i2c_sync_ctrl.v)
localparam SYNC_SWITCH_SIZE = 32;
localparam SYNC_SWITCH_MASK = 32'h7;
localparam CONTROL_PIN_V1_SIZE = 1; //SYNC_SWITCH:CONTROL_PIN_V1
localparam CONTROL_PIN_V1_MSB = 0; //SYNC_SWITCH:CONTROL_PIN_V1
localparam CONTROL_PIN_V1 = 0; //SYNC_SWITCH:CONTROL_PIN_V1
localparam CONTROL_PIN_V2_SIZE = 1; //SYNC_SWITCH:CONTROL_PIN_V2
localparam CONTROL_PIN_V2_MSB = 1; //SYNC_SWITCH:CONTROL_PIN_V2
localparam CONTROL_PIN_V2 = 1; //SYNC_SWITCH:CONTROL_PIN_V2
localparam CONTROL_PIN_V3_SIZE = 1; //SYNC_SWITCH:CONTROL_PIN_V3
localparam CONTROL_PIN_V3_MSB = 2; //SYNC_SWITCH:CONTROL_PIN_V3
localparam CONTROL_PIN_V3 = 2; //SYNC_SWITCH:CONTROL_PIN_V3
//===============================================================================
// Register Group RF_SYNC_REGISTERS
//===============================================================================
// Enumerated type IO_EXPANDER_REGISTER_ADRS
localparam IO_EXPANDER_REGISTER_ADRS_SIZE = 8;
localparam IO_EXP_INPUT_PORT0_REG = 'h0; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_INPUT_PORT0_REG
localparam IO_EXP_INPUT_PORT1_REG = 'h1; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_INPUT_PORT1_REG
localparam IO_EXP_OUTPUT_PORT0_REG = 'h2; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_OUTPUT_PORT0_REG
localparam IO_EXP_OUTPUT_PORT1_REG = 'h3; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_OUTPUT_PORT1_REG
localparam IO_EXP_POLARITY_INV0_REG = 'h4; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_POLARITY_INV0_REG
localparam IO_EXP_POLARITY_INV1_REG = 'h5; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_POLARITY_INV1_REG
localparam IO_EXP_CONFIG0_REG = 'h6; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_CONFIG0_REG
localparam IO_EXP_CONFIG1_REG = 'h7; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_CONFIG1_REG
// SYNC_1_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam SYNC_1_REG = 'h0; // Register Offset
localparam SYNC_1_REG_SIZE = 32; // register width in bits
// SYNC_2_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam SYNC_2_REG = 'h4; // Register Offset
localparam SYNC_2_REG_SIZE = 32; // register width in bits
// SYNC_3_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam SYNC_3_REG = 'h8; // Register Offset
localparam SYNC_3_REG_SIZE = 32; // register width in bits
// SYNC_4_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam SYNC_4_REG = 'hC; // Register Offset
localparam SYNC_4_REG_SIZE = 32; // register width in bits
// SYNC_5_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam SYNC_5_REG = 'h10; // Register Offset
localparam SYNC_5_REG_SIZE = 32; // register width in bits
// RFS_EN_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam RFS_EN_REG = 'h14; // Register Offset
localparam RFS_EN_REG_SIZE = 32; // register width in bits
localparam RFS_EN_REG_MASK = 32'h1;
localparam RFS_EN_PIN_SIZE = 1; //RFS_EN_REG:RFS_EN_PIN
localparam RFS_EN_PIN_MSB = 0; //RFS_EN_REG:RFS_EN_PIN
localparam RFS_EN_PIN = 0; //RFS_EN_REG:RFS_EN_PIN
// SETUP_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam SETUP_REG = 'h18; // Register Offset
localparam SETUP_REG_SIZE = 32; // register width in bits
localparam SETUP_REG_MASK = 32'h1;
localparam SETUP_TRIG_SIZE = 1; //SETUP_REG:SETUP_TRIG
localparam SETUP_TRIG_MSB = 0; //SETUP_REG:SETUP_TRIG
localparam SETUP_TRIG = 0; //SETUP_REG:SETUP_TRIG
// SETUP_STATUS_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam SETUP_STATUS_REG = 'h18; // Register Offset
localparam SETUP_STATUS_REG_SIZE = 32; // register width in bits
localparam SETUP_STATUS_REG_MASK = 32'h1;
localparam SETUP_STATUS_SIZE = 1; //SETUP_STATUS_REG:SETUP_STATUS
localparam SETUP_STATUS_MSB = 0; //SETUP_STATUS_REG:SETUP_STATUS
localparam SETUP_STATUS = 0; //SETUP_STATUS_REG:SETUP_STATUS
// CONFIG_IO_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam CONFIG_IO_REG = 'h1C; // Register Offset
localparam CONFIG_IO_REG_SIZE = 32; // register width in bits
localparam CONFIG_IO_REG_MASK = 32'h1;
localparam CONFIG_IO_TRIG_SIZE = 1; //CONFIG_IO_REG:CONFIG_IO_TRIG
localparam CONFIG_IO_TRIG_MSB = 0; //CONFIG_IO_REG:CONFIG_IO_TRIG
localparam CONFIG_IO_TRIG = 0; //CONFIG_IO_REG:CONFIG_IO_TRIG
// CONFIG_IO_STATUS_REG Register (from ctrlport_to_i2c_sync_ctrl.v)
localparam CONFIG_IO_STATUS_REG = 'h1C; // Register Offset
localparam CONFIG_IO_STATUS_REG_SIZE = 32; // register width in bits
localparam CONFIG_IO_STATUS_REG_MASK = 32'h1;
localparam CONFIG_IO_STATUS_SIZE = 1; //CONFIG_IO_STATUS_REG:CONFIG_IO_STATUS
localparam CONFIG_IO_STATUS_MSB = 0; //CONFIG_IO_STATUS_REG:CONFIG_IO_STATUS
localparam CONFIG_IO_STATUS = 0; //CONFIG_IO_STATUS_REG:CONFIG_IO_STATUS
top/x400/dboards/fbx/rf_atr_control.v
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//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rf_atr_control
//
// Description:
//
// Implements control over RF switches via CtrlPort. Uses RAM to store multiple
// ATR configurations.
// There are three supported control schemes for these switches:
// - ATR Disabled - Single persistent state.
// - Classic ATR - Each channel's switches depend on the transmission state
// of the respective channel.
// - DB State - Each channel's switches depend on the transmission state
// of all channels in this radio.
//
// Parameters:
//
// REG_BASE : Base address to use for registers.
// REG_SIZE : Register space size.
//
module rf_atr_control #(
parameter REG_BASE = 0,
parameter REG_SIZE = 'h2000
) (
// Slave ctrlport interface
input wire ctrlport_clk,
input wire ctrlport_rst,
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
output reg s_ctrlport_resp_ack = 1'b0,
output reg [ 1:0] s_ctrlport_resp_status = 2'b00,
output reg [31:0] s_ctrlport_resp_data = {32 {1'b0}},
// Run state signals that indicate tx and rx operation
input wire [7:0] db_state,
// Switch control outputs
output reg rf0_tx_rx_rfs,
output reg rf0_rx_rfs,
output reg rf0_tdds,
output reg rf1_tx_rx_rfs,
output reg rf1_rx_rfs,
output reg rf1_tdds,
output reg rf2_tx_rx_rfs,
output reg rf2_rx_rfs,
output reg rf2_tdds,
output reg rf3_tx_rx_rfs,
output reg rf3_rx_rfs,
output reg rf3_tdds
);
`include "../../../../lib/rfnoc/core/ctrlport.vh"
`include "regmap/rf_atr_regmap_utils.vh"
//---------------------------------------------------------------
// ATR memory signals
//---------------------------------------------------------------
reg ram_rf0_wea;
wire [RFS_SIZE-1:0] ram_rf0_doa;
wire [RFS_SIZE-1:0] ram_rf0_dob;
reg ram_rf1_wea;
wire [RFS_SIZE-1:0] ram_rf1_doa;
wire [RFS_SIZE-1:0] ram_rf1_dob;
reg ram_rf2_wea;
wire [RFS_SIZE-1:0] ram_rf2_doa;
wire [RFS_SIZE-1:0] ram_rf2_dob;
reg ram_rf3_wea;
wire [RFS_SIZE-1:0] ram_rf3_doa;
wire [RFS_SIZE-1:0] ram_rf3_dob;
//---------------------------------------------------------------
// ATR Scheme signals
//---------------------------------------------------------------
reg [3:0] atr_disable = 4'b0;
// DB state/Classic ATR selector
reg [3:0] atr_mode = 4'b0;
//---------------------------------------------------------------------------
// Control interface handling
//---------------------------------------------------------------------------
// Check that address is within this module's range.
wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE);
// Check that address is targeting an ATR state.
wire address_is_atr = (s_ctrlport_req_addr >= REG_BASE + RF0_ATR_STATE(0)) && (s_ctrlport_req_addr <= REG_BASE + RF3_ATR_STATE(RF3_ATR_STATE_COUNT-1));
// Read request shift register to align memory read and response generation.
reg [ 1:0] read_req_shift_reg = 2'b0;
// Mask out 8 bits for ATR configurations to be able to compare all ATR
// configurations against the same base register address.
wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};
// Decode the ATR state being addressed.
wire [ 7:0] atr_address = s_ctrlport_req_addr[9:2];
always @ (posedge ctrlport_clk) begin
if (ctrlport_rst) begin
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_data <= 32'b0;
s_ctrlport_resp_status <= 2'b00;
atr_disable <= 4'b0;
atr_mode <= 4'b0;
ram_rf0_wea <= 1'b0;
ram_rf1_wea <= 1'b0;
ram_rf2_wea <= 1'b0;
ram_rf3_wea <= 1'b0;
end else begin
// default assignments
read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};
ram_rf0_wea <= 1'b0;
ram_rf1_wea <= 1'b0;
ram_rf2_wea <= 1'b0;
ram_rf3_wea <= 1'b0;
// Write registers
if (s_ctrlport_req_wr) begin
// Acknowledge by default
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
// Address ATR state writes
if(address_is_atr) begin
case (register_base_address)
REG_BASE + RF0_ATR_STATE(0): begin
ram_rf0_wea <= 1'b1;
end
REG_BASE + RF1_ATR_STATE(0): begin
ram_rf1_wea <= 1'b1;
end
REG_BASE + RF2_ATR_STATE(0): begin
ram_rf2_wea <= 1'b1;
end
REG_BASE + RF3_ATR_STATE(0): begin
ram_rf3_wea <= 1'b1;
end
// error on undefined address
default: begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
end
endcase
end else begin
// Address writes to the rest of the register space
case (s_ctrlport_req_addr)
REG_BASE + ATR_OPTION_REGISTER: begin
atr_mode[0] <= s_ctrlport_req_data[RF0_ATR_OPTION];
atr_mode[1] <= s_ctrlport_req_data[RF1_ATR_OPTION];
atr_mode[2] <= s_ctrlport_req_data[RF2_ATR_OPTION];
atr_mode[3] <= s_ctrlport_req_data[RF3_ATR_OPTION];
end
REG_BASE + RF_ATR_DISABLED: begin
atr_disable[0] <= s_ctrlport_req_data[RF0_ATR_DISABLED];
atr_disable[1] <= s_ctrlport_req_data[RF1_ATR_DISABLED];
atr_disable[2] <= s_ctrlport_req_data[RF2_ATR_DISABLED];
atr_disable[3] <= s_ctrlport_req_data[RF3_ATR_DISABLED];
end
// No register implementation for provided address
default: begin
// Acknowledge and provide error status if address is in range
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
end
// Read registers
end else if (read_req_shift_reg[1]) begin
// Acknowledge by default
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
// Address ATR state reads
if(address_is_atr) begin
case (register_base_address)
REG_BASE + RF0_ATR_STATE(0): begin
s_ctrlport_resp_data <= ram_rf0_doa & RF_ATR_STATE_MASK;
end
REG_BASE + RF1_ATR_STATE(0): begin
s_ctrlport_resp_data <= ram_rf1_doa & RF_ATR_STATE_MASK;
end
REG_BASE + RF2_ATR_STATE(0): begin
s_ctrlport_resp_data <= ram_rf2_doa & RF_ATR_STATE_MASK;
end
REG_BASE + RF3_ATR_STATE(0): begin
s_ctrlport_resp_data <= ram_rf3_doa & RF_ATR_STATE_MASK;
end
default: begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
end
endcase
end else begin
// Address reads to the rest of the register space
case (s_ctrlport_req_addr)
REG_BASE + ATR_OPTION_REGISTER: begin
s_ctrlport_resp_data[RF0_ATR_OPTION] <= atr_mode[0];
s_ctrlport_resp_data[RF1_ATR_OPTION] <= atr_mode[1];
s_ctrlport_resp_data[RF2_ATR_OPTION] <= atr_mode[2];
s_ctrlport_resp_data[RF3_ATR_OPTION] <= atr_mode[3];
end
REG_BASE + RF_ATR_DISABLED: begin
s_ctrlport_resp_data[RF0_ATR_DISABLED] <= atr_disable[0];
s_ctrlport_resp_data[RF1_ATR_DISABLED] <= atr_disable[1];
s_ctrlport_resp_data[RF2_ATR_DISABLED] <= atr_disable[2];
s_ctrlport_resp_data[RF3_ATR_DISABLED] <= atr_disable[3];
end
// No register implementation for provided address
default: begin
// Acknowledge and provide error status if address is in range
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// No response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
end
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
// register without reset
reg [ 7:0] ram_addr = 8'b0;
reg [RFS_SIZE-1:0] ram_datain = {RFS_SIZE{1'b0}};
always @(posedge ctrlport_clk) begin
// memories
ram_addr <= atr_address;
ram_datain <= s_ctrlport_req_data[RFS_SIZE-1:0];
end
// ATR Scheme selection
reg [7:0] atr_config_rf [3:0];
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin: read_address_gen
always @(posedge ctrlport_clk) begin
if (atr_disable[i]) begin
atr_config_rf[i] <= 8'b0;
end else begin
if (atr_mode[i]) begin
atr_config_rf[i] <= {6'b0, db_state[2*i+:2]};
end else begin
atr_config_rf[i] <= db_state;
end
end
end
end
endgenerate
// Output decoding
always @(posedge ctrlport_clk) begin
rf0_tx_rx_rfs <= ram_rf0_dob[TX_RX_RFS];
rf0_rx_rfs <= ram_rf0_dob[RX_RFS];
rf0_tdds <= ram_rf0_dob[TDDS];
rf1_tx_rx_rfs <= ram_rf1_dob[TX_RX_RFS];
rf1_rx_rfs <= ram_rf1_dob[RX_RFS];
rf1_tdds <= ram_rf1_dob[TDDS];
rf2_tx_rx_rfs <= ram_rf2_dob[TX_RX_RFS];
rf2_rx_rfs <= ram_rf2_dob[RX_RFS];
rf2_tdds <= ram_rf2_dob[TDDS];
rf3_tx_rx_rfs <= ram_rf3_dob[TX_RX_RFS];
rf3_rx_rfs <= ram_rf3_dob[RX_RFS];
rf3_tdds <= ram_rf3_dob[TDDS];
end
//---------------------------------------------------------------
// ATR memory
//---------------------------------------------------------------
ram_2port #(
.DWIDTH (RFS_SIZE),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0)
) ram_rf0_i (
.clka (ctrlport_clk),
.ena (1'b1),
.wea (ram_rf0_wea),
.addra (ram_addr),
.dia (ram_datain),
.doa (ram_rf0_doa),
.clkb (ctrlport_clk),
.enb (1'b1),
.web (1'b0),
.addrb (atr_config_rf[0]),
.dib ({RFS_SIZE{1'b0}}),
.dob (ram_rf0_dob));
ram_2port #(
.DWIDTH (RFS_SIZE),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0)
) ram_rf1_i (
.clka (ctrlport_clk),
.ena (1'b1),
.wea (ram_rf1_wea),
.addra (ram_addr),
.dia (ram_datain),
.doa (ram_rf1_doa),
.clkb (ctrlport_clk),
.enb (1'b1),
.web (1'b0),
.addrb (atr_config_rf[1]),
.dib ({RFS_SIZE{1'b0}}),
.dob (ram_rf1_dob));
ram_2port #(
.DWIDTH (RFS_SIZE),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0)
) ram_rf2_i (
.clka (ctrlport_clk),
.ena (1'b1),
.wea (ram_rf2_wea),
.addra (ram_addr),
.dia (ram_datain),
.doa (ram_rf2_doa),
.clkb (ctrlport_clk),
.enb (1'b1),
.web (1'b0),
.addrb (atr_config_rf[2]),
.dib ({RFS_SIZE{1'b0}}),
.dob (ram_rf2_dob));
ram_2port #(
.DWIDTH (RFS_SIZE),
.AWIDTH (8),
.RW_MODE ("READ-FIRST"),
.RAM_TYPE ("AUTOMATIC"),
.OUT_REG (0)
) ram_rf3_i (
.clka (ctrlport_clk),
.ena (1'b1),
.wea (ram_rf3_wea),
.addra (ram_addr),
.dia (ram_datain),
.doa (ram_rf3_doa),
.clkb (ctrlport_clk),
.enb (1'b1),
.web (1'b0),
.addrb (atr_config_rf[3]),
.dib ({RFS_SIZE{1'b0}}),
.dob (ram_rf3_dob));
endmodule
//XmlParse xml_on
//<regmap name="RF_ATR_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="RF_ATR_REGISTERS">
// <info>
// Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1
// switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for
// all four switches are not considered time critical controls, and are hence driven by an I/O
// expander controlled via I2C.
// This register map describes how to control the behavior of the 3 HMC849A switches' control lines.
// There are three supported control schemes for these switches:</br>
// <ul>
// <li>ATR Disabled - Single persistent state.</li>
// <li>Classic ATR - Each channel's switches depend on the transmission state
// of the respective channel.</li>
// <li>DB State - Each channel's switches depend on the transmission state
// of all channels in this radio.</li>
// </ul>
// </info>
//
// <enumeratedtype name="RF_SWITCHES_SIZE_TYPE">
// <value name="RFS_SIZE" integer="3"/>
// </enumeratedtype>
//
// <regtype name="RF_ATR_STATE" size="32">
// <info>Holds the value for the control lines of each channel's switches
// for a particular ATR sate</info>
// <bitfield name="TX_RX_RFS" range="0" initialvalue="0"/>
// <bitfield name="RX_RFS" range="1" initialvalue="0"/>
// <bitfield name="TDDS" range="2" initialvalue="0"/>
// </regtype>
//
// <register name="RF0_ATR_STATE" typename="RF_ATR_STATE" offset="0x00" count="256" options="--step 4">
// <info>
// Describes switch control behavior for the different ATR states. When @.RF0_ATR_OPTION
// is set to use the DB states, TX and RX states for RF0-RF3 are
// combined to create a single vector. This creates 256 different
// combinations, each with its own register. When @.RF0_ATR_OPTION is set to
// classic ATR, the first 4 offsets in this register group will be driven
// in accordance with the state of RF0.
// CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1,
// TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1]
// </info>
// </register>
//
// <register name="RF1_ATR_STATE" typename="RF_ATR_STATE" offset="0x400" count="256" options="--step 4">
// <info>
// Describes switch control behavior for the different ATR states. When @.RF1_ATR_OPTION
// is set to use the DB states, TX and RX states for RF0-RF3 are
// combined to create a single vector. This creates 256 different
// combinations, each with its own register. When @.RF1_ATR_OPTION is set to
// classic ATR, the first 4 offsets in this register group will be driven
// in accordance with the state of RF1.
// CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1,
// TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1]
// </info>
// </register>
//
// <register name="RF2_ATR_STATE" typename="RF_ATR_STATE" offset="0x800" count="256" options="--step 4">
// <info>
// Describes switch control behavior for the different ATR states. When @.RF2_ATR_OPTION
// is set to use the DB states, TX and RX states for RF0-RF3 are
// combined to create a single vector. This creates 256 different
// combinations, each with its own register. When @.RF2_ATR_OPTION is set to
// classic ATR, the first 4 offsets in this register group will be driven
// in accordance with the state of RF2.
// CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1,
// TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1]
// </info>
// </register>
//
// <register name="RF3_ATR_STATE" typename="RF_ATR_STATE" offset="0xC00" count="256" options="--step 4">
// <info>
// Describes switch control behavior for the different ATR states. When @.RF3_ATR_OPTION
// is set to use the DB states, TX and RX states for RF0-RF3 are
// combined to create a single vector. This creates 256 different
// combinations, each with its own register. When @.RF3_ATR_OPTION is set to
// classic ATR, the first 4 offsets in this register group will be driven
// in accordance with the state of RF3.
// CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1,
// TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1]
// </info>
// </register>
// <register name="ATR_OPTION_REGISTER" offset="0x1000" size="32">
// <info>
// Controls whether switch control lines use the TX and RX state of
// their respective channel (Classic ATR) or the daughterboard state
// to select which state to use from values set in RF_ATR_STATE registers.
// For each particular bit:</br>
// 0: Use DB state for ATR</br>
// 1: Classic ATR mode.
// </info>
// <bitfield name="RF0_ATR_OPTION" range="0" initialvalue="0">
// <info>
// Control ATR scheme for RF0.
// </info>
// </bitfield>
// <bitfield name="RF1_ATR_OPTION" range="1" initialvalue="0">
// <info>
// Control ATR scheme for RF1.
// </info>
// </bitfield>
// <bitfield name="RF2_ATR_OPTION" range="2" initialvalue="0">
// <info>
// Control ATR scheme for RF2.
// </info>
// </bitfield>
// <bitfield name="RF3_ATR_OPTION" range="3" initialvalue="0">
// <info>
// Control ATR scheme for RF3.
// </info>
// </bitfield>
// </register>
// <register name="RF_ATR_DISABLED" offset="0x1004" size="32">
// <info>
// Disable ATR Control. DB state 0 will be reflected regardless of the ATR state.
// </info>
// <bitfield name="RF0_ATR_DISABLED" range="0" initialvalue="0"/>
// <bitfield name="RF1_ATR_DISABLED" range="1" initialvalue="0"/>
// <bitfield name="RF2_ATR_DISABLED" range="2" initialvalue="0"/>
// <bitfield name="RF3_ATR_DISABLED" range="3" initialvalue="0"/>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/dboards/fbx/sim/clock_en_control/Makefile
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir.
BASE_DIR = ../../../../..
# Include viv_sim_preample after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Define part using PART_ID (<device>/<package>/<speedgrade>)
ARCH = zynquplusRFSOC
PART_ID = xczu28dr/ffvg1517/-1/e
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/control/Makefile.srcs
DESIGN_SRCS += $(abspath \
$(FIFO_SRCS) \
$(AXI_SRCS) \
$(CONTROL_LIB_SRCS) \
$(WISHBONE_SRCS) \
)
DESIGN_SRCS += $(abspath \
../../regmap/fbx_ctrl_regmap_utils.vh \
../../regmap/clock_en_regmap_utils.vh \
../../clock_en_control.v \
)
#-------------------------------------------------
# IP Specific
#-------------------------------------------------
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory
IP_DIR = $(BASE_DIR)/x400/ip
LIB_IP_DIR = $(BASE_DIR)/../lib/ip
# Include makefiles and sources for all IP components
# *after* defining the IP_DIR
#
# These TBs don't use any IP yet :)
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
include $(BASE_DIR)/../sim/general/Makefile.srcs
# Define only one top-level module
SIM_TOP = clock_en_control_tb glbl
# Simulation runtime in microseconds
SIM_RUNTIME_US = 100000
SIM_SRCS = \
$(abspath clock_en_control_tb.sv) \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak
top/x400/dboards/fbx/sim/clock_en_control/clock_en_control_tb.sv
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//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: clock_en_control_tb
//
// Description:
// Testbench for clock_en_control and clock_div modules. Tasks defined for ctrlport write and
// read transactions. Tests clock enable control with ctrlport reads and writes.
//
`timescale 1ns / 1ps
`define NS_PER_TICK 1
`define NUM_TEST_CASES 4
`include "sim_exec_report.vh"
`include "sim_clks_rsts.vh"
module clock_en_control_tb();
import PkgRandom::*;
PkgRandom::Rand #(5) rand_clk_count;
`TEST_BENCH_INIT("clock_en_control_tb", `NUM_TEST_CASES, `NS_PER_TICK);
//sets up clock
localparam CLK_PERIOD = $ceil(1e9/50.0e6);
localparam CLK_PERIOD_10 = $ceil(1e9/10.0e6);
`DEFINE_CLK(clk50, CLK_PERIOD, 50);
`DEFINE_CLK(clk10, CLK_PERIOD_10, 50);
localparam N = 2;
localparam N_DIV2 = N/2;
reg reset_clk50;
reg clk10_rst;
reg s_ctrlport_req_wr;
reg s_ctrlport_req_rd;
reg [19:0] s_ctrlport_req_addr;
reg [31:0] s_ctrlport_req_data;
// Response
wire s_ctrlport_resp_ack;
wire [ 1:0] s_ctrlport_resp_status;
wire [31:0] s_ctrlport_resp_data;
wire clk5, clk5_buf;
`include "../../regmap/clock_en_regmap_utils.vh"
task cp_write;
input [19:0] a;
input [31:0] d;
begin
s_ctrlport_req_addr = a;
s_ctrlport_req_data = d;
@(posedge clk50);
s_ctrlport_req_wr = 1;
@(posedge clk50);
while(~s_ctrlport_resp_ack) @(posedge clk50);
s_ctrlport_req_wr = 0;
@(posedge clk50);
end
endtask
task cp_read;
input [19:0] a;
input [31:0] d;
input debug;
begin
s_ctrlport_req_addr = a;
@(posedge clk50);
s_ctrlport_req_rd = 1;
@(posedge clk50);
while(~s_ctrlport_resp_ack) @(posedge clk50);
s_ctrlport_req_rd = 0;
@(posedge clk50);
if(debug) begin
$display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data);
end
`ASSERT_ERROR( s_ctrlport_resp_data == d, "CtrlPort read returned unexpected value.");
end
endtask
clock_div #(
.N(N)
) clock_div_5mhz (
.clk_in (clk10),
.clk_in_rst (clk10_rst),
.clk_out (clk5)
);
clock_en_control #(
.BASE_ADDRESS(0)
) clock_en_control_inst (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (s_ctrlport_req_wr),
.s_ctrlport_req_rd (s_ctrlport_req_rd),
.s_ctrlport_req_addr (s_ctrlport_req_addr),
.s_ctrlport_req_data (s_ctrlport_req_data),
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
.s_ctrlport_resp_status (s_ctrlport_resp_status),
.s_ctrlport_resp_data (s_ctrlport_resp_data),
.clk_in (clk5),
.clk_out (clk5_buf)
);
// clock counters to verify clock division
reg counter_reset;
reg [8:0] clock_counter;
reg [10:0] div_clock_counter;
reg [10:0] expected_clock_count;
reg [8:0] expected_div_clock_count;
always @(posedge clk10) begin
if(counter_reset) begin
clock_counter <= 0;
end else begin
clock_counter <= clock_counter + 1;
end
end
always @(posedge clk5_buf) begin
if(counter_reset) begin
div_clock_counter <= 0;
end else begin
div_clock_counter <= div_clock_counter + 1;
end
end
// main test cases
initial begin : tb_main
`TEST_CASE_START("initialize UUT");
reset_clk50 = 1;
clk10_rst = 1;
s_ctrlport_req_wr = 0;
s_ctrlport_req_rd = 0;
s_ctrlport_req_addr = 0;
s_ctrlport_req_data = 0;
#200 //wait a cycle for the 10mhz clk rst
reset_clk50 = 0;
clk10_rst = 0;
$display("status: %t done reset here", $time);
`TEST_CASE_DONE(~reset_clk50);
// trigger setup
`TEST_CASE_START("Check that clock_out is not running");
@(posedge clk5);
@(posedge clk10);
`ASSERT_ERROR( clk5_buf == 0, "clk5_buf should be zero now.");
repeat (N) @(posedge clk10);
`TEST_CASE_DONE(clk5_buf == 0 && clk5 == 1);
`TEST_CASE_START("Enable clock with clock_en_control enable register");
cp_read(CLK_EN_CONTROL, 0, 1); //initial value should be zero
cp_write(CLK_EN_CONTROL, CLK_EN_CONTROL_MASK);
cp_read(CLK_EN_CONTROL, CLK_EN_CONTROL_MASK, 1);
@(posedge clk5_buf);
repeat (N_DIV2+1) @(posedge clk10);
`ASSERT_ERROR( clk5_buf == 0, "clk5_buf should be zero now.");
repeat (N_DIV2) @(posedge clk10);
`TEST_CASE_DONE(clk5_buf == 1 && s_ctrlport_resp_data == CLK_EN_CONTROL_MASK);
`TEST_CASE_START("Verify expected clock division.");
expected_div_clock_count = 5 + rand_clk_count.rand_bit();
expected_clock_count = N*expected_div_clock_count;
$display("Reset clock counters @ time %t and then count main clock &d times and divided clock %d times", $time, expected_clock_count, expected_div_clock_count);
@(posedge clk5_buf);
counter_reset = 1;
@(posedge clk5_buf);
counter_reset = 0;
repeat (expected_div_clock_count) @(posedge clk5_buf);
@(posedge clk10);
`TEST_CASE_DONE(div_clock_counter == expected_div_clock_count && clock_counter == expected_clock_count);
`TEST_BENCH_DONE;
end
endmodule
top/x400/dboards/fbx/sim/i2c_sync_ctrl/Makefile
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir.
BASE_DIR = ../../../../..
# Include viv_sim_preample after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Define part using PART_ID (<device>/<package>/<speedgrade>)
ARCH = zynquplusRFSOC
PART_ID = xczu28dr/ffvg1517/-1/e
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/control/Makefile.srcs
include $(BASE_DIR)/../lib/wishbone/Makefile.srcs
DESIGN_SRCS += $(abspath \
$(FIFO_SRCS) \
$(AXI_SRCS) \
$(CONTROL_LIB_SRCS) \
$(WISHBONE_SRCS) \
)
DESIGN_SRCS += $(abspath \
../../regmap/fbx_ctrl_regmap_utils.vh \
../../regmap/rf_sync_regmap_utils.vh \
../../ctrlport_to_i2c_sync_ctrl.v \
)
#-------------------------------------------------
# IP Specific
#-------------------------------------------------
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory
IP_DIR = $(BASE_DIR)/x400/ip
LIB_IP_DIR = $(BASE_DIR)/../lib/ip
# Include makefiles and sources for all IP components
# *after* defining the IP_DIR
#
# These TBs don't use any IP yet :)
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
include $(BASE_DIR)/../sim/general/Makefile.srcs
# Define only one top-level module
SIM_TOP = ctrlport_to_i2c_sync_ctrl_tb
# Simulation runtime in microseconds
SIM_RUNTIME_US = 200000
SIM_SRCS = \
$(abspath ctrlport_to_i2c_sync_ctrl_tb.sv) \
$(abspath $(BASE_DIR)/../lib/sim/wishbone/i2c/i2c_slave_model.v) \
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak
top/x400/dboards/fbx/sim/i2c_sync_ctrl/ctrlport_to_i2c_sync_ctrl_tb.sv
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//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: ctrlport_to_i2c_sync_ctrl_tb
//
// Description:
// testbench for ctrlport_to_i2c_sync_ctrl module. Tasks defined for ctrlport write and
// read transactions. Tests ability to write to SYNC/RFS_EN regs and then
// initialize i2c_master and i2c peripheral and then configure io through the
// i2c interface to the io expander.
//
`timescale 1ns / 1ps
`define NS_PER_TICK 1
`define NUM_TEST_CASES 5
`include "sim_exec_report.vh"
`include "sim_clks_rsts.vh"
`define SIM_TIMEOUT_US 200000 //overwrite this def from sim_exec_report.vh
module ctrlport_to_i2c_sync_ctrl_tb();
import PkgRandom::*;
`TEST_BENCH_INIT("ctrlport_to_i2c_sync_ctrl_tb", `NUM_TEST_CASES, `NS_PER_TICK);
//sets up clock
localparam CLK_PERIOD = $ceil(1e9/50.0e6);
`DEFINE_CLK(clk50, CLK_PERIOD, 50);
reg reset_clk50;
reg s_ctrlport_req_wr;
reg s_ctrlport_req_rd;
reg [19:0] s_ctrlport_req_addr;
reg [31:0] s_ctrlport_req_data;
// Response
wire s_ctrlport_resp_ack;
wire [ 1:0] s_ctrlport_resp_status;
wire [31:0] s_ctrlport_resp_data;
wire i2c_scl_i, i2c_scl_o, i2c_scl_en_o;
wire i2c_sda_i, i2c_sda_o, i2c_sda_en_o;
PkgRandom::Rand #(3) rand_sync;
PkgRandom::Rand #(1) rand_rfs_en;
reg [2:0] sync1, sync2, sync3, sync4, sync5;
reg rfs_en;
`include "../../regmap/rf_sync_regmap_utils.vh"
task cp_write;
input [19:0] a;
input [31:0] d;
begin
s_ctrlport_req_addr = a;
s_ctrlport_req_data = d;
@(posedge clk50);
s_ctrlport_req_wr = 1;
@(posedge clk50);
while(~s_ctrlport_resp_ack) @(posedge clk50);
s_ctrlport_req_wr = 0;
@(posedge clk50);
end
endtask
task cp_read;
input [19:0] a;
input [31:0] d;
input debug;
begin
s_ctrlport_req_addr = a;
s_ctrlport_req_rd = 1;
@(posedge clk50);
while(~s_ctrlport_resp_ack) @(posedge clk50);
s_ctrlport_req_rd = 0;
@(posedge clk50);
if(debug) begin
$display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data);
end
`ASSERT_ERROR( s_ctrlport_resp_data == d, "CtrlPort read returned unexpected value.");
end
endtask
task cp_poll;
input [19:0] a;
input [31:0] d;
input debug;
begin
s_ctrlport_req_addr = a;
s_ctrlport_req_rd = 1;
@(posedge clk50);
while(~s_ctrlport_resp_ack) @(posedge clk50);
s_ctrlport_req_rd = 0;
@(posedge clk50);
while(s_ctrlport_resp_data != d && s_ctrlport_req_addr == a) begin
s_ctrlport_req_addr = a;
s_ctrlport_req_rd = 1;
@(posedge clk50);
while(~s_ctrlport_resp_ack) @(posedge clk50);
s_ctrlport_req_rd = 0;
@(posedge clk50);
end
if(debug) begin
$display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data);
end
end
endtask
ctrlport_to_i2c_sync_ctrl #(
.BASE_ADDRESS(0)
) ctrlport_to_i2c_inst (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (s_ctrlport_req_wr),
.s_ctrlport_req_rd (s_ctrlport_req_rd),
.s_ctrlport_req_addr (s_ctrlport_req_addr),
.s_ctrlport_req_data (s_ctrlport_req_data),
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
.s_ctrlport_resp_status (s_ctrlport_resp_status),
.s_ctrlport_resp_data (s_ctrlport_resp_data),
.scl_pad_i (i2c_scl_i),
.scl_pad_o (i2c_scl_o),
.scl_pad_en_o (i2c_scl_en_o),
.sda_pad_i (i2c_sda_i),
.sda_pad_o (i2c_sda_o),
.sda_pad_en_o (i2c_sda_en_o)
);
// hookup i2c slave model
i2c_slave_model #(
ctrlport_to_i2c_inst.SYNC_IO_SLV_ADR
) i2c_slave (
.scl(i2c_scl_i),
.sda(i2c_sda_i)
);
// create i2c lines
delay m0_scl (i2c_scl_en_o ? 1'bz : i2c_scl_o, i2c_scl_i),
m0_sda (i2c_sda_en_o ? 1'bz : i2c_sda_o, i2c_sda_i);
pullup p1(i2c_scl_i); // pullup scl line
pullup p2(i2c_sda_i); // pullup sda line
initial begin : tb_main
`TEST_CASE_START("initialize UUT");
clk50 = 0;
reset_clk50 = 1;
s_ctrlport_req_wr = 0;
s_ctrlport_req_rd = 0;
s_ctrlport_req_addr = 0;
s_ctrlport_req_data = 0;
#100
reset_clk50 = 0;
$display("status: %t done reset here", $time);
`TEST_CASE_DONE(~reset_clk50);
// trigger setup
`TEST_CASE_START("Initialize core and I2C peripheral");
cp_write(SETUP_REG, 1);
cp_poll(SETUP_STATUS_REG,1,1);
`TEST_CASE_DONE(i2c_slave.mem[7] == 0 & i2c_slave.mem[6] == 0);
$display("status: %t SETUP DONE", $time);
// configure SYNC and RFS_EN Regs
for (int i=0; i<3; i=i+1) begin
`TEST_CASE_START("configure SYNC and RFS_EN Regs loop");
$display("loop # %d", i);
sync1 = rand_sync.rand_bit();
sync2 = rand_sync.rand_bit();
sync3 = rand_sync.rand_bit();
sync4 = rand_sync.rand_bit();
sync5 = rand_sync.rand_bit();
rfs_en = rand_rfs_en.rand_bit();
cp_write(SYNC_1_REG, sync1);
cp_write(SYNC_2_REG, sync2);
cp_write(SYNC_3_REG, sync3);
cp_write(SYNC_4_REG, sync4);
cp_write(SYNC_5_REG, sync5);
cp_write(RFS_EN_REG, rfs_en);
cp_read(SYNC_1_REG, {28'b0, sync1}, 1);
cp_read(SYNC_2_REG, {28'b0, sync2}, 1);
cp_read(SYNC_3_REG, {28'b0, sync3}, 1);
cp_read(SYNC_4_REG, {28'b0, sync4}, 1);
cp_read(SYNC_5_REG, {28'b0, sync5}, 1);
cp_read(RFS_EN_REG, {31'b0, rfs_en}, 1);
$display("status: %t Configured ControlPort regs, now configure I2C peripheral.", $time);
cp_write(CONFIG_IO_REG, 1);
cp_poll(CONFIG_IO_STATUS_REG,32'h1,1);
`TEST_CASE_DONE(i2c_slave.mem[2] == {sync3[1:0], sync2, sync1} &
i2c_slave.mem[3] == {rfs_en, sync5, sync4, sync3[2]});
end
`TEST_BENCH_DONE;
end
endmodule
module delay (in, out);
input in;
output out;
assign out = in;
specify
(in => out) = (600,600);
endspecify
endmodule
top/x400/doc/X4XX_FPGA.htm → top/x400/doc/X440/X440_FPGA.htm
+3 -3
View File
@@ -1,10 +1,10 @@
<HTML>
<HEAD>
<title>X4XX_FPGA</title>
<title>X440_FPGA</title>
<FRAMESET COLS="20%,*" onload=window.frames[1].location.hash=window.location.href.split("#")[1];>
<FRAME name="leftframe" SRC="X4XX_FPGA_left.htm">
<FRAME name="rightframe" SRC="X4XX_FPGA_right.htm">
<FRAME name="leftframe" SRC="X440_FPGA_left.htm">
<FRAME name="rightframe" SRC="X440_FPGA_right.htm">
</FRAMESET>
</HEAD>
</HTML>
top/x400/doc/X4XX_FPGA_left.htm → top/x400/doc/X440/X440_FPGA_left.htm
+127 -26
View File
@@ -127,10 +127,10 @@
<div class="nav">
<p>
<span class="pm" id="pm_X4XX_FPGA" onclick="pm('X4XX_FPGA');">+</span>
<span class="regmap" id="a_X4XX_FPGA" onclick="a('X4XX_FPGA');">X4XX_FPGA</span>
<span class="pm" id="pm_X440_FPGA" onclick="pm('X440_FPGA');">+</span>
<span class="regmap" id="a_X440_FPGA" onclick="a('X440_FPGA');">X440_FPGA</span>
</p>
<div class="sh" id="div_X4XX_FPGA">
<div class="sh" id="div_X440_FPGA">
<p>
<span class="pm" id="pm_P5 Content" onclick="pm('P5 Content');">+</span>
<span class="group" id="a_P5 Content" onclick="a('P5 Content');">P5 Content</span>
@@ -142,10 +142,10 @@
<span class="group" id="a_ports" onclick="a('ports');">ports</span>
</p>
<div class="sh" id="div_ports">
<p><span class="register" id="a_X4XX_FPGA|ARM_M_AXI_HPM0" onclick="a('X4XX_FPGA|ARM_M_AXI_HPM0');">ARM_M_AXI_HPM0</span></p>
<p><span class="register" id="a_X4XX_FPGA|ARM_S_AXI_HPC0" onclick="a('X4XX_FPGA|ARM_S_AXI_HPC0');">ARM_S_AXI_HPC0</span></p>
<p><span class="register" id="a_X4XX_FPGA|ARM_S_AXI_HPC1" onclick="a('X4XX_FPGA|ARM_S_AXI_HPC1');">ARM_S_AXI_HPC1</span></p>
<p><span class="register" id="a_X4XX_FPGA|ARM_SPI1_CS3" onclick="a('X4XX_FPGA|ARM_SPI1_CS3');">ARM_SPI1_CS3</span></p>
<p><span class="register" id="a_X440_FPGA|ARM_M_AXI_HPM0" onclick="a('X440_FPGA|ARM_M_AXI_HPM0');">ARM_M_AXI_HPM0</span></p>
<p><span class="register" id="a_X440_FPGA|ARM_S_AXI_HPC0" onclick="a('X440_FPGA|ARM_S_AXI_HPC0');">ARM_S_AXI_HPC0</span></p>
<p><span class="register" id="a_X440_FPGA|ARM_S_AXI_HPC1" onclick="a('X440_FPGA|ARM_S_AXI_HPC1');">ARM_S_AXI_HPC1</span></p>
<p><span class="register" id="a_X440_FPGA|ARM_SPI1_CS3" onclick="a('X440_FPGA|ARM_SPI1_CS3');">ARM_SPI1_CS3</span></p>
</div>
</div>
<p>
@@ -203,6 +203,18 @@
<p><span class="enum" id="a_MB_CPLD_PS_REGMAP|SPI_ENDPOINT" onclick="a('MB_CPLD_PS_REGMAP|SPI_ENDPOINT');">enum SPI_ENDPOINT</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_CLK_EN_REGMAP" onclick="pm('CLK_EN_REGMAP');">+</span>
<span class="regmap" id="a_CLK_EN_REGMAP" onclick="a('CLK_EN_REGMAP');">CLK_EN_REGMAP</span>
</p> <div class="sh" id="div_CLK_EN_REGMAP">
<p>
<span class="pm" id="pm_CLK_EN_REGMAP|CLK_EN_REGISTERS" onclick="pm('CLK_EN_REGMAP|CLK_EN_REGISTERS');">+</span>
<span class="group" id="a_CLK_EN_REGMAP|CLK_EN_REGISTERS" onclick="a('CLK_EN_REGMAP|CLK_EN_REGISTERS');">CLK_EN_REGISTERS</span>
</p>
<div class="sh" id="div_CLK_EN_REGMAP|CLK_EN_REGISTERS">
<p><span class="register" id="a_CLK_EN_REGMAP|CLK_EN_CONTROL" onclick="a('CLK_EN_REGMAP|CLK_EN_CONTROL');">CLK_EN_CONTROL</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_CMAC_REGMAP" onclick="pm('CMAC_REGMAP');">+</span>
<span class="regmap" id="a_CMAC_REGMAP" onclick="a('CMAC_REGMAP');">CMAC_REGMAP</span>
@@ -237,7 +249,8 @@
<div class="sh" id="div_CORE_REGS_REGMAP|CORE_REGS">
<p><span class="register" id="a_CORE_REGS_REGMAP|GLOBAL_REGS" onclick="a('CORE_REGS_REGMAP|GLOBAL_REGS');">GLOBAL_REGS</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|VERSIONING_REGS" onclick="a('CORE_REGS_REGMAP|VERSIONING_REGS');">VERSIONING_REGS</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|TIMEKEEPER" onclick="a('CORE_REGS_REGMAP|TIMEKEEPER');">TIMEKEEPER</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|TIMEKEEPER_A" onclick="a('CORE_REGS_REGMAP|TIMEKEEPER_A');">TIMEKEEPER_A</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|TIMEKEEPER_B" onclick="a('CORE_REGS_REGMAP|TIMEKEEPER_B');">TIMEKEEPER_B</span></p>
<p><span class="register" id="a_CORE_REGS_REGMAP|DIO" onclick="a('CORE_REGS_REGMAP|DIO');">DIO</span></p>
</div>
</div>
@@ -329,6 +342,21 @@
<p><span class="register" id="a_ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL" onclick="a('ETH_DMA_CTRL_REGMAP|ETH_IO_CTRL');">ETH_IO_CTRL</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_FBX_CTRL_REGMAP" onclick="pm('FBX_CTRL_REGMAP');">+</span>
<span class="regmap" id="a_FBX_CTRL_REGMAP" onclick="a('FBX_CTRL_REGMAP');">FBX_CTRL_REGMAP</span>
</p> <div class="sh" id="div_FBX_CTRL_REGMAP">
<p>
<span class="pm" id="pm_FBX_CTRL_REGMAP|FBX_CONTROLS" onclick="pm('FBX_CTRL_REGMAP|FBX_CONTROLS');">+</span>
<span class="group" id="a_FBX_CTRL_REGMAP|FBX_CONTROLS" onclick="a('FBX_CTRL_REGMAP|FBX_CONTROLS');">FBX_CONTROLS</span>
</p>
<div class="sh" id="div_FBX_CTRL_REGMAP|FBX_CONTROLS">
<p><span class="register" id="a_FBX_CTRL_REGMAP|RF_ATR_REGS" onclick="a('FBX_CTRL_REGMAP|RF_ATR_REGS');">RF_ATR_REGS</span></p>
<p><span class="register" id="a_FBX_CTRL_REGMAP|RF_SYNC_REGS" onclick="a('FBX_CTRL_REGMAP|RF_SYNC_REGS');">RF_SYNC_REGS</span></p>
<p><span class="register" id="a_FBX_CTRL_REGMAP|LED_ATR_REGS" onclick="a('FBX_CTRL_REGMAP|LED_ATR_REGS');">LED_ATR_REGS</span></p>
<p><span class="register" id="a_FBX_CTRL_REGMAP|SYNC_CLK_EN_REGS" onclick="a('FBX_CTRL_REGMAP|SYNC_CLK_EN_REGS');">SYNC_CLK_EN_REGS</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_GLOBAL_REGS_REGMAP" onclick="pm('GLOBAL_REGS_REGMAP');">+</span>
<span class="regmap" id="a_GLOBAL_REGS_REGMAP" onclick="a('GLOBAL_REGS_REGMAP');">GLOBAL_REGS_REGMAP</span>
@@ -386,18 +414,33 @@
</div>
</div>
<p>
<span class="pm" id="pm_JTAG_REGMAP" onclick="pm('JTAG_REGMAP');">+</span>
<span class="regmap" id="a_JTAG_REGMAP" onclick="a('JTAG_REGMAP');">JTAG_REGMAP</span>
</p> <div class="sh" id="div_JTAG_REGMAP">
<span class="pm" id="pm_LED_ATR_REGMAP" onclick="pm('LED_ATR_REGMAP');">+</span>
<span class="regmap" id="a_LED_ATR_REGMAP" onclick="a('LED_ATR_REGMAP');">LED_ATR_REGMAP</span>
</p> <div class="sh" id="div_LED_ATR_REGMAP">
<p>
<span class="pm" id="pm_JTAG_REGMAP|JTAG_REGS" onclick="pm('JTAG_REGMAP|JTAG_REGS');">+</span>
<span class="group" id="a_JTAG_REGMAP|JTAG_REGS" onclick="a('JTAG_REGMAP|JTAG_REGS');">JTAG_REGS</span>
<span class="pm" id="pm_LED_ATR_REGMAP|LED_ATR_REGISTERS" onclick="pm('LED_ATR_REGMAP|LED_ATR_REGISTERS');">+</span>
<span class="group" id="a_LED_ATR_REGMAP|LED_ATR_REGISTERS" onclick="a('LED_ATR_REGMAP|LED_ATR_REGISTERS');">LED_ATR_REGISTERS</span>
</p>
<div class="sh" id="div_JTAG_REGMAP|JTAG_REGS">
<p><span class="register" id="a_JTAG_REGMAP|TX_DATA" onclick="a('JTAG_REGMAP|TX_DATA');">TX_DATA</span></p>
<p><span class="register" id="a_JTAG_REGMAP|STB_DATA" onclick="a('JTAG_REGMAP|STB_DATA');">STB_DATA</span></p>
<p><span class="register" id="a_JTAG_REGMAP|CONTROL" onclick="a('JTAG_REGMAP|CONTROL');">CONTROL</span></p>
<p><span class="register" id="a_JTAG_REGMAP|RX_DATA" onclick="a('JTAG_REGMAP|RX_DATA');">RX_DATA</span></p>
<div class="sh" id="div_LED_ATR_REGMAP|LED_ATR_REGISTERS">
<p><span class="enum" id="a_LED_ATR_REGMAP|LED_SIZE_TYPE" onclick="a('LED_ATR_REGMAP|LED_SIZE_TYPE');">enum LED_SIZE_TYPE</span></p>
<p><span class="register" id="a_LED_ATR_REGMAP|LED0_ATR_STATE" onclick="a('LED_ATR_REGMAP|LED0_ATR_STATE');">LED0_ATR_STATE</span></p>
<p><span class="register" id="a_LED_ATR_REGMAP|LED1_ATR_STATE" onclick="a('LED_ATR_REGMAP|LED1_ATR_STATE');">LED1_ATR_STATE</span></p>
<p><span class="register" id="a_LED_ATR_REGMAP|LED2_ATR_STATE" onclick="a('LED_ATR_REGMAP|LED2_ATR_STATE');">LED2_ATR_STATE</span></p>
<p><span class="register" id="a_LED_ATR_REGMAP|LED3_ATR_STATE" onclick="a('LED_ATR_REGMAP|LED3_ATR_STATE');">LED3_ATR_STATE</span></p>
<p><span class="register" id="a_LED_ATR_REGMAP|LED_ATR_OPTION_REGISTER" onclick="a('LED_ATR_REGMAP|LED_ATR_OPTION_REGISTER');">LED_ATR_OPTION_REGISTER</span></p>
<p><span class="register" id="a_LED_ATR_REGMAP|LED_ATR_DISABLED" onclick="a('LED_ATR_REGMAP|LED_ATR_DISABLED');">LED_ATR_DISABLED</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_LED_SETUP_REGMAP" onclick="pm('LED_SETUP_REGMAP');">+</span>
<span class="regmap" id="a_LED_SETUP_REGMAP" onclick="a('LED_SETUP_REGMAP');">LED_SETUP_REGMAP</span>
</p> <div class="sh" id="div_LED_SETUP_REGMAP">
<p>
<span class="pm" id="pm_LED_SETUP_REGMAP|LED_SETUP_REGISTERS" onclick="pm('LED_SETUP_REGMAP|LED_SETUP_REGISTERS');">+</span>
<span class="group" id="a_LED_SETUP_REGMAP|LED_SETUP_REGISTERS" onclick="a('LED_SETUP_REGMAP|LED_SETUP_REGISTERS');">LED_SETUP_REGISTERS</span>
</p>
<div class="sh" id="div_LED_SETUP_REGMAP|LED_SETUP_REGISTERS">
<p><span class="register" id="a_LED_SETUP_REGMAP|LED_CONTROL" onclick="a('LED_SETUP_REGMAP|LED_CONTROL');">LED_CONTROL</span></p>
</div>
</div>
<p>
@@ -410,8 +453,8 @@
</p>
<div class="sh" id="div_MB_CPLD_PL_REGMAP|MB_CPLD_PL_WINDOWS">
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|PL_REGISTERS" onclick="a('MB_CPLD_PL_REGMAP|PL_REGISTERS');">PL_REGISTERS</span></p>
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|JTAG_DB0" onclick="a('MB_CPLD_PL_REGMAP|JTAG_DB0');">JTAG_DB0</span></p>
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|JTAG_DB1" onclick="a('MB_CPLD_PL_REGMAP|JTAG_DB1');">JTAG_DB1</span></p>
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|PL_DB0_LED_REGISTERS" onclick="a('MB_CPLD_PL_REGMAP|PL_DB0_LED_REGISTERS');">PL_DB0_LED_REGISTERS</span></p>
<p><span class="register" id="a_MB_CPLD_PL_REGMAP|PL_DB1_LED_REGISTERS" onclick="a('MB_CPLD_PL_REGMAP|PL_DB1_LED_REGISTERS');">PL_DB1_LED_REGISTERS</span></p>
</div>
</div>
<p>
@@ -619,6 +662,59 @@
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG');">FLASH_CFM0_END_ADDR_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RF_ATR_REGMAP" onclick="pm('RF_ATR_REGMAP');">+</span>
<span class="regmap" id="a_RF_ATR_REGMAP" onclick="a('RF_ATR_REGMAP');">RF_ATR_REGMAP</span>
</p> <div class="sh" id="div_RF_ATR_REGMAP">
<p>
<span class="pm" id="pm_RF_ATR_REGMAP|RF_ATR_REGISTERS" onclick="pm('RF_ATR_REGMAP|RF_ATR_REGISTERS');">+</span>
<span class="group" id="a_RF_ATR_REGMAP|RF_ATR_REGISTERS" onclick="a('RF_ATR_REGMAP|RF_ATR_REGISTERS');">RF_ATR_REGISTERS</span>
</p>
<div class="sh" id="div_RF_ATR_REGMAP|RF_ATR_REGISTERS">
<p><span class="enum" id="a_RF_ATR_REGMAP|RF_SWITCHES_SIZE_TYPE" onclick="a('RF_ATR_REGMAP|RF_SWITCHES_SIZE_TYPE');">enum RF_SWITCHES_SIZE_TYPE</span></p>
<p><span class="register" id="a_RF_ATR_REGMAP|RF0_ATR_STATE" onclick="a('RF_ATR_REGMAP|RF0_ATR_STATE');">RF0_ATR_STATE</span></p>
<p><span class="register" id="a_RF_ATR_REGMAP|RF1_ATR_STATE" onclick="a('RF_ATR_REGMAP|RF1_ATR_STATE');">RF1_ATR_STATE</span></p>
<p><span class="register" id="a_RF_ATR_REGMAP|RF2_ATR_STATE" onclick="a('RF_ATR_REGMAP|RF2_ATR_STATE');">RF2_ATR_STATE</span></p>
<p><span class="register" id="a_RF_ATR_REGMAP|RF3_ATR_STATE" onclick="a('RF_ATR_REGMAP|RF3_ATR_STATE');">RF3_ATR_STATE</span></p>
<p><span class="register" id="a_RF_ATR_REGMAP|ATR_OPTION_REGISTER" onclick="a('RF_ATR_REGMAP|ATR_OPTION_REGISTER');">ATR_OPTION_REGISTER</span></p>
<p><span class="register" id="a_RF_ATR_REGMAP|RF_ATR_DISABLED" onclick="a('RF_ATR_REGMAP|RF_ATR_DISABLED');">RF_ATR_DISABLED</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RF_SYNC_REGMAP" onclick="pm('RF_SYNC_REGMAP');">+</span>
<span class="regmap" id="a_RF_SYNC_REGMAP" onclick="a('RF_SYNC_REGMAP');">RF_SYNC_REGMAP</span>
</p> <div class="sh" id="div_RF_SYNC_REGMAP">
<p>
<span class="pm" id="pm_RF_SYNC_REGMAP|RF_SYNC_REGISTERS" onclick="pm('RF_SYNC_REGMAP|RF_SYNC_REGISTERS');">+</span>
<span class="group" id="a_RF_SYNC_REGMAP|RF_SYNC_REGISTERS" onclick="a('RF_SYNC_REGMAP|RF_SYNC_REGISTERS');">RF_SYNC_REGISTERS</span>
</p>
<div class="sh" id="div_RF_SYNC_REGMAP|RF_SYNC_REGISTERS">
<p><span class="enum" id="a_RF_SYNC_REGMAP|IO_EXPANDER_REGISTER_ADRS" onclick="a('RF_SYNC_REGMAP|IO_EXPANDER_REGISTER_ADRS');">enum IO_EXPANDER_REGISTER_ADRS</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|SYNC_1_REG" onclick="a('RF_SYNC_REGMAP|SYNC_1_REG');">SYNC_1_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|SYNC_2_REG" onclick="a('RF_SYNC_REGMAP|SYNC_2_REG');">SYNC_2_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|SYNC_3_REG" onclick="a('RF_SYNC_REGMAP|SYNC_3_REG');">SYNC_3_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|SYNC_4_REG" onclick="a('RF_SYNC_REGMAP|SYNC_4_REG');">SYNC_4_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|SYNC_5_REG" onclick="a('RF_SYNC_REGMAP|SYNC_5_REG');">SYNC_5_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|RFS_EN_REG" onclick="a('RF_SYNC_REGMAP|RFS_EN_REG');">RFS_EN_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|SETUP_REG" onclick="a('RF_SYNC_REGMAP|SETUP_REG');">SETUP_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|SETUP_STATUS_REG" onclick="a('RF_SYNC_REGMAP|SETUP_STATUS_REG');">SETUP_STATUS_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|CONFIG_IO_REG" onclick="a('RF_SYNC_REGMAP|CONFIG_IO_REG');">CONFIG_IO_REG</span></p>
<p><span class="register" id="a_RF_SYNC_REGMAP|CONFIG_IO_STATUS_REG" onclick="a('RF_SYNC_REGMAP|CONFIG_IO_STATUS_REG');">CONFIG_IO_STATUS_REG</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RFDC_MAPPING_REGMAP" onclick="pm('RFDC_MAPPING_REGMAP');">+</span>
<span class="regmap" id="a_RFDC_MAPPING_REGMAP" onclick="a('RFDC_MAPPING_REGMAP');">RFDC_MAPPING_REGMAP</span>
</p> <div class="sh" id="div_RFDC_MAPPING_REGMAP">
<p>
<span class="pm" id="pm_RFDC_MAPPING_REGMAP|CHANNEL_SWAPPING" onclick="pm('RFDC_MAPPING_REGMAP|CHANNEL_SWAPPING');">+</span>
<span class="group" id="a_RFDC_MAPPING_REGMAP|CHANNEL_SWAPPING" onclick="a('RFDC_MAPPING_REGMAP|CHANNEL_SWAPPING');">CHANNEL_SWAPPING</span>
</p>
<div class="sh" id="div_RFDC_MAPPING_REGMAP|CHANNEL_SWAPPING">
<p><span class="enum" id="a_RFDC_MAPPING_REGMAP|RFDC_ADC_MAPPING" onclick="a('RFDC_MAPPING_REGMAP|RFDC_ADC_MAPPING');">enum RFDC_ADC_MAPPING</span></p>
<p><span class="enum" id="a_RFDC_MAPPING_REGMAP|RFDC_DAC_MAPPING" onclick="a('RFDC_MAPPING_REGMAP|RFDC_DAC_MAPPING');">enum RFDC_DAC_MAPPING</span></p>
</div>
</div>
<p>
<span class="pm" id="pm_RFDC_REGS_REGMAP" onclick="pm('RFDC_REGS_REGMAP');">+</span>
<span class="regmap" id="a_RFDC_REGS_REGMAP" onclick="a('RFDC_REGS_REGMAP');">RFDC_REGS_REGMAP</span>
@@ -630,17 +726,23 @@
<div class="sh" id="div_RFDC_REGS_REGMAP|RFDC_REGS">
<p><span class="enum" id="a_RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM" onclick="a('RFDC_REGS_REGMAP|FABRIC_DSP_BW_ENUM');">enum FABRIC_DSP_BW_ENUM</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|MMCM" onclick="a('RFDC_REGS_REGMAP|MMCM');">MMCM</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|INVERT_IQ_REG" onclick="a('RFDC_REGS_REGMAP|INVERT_IQ_REG');">INVERT_IQ_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|INVERT_DB0_IQ_REG" onclick="a('RFDC_REGS_REGMAP|INVERT_DB0_IQ_REG');">INVERT_DB0_IQ_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|INVERT_DB1_IQ_REG" onclick="a('RFDC_REGS_REGMAP|INVERT_DB1_IQ_REG');">INVERT_DB1_IQ_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|MMCM_RESET_REG" onclick="a('RFDC_REGS_REGMAP|MMCM_RESET_REG');">MMCM_RESET_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG" onclick="a('RFDC_REGS_REGMAP|RF_RESET_CONTROL_REG');">RF_RESET_CONTROL_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_RESET_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_RESET_STATUS_REG');">RF_RESET_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF0_RESET_CONTROL_REG" onclick="a('RFDC_REGS_REGMAP|RF0_RESET_CONTROL_REG');">RF0_RESET_CONTROL_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF0_RESET_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF0_RESET_STATUS_REG');">RF0_RESET_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF1_RESET_CONTROL_REG" onclick="a('RFDC_REGS_REGMAP|RF1_RESET_CONTROL_REG');">RF1_RESET_CONTROL_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF1_RESET_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF1_RESET_STATUS_REG');">RF1_RESET_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_AXI_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_AXI_STATUS_REG');">RF_AXI_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|FABRIC_DSP_REG" onclick="a('RFDC_REGS_REGMAP|FABRIC_DSP_REG');">FABRIC_DSP_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|CALIBRATION_DATA" onclick="a('RFDC_REGS_REGMAP|CALIBRATION_DATA');">CALIBRATION_DATA</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|CALIBRATION_ENABLE" onclick="a('RFDC_REGS_REGMAP|CALIBRATION_ENABLE');">CALIBRATION_ENABLE</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|THRESHOLD_STATUS" onclick="a('RFDC_REGS_REGMAP|THRESHOLD_STATUS');">THRESHOLD_STATUS</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG" onclick="a('RFDC_REGS_REGMAP|RF_PLL_CONTROL_REG');">RF_PLL_CONTROL_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_PLL_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_PLL_STATUS_REG');">RF_PLL_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RF_PLL_STATUS_REG" onclick="a('RFDC_REGS_REGMAP|RF_PLL_STATUS_REG');">RF_PLL_STATUS_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|ADC_TILEMAP_REG" onclick="a('RFDC_REGS_REGMAP|ADC_TILEMAP_REG');">ADC_TILEMAP_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|DAC_TILEMAP_REG" onclick="a('RFDC_REGS_REGMAP|DAC_TILEMAP_REG');">DAC_TILEMAP_REG</span></p>
<p><span class="register" id="a_RFDC_REGS_REGMAP|RFDC_INFO_REG" onclick="a('RFDC_REGS_REGMAP|RFDC_INFO_REG');">RFDC_INFO_REG</span></p>
</div>
</div>
<p>
@@ -707,8 +809,7 @@
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION" onclick="a('VERSIONING_REGS_REGMAP|CPLD_IFC_VERSION');">enum CPLD_IFC_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION" onclick="a('VERSIONING_REGS_REGMAP|DB_GPIO_IFC_VERSION');">enum DB_GPIO_IFC_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|FPGA_VERSION" onclick="a('VERSIONING_REGS_REGMAP|FPGA_VERSION');">enum FPGA_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION" onclick="a('VERSIONING_REGS_REGMAP|RF_CORE_100M_VERSION');">enum RF_CORE_100M_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION" onclick="a('VERSIONING_REGS_REGMAP|RF_CORE_400M_VERSION');">enum RF_CORE_400M_VERSION</span></p>
<p><span class="enum" id="a_VERSIONING_REGS_REGMAP|RF_CORE_FULL_VERSION" onclick="a('VERSIONING_REGS_REGMAP|RF_CORE_FULL_VERSION');">enum RF_CORE_FULL_VERSION</span></p>
</div>
<p>
<span class="pm" id="pm_VERSIONING_REGS_REGMAP|VERSIONING_REGS" onclick="pm('VERSIONING_REGS_REGMAP|VERSIONING_REGS');">+</span>
top/x400/doc/X4XX_FPGA_right.htm → top/x400/doc/X440/X440_FPGA_right.htm
+5760 -1871
View File
File diff suppressed because one or more lines are too long
top/x400/dts/usrp_x440_fpga_C1.dts
+20
View File
@@ -0,0 +1,20 @@
/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x440-version-info.dtsi"
#include "x440-fpga.dtsi"
#include "x4xx-common.dtsi"
#include "x440-rfdc.dtsi"
#include "x4xx-dma.dtsi"
#include "x4xx-100gbe-port0.dtsi"
top/x400/dts/usrp_x440_fpga_CG.dts
+22
View File
@@ -0,0 +1,22 @@
/*
* Copyright 2022 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x440-version-info.dtsi"
#include "x440-fpga.dtsi"
#include "x4xx-common.dtsi"
#include "x440-rfdc.dtsi"
#include "x4xx-dma.dtsi"
#include "x4xx-100gbe-port0.dtsi"
#include "x4xx-100gbe-port1.dtsi"
top/x400/dts/usrp_x440_fpga_X1.dts
+21
View File
@@ -0,0 +1,21 @@
/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x440-version-info.dtsi"
#include "x440-fpga.dtsi"
#include "x4xx-common.dtsi"
#include "x440-rfdc.dtsi"
#include "x4xx-dma.dtsi"
#include "x4xx-10gbe-port0.dtsi"
top/x400/dts/usrp_x440_fpga_X4.dts
+20
View File
@@ -0,0 +1,20 @@
/*
* Copyright 2022 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
/dts-v1/;
/plugin/;
#include "x440-version-info.dtsi"
#include "x440-fpga.dtsi"
#include "x4xx-common.dtsi"
#include "x440-rfdc.dtsi"
#include "x4xx-dma.dtsi"
#include "x4xx-10gbe-port0-x4.dtsi"
top/x400/dts/x440-fpga.dtsi
+9
View File
@@ -0,0 +1,9 @@
/*
* Copyright 2022 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
firmware-name = "x440.bin";
};
top/x400/dts/x440-rfdc.dtsi
+38
View File
@@ -0,0 +1,38 @@
/*
* Copyright 2021 Ettus Research, a National Instruments Brand
*
* SPDX-License-Identifier: LGPL-3.0-or-later
*/
&fpga_full {
#address-cells = <2>;
#size-cells = <2>;
misc_clk_1: misc_clk_1 {
#clock-cells = <0>;
clock-frequency = <40000000>;
compatible = "fixed-clock";
};
misc_clk_2: misc_clk_2 {
#clock-cells = <0>;
clock-frequency = <184320000>;
compatible = "fixed-clock";
};
rf_data_converter: usp_rf_data_converter@1000100000 {
clock-names = "s_axi_aclk", "m0_axis_aclk", "m1_axis_aclk", "m2_axis_aclk", "m3_axis_aclk", "s0_axis_aclk", "s1_axis_aclk";
clocks = <&misc_clk_1>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>;
compatible = "xlnx,usp-rf-data-converter-2.1";
num-insts = <0x1>;
param-list = [ 00 00 00 00 00 10 00 10 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 67 40 0a d7 a3 70 3d 0a 67 40 30 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 67 40 0a d7 a3 70 3d 0a 67 40 30 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 9a 99 99 99 99 99 19 40 00 00 00 00 00 00 b9 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 9a 99 99 99 99 99 19 40 00 00 00 00 00 00 b9 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 77 40 0a d7 a3 70 3d 0a 67 40 18 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 77 40 0a d7 a3 70 3d 0a 67 40 18 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 77 40 0a d7 a3 70 3d 0a 67 40 18 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 77 40 0a d7 a3 70 3d 0a 67 40 18 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00];
reg = <0x00000010 0x00100000 0x0 0x40000>;
};
rfdc_regs: uio@1000140000 {
status = "okay";
compatible = "usrp-uio";
reg = <0x10 0x00140000 0x0 0x20000>;
reg-names = "rfdc-regs";
};
};
top/x400/ip/Makefile.inc
+35
View File
@@ -33,6 +33,14 @@ include $(IP_DIR)/dac_400m_bd/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc
endif
ifdef X440
include $(IP_DIR)/adc_full_bd/Makefile.inc
include $(IP_DIR)/adc_100m_bd/Makefile.inc
include $(IP_DIR)/dac_100m_bd/Makefile.inc
include $(IP_DIR)/ddr4_64bits_x440/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc
endif
BD_SRCS = \
$(IP_X4XX_PS_RFDC_BD_SRCS) \
$(IP_X4XX_PS_RFDC_HDL_SRCS) \
@@ -66,6 +74,16 @@ $(IP_DAC_400M_BD_SRCS) \
$(IP_DAC_400M_HDL_SRCS)
endif
ifdef X440
BD_SRCS += \
$(IP_ADC_FULL_BD_SRCS) \
$(IP_ADC_FULL_HDL_SRCS) \
$(IP_ADC_100M_BD_SRCS) \
$(IP_ADC_100M_HDL_SRCS) \
$(IP_DAC_100M_BD_SRCS) \
$(IP_DAC_100M_HDL_SRCS)
endif
IP_XCI_SRCS = \
$(IP_XGE_PCS_PMA_SRCS) \
$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
@@ -79,6 +97,11 @@ IP_XCI_SRCS += \
$(IP_DDR4_64BITS_SRCS)
endif
ifdef X440
IP_XCI_SRCS += \
$(IP_DDR4_64BITS_X440_SRCS)
endif
BD_OUTPUTS = \
$(BD_X4XX_PS_RFDC_BD_OUTS) \
$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
@@ -103,6 +126,13 @@ $(BD_DAC_100M_BD_OUTS) \
$(BD_DAC_400M_BD_OUTS)
endif
ifdef X440
BD_OUTPUTS += \
$(BD_ADC_FULL_BD_OUTS) \
$(BD_ADC_100M_BD_OUTS) \
$(BD_DAC_100M_BD_OUTS)
endif
IP_SYNTH_OUTPUTS = \
$(IP_XGE_PCS_PMA_OUTS) \
$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
@@ -116,6 +146,11 @@ IP_SYNTH_OUTPUTS += \
$(IP_DDR4_64BITS_OUTS)
endif
ifdef X440
IP_SYNTH_OUTPUTS += \
$(IP_DDR4_64BITS_X440_OUTS)
endif
IP_HDL_SIM_SRCS = \
$(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \
$(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \
top/x400/ip/adc_full_bd/Makefile.inc
+38
View File
@@ -0,0 +1,38 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_ADC_FULL_ORIG_SRCS = $(addprefix $(IP_DIR)/adc_full_bd/, \
adc_full_bd.tcl \
)
IP_ADC_FULL_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/, \
common/adc_iq_repacker.v \
)
IP_ADC_FULL_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \
adc_full_bd.tcl \
)
IP_ADC_FULL_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \
adc_full_bd/adc_full_bd.bd \
)
BD_ADC_FULL_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \
adc_full_bd.bd.out \
adc_full_bd/adc_full_bd_ooc.xdc \
adc_full_bd/synth/adc_full_bd.v \
)
EMPTY_IP_SRCS =
.INTERMEDIATE: IP_ADC_FULL_BD_TRGT
$(IP_ADC_FULL_BD_SRCS) $(BD_ADC_FULL_BD_OUTS) $(IP_ADC_FULL_BDTCL_SRCS): IP_ADC_FULL_BD_TRGT
@:
IP_ADC_FULL_BD_TRGT: $(IP_ADC_FULL_ORIG_SRCS) $(IP_ADC_FULL_HDL_SRCS)
$(call BUILD_VIVADO_BDTCL,adc_full_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_FULL_HDL_SRCS),)
top/x400/ip/adc_full_bd/adc_full_bd.tcl
+338
View File
@@ -0,0 +1,338 @@
################################################################
# This is a generated script based on design: adc_full_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
################################################################
# START
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source adc_full_bd_script.tcl
# The design that will be created by this Tcl script contains the following
# module references:
# adc_iq_repacker
# Please add the sources of those modules before sourcing this Tcl script.
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
}
# CHANGE DESIGN NAME HERE
variable design_name
set design_name adc_full_bd
# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name
# Creating design if needed
set errMsg ""
set nRet 0
set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]
if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set
set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2
} else {
# USE CASES:
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
# Add USER_COMMENTS on $design_name
set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name]
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axis_register_slice:1.1\
xilinx.com:ip:xlconstant:1.1\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
adc_iq_repacker\
"
set list_mods_missing ""
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
##################################################################
# DESIGN PROCs
##################################################################
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
variable script_folder
variable design_name
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ]
set_property -dict [ list \
CONFIG.FREQ_HZ {512000000} \
] $adc_data_out
set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ]
set_property -dict [ list \
CONFIG.FREQ_HZ {512000000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {16} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $adc_i_data_in
set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ]
set_property -dict [ list \
CONFIG.FREQ_HZ {512000000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {16} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $adc_q_data_in
# Create ports
set enable_data_to_repacker_rclk [ create_bd_port -dir I enable_data_to_repacker_rclk ]
set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ]
set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 512000000 rfdc_clk ]
set swap_iq_rclk [ create_bd_port -dir I swap_iq_rclk ]
# Create instance: adc_data_to_axi, and set properties
set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ]
set_property -dict [ list \
CONFIG.REG_CONFIG {1} \
CONFIG.TDATA_NUM_BYTES {32} \
] $adc_data_to_axi
# Create instance: adc_i_data_from_axi, and set properties
set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ]
set_property -dict [ list \
CONFIG.REG_CONFIG {0} \
CONFIG.TDATA_NUM_BYTES {16} \
] $adc_i_data_from_axi
# Create instance: adc_iq_repacker, and set properties
set block_name adc_iq_repacker
set block_cell_name adc_iq_repacker
if { [catch {set adc_iq_repacker [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $adc_iq_repacker eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
set_property -dict [ list \
CONFIG.SPC {8} \
] $adc_iq_repacker
# Create instance: adc_q_data_from_axi, and set properties
set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ]
set_property -dict [ list \
CONFIG.REG_CONFIG {0} \
CONFIG.TDATA_NUM_BYTES {16} \
] $adc_q_data_from_axi
# Create instance: const_1, and set properties
set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ]
# Create interface connections
connect_bd_intf_net -intf_net adc_i_data_in_1 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS]
connect_bd_intf_net -intf_net adc_iq_repacker_0_data_out [get_bd_intf_pins adc_data_to_axi/S_AXIS] [get_bd_intf_pins adc_iq_repacker/data_out]
connect_bd_intf_net -intf_net adc_q_data_from_axi1_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS]
connect_bd_intf_net -intf_net adc_q_data_in_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS]
# Create port connections
connect_bd_net -net adc_i_data_from_axi_m_axis_tdata [get_bd_pins adc_i_data_from_axi/m_axis_tdata] [get_bd_pins adc_iq_repacker/adc_i_in]
connect_bd_net -net adc_i_data_from_axi_m_axis_tvalid [get_bd_pins adc_i_data_from_axi/m_axis_tvalid] [get_bd_pins adc_iq_repacker/valid_in]
connect_bd_net -net adc_q_data_from_axi_m_axis_tdata [get_bd_pins adc_iq_repacker/adc_q_in] [get_bd_pins adc_q_data_from_axi/m_axis_tdata]
connect_bd_net -net const_1_dout [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout]
connect_bd_net -net enable_data_to_repacker_rclk_1 [get_bd_ports enable_data_to_repacker_rclk] [get_bd_pins adc_iq_repacker/enable]
connect_bd_net -net rfdc_adc_axi_resetn_rclk_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_data_to_axi/aresetn] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn]
connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_iq_repacker/clk] [get_bd_pins adc_q_data_from_axi/aclk]
connect_bd_net -net swap_iq_rclk_1 [get_bd_ports swap_iq_rclk] [get_bd_pins adc_iq_repacker/swap_iq]
# Create address segments
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
}
# End of create_root_design()
##################################################################
# MAIN FLOW
##################################################################
create_root_design ""
top/x400/ip/adc_full_bd/hdl_sources.tcl
+6
View File
@@ -0,0 +1,6 @@
set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
# Vivado's block diagram default library for files not belonging to any special
# library is called xil_defaultlib
read_verilog -library xil_defaultlib $script_dir/../../rf/common/adc_iq_repacker.v
top/x400/ip/ddr4_64bits_x440/Makefile.inc
+21
View File
@@ -0,0 +1,21 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_DDR4_64BITS_X440_SRCS = \
$(IP_BUILD_DIR)/ddr4_64bits_x440/ddr4_64bits_x440.xci
IP_DDR4_64BITS_X440_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr4_64bits_x440/, \
ddr4_64bits_x440.xci.out \
)
.INTERMEDIATE: IP_DDR4_64BITS_X440_TRGT
$(IP_DDR4_64BITS_X440_SRCS) $(IP_DDR4_64BITS_X440_OUTS): IP_DDR4_64BITS_X440_TRGT
@:
IP_DDR4_64BITS_X440_TRGT: $(IP_DIR)/ddr4_64bits_x440/ddr4_64bits_x440.xci
$(call BUILD_VIVADO_IP,ddr4_64bits_x440,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x400/ip/ddr4_64bits_x440/ddr4_64bits_x440.xci
+493
View File
@@ -0,0 +1,493 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>ddr4_64bits_x440</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ddr4" spirit:version="2.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATA_MASK">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">8</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_PART">MT40A512M16HA-075E</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_TYPE">Components</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">8Gb</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">8192</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">750</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_750_Timing</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ROW_WIDTH">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">075E</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">300000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tREFI">9363</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC">421</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">145</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRP">17</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD"/>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_L">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_S">7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRTP">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWR">19</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR"/>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_L">10</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MEM_TYPE">DDR4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">9996</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CustomParts">no_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">DM_NO_DBI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">64</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">9996</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryName">MainMemory</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MT40A512M16HA-075E</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl">RZQ/7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PAR_SKEW">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TREFI">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplusRFSOC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu28dr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvg1517</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.BANK_GROUP_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
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<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{&quot;ip_boundary&quot;:{&quot;ports&quot;:{&quot;c0_ddr4_act_n&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_adr&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;16&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_aresetn&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_ba&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_bg&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_ck_c&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_ck_t&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_cke&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_cs_n&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_dm_dbi_n&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}
],&quot;c0_ddr4_dq&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_dqs_c&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_dqs_t&quot;:[{&quot;direction&quot;:&quot;inout&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_odt&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_reset_n&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_araddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arburst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arcache&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arlen&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is
_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arlock&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arqos&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_arsize&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_arvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_awaddr&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awburst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awcache&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awid&quot;:[{&quot;direction&quot;:&quot;in
&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awlen&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awlock&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awprot&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awqos&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_awsize&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_awvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_bid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_bready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;
}],&quot;c0_ddr4_s_axi_bresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_bvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_rdata&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_rid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_rlast&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_rready&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_rresp&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_rvalid&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_wdata&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_wlast&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_le
ft&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_wready&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_s_axi_wstrb&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;c0_ddr4_s_axi_wvalid&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_ui_clk&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_ddr4_ui_clk_sync_rst&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_init_calib_complete&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_sys_clk_n&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;c0_sys_clk_p&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;dbg_bus&quot;:[{&quot;direction&quot;:&quot;out&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;true&quot;}],&quot;dbg_clk&quot;:[{&quot;direction&quot;:&quot;out
&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}],&quot;sys_rst&quot;:[{&quot;direction&quot;:&quot;in&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;is_vector&quot;:&quot;false&quot;}]},&quot;interfaces&quot;:{&quot;C0_DDR4&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:ddr4:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:ddr4_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;AXI_ARBITRATION_SCHEME&quot;:[{&quot;value&quot;:&quot;TDM&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;C0_DDR4_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CAN_DEBUG&quot;:[{&quot;value&quot;:&quot;false&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_ty
pe&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;bool&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CAS_LATENCY&quot;:[{&quot;value&quot;:&quot;11&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CAS_WRITE_LATENCY&quot;:[{&quot;value&quot;:&quot;11&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CS_ENABLED&quot;:[{&quot;value&quot;:&quot;true&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;bool&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CUSTOM_PARTS&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_MASK_ENABLED&quot;:[{&quot;value&quot;:&quot;true&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;bool&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inf
erred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;8&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MEMORY_PART&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MEMORY_TYPE&quot;:[{&quot;value&quot;:&quot;COMPONENTS&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MEM_ADDR_MAP&quot;:[{&quot;value&quot;:&quot;ROW_COLUMN_BANK&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;SLOT&quot;:[{&quot;value&quot;:&quot;Single&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;TIMEPERIOD_
PS&quot;:[{&quot;value&quot;:&quot;1250&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ACT_N&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_act_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ADR&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_adr&quot;,&quot;physical_left&quot;:&quot;16&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;16&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BA&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ba&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BG&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_bg&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CKE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_cke&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CK_C&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ck_c&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;lo
gical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CK_T&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ck_t&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CS_N&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_cs_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;C_ID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_c&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;DM_N&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_dm_dbi_n&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;DQ&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_dq&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;DQS_C&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_dqs_c&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;DQS_T&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_dqs_t&quot;,&quot;physical_left&quot;:&quot;7
&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ODT&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_odt&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;PAR&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_parity&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RESET_N&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_reset_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4_ARESETN&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_LOW&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all
&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_aresetn&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4_CLOCK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;ASSOCIATED_BUSIF&quot;:[{&quot;value&quot;:&quot;C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;ASSOCIATED_RESET&quot;:[{&quot;value&quot;:&quot;c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[
{&quot;value&quot;:&quot;3e+08&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;dependent&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;FREQ_TOLERANCE_HZ&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.00&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;CLK&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4_RESET&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1
.0&quot;,&quot;mode&quot;:&quot;master&quot;,&quot;parameters&quot;:{&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_ui_clk_sync_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_DDR4_S_AXI&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:aximm:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:interface:aximm_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;memory_map_ref&quot;:&quot;C0_DDR4_MEMORY_MAP&quot;,&quot;parameters&quot;:{&quot;ADDR_WIDTH&quot;:[{&quot;value&quot;:&quot;32&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ARUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_sr
c&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;AWUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;BUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;CLK_DOMAIN&quot;:[{&quot;value&quot;:&quot;&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;DATA_WIDTH&quot;:[{&quot;value&quot;:&quot;512&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;3e+08&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permissio
n&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;dependent&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;HAS_BRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_BURST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_CACHE&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_LOCK&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_PROT&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long
&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_QOS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_REGION&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_RRESP&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;HAS_WSTRB&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;ID_WIDTH&quot;:[{&quot;value&quot;:&quot;4&quot;,&quot;value_src&quot;:&quot;auto&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred
&quot;:true,&quot;is_static_object&quot;:false}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;MAX_BURST_LENGTH&quot;:[{&quot;value&quot;:&quot;256&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_READ_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_OUTSTANDING&quot;:[{&quot;value&quot;:&quot;2&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:tr
ue,&quot;is_static_object&quot;:false}],&quot;NUM_WRITE_THREADS&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PHASE&quot;:[{&quot;value&quot;:&quot;0.0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;float&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;PROTOCOL&quot;:[{&quot;value&quot;:&quot;AXI4&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;READ_WRITE_MODE&quot;:[{&quot;value&quot;:&quot;READ_WRITE&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;RUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:tru
e,&quot;is_static_object&quot;:false}],&quot;RUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;SUPPORTS_NARROW_BURST&quot;:[{&quot;value&quot;:&quot;1&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_BITS_PER_BYTE&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;WUSER_WIDTH&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.tlm&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;ARADDR&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_araddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;A
RBURST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARCACHE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arid&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLEN&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARLOCK&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARPROT&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARQOS&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arqos&quot;,&quot;physical_left&quot;:&quot;3&quot;
,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARREADY&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARSIZE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARUSER&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_aruser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;ARVALID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_arvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWADDR&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awaddr&quot;,&quot;physical_left&quot;:&quot;31&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;31&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWBURST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awburst&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right
&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWCACHE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awcache&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awid&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLEN&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awlen&quot;,&quot;physical_left&quot;:&quot;7&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;7&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWLOCK&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awlock&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWPROT&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awprot&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWQOS&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awqos&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWREADY&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_
s_axi_awready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWSIZE&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awsize&quot;,&quot;physical_left&quot;:&quot;2&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;2&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWUSER&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awuser&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;AWVALID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_awvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_bid&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BREADY&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_bready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BRESP&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_bresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left
&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;BVALID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_bvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RDATA&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_rdata&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;511&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_rid&quot;,&quot;physical_left&quot;:&quot;3&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;3&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RLAST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_rlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RREADY&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_rready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RRESP&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_rresp&quot;,&quot;physical_left&quot;:&quot;1&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;1&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;RVALID&quot;:[{&quot;physica
l_name&quot;:&quot;c0_ddr4_s_axi_rvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WDATA&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_wdata&quot;,&quot;physical_left&quot;:&quot;511&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;511&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WLAST&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_wlast&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WREADY&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_wready&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WSTRB&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_wstrb&quot;,&quot;physical_left&quot;:&quot;63&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;63&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;WVALID&quot;:[{&quot;physical_name&quot;:&quot;c0_ddr4_s_axi_wvalid&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;C0_SYS_CLK&quot;:{&quot;vlnv&quot;:&quot;xilinx.com:interface:diff_clock:1.0&quot;,&quot;abstraction_type&quot;:&quot;x
ilinx.com:interface:diff_clock_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;C0_CLOCK_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;CAN_DEBUG&quot;:[{&quot;value&quot;:&quot;false&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;bool&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;FREQ_HZ&quot;:[{&quot;value&quot;:&quot;100000000&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;generated&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;none&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}]},&quot;port_maps&quot;:{&quot;CLK_N&quot;:[{&quot;physical_name&quot;:&quot;c0_sys_clk_n&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}],&quot;CLK_P&quot;:[{&quot;physical_name&quot;:&quot;c0_sys_clk_p&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}},&quot;SYSTEM_RESET&quot;:{&quot;vlnv&quot;:&quot;xi
linx.com:signal:reset:1.0&quot;,&quot;abstraction_type&quot;:&quot;xilinx.com:signal:reset_rtl:1.0&quot;,&quot;mode&quot;:&quot;slave&quot;,&quot;parameters&quot;:{&quot;BOARD.ASSOCIATED_PARAM&quot;:[{&quot;value&quot;:&quot;RESET_BOARD_INTERFACE&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}],&quot;INSERT_VIP&quot;:[{&quot;value&quot;:&quot;0&quot;,&quot;value_src&quot;:&quot;default&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;user&quot;,&quot;format&quot;:&quot;long&quot;,&quot;usage&quot;:&quot;simulation.rtl&quot;,&quot;is_ips_inferred&quot;:true,&quot;is_static_object&quot;:false}],&quot;POLARITY&quot;:[{&quot;value&quot;:&quot;ACTIVE_HIGH&quot;,&quot;value_src&quot;:&quot;constant&quot;,&quot;value_permission&quot;:&quot;user&quot;,&quot;resolve_type&quot;:&quot;immediate&quot;,&quot;format&quot;:&quot;string&quot;,&quot;usage&quot;:&quot;all&quot;,&quot;is_ips_inferred&quot;:false,&quot;is_static_object&quot;:true}]},&quot;port_maps&quot;:{&quot;RST&quot;:[{&quot;physical_name&quot;:&quot;sys_rst&quot;,&quot;physical_left&quot;:&quot;0&quot;,&quot;physical_right&quot;:&quot;0&quot;,&quot;logical_left&quot;:&quot;0&quot;,&quot;logical_right&quot;:&quot;0&quot;,&quot;port_maps_used&quot;:&quot;none&quot;}]}}},&quot;memory_maps&quot;:{&quot;C0_DDR4_MEMORY_MAP&quot;:{&quot;address_blocks&quot;:{&quot;C0_DDR4_ADDRESS_BLOCK&quot;:[{&quot;base_address&quot;:&quot;0&quot;,&quot;range&quot;:&quot;4294967296&quot;,&quot;display_name&quot;
:&quot;&quot;,&quot;description&quot;:&quot;&quot;,&quot;usage&quot;:&quot;memory&quot;,&quot;access&quot;:&quot;read-write&quot;}]}},&quot;C0_DDR4_MEMORY_MAP_CTRL&quot;:{&quot;address_blocks&quot;:{&quot;C0_REG&quot;:[{&quot;base_address&quot;:&quot;0&quot;,&quot;range&quot;:&quot;4096&quot;,&quot;display_name&quot;:&quot;&quot;,&quot;description&quot;:&quot;&quot;,&quot;usage&quot;:&quot;register&quot;,&quot;access&quot;:&quot;read-write&quot;}]}}}}}"/>
</xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc
-50
View File
@@ -1,50 +0,0 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/, \
x4xx_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
capture_sysref.v \
rf_nco_reset.vhd \
rf_reset_controller.vhd \
rf_reset.vhd \
clock_gates.vhd \
sync_wrapper.v \
axis_mux.vhd \
gpio_to_axis_mux.vhd \
) \
$(addprefix $(BASE_DIR)/../lib/control/, \
synchronizer.v \
synchronizer_impl.v \
) \
$(addprefix $(BASE_DIR)/x400/regmap/, PkgRFDC_REGS_REGMAP.vhd )
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
x4xx_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.bd \
)
BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
x4xx_ps_rfdc_bd.bd.out \
x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd_ooc.xdc \
x4xx_ps_rfdc_bd/synth/x4xx_ps_rfdc_bd.v \
)
EMPTY_IP_SRCS =
.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT
$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT
@:
IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,x4xx_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl
-14
View File
@@ -1,14 +0,0 @@
set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../rf/common/capture_sysref.v
read_verilog -library work $script_dir/../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../rf/common/sync_wrapper.v
read_vhdl -library work $script_dir/../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../regmap/PkgRFDC_REGS_REGMAP.vhd
read_vhdl -library work $script_dir/../../rf/common/rf_reset_controller.vhd
read_vhdl -library work $script_dir/../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../rf/common/clock_gates.vhd
read_vhdl -library work $script_dir/../../rf/common/axis_mux.vhd
read_vhdl -library work $script_dir/../../rf/common/gpio_to_axis_mux.vhd
top/x400/ip/x4xx_ps_rfdc_bd/regmap/common_regs.v
-550
View File
@@ -1,550 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: common_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<top name="X4XX_FPGA">
// <ports>
// <info>
// This section lists all common Processing System ports through
// which the register maps in this project are accessed. Each input
// port to the fabric will point to a regmap.
// </info>
// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP">
// <info>
// This is the main AXI4-Lite master interface that the PS
// exposes to the kernel to interact with the FPGA fabric.
// There are multiple endpoints connected to this interface.
// </info>
// </port>
// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP">
// <info>
// This is the SPI1 interface
// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
// of the PS.
// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br}
// The request format on SPI is defined as.{br}
// {b}Write request:{/b}
// {ul}
// {li}1'b1 = write
// {li}15 bit address
// {li}32 bit data (MOSI)
// {li}8 bit processing gap
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// {b}Read request:{/b}
// {ul}
// {li}1'b0 = read
// {li}15 bit address
// {li}8 bit processing gap
// {li}32 bit data (MISO)
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// </info>
// </port>
// </ports>
// <regmapcfg readablestrobes="false">
// <map name="AXI_HPM0_REGMAP"/>
// <map name="MB_CPLD_PS_REGMAP"/>
// </regmapcfg>
//</top>
//
//<regmap name="AXI_HPM0_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <info>
// This is the map for the register space that the Processing System's
// M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
// This port has a 40-bit address bus.
// </info>
// <group name="COMMON">
// <window name="RPU" offset="0x0080000000" size="0x00010000">
// <info>Space reserved for RPU access</info>
// </window>
// <window name="JTAG_ENGINE" offset="0x1000000000" size="0x1000">
// <info>Register space for the JTAG engine for MB CPLD programming.</info>
// </window>
// <window name="RESERVED" offset="0x100003F000" size="0x1000">
// <info>Register space reserved for future use.</info>
// </window>
// <window name="MPM_ENDPOINT" offset="0x1000080000" size="0x20000"
// targetregmap="PL_CPLD_REGMAP">
// <info>MPM endpoint fro MB/DB communication.</info>
// </window>
// <window name="CORE_REGS" offset="0x10000A0000" size="0x4000"
// targetregmap="CORE_REGS_REGMAP">
// <info>Register space reserved for mboard-regs (Core).</info>
// </window>
// <window name="INT_ETH_DMA" offset="0x10000A4000" size="0x6000"
// targetregmap="ETH_DMA_CTRL_REGMAP">
// <info>AXI DMA engine for internal Ethernet interface.</info>
// </window>
// <window name="INT_ETH_REGS" offset="0x10000AA000" size="0x2000">
// <info>Misc. registers for internal Ethernet.</info>
// </window>
// <window name="RFDC" offset="0x1000100000" size="0x40000">
// <info>Register space occupied by the Xilinx RFDC IP block.</info>
// </window>
// <window name="RFDC_REGS" offset="0x1000140000" size="0x20000"
// targetregmap="RFDC_REGS_REGMAP">
// <info>Register space for RFDC control/status registers.</info>
// </window>
// </group>
//</regmap>
//
//<regmap name="ETH_DMA_CTRL_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
// <info>
// This is the map that the nixge driver uses in Ethernet DMA to
// move data between the Processing System's architecture and the fabric.
// This map is a combination of two main components: a Xilix AXI DMA engine
// and some registers for MAC/PHY control.
// </info>
// <group name="ETH_DMA_CTRL">
// <window name="AXI_DMA_CTRL" offset="0x0" size="0x4000">
// <info>
// Refer to Xilinx' AXI DMA v7.1 IP product guide for further
// information on this register map:
// https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
// </info>
// </window>
// <window name="ETH_IO_CTRL" offset="0x4000" size="0x2000">
// <info>MAC/PHY control for the Ethernet interface.</info>
// </window>
// </group>
//</regmap>
//<regmap name="PL_DMA_MASTER_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
// <info>
// This is a regmap to document the different ports that have access to the PS system memory.
// Each port may have different restrictions on system memory. See the corresponding window
// for details
// </info>
// <group name="HPC0_DMA">
// <window name="AXI_HPC0_WINDOW" offset="0x0" size="0x10000000000">
// <info>
// The HPC0 port of the PS is used for general purpose cache-coherent accesses
// to the PS system memory. Different applications may use it for different
// purposes. Its access is configured as follows: {br}
// {table border="1"}
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
// {tr}{td}0xFF000000{/td} {td}0x01000000{/td} {td}LPS_OCM{/td}{tr}
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
// {/table}
// </info>
// </window>
// </group>
// <group name="HPC1_DMA">
// <window name="AXI_HPC1_WINDOW" offset="0x0" size="0x1000000000">
// <info>
// The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
// interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
// Its access is configured as follows: {br}
// {table border="1"}
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
// {/table}
// </info>
// </window>
// </group>
//</regmap>
//
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="RFDC_REGS">
// <info>
// These are the registers located within the RFDC block design
// that provide control and status support for the RF chain.
// </info>
//
// <window name="MMCM" offset="0x0" size="0x10000">
// <info>
// Register space for controlling the data clock MMCM instance
// within the RFDC block design.
// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
// regiter space description in chapter 2.
// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
// </info>
// </window>
//
// <register name="INVERT_IQ_REG" offset="0x10000" size="32">
// <info>Control register for inverting I/Q data.</info>
// <!-- TODO: possibly redo these bitfields -->
// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB1_ADC0_IQ" range="4"/>
// <bitfield name="INVERT_DB1_ADC1_IQ" range="5"/>
// <bitfield name="INVERT_DB1_ADC2_IQ" range="6"/>
// <bitfield name="INVERT_DB1_ADC3_IQ" range="7"/>
// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/>
// <bitfield name="INVERT_DB1_DAC0_IQ" range="12"/>
// <bitfield name="INVERT_DB1_DAC1_IQ" range="13"/>
// <bitfield name="INVERT_DB1_DAC2_IQ" range="14"/>
// <bitfield name="INVERT_DB1_DAC3_IQ" range="15"/>
// </register>
//
// <register name="MMCM_RESET_REG" offset="0x11000" size="32">
// <info>Control register for resetting the data clock MMCM.</info>
// <bitfield name="RESET_MMCM" range="0">
// <info>
// Write a '1' to this bit to reset the MMCM. Then write a
// '0' to place the MMCM out of reset.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_RESET_CONTROL_REG" offset="0x12000" size="32">
// <info>
// Control register for the RF reset controller.
// Verify the FSM ID before polling starting any reset sequence.
// To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
// Assert either the *_RESET or *_ENABLE bitfields.
// Wait until DB*_DONE is asserted to release the trigger.
// The DB*_DONE signal should then de-assert.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FSM_RESET" range="0">
// <info>
// Write a '1' to this bit to reset the RF reset controller.
// Write a '0' once db0_fsm_reset_done asserts.
// </info>
// </bitfield>
// <bitfield name="ADC_RESET" range="4">
// <info>
// Write a '1' to this bit to trigger a reset for the
// daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
// is asserted.
// </info>
// </bitfield>
// <bitfield name="ADC_ENABLE" range="5">
// <info>
// Write a '1' to this bit to trigger the enable sequence for
// the daughterboard 0 ADC chain. Write a '0' once
// db0_adc_seq_done is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_RESET" range="8">
// <info>
// Write a '1' to this bit to trigger a reset for the
// daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
// is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_ENABLE" range="9">
// <info>
// Write a '1' to this bit to trigger the enable sequence for
// the daughterboard 0 DAC chain. Write a '0' once
// db0_dac_seq_done is asserted.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_RESET_STATUS_REG" offset="0x12008" size="32" writable="false">
// <info>
// Status register for the RF reset controller.
// Verify the FSM ID before polling starting any reset sequence.
// Refer to RF_RESET_CONTROL_REG for instructions on how to use
// the status bits in this register.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FSM_RESET_DONE" range="3">
// <info>
// This bit asserts ('1') when the DB0 RF reset controller FSM
// reset sequence is completed. The bitfield deasserts ('0')
// after deasserting db0_fsm_reset.
// </info>
// </bitfield>
// <bitfield name="ADC_SEQ_DONE" range="7">
// <info>
// This bit asserts ('1') when the DB0 ADC chain reset sequence
// is completed. The bitfield deasserts ('0') after
// deasserting the issued triggered (enable or reset).
// </info>
// </bitfield>
// <bitfield name="DAC_SEQ_DONE" range="11">
// <info>
// This bit asserts ('1') when the DB0 DAC chain reset sequence
// is completed. The bitfield deasserts ('0') after
// deasserting the issued triggered (enable or reset).
// </info>
// </bitfield>
// </register>
//
// <register name="RF_AXI_STATUS_REG" offset="0x13000" size="32" writable="false">
// <info>
// Status register for the RF AXI-Stream interfaces.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="RFDC_DAC_TREADY" range="1..0">
// <info>
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TVALID" range="3..2">
// <info>
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TREADY" range="5..4">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TReady handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TREADY" range="7..6">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TReady handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TVALID" range="9..8">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TValid handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TVALID" range="11..10">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TValid handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TVALID" range="13..12">
// <info>
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TREADY" range="15..14">
// <info>
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TREADY_DB1" range="17..16">
// <info>
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TVALID_DB1" range="19..18">
// <info>
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TREADY_DB1" range="21..20">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TReady handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TREADY_DB1" range="23..22">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TReady handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TVALID_DB1" range="25..24">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TValid handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TVALID_DB1" range="27..26">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TValid handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TVALID_DB1" range="29..28">
// <info>
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TREADY_DB1" range="31..30">
// <info>
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// </register>
//
// <register name="CALIBRATION_DATA" offset="0x014000">
// <info>
// The fields of this register provide data to all the DAC channels when enabled
// by the CALIBRATION_ENABLE register.
// </info>
// <bitfield name="Q_DATA" range="31..16">
// </bitfield>
// <bitfield name="I_DATA" range="15..00">
// </bitfield>
// </register>
//
// <register name="CALIBRATION_ENABLE" offset="0x014008">
// <info>
// This register enables calibration data in the DAC data path for each of the
// four channels. Each of these bits is normally '0'. When written '1', DAC data
// for the corresponding channel will be constantly driven with the contents of
// the CALIBRATION_DATA register.
// </info>
// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0">
// <info>
// Enables calibration data for channel 0.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1">
// <info>
// Enables calibration data for channel 1.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="4">
// <info>
// Enables calibration data for channel 2.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="5">
// <info>
// Enables calibration data for channel 3.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true">
// <info>
// Enable RF MMCM outputs.
// </info>
// <bitfield name="ENABLE_DATA_CLK" range="0"/>
// <bitfield name="ENABLE_DATA_CLK_2X" range="4"/>
// <bitfield name="ENABLE_RF_CLK" range="8"/>
// <bitfield name="ENABLE_RF_CLK_2X" range="12"/>
// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/>
// </register>
//
// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false">
// <info>
// Data Clk Pll Status Register
// </info>
// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/>
// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/>
// </register>
//
// <register name="THRESHOLD_STATUS" offset="0x015000">
// <info>
// This register shows threshold status for the ADCs. Each bit reflects the
// RFDC's real-time ADC status signals, which will assert when the ADC input
// signal exceeds the programmed threshold value. The status will remain
// asserted until cleared by software.
// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
// the location of the tile in the converter column and ZZ is either 01 (the
// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
// See also the Xilinx document PG269.
// </info>
// <bitfield name="ADC0_01_THRESHOLD1" range="0">
// </bitfield>
// <bitfield name="ADC0_01_THRESHOLD2" range="1">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD1" range="2">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD2" range="3">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD1" range="8">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD2" range="9">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD1" range="10">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD2" range="11">
// </bitfield>
// </register>
//
// <enumeratedtype name="FABRIC_DSP_BW_ENUM" showhex="true">
// <value name="FABRIC_DSP_BW_NONE" integer="0"/>
// <value name="FABRIC_DSP_BW_100M" integer="100"/>
// <value name="FABRIC_DSP_BW_200M" integer="200"/>
// <value name="FABRIC_DSP_BW_400M" integer="400"/>
// </enumeratedtype>
//
// <register name="FABRIC_DSP_REG" offset="0x13008" size="32" writable="false">
// <info>
// This register provides information to the driver on the type
// of DSP that is instantiated in the fabric.{BR/}
// The X410 platform supports multiple RF daughterboards, each requiring
// a different fabric RF DSP chain that works with specific RFDC settings.
// Each bandwidth DSP chain has a unique identifier (BW in MHz), this
// information is conveyed in this register to let the driver
// configure the RFDC with the proper settings.
// Also, channel count for the DSP module is included.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FABRIC_DSP_BW" range="11..0" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE">
// <info>Fabric DSP BW in MHz for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RX_CNT" range="13..12" initialvalue="0">
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_TX_CNT" range="15..14" initialvalue="0">
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_BW_DB1" range="27..16" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE">
// <info>Fabric DSP BW in MHz for daughterboard 1.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RX_CNT_DB1" range="29..28" initialvalue="0">
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_TX_CNT_DB1" range="31..30" initialvalue="0">
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
// </bitfield>
// </register>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/regmap/uhd_regs.v
-336
View File
@@ -1,336 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: uhd_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<regmap name="CMAC_REGMAP" markdown="true" generateverilog="false">
// <group name="XILINX_CMAC_REGISTERS">
// <info>
// 100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.
//
// - http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
//
// </info>
// </group>
//</regmap>
//XmlParse xml_on
//<regmap name="XGE_MAC_REGMAP" markdown="true" generateverilog="false">
// <group name="OPENCORE_XGE_REGISTERS">
// <info>
//
// 10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
//
// </info>
// </group>
//</regmap>
//<regmap name="DMA_REGMAP" markdown="true" generateverilog="false">
// <group name="XILINX_DMA_REGISTERS">
// <info>
// Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11
//
// - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
//
// </info>
// </group>
//</regmap>
//<regmap name="NIXGE_REGMAP" markdown="true" generateverilog="false">
// <group name="XGE_MAC_WINDOW">
// <window name="XGE_MAC" offset="0x1000" size="0x1000" targetregmap="XGE_MAC_REGMAP"/>
// </group>
// <group name="XGE_MAC_REGS">
// <info>
// nixge (maps to 10g mac if present)
// </info>
// <register name="PORT_INFO" offset="0x0000">
// <bitfield name="COMPAT_NUM" range="31..24">
// <info>
// Constant indicating version for this space.
// Not used by the NIXGE driver (12/4/2020)
// </info>
// </bitfield>
// <bitfield name="ACTIVITY" range="17">
// <info>
// Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL.
// </info>
// </bitfield>
// <bitfield name="LINK_UP" range="16">
// <info>
// Generically means that a connection with a peer has been established. Specific
// meaning varies based on the MGT_PROTOCOL.
// </info>
// </bitfield>
// <bitfield name="MGT_PROTOCOL" range="15..8">
// <info>
// Constant indicating what flavor of communication this port is using
//
// - 0 = NONE
// - 1 = 1GbE
// - 2 = 10GbE
// - 3 = Aurora
// - 4 = WhiteRabbit
// - 5 = 100GbE
//
// </info>
// </bitfield>
// <bitfield name="PORTNUM" range="7..0">
// <info>
// Constant indicating which port this register is hooked to
//
// - 0 = QSFP0
// - 1 = QSFP1
//
// </info>
// </bitfield>
// </register>
// <register name="MAC_CTRL_STATUS" offset="0x0004">
// <info>
// Definition of this register depends on Protocol
//
// **10GBE**
//
// *READ - Status*
//
// - 0 = status_crc_error
// - 1 = status_fragment_error
// - 2 = status_txdfifo_ovflow
// - 3 = status_txdfifo_udflow
// - 4 = status_rxdfifo_ovflow
// - 5 = status_rxdfifo_udflow
// - 6 = status_pause_frame_rx
// - 7 = status_local_fault
// - 8 = status_remote_fault
//
// *WRITE - Ctl*
//
// - 0 = ctrl_tx_enable
//
// **100 GBE**
//
// *READ - Status*
//
// - 0 = tx_ovfout - Sets if TX overflow reported by CMAC
// (Stays set till MAC is reset). This is a fatal error
// - 1 = tx_unfout - Sets if TX underflow reported by CMAC
// (Stays set till MAC is reset). This is a fatal error
// - 2 = stat_rx_aligned - goes high when CMAC has finished
// alignment, and is ready to start reception of traffic.
// - 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
// but upstream is trying to hold(TREADY)off we drop a packet.
// Upstream circuitry should detect this when traffic is forked
// between CHDR and CPU, so this bit will only set if there is a
// HW design error.
// - 4 = auto_config_done - This bit goes high when the auto_config
// state machine finishes operation. It is very similiar to
// stat_rx_alligned, but waits for extra writes which occur
// after allignement to complete.
// - 24:16 = pause_mask - readable version of pause_mask bellow.
//
// *WRITE - Ctl*
//
// - 0 = auto_enable - Defaults to ON after reset - Enables a
// state machine that performs CMAC register writes to
// bring up the MAC without SW intervention.
// - 24:16 = pause_mask - A second layer of enables(the first being
// register in the CMAC) on the pause_request mechanic. Bits
// 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
// request (not priority controlled). The mask is used for TX
// and RX.
// </info>
// </register>
// <register name="MAC_PHY_STATUS" offset="0x0008">
// <info>
//
// Definition of this register depends on Protocol
//
// **10GBE**
//
// *READ - Status *
//
// - 0 = core_status 0 - link_up
// - 1 = core_status 1
// - 2 = core_status 2
// - 3 = core_status 3
// - 4 = core_status 4
// - 5 = core_status 5
// - 6 = core_status 6
// - 7 = core_status 7
//
// **100 GBE**
//
// *READ - Status*
//
// - 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.
// - 1 = usr_rx_reset - RX PLL's have locked
//
// </info>
// </register>
// <register name="MAC_LED_CTL" offset="0x000C">
// <bitfield name="identify_enable" range="0">
// <info>
// When set identify_value is used to control the activity LED.
// When clear the activity LED set on any TX or RX traffic to the mgt
// </info>
// </bitfield>
// <bitfield name="identify_value" range="1">
// <info>
// When identify_enable is set, this value controls the activity LED.
// </info>
// </bitfield>
// </register>
// <register name="ETH_MDIO_BASE" offset="0x0010">
// <info>
// The x4xx family of products does not use MDIO.
// </info>
// </register>
// <register name="AURORA_OVERRUNS" offset="0x0020">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_CHECKSUM_ERRORS" offset="0x0024">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_BIST_CHECKER_SAMPS" offset="0x0028">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_BIST_CHECKER_ERRORS" offset="0x002C">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// </group>
//</regmap>
//
//<regmap name="UIO_REGMAP" markdown="true" generateverilog="false">
// <group name="UIO_REGS">
// <info>
// UIO
// </info>
// <register name="IP" offset="0x0000">
// <info>
// Set this port's IP address
// </info>
// </register>
// <register name="UDP" offset="0x0004">
// <info>
// Set the UDP port for CHDR_traffic
// </info>
// </register>
// <register name="BRIDGE_MAC_LSB" offset="0x0010">
// <info>
// If BRIDGE_ENABLE is set use this MAC_ID
// </info>
// </register>
// <register name="BRIDGE_MAC_MSB" offset="0x0014">
// <info>
// If BRIDGE_ENABLE is set use this MAC_ID
// </info>
// </register>
// <register name="BRIDGE_IP" offset="0x0018">
// <info>
// If BRIDGE_ENABLE is set use this IP Address
// </info>
// </register>
// <register name="BRIDGE_UDP" offset="0x001C">
// <info>
// If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic
// </info>
// </register>
// <register name="BRIDGE_ENABLE" offset="0x0020">
// <info>
// Bit 0 Controls the following logic
//
//```verilog
// always_comb begin : bridge_mux
// my_mac = bridge_en ? bridge_mac_reg : mac_reg;
// my_ip = bridge_en ? bridge_ip_reg : ip_reg;
// my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
// end
//```
//
// </info>
// </register>
// <register name="CHDR_DROPPED" offset="0x0030">
// <info>
// Count the number of Packets dropped that were addressed to the CHDR section.
// </info>
// </register>
// <register name="CPU_DROPPED" offset="0x0034">
// <info>
// Count the number of Packets dropped that were addressed to us, but not to the CHDR section.
// </info>
// </register>
// <register name="PAUSE" offset="0x0038">
// <bitfield name="pause_set" range="15..0">
// <info>
// If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
// used with 100Gb ethernet
// </info>
// </bitfield>
// <bitfield name="pause_clear" range="31..16">
// <info>
// If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
// *Pause clear must be less than pause set or terrible things will happen.*
// The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
// used with 100Gb ethernet
// </info>
// </bitfield>
// </register>
// </group>
//</regmap>
//<regmap name="QSFP_REGMAP" markdown="true" generateverilog="false">
// <group name="QSFP_WINDOWS">
// <info>
// Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations
//
// - 1X10GB Ethernet - Using OpenCore XGE MAC
// - 1x100GB Ethernet - Using Xilinx CMAC
// - (future possible) - Xilinx Aurora (various rates and lane widths)
// - (future possible) - 4X10GB Ethernet
//
// </info>
// <window name="ETH_DMA" offset="0x000" size="0x4000" targetregmap="DMA_REGMAP"/>
// <window name="NIXGE" offset="0x8000" size="0x2000" targetregmap="NIXGE_REGMAP"/>
// <window name="UIO" offset="0xA000" size="0x2000" targetregmap="UIO_REGMAP"/>
// <window name="CMAC" offset="0xC000" size="0x2000" targetregmap="CMAC_REGMAP"/>
// </group>
//</regmap>
//<regmap name="AXI_HPM0_REGMAP" markdown="true" generateverilog="false">
// <group name="UHD_ONLY">
// <info>
// - 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0
// - 0_1 indicates QSFP0 - Lane1
// - 0_2 indicates QSFP0 - Lane2
// - 0_3 indicates QSFP0 - Lane3
// - 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1
// - 1_1 indicates QSFP1 - Lane1
// - 1_2 indicates QSFP1 - Lane2
// - 1_3 indicates QSFP1 - Lane3
// </info>
// <window name="QSFP_0_0" offset="0x1200000000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_1" offset="0x1200010000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_2" offset="0x1200020000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_3" offset="0x1200030000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_0" offset="0x1200040000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_1" offset="0x1200050000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_2" offset="0x1200060000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_3" offset="0x1200070000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc
+56
View File
@@ -0,0 +1,56 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/, \
x440_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
capture_sysref.v \
rf_nco_reset.vhd \
rf_reset.vhd \
sync_wrapper.v \
axis_mux.vhd \
gpio_to_axis_mux.vhd \
) \
$(addprefix $(BASE_DIR)/x400/rf/x440/, \
x440_clock_gates.vhd \
x440_rf_reset_controller.vhd \
x440_rfdc_tx_control_remap.v \
) \
$(addprefix $(BASE_DIR)/../lib/control/, \
synchronizer.v \
synchronizer_impl.v \
) \
$(addprefix $(BASE_DIR)/x400/regmap/x440/, \
PkgRFDC_REGS_REGMAP.vhd \
rfdc_mapping_regmap_utils.vh \
)
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
x440_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
x440_ps_rfdc_bd/x440_ps_rfdc_bd.bd \
)
BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
x440_ps_rfdc_bd.bd.out \
x440_ps_rfdc_bd/x440_ps_rfdc_bd_ooc.xdc \
x440_ps_rfdc_bd/synth/x440_ps_rfdc_bd.v \
)
EMPTY_IP_SRCS =
.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT
$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT
@:
IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,x440_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR)/x4xx_ps_rfdc_bd,$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/hdl_sources.tcl
+16
View File
@@ -0,0 +1,16 @@
set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh
read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd
read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/regmap/x440_rfdc_regs.v
+262
View File
@@ -0,0 +1,262 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x440_rfdc_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<top name="X440_FPGA">
// <ports>
// <info>
// This section lists all common Processing System ports through
// which the register maps in this project are accessed. Each input
// port to the fabric will point to a regmap.
// </info>
// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP">
// <info>
// This is the main AXI4-Lite master interface that the PS
// exposes to the kernel to interact with the FPGA fabric.
// There are multiple endpoints connected to this interface.
// </info>
// </port>
// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP">
// <info>
// This is the SPI1 interface
// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
// of the PS.
// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br}
// The request format on SPI is defined as.{br}
// {b}Write request:{/b}
// {ul}
// {li}1'b1 = write
// {li}15 bit address
// {li}32 bit data (MOSI)
// {li}8 bit processing gap
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// {b}Read request:{/b}
// {ul}
// {li}1'b0 = read
// {li}15 bit address
// {li}8 bit processing gap
// {li}32 bit data (MISO)
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// </info>
// </port>
// </ports>
// <regmapcfg readablestrobes="false">
// <map name="AXI_HPM0_REGMAP"/>
// <map name="MB_CPLD_PS_REGMAP"/>
// </regmapcfg>
//</top>
//
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="RFDC_REGS">
// <info>
// These are the registers located within the RFDC block design
// that provide control and status support for the RF chain.
// </info>
//
// <window name="MMCM" offset="0x0" size="0x10000">
// <info>
// Register space for controlling the data clock MMCM instance
// within the RFDC block design.
// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
// regiter space description in chapter 2.
// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
// </info>
// </window>
//
// <register name="INVERT_DB0_IQ_REG" offset="0x10000" size="32">
// <info>Control register for inverting I/Q data.</info>
// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/>
// </register>
//
// <register name="INVERT_DB1_IQ_REG" offset="0x10800" size="32">
// <info>Control register for inverting I/Q data.</info>
// <bitfield name="INVERT_DB1_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB1_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB1_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB1_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB1_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB1_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB1_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB1_DAC3_IQ" range="11"/>
// </register>
//
// <register name="MMCM_RESET_REG" offset="0x11000" size="32">
// <info>Control register for resetting the data clock MMCM.</info>
// <bitfield name="RESET_MMCM" range="0">
// <info>
// Write a '1' to this bit to reset the MMCM. Then write a
// '0' to place the MMCM out of reset.
// </info>
// </bitfield>
// </register>
//
// <register name="RF0_RESET_CONTROL_REG" offset="0x12000" typename="RF_RESET_CONTROL_REGTYPE"/>
// <register name="RF0_RESET_STATUS_REG" offset="0x12008" typename="RF_RESET_STATUS_REGTYPE"/>
// <register name="RF1_RESET_CONTROL_REG" offset="0x12800" typename="RF_RESET_CONTROL_REGTYPE"/>
// <register name="RF1_RESET_STATUS_REG" offset="0x12808" typename="RF_RESET_STATUS_REGTYPE"/>
//
// <register name="RF_AXI_STATUS_REG" offset="0x13000" typename="RF_AXI_STATUS_REGTYPE"/>
//
// <register name="CALIBRATION_DATA" offset="0x014000">
// <info>
// The fields of this register provide data to all the DAC channels when enabled
// by the CALIBRATION_ENABLE register.
// </info>
// <bitfield name="Q_DATA" range="31..16">
// </bitfield>
// <bitfield name="I_DATA" range="15..00">
// </bitfield>
// </register>
//
// <register name="CALIBRATION_ENABLE" offset="0x014008">
// <info>
// This register enables calibration data in the DAC data path for each of the
// four channels. Each of these bits is normally '0'. When written '1', DAC data
// for the corresponding channel will be constantly driven with the contents of
// the CALIBRATION_DATA register.
// </info>
// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0">
// <info>
// Enables calibration data for channel #0/0.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1">
// <info>
// Enables calibration data for channel #0/1.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="2">
// <info>
// Enables calibration data for channel #0/2.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="3">
// <info>
// Enables calibration data for channel #0/3.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_4" range="4">
// <info>
// Enables calibration data for channel #1/0.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_5" range="5">
// <info>
// Enables calibration data for channel #1/1.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_6" range="6">
// <info>
// Enables calibration data for channel #1/2.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_7" range="7">
// <info>
// Enables calibration data for channel #1/3.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true">
// <info>
// Enable RF MMCM outputs.
// </info>
// <bitfield name="ENABLE_RF0_CLK" range="8"/>
// <bitfield name="ENABLE_RF0_CLK_2X" range="12"/>
// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/>
// <bitfield name="ENABLE_RF1_CLK" range="20"/>
// <bitfield name="ENABLE_RF1_CLK_2X" range="24"/>
// </register>
//
// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false">
// <info>
// Data Clk Pll Status Register
// </info>
// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/>
// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/>
// </register>
//
// <register name="THRESHOLD_STATUS" offset="0x015000">
// <info>
// This register shows threshold status for the ADCs. Each bit reflects the
// RFDC's real-time ADC status signals, which will assert when the ADC input
// signal exceeds the programmed threshold value. The status will remain
// asserted until cleared by software.
// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
// the location of the tile in the converter column and ZZ is either 01 (the
// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
// See also the Xilinx document PG269.
// </info>
// <bitfield name="ADC0_01_THRESHOLD1" range="0">
// </bitfield>
// <bitfield name="ADC0_01_THRESHOLD2" range="1">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD1" range="2">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD2" range="3">
// </bitfield>
// <bitfield name="ADC1_01_THRESHOLD1" range="4">
// </bitfield>
// <bitfield name="ADC1_01_THRESHOLD2" range="5">
// </bitfield>
// <bitfield name="ADC1_23_THRESHOLD1" range="6">
// </bitfield>
// <bitfield name="ADC1_23_THRESHOLD2" range="7">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD1" range="8">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD2" range="9">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD1" range="10">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD2" range="11">
// </bitfield>
// <bitfield name="ADC3_01_THRESHOLD1" range="12">
// </bitfield>
// <bitfield name="ADC3_01_THRESHOLD2" range="13">
// </bitfield>
// <bitfield name="ADC3_23_THRESHOLD1" range="14">
// </bitfield>
// <bitfield name="ADC3_23_THRESHOLD2" range="15">
// </bitfield>
// </register>
//
// <register name="FABRIC_DSP_REG" offset="0x13008" typename="FABRIC_DSP_REGTYPE"/>
// <register name="ADC_TILEMAP_REG" offset="0x17000" typename="ADC_TILEMAP_REGTYPE"/>
// <register name="DAC_TILEMAP_REG" offset="0x17008" typename="DAC_TILEMAP_REGTYPE"/>
// <register name="RFDC_INFO_REG" offset="0x18000" typename="RFDC_INFO_REGTYPE"/>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd → top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/synthstub/x440_ps_rfdc_bd.vhd
+98 -32
View File
@@ -1,9 +1,9 @@
------------------------------------------------------------------------------------------
--
-- File: x4xx_ps_rfdc_bd.vhd
-- File: x440_ps_rfdc_bd.vhd
-- Author: niBlockDesign::niBdExportStub
-- Original Project: HwBuildTools
-- Date: 27 September 2021
-- Date: 06 September 2022
--
------------------------------------------------------------------------------------------
-- (c) Copyright National Instruments Corporation
@@ -12,7 +12,7 @@
------------------------------------------------------------------------------------------
--
-- Purpose: This is an automatically generated stub file to match the entity
-- declaration for 'x4xx_ps_rfdc_bd'. This file was created using niBdExportStub
-- declaration for 'x440_ps_rfdc_bd'. This file was created using niBdExportStub
-- Do not modify this file directly!
--
------------------------------------------------------------------------------------------
@@ -22,37 +22,44 @@ use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity x4xx_ps_rfdc_bd is
entity x440_ps_rfdc_bd is
port (
adc_data_out_resetn_dclk : out STD_LOGIC;
adc_enable_data_rclk : out STD_LOGIC;
adc_reset_pulse_dclk : in STD_LOGIC;
adc_rfdc_axi_resetn_rclk : out STD_LOGIC;
adc_enable_data_r0clk : out STD_LOGIC;
adc_enable_data_r1clk : out STD_LOGIC;
adc_reset_pulse_r0clk : in STD_LOGIC;
adc_reset_pulse_r1clk : in STD_LOGIC;
adc_resetn_r0clk2x : out STD_LOGIC;
adc_resetn_r1clk2x : out STD_LOGIC;
adc_rfdc_axi_resetn_r0clk : out STD_LOGIC;
adc_rfdc_axi_resetn_r1clk : out STD_LOGIC;
bus_clk : in STD_LOGIC;
bus_rstn : in STD_LOGIC;
clk40 : in STD_LOGIC;
clk40_rstn : in STD_LOGIC;
dac_data_in_resetn_dclk : out STD_LOGIC;
dac_data_in_resetn_dclk2x : out STD_LOGIC;
dac_data_in_resetn_rclk : out STD_LOGIC;
dac_data_in_resetn_rclk2x : out STD_LOGIC;
dac_reset_pulse_dclk : in STD_LOGIC;
data_clk : out STD_LOGIC;
data_clk_2x : out STD_LOGIC;
dac_data_in_resetn_r0clk : out STD_LOGIC;
dac_data_in_resetn_r0clk2x : out STD_LOGIC;
dac_data_in_resetn_r1clk : out STD_LOGIC;
dac_data_in_resetn_r1clk2x : out STD_LOGIC;
dac_reset_pulse_r0clk : in STD_LOGIC;
dac_reset_pulse_r1clk : in STD_LOGIC;
data_clock_locked : out STD_LOGIC;
enable_gated_clocks_clk40 : in STD_LOGIC;
enable_sysref_rclk : in STD_LOGIC;
fir_resetn_rclk2x : out STD_LOGIC;
enable_sysref_r0clk : in STD_LOGIC;
enable_sysref_r1clk : in STD_LOGIC;
gated_base_clks_valid_clk40 : out STD_LOGIC;
invert_adc_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_dac_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_adc_iq_r0clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_adc_iq_r1clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_dac_iq_r0clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_dac_iq_r1clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
irq0_lpd_rpu_n : in STD_LOGIC;
irq1_lpd_rpu_n : in STD_LOGIC;
jtag0_tck : inout STD_LOGIC;
jtag0_tdi : inout STD_LOGIC;
jtag0_tdo : in STD_LOGIC;
jtag0_tms : inout STD_LOGIC;
nco_reset_done_dclk : out STD_LOGIC;
nco_reset_done_r0clk : out STD_LOGIC;
nco_reset_done_r1clk : out STD_LOGIC;
pl_clk40 : out STD_LOGIC;
pl_clk100 : out STD_LOGIC;
pl_clk166 : out STD_LOGIC;
@@ -65,15 +72,18 @@ port (
pl_resetn3 : out STD_LOGIC;
pll_ref_clk_in : in STD_LOGIC;
pll_ref_clk_out : out STD_LOGIC;
radio0_rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
radio0_rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
radio1_rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
radio1_rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
rf_axi_status_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rf_dsp_info_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
rfdc_irq : out STD_LOGIC;
s_axi_hp0_aclk : in STD_LOGIC;
s_axi_hp1_aclk : in STD_LOGIC;
s_axi_hpc0_aclk : in STD_LOGIC;
start_nco_reset_dclk : in STD_LOGIC;
start_nco_reset_r0clk : in STD_LOGIC;
start_nco_reset_r1clk : in STD_LOGIC;
sysref_out_pclk : out STD_LOGIC;
sysref_out_rclk : out STD_LOGIC;
sysref_pl_in : in STD_LOGIC;
@@ -201,8 +211,20 @@ port (
s_axi_hpc0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
adc0_clk_clk_n : in STD_LOGIC;
adc0_clk_clk_p : in STD_LOGIC;
adc1_clk_clk_n : in STD_LOGIC;
adc1_clk_clk_p : in STD_LOGIC;
adc2_clk_clk_n : in STD_LOGIC;
adc2_clk_clk_p : in STD_LOGIC;
adc3_clk_clk_n : in STD_LOGIC;
adc3_clk_clk_p : in STD_LOGIC;
adc_tile225_ch0_vin_v_n : in STD_LOGIC;
adc_tile225_ch0_vin_v_p : in STD_LOGIC;
adc_tile225_ch1_vin_v_n : in STD_LOGIC;
adc_tile225_ch1_vin_v_p : in STD_LOGIC;
adc_tile227_ch0_vin_v_n : in STD_LOGIC;
adc_tile227_ch0_vin_v_p : in STD_LOGIC;
adc_tile227_ch1_vin_v_n : in STD_LOGIC;
adc_tile227_ch1_vin_v_p : in STD_LOGIC;
m_axi_app_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_app_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_app_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
@@ -226,6 +248,18 @@ port (
dac0_clk_clk_p : in STD_LOGIC;
dac1_clk_clk_n : in STD_LOGIC;
dac1_clk_clk_p : in STD_LOGIC;
dac_tile228_ch2_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch2_din_tvalid : in STD_LOGIC;
dac_tile228_ch2_din_tready : out STD_LOGIC;
dac_tile228_ch3_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch3_din_tvalid : in STD_LOGIC;
dac_tile228_ch3_din_tready : out STD_LOGIC;
dac_tile229_ch2_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile229_ch2_din_tvalid : in STD_LOGIC;
dac_tile229_ch2_din_tready : out STD_LOGIC;
dac_tile229_ch3_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile229_ch3_din_tvalid : in STD_LOGIC;
dac_tile229_ch3_din_tready : out STD_LOGIC;
gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 );
@@ -310,6 +344,14 @@ port (
m_axi_mpm_ep_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mpm_ep_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
dac_tile228_ch0_vout_v_n : out STD_LOGIC;
dac_tile228_ch0_vout_v_p : out STD_LOGIC;
dac_tile228_ch1_vout_v_n : out STD_LOGIC;
dac_tile228_ch1_vout_v_p : out STD_LOGIC;
dac_tile229_ch0_vout_v_n : out STD_LOGIC;
dac_tile229_ch0_vout_v_p : out STD_LOGIC;
dac_tile229_ch1_vout_v_n : out STD_LOGIC;
dac_tile229_ch1_vout_v_p : out STD_LOGIC;
adc_tile224_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch0_dout_i_tready : in STD_LOGIC;
adc_tile224_ch0_dout_i_tvalid : out STD_LOGIC;
@@ -322,6 +364,18 @@ port (
adc_tile224_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch1_dout_q_tready : in STD_LOGIC;
adc_tile224_ch1_dout_q_tvalid : out STD_LOGIC;
adc_tile225_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile225_ch0_dout_i_tready : in STD_LOGIC;
adc_tile225_ch0_dout_i_tvalid : out STD_LOGIC;
adc_tile225_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile225_ch0_dout_q_tready : in STD_LOGIC;
adc_tile225_ch0_dout_q_tvalid : out STD_LOGIC;
adc_tile225_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile225_ch1_dout_i_tready : in STD_LOGIC;
adc_tile225_ch1_dout_i_tvalid : out STD_LOGIC;
adc_tile225_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile225_ch1_dout_q_tready : in STD_LOGIC;
adc_tile225_ch1_dout_q_tvalid : out STD_LOGIC;
adc_tile226_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch0_dout_i_tready : in STD_LOGIC;
adc_tile226_ch0_dout_i_tvalid : out STD_LOGIC;
@@ -334,14 +388,26 @@ port (
adc_tile226_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch1_dout_q_tready : in STD_LOGIC;
adc_tile226_ch1_dout_q_tvalid : out STD_LOGIC;
dac_tile228_ch0_vout_v_n : out STD_LOGIC;
dac_tile228_ch0_vout_v_p : out STD_LOGIC;
dac_tile228_ch1_vout_v_n : out STD_LOGIC;
dac_tile228_ch1_vout_v_p : out STD_LOGIC;
dac_tile229_ch0_vout_v_n : out STD_LOGIC;
dac_tile229_ch0_vout_v_p : out STD_LOGIC;
dac_tile229_ch1_vout_v_n : out STD_LOGIC;
dac_tile229_ch1_vout_v_p : out STD_LOGIC;
adc_tile227_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile227_ch0_dout_i_tready : in STD_LOGIC;
adc_tile227_ch0_dout_i_tvalid : out STD_LOGIC;
adc_tile227_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile227_ch0_dout_q_tready : in STD_LOGIC;
adc_tile227_ch0_dout_q_tvalid : out STD_LOGIC;
adc_tile227_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile227_ch1_dout_i_tready : in STD_LOGIC;
adc_tile227_ch1_dout_i_tvalid : out STD_LOGIC;
adc_tile227_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile227_ch1_dout_q_tready : in STD_LOGIC;
adc_tile227_ch1_dout_q_tvalid : out STD_LOGIC;
dac_tile228_ch2_vout_v_n : out STD_LOGIC;
dac_tile228_ch2_vout_v_p : out STD_LOGIC;
dac_tile228_ch3_vout_v_n : out STD_LOGIC;
dac_tile228_ch3_vout_v_p : out STD_LOGIC;
dac_tile229_ch2_vout_v_n : out STD_LOGIC;
dac_tile229_ch2_vout_v_p : out STD_LOGIC;
dac_tile229_ch3_vout_v_n : out STD_LOGIC;
dac_tile229_ch3_vout_v_p : out STD_LOGIC;
dac_tile228_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch0_din_tvalid : in STD_LOGIC;
dac_tile228_ch0_din_tready : out STD_LOGIC;
@@ -404,8 +470,8 @@ port (
s_axi_hpc1_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_awuser : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end entity x4xx_ps_rfdc_bd;
end entity x440_ps_rfdc_bd;
architecture stub of x4xx_ps_rfdc_bd is
architecture stub of x440_ps_rfdc_bd is
begin
end architecture stub;
top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl → top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl
+746 -257
View File
File diff suppressed because it is too large Load Diff
top/x400/ipass_present_controller.v
+5 -1
View File
@@ -40,7 +40,11 @@ module ipass_present_controller (
);
`include "regmap/pl_cpld_regmap_utils.vh"
`include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh"
`ifdef X440
`include "cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh"
`else // Use X410 as the default variant for regmap.
`include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh"
`endif
`include "cpld/regmap/pl_cpld_base_regmap_utils.vh"
`include "../../lib/rfnoc/core/ctrlport.vh"
top/x400/regmap/rfdc_regs_regmap_utils.vh
-303
View File
@@ -1,303 +0,0 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfdc_regs_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// MMCM : 0x0 (common_regs.v)
// INVERT_IQ_REG : 0x10000 (common_regs.v)
// MMCM_RESET_REG : 0x11000 (common_regs.v)
// RF_RESET_CONTROL_REG : 0x12000 (common_regs.v)
// RF_RESET_STATUS_REG : 0x12008 (common_regs.v)
// RF_AXI_STATUS_REG : 0x13000 (common_regs.v)
// FABRIC_DSP_REG : 0x13008 (common_regs.v)
// CALIBRATION_DATA : 0x14000 (common_regs.v)
// CALIBRATION_ENABLE : 0x14008 (common_regs.v)
// THRESHOLD_STATUS : 0x15000 (common_regs.v)
// RF_PLL_CONTROL_REG : 0x16000 (common_regs.v)
// RF_PLL_STATUS_REG : 0x16008 (common_regs.v)
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group RFDC_REGS
//===============================================================================
// Enumerated type FABRIC_DSP_BW_ENUM
localparam FABRIC_DSP_BW_ENUM_SIZE = 4;
localparam FABRIC_DSP_BW_NONE = 'h0; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE
localparam FABRIC_DSP_BW_100M = 'h64; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M
localparam FABRIC_DSP_BW_200M = 'hC8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M
localparam FABRIC_DSP_BW_400M = 'h190; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M
// MMCM Window (from common_regs.v)
localparam MMCM = 'h0; // Window Offset
localparam MMCM_SIZE = 'h10000; // size in bytes
// INVERT_IQ_REG Register (from common_regs.v)
localparam INVERT_IQ_REG = 'h10000; // Register Offset
localparam INVERT_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_IQ_REG_MASK = 32'hFFFF;
localparam INVERT_DB0_ADC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ_MSB = 0; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ = 0; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ_MSB = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ_MSB = 2; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ = 2; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ_MSB = 3; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ = 3; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB1_ADC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ_MSB = 4; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ = 4; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ_MSB = 5; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ = 5; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ_MSB = 6; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ = 6; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ_MSB = 7; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ = 7; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB0_DAC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ_MSB = 8; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ = 8; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ_MSB = 9; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ = 9; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ_MSB = 10; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ = 10; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ_MSB = 11; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ = 11; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB1_DAC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ_MSB = 12; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ = 12; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ_MSB = 13; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ = 13; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ_MSB = 14; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ = 14; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ_MSB = 15; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ = 15; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ
// MMCM_RESET_REG Register (from common_regs.v)
localparam MMCM_RESET_REG = 'h11000; // Register Offset
localparam MMCM_RESET_REG_SIZE = 32; // register width in bits
localparam MMCM_RESET_REG_MASK = 32'h1;
localparam RESET_MMCM_SIZE = 1; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM_MSB = 0; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM = 0; //MMCM_RESET_REG:RESET_MMCM
// RF_RESET_CONTROL_REG Register (from common_regs.v)
localparam RF_RESET_CONTROL_REG = 'h12000; // Register Offset
localparam RF_RESET_CONTROL_REG_SIZE = 32; // register width in bits
localparam RF_RESET_CONTROL_REG_MASK = 32'h331;
localparam FSM_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:FSM_RESET
localparam FSM_RESET_MSB = 0; //RF_RESET_CONTROL_REG:FSM_RESET
localparam FSM_RESET = 0; //RF_RESET_CONTROL_REG:FSM_RESET
localparam ADC_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:ADC_RESET
localparam ADC_RESET_MSB = 4; //RF_RESET_CONTROL_REG:ADC_RESET
localparam ADC_RESET = 4; //RF_RESET_CONTROL_REG:ADC_RESET
localparam ADC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REG:ADC_ENABLE
localparam ADC_ENABLE_MSB = 5; //RF_RESET_CONTROL_REG:ADC_ENABLE
localparam ADC_ENABLE = 5; //RF_RESET_CONTROL_REG:ADC_ENABLE
localparam DAC_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:DAC_RESET
localparam DAC_RESET_MSB = 8; //RF_RESET_CONTROL_REG:DAC_RESET
localparam DAC_RESET = 8; //RF_RESET_CONTROL_REG:DAC_RESET
localparam DAC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REG:DAC_ENABLE
localparam DAC_ENABLE_MSB = 9; //RF_RESET_CONTROL_REG:DAC_ENABLE
localparam DAC_ENABLE = 9; //RF_RESET_CONTROL_REG:DAC_ENABLE
// RF_RESET_STATUS_REG Register (from common_regs.v)
localparam RF_RESET_STATUS_REG = 'h12008; // Register Offset
localparam RF_RESET_STATUS_REG_SIZE = 32; // register width in bits
localparam RF_RESET_STATUS_REG_MASK = 32'h888;
localparam FSM_RESET_DONE_SIZE = 1; //RF_RESET_STATUS_REG:FSM_RESET_DONE
localparam FSM_RESET_DONE_MSB = 3; //RF_RESET_STATUS_REG:FSM_RESET_DONE
localparam FSM_RESET_DONE = 3; //RF_RESET_STATUS_REG:FSM_RESET_DONE
localparam ADC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REG:ADC_SEQ_DONE
localparam ADC_SEQ_DONE_MSB = 7; //RF_RESET_STATUS_REG:ADC_SEQ_DONE
localparam ADC_SEQ_DONE = 7; //RF_RESET_STATUS_REG:ADC_SEQ_DONE
localparam DAC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REG:DAC_SEQ_DONE
localparam DAC_SEQ_DONE_MSB = 11; //RF_RESET_STATUS_REG:DAC_SEQ_DONE
localparam DAC_SEQ_DONE = 11; //RF_RESET_STATUS_REG:DAC_SEQ_DONE
// RF_AXI_STATUS_REG Register (from common_regs.v)
localparam RF_AXI_STATUS_REG = 'h13000; // Register Offset
localparam RF_AXI_STATUS_REG_SIZE = 32; // register width in bits
localparam RF_AXI_STATUS_REG_MASK = 32'hFFFFFFFF;
localparam RFDC_DAC_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY_MSB = 1; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY = 0; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY
localparam RFDC_DAC_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID_MSB = 3; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID
localparam RFDC_ADC_Q_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY_MSB = 5; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY = 4; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_I_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY_MSB = 7; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY = 6; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY
localparam RFDC_ADC_Q_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID_MSB = 9; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID = 8; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_I_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID_MSB = 11; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID = 10; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID
localparam USER_ADC_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TVALID
localparam USER_ADC_TVALID_MSB = 13; //RF_AXI_STATUS_REG:USER_ADC_TVALID
localparam USER_ADC_TVALID = 12; //RF_AXI_STATUS_REG:USER_ADC_TVALID
localparam USER_ADC_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TREADY
localparam USER_ADC_TREADY_MSB = 15; //RF_AXI_STATUS_REG:USER_ADC_TREADY
localparam USER_ADC_TREADY = 14; //RF_AXI_STATUS_REG:USER_ADC_TREADY
localparam RFDC_DAC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1_MSB = 17; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1 = 16; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1_MSB = 19; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1 = 18; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1
localparam RFDC_ADC_Q_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1_MSB = 21; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1 = 20; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_MSB = 23; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1 = 22; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_Q_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1_MSB = 25; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1 = 24; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_MSB = 27; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1 = 26; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1
localparam USER_ADC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1_MSB = 29; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1 = 28; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1
localparam USER_ADC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1_MSB = 31; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1 = 30; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1
// FABRIC_DSP_REG Register (from common_regs.v)
localparam FABRIC_DSP_REG = 'h13008; // Register Offset
localparam FABRIC_DSP_REG_SIZE = 32; // register width in bits
localparam FABRIC_DSP_REG_MASK = 32'hFFFFFFFF;
localparam FABRIC_DSP_BW_SIZE = 12; //FABRIC_DSP_REG:FABRIC_DSP_BW
localparam FABRIC_DSP_BW_MSB = 11; //FABRIC_DSP_REG:FABRIC_DSP_BW
localparam FABRIC_DSP_BW = 0; //FABRIC_DSP_REG:FABRIC_DSP_BW
localparam FABRIC_DSP_RX_CNT_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT_MSB = 13; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT = 12; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_TX_CNT_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT_MSB = 15; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT = 14; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_BW_DB1_SIZE = 12; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
localparam FABRIC_DSP_BW_DB1_MSB = 27; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
localparam FABRIC_DSP_BW_DB1 = 16; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1
localparam FABRIC_DSP_RX_CNT_DB1_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1_MSB = 29; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1 = 28; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_MSB = 31; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1 = 30; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1
// CALIBRATION_DATA Register (from common_regs.v)
localparam CALIBRATION_DATA = 'h14000; // Register Offset
localparam CALIBRATION_DATA_SIZE = 32; // register width in bits
localparam CALIBRATION_DATA_MASK = 32'hFFFFFFFF;
localparam I_DATA_SIZE = 16; //CALIBRATION_DATA:I_DATA
localparam I_DATA_MSB = 15; //CALIBRATION_DATA:I_DATA
localparam I_DATA = 0; //CALIBRATION_DATA:I_DATA
localparam Q_DATA_SIZE = 16; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA_MSB = 31; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA = 16; //CALIBRATION_DATA:Q_DATA
// CALIBRATION_ENABLE Register (from common_regs.v)
localparam CALIBRATION_ENABLE = 'h14008; // Register Offset
localparam CALIBRATION_ENABLE_SIZE = 32; // register width in bits
localparam CALIBRATION_ENABLE_MASK = 32'h33;
localparam ENABLE_CALIBRATION_DATA_0_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0_MSB = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0 = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_1_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1_MSB = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1 = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_2_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2_MSB = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2 = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_3_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3_MSB = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3 = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
// THRESHOLD_STATUS Register (from common_regs.v)
localparam THRESHOLD_STATUS = 'h15000; // Register Offset
localparam THRESHOLD_STATUS_SIZE = 32; // register width in bits
localparam THRESHOLD_STATUS_MASK = 32'hF0F;
localparam ADC0_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1_MSB = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1 = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2_MSB = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2 = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1_MSB = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1 = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2_MSB = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2 = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC2_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1_MSB = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1 = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2_MSB = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2 = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1_MSB = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1 = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2_MSB = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2 = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
// RF_PLL_CONTROL_REG Register (from common_regs.v)
localparam RF_PLL_CONTROL_REG = 'h16000; // Register Offset
localparam RF_PLL_CONTROL_REG_SIZE = 32; // register width in bits
localparam RF_PLL_CONTROL_REG_MASK = 32'h11111;
localparam ENABLE_DATA_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK_MSB = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK
localparam ENABLE_DATA_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_DATA_CLK_2X_MSB = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_DATA_CLK_2X = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X
localparam ENABLE_RF_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK_MSB = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK
localparam ENABLE_RF_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam ENABLE_RF_CLK_2X_MSB = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam ENABLE_RF_CLK_2X = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X
localparam CLEAR_DATA_CLK_UNLOCKED_SIZE = 1; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED_MSB = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
// RF_PLL_STATUS_REG Register (from common_regs.v)
localparam RF_PLL_STATUS_REG = 'h16008; // Register Offset
localparam RF_PLL_STATUS_REG_SIZE = 32; // register width in bits
localparam RF_PLL_STATUS_REG_MASK = 32'h110000;
localparam DATA_CLK_PLL_UNLOCKED_STICKY_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY_MSB = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_LOCKED_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED_MSB = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
top/x400/regmap/x440/PkgRFDC_REGS_REGMAP.vhd
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top/x400/regmap/x440/rfdc_mapping_regmap_utils.vh
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfdc_mapping_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group CHANNEL_SWAPPING
//===============================================================================
// Enumerated type RFDC_ADC_MAPPING
localparam RFDC_ADC_MAPPING_SIZE = 8;
localparam CH2_RX_MAPPING = 'h0; // RFDC_ADC_MAPPING:CH2_RX_MAPPING
localparam CH1_RX_MAPPING = 'h1; // RFDC_ADC_MAPPING:CH1_RX_MAPPING
localparam CH3_RX_MAPPING = 'h2; // RFDC_ADC_MAPPING:CH3_RX_MAPPING
localparam CH0_RX_MAPPING = 'h3; // RFDC_ADC_MAPPING:CH0_RX_MAPPING
localparam CH6_RX_MAPPING = 'h4; // RFDC_ADC_MAPPING:CH6_RX_MAPPING
localparam CH5_RX_MAPPING = 'h5; // RFDC_ADC_MAPPING:CH5_RX_MAPPING
localparam CH7_RX_MAPPING = 'h6; // RFDC_ADC_MAPPING:CH7_RX_MAPPING
localparam CH4_RX_MAPPING = 'h7; // RFDC_ADC_MAPPING:CH4_RX_MAPPING
// Enumerated type RFDC_DAC_MAPPING
localparam RFDC_DAC_MAPPING_SIZE = 8;
localparam CH0_TX_MAPPING = 'h0; // RFDC_DAC_MAPPING:CH0_TX_MAPPING
localparam CH3_TX_MAPPING = 'h1; // RFDC_DAC_MAPPING:CH3_TX_MAPPING
localparam CH1_TX_MAPPING = 'h2; // RFDC_DAC_MAPPING:CH1_TX_MAPPING
localparam CH2_TX_MAPPING = 'h3; // RFDC_DAC_MAPPING:CH2_TX_MAPPING
localparam CH4_TX_MAPPING = 'h4; // RFDC_DAC_MAPPING:CH4_TX_MAPPING
localparam CH7_TX_MAPPING = 'h5; // RFDC_DAC_MAPPING:CH7_TX_MAPPING
localparam CH5_TX_MAPPING = 'h6; // RFDC_DAC_MAPPING:CH5_TX_MAPPING
localparam CH6_TX_MAPPING = 'h7; // RFDC_DAC_MAPPING:CH6_TX_MAPPING
top/x400/regmap/x440/rfdc_regs_regmap_utils.vh
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfdc_regs_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// MMCM : 0x0 (x440_rfdc_regs.v)
// INVERT_DB0_IQ_REG : 0x10000 (x440_rfdc_regs.v)
// INVERT_DB1_IQ_REG : 0x10800 (x440_rfdc_regs.v)
// MMCM_RESET_REG : 0x11000 (x440_rfdc_regs.v)
// RF0_RESET_CONTROL_REG : 0x12000 (x440_rfdc_regs.v)
// RF0_RESET_STATUS_REG : 0x12008 (x440_rfdc_regs.v)
// RF1_RESET_CONTROL_REG : 0x12800 (x440_rfdc_regs.v)
// RF1_RESET_STATUS_REG : 0x12808 (x440_rfdc_regs.v)
// RF_AXI_STATUS_REG : 0x13000 (x440_rfdc_regs.v)
// FABRIC_DSP_REG : 0x13008 (x440_rfdc_regs.v)
// CALIBRATION_DATA : 0x14000 (x440_rfdc_regs.v)
// CALIBRATION_ENABLE : 0x14008 (x440_rfdc_regs.v)
// THRESHOLD_STATUS : 0x15000 (x440_rfdc_regs.v)
// RF_PLL_CONTROL_REG : 0x16000 (x440_rfdc_regs.v)
// RF_PLL_STATUS_REG : 0x16008 (x440_rfdc_regs.v)
// ADC_TILEMAP_REG : 0x17000 (x440_rfdc_regs.v)
// DAC_TILEMAP_REG : 0x17008 (x440_rfdc_regs.v)
// RFDC_INFO_REG : 0x18000 (x440_rfdc_regs.v)
//===============================================================================
// RegTypes
//===============================================================================
// ADC_TILEMAP_REGTYPE Type (from common_regs.v)
localparam ADC_TILEMAP_REGTYPE_SIZE = 32;
localparam ADC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam ADC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_TILE = 0; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_TILE = 4; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK = 6; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_TILE = 8; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK = 10; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_TILE = 12; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK = 14; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_TILE = 16; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK = 18; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_TILE = 20; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK = 22; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_TILE = 24; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK = 26; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_TILE = 28; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK = 30; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
// DAC_TILEMAP_REGTYPE Type (from common_regs.v)
localparam DAC_TILEMAP_REGTYPE_SIZE = 32;
localparam DAC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam DAC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_TILE = 0; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_TILE = 4; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK = 6; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_TILE = 8; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK = 10; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_TILE = 12; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK = 14; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_TILE = 16; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK = 18; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_TILE = 20; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK = 22; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_TILE = 24; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK = 26; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_TILE = 28; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK = 30; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
// FABRIC_DSP_REGTYPE Type (from common_regs.v)
localparam FABRIC_DSP_REGTYPE_SIZE = 32;
localparam FABRIC_DSP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam FABRIC_DSP_RX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT_MSB = 3; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT = 0; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_TX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT_MSB = 7; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_RESERVED_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RESERVED_MSB = 9; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RESERVED = 8; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1_MSB = 13; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1 = 10; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_MSB = 17; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1 = 14; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_RESERVED_DB1_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_RESERVED_DB1_MSB = 19; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_RESERVED_DB1 = 18; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_BW_SIZE = 12; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
localparam FABRIC_DSP_BW_MSB = 31; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
localparam FABRIC_DSP_BW = 20; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
// RF_AXI_STATUS_REGTYPE Type (from common_regs.v)
localparam RF_AXI_STATUS_REGTYPE_SIZE = 32;
localparam RF_AXI_STATUS_REGTYPE_MASK = 32'hFFFFFFFF;
localparam RFDC_DAC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY_MSB = 1; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY = 0; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID_MSB = 3; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_ADC_Q_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY_MSB = 5; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY = 4; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_I_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY_MSB = 7; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY = 6; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_Q_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID_MSB = 9; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID = 8; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_I_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID_MSB = 11; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID = 10; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam USER_ADC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TVALID_MSB = 13; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TVALID = 12; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam USER_ADC_TREADY_MSB = 15; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam USER_ADC_TREADY = 14; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam RFDC_DAC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1_MSB = 17; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1 = 16; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1_MSB = 19; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1 = 18; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_ADC_Q_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1_MSB = 21; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1 = 20; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_MSB = 23; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1 = 22; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_Q_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1_MSB = 25; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1 = 24; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_MSB = 27; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1 = 26; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam USER_ADC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1_MSB = 29; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1 = 28; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1_MSB = 31; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1 = 30; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
// RF_RESET_CONTROL_REGTYPE Type (from common_regs.v)
localparam RF_RESET_CONTROL_REGTYPE_SIZE = 32;
localparam RF_RESET_CONTROL_REGTYPE_MASK = 32'h331;
localparam FSM_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam FSM_RESET_MSB = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam FSM_RESET = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam ADC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_RESET_MSB = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_RESET = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam ADC_ENABLE_MSB = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam ADC_ENABLE = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam DAC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_RESET_MSB = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_RESET = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
localparam DAC_ENABLE_MSB = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
localparam DAC_ENABLE = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
// RF_RESET_STATUS_REGTYPE Type (from common_regs.v)
localparam RF_RESET_STATUS_REGTYPE_SIZE = 32;
localparam RF_RESET_STATUS_REGTYPE_MASK = 32'h888;
localparam FSM_RESET_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam FSM_RESET_DONE_MSB = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam FSM_RESET_DONE = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam ADC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam ADC_SEQ_DONE_MSB = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam ADC_SEQ_DONE = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam DAC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
localparam DAC_SEQ_DONE_MSB = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
localparam DAC_SEQ_DONE = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
// RFDC_INFO_REGTYPE Type (from common_regs.v)
localparam RFDC_INFO_REGTYPE_SIZE = 32;
localparam RFDC_INFO_REGTYPE_MASK = 32'h3FF03FF;
localparam RFDC_INFO_XTRA_RESAMP_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_XTRA_RESAMP_MSB = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_XTRA_RESAMP = 0; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_SPC_RX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_RX_MSB = 6; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_RX = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_TX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_SPC_TX_MSB = 9; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_SPC_TX = 7; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_XTRA_RESAMP_DB1_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_XTRA_RESAMP_DB1_MSB = 19; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_XTRA_RESAMP_DB1 = 16; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_SPC_RX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_RX_DB1_MSB = 22; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_RX_DB1 = 20; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_TX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
localparam RFDC_INFO_SPC_TX_DB1_MSB = 25; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
localparam RFDC_INFO_SPC_TX_DB1 = 23; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
//===============================================================================
// Register Group RFDC_REGS
//===============================================================================
// Enumerated type FABRIC_DSP_BW_ENUM
localparam FABRIC_DSP_BW_ENUM_SIZE = 5;
localparam FABRIC_DSP_BW_NONE = 'h0; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE
localparam FABRIC_DSP_BW_100M = 'h64; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M
localparam FABRIC_DSP_BW_200M = 'hC8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M
localparam FABRIC_DSP_BW_400M = 'h190; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M
localparam FABRIC_DSP_BW_FULL = 'h3E8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_FULL
// MMCM Window (from x440_rfdc_regs.v)
localparam MMCM = 'h0; // Window Offset
localparam MMCM_SIZE = 'h10000; // size in bytes
// INVERT_DB0_IQ_REG Register (from x440_rfdc_regs.v)
localparam INVERT_DB0_IQ_REG = 'h10000; // Register Offset
localparam INVERT_DB0_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_DB0_IQ_REG_MASK = 32'hF0F;
localparam INVERT_DB0_ADC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ_MSB = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ_MSB = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ_MSB = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ_MSB = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_DAC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ_MSB = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ_MSB = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ_MSB = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ_MSB = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
// INVERT_DB1_IQ_REG Register (from x440_rfdc_regs.v)
localparam INVERT_DB1_IQ_REG = 'h10800; // Register Offset
localparam INVERT_DB1_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_DB1_IQ_REG_MASK = 32'hF0F;
localparam INVERT_DB1_ADC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ_MSB = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ_MSB = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ_MSB = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ_MSB = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_DAC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ_MSB = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ_MSB = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ_MSB = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ_MSB = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
// MMCM_RESET_REG Register (from x440_rfdc_regs.v)
localparam MMCM_RESET_REG = 'h11000; // Register Offset
localparam MMCM_RESET_REG_SIZE = 32; // register width in bits
localparam MMCM_RESET_REG_MASK = 32'h1;
localparam RESET_MMCM_SIZE = 1; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM_MSB = 0; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM = 0; //MMCM_RESET_REG:RESET_MMCM
// RF0_RESET_CONTROL_REG Register (from x440_rfdc_regs.v)
localparam RF0_RESET_CONTROL_REG = 'h12000; // Register Offset
localparam RF0_RESET_CONTROL_REG_SIZE = 32; // register width in bits
// RF0_RESET_STATUS_REG Register (from x440_rfdc_regs.v)
localparam RF0_RESET_STATUS_REG = 'h12008; // Register Offset
localparam RF0_RESET_STATUS_REG_SIZE = 32; // register width in bits
// RF1_RESET_CONTROL_REG Register (from x440_rfdc_regs.v)
localparam RF1_RESET_CONTROL_REG = 'h12800; // Register Offset
localparam RF1_RESET_CONTROL_REG_SIZE = 32; // register width in bits
// RF1_RESET_STATUS_REG Register (from x440_rfdc_regs.v)
localparam RF1_RESET_STATUS_REG = 'h12808; // Register Offset
localparam RF1_RESET_STATUS_REG_SIZE = 32; // register width in bits
// RF_AXI_STATUS_REG Register (from x440_rfdc_regs.v)
localparam RF_AXI_STATUS_REG = 'h13000; // Register Offset
localparam RF_AXI_STATUS_REG_SIZE = 32; // register width in bits
// FABRIC_DSP_REG Register (from x440_rfdc_regs.v)
localparam FABRIC_DSP_REG = 'h13008; // Register Offset
localparam FABRIC_DSP_REG_SIZE = 32; // register width in bits
// CALIBRATION_DATA Register (from x440_rfdc_regs.v)
localparam CALIBRATION_DATA = 'h14000; // Register Offset
localparam CALIBRATION_DATA_SIZE = 32; // register width in bits
localparam CALIBRATION_DATA_MASK = 32'hFFFFFFFF;
localparam I_DATA_SIZE = 16; //CALIBRATION_DATA:I_DATA
localparam I_DATA_MSB = 15; //CALIBRATION_DATA:I_DATA
localparam I_DATA = 0; //CALIBRATION_DATA:I_DATA
localparam Q_DATA_SIZE = 16; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA_MSB = 31; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA = 16; //CALIBRATION_DATA:Q_DATA
// CALIBRATION_ENABLE Register (from x440_rfdc_regs.v)
localparam CALIBRATION_ENABLE = 'h14008; // Register Offset
localparam CALIBRATION_ENABLE_SIZE = 32; // register width in bits
localparam CALIBRATION_ENABLE_MASK = 32'hFF;
localparam ENABLE_CALIBRATION_DATA_0_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0_MSB = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0 = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_1_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1_MSB = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1 = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_2_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2_MSB = 2; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2 = 2; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_3_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3_MSB = 3; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3 = 3; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_4_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4
localparam ENABLE_CALIBRATION_DATA_4_MSB = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4
localparam ENABLE_CALIBRATION_DATA_4 = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4
localparam ENABLE_CALIBRATION_DATA_5_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5
localparam ENABLE_CALIBRATION_DATA_5_MSB = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5
localparam ENABLE_CALIBRATION_DATA_5 = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5
localparam ENABLE_CALIBRATION_DATA_6_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6
localparam ENABLE_CALIBRATION_DATA_6_MSB = 6; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6
localparam ENABLE_CALIBRATION_DATA_6 = 6; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6
localparam ENABLE_CALIBRATION_DATA_7_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7
localparam ENABLE_CALIBRATION_DATA_7_MSB = 7; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7
localparam ENABLE_CALIBRATION_DATA_7 = 7; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7
// THRESHOLD_STATUS Register (from x440_rfdc_regs.v)
localparam THRESHOLD_STATUS = 'h15000; // Register Offset
localparam THRESHOLD_STATUS_SIZE = 32; // register width in bits
localparam THRESHOLD_STATUS_MASK = 32'hFFFF;
localparam ADC0_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1_MSB = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1 = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2_MSB = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2 = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1_MSB = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1 = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2_MSB = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2 = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC1_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1
localparam ADC1_01_THRESHOLD1_MSB = 4; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1
localparam ADC1_01_THRESHOLD1 = 4; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1
localparam ADC1_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2
localparam ADC1_01_THRESHOLD2_MSB = 5; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2
localparam ADC1_01_THRESHOLD2 = 5; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2
localparam ADC1_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1
localparam ADC1_23_THRESHOLD1_MSB = 6; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1
localparam ADC1_23_THRESHOLD1 = 6; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1
localparam ADC1_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2
localparam ADC1_23_THRESHOLD2_MSB = 7; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2
localparam ADC1_23_THRESHOLD2 = 7; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2
localparam ADC2_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1_MSB = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1 = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2_MSB = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2 = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1_MSB = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1 = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2_MSB = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2 = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC3_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1
localparam ADC3_01_THRESHOLD1_MSB = 12; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1
localparam ADC3_01_THRESHOLD1 = 12; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1
localparam ADC3_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2
localparam ADC3_01_THRESHOLD2_MSB = 13; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2
localparam ADC3_01_THRESHOLD2 = 13; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2
localparam ADC3_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1
localparam ADC3_23_THRESHOLD1_MSB = 14; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1
localparam ADC3_23_THRESHOLD1 = 14; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1
localparam ADC3_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2
localparam ADC3_23_THRESHOLD2_MSB = 15; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2
localparam ADC3_23_THRESHOLD2 = 15; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2
// RF_PLL_CONTROL_REG Register (from x440_rfdc_regs.v)
localparam RF_PLL_CONTROL_REG = 'h16000; // Register Offset
localparam RF_PLL_CONTROL_REG_SIZE = 32; // register width in bits
localparam RF_PLL_CONTROL_REG_MASK = 32'h1111100;
localparam ENABLE_RF0_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK
localparam ENABLE_RF0_CLK_MSB = 8; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK
localparam ENABLE_RF0_CLK = 8; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK
localparam ENABLE_RF0_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X
localparam ENABLE_RF0_CLK_2X_MSB = 12; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X
localparam ENABLE_RF0_CLK_2X = 12; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X
localparam CLEAR_DATA_CLK_UNLOCKED_SIZE = 1; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED_MSB = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam ENABLE_RF1_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK
localparam ENABLE_RF1_CLK_MSB = 20; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK
localparam ENABLE_RF1_CLK = 20; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK
localparam ENABLE_RF1_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X
localparam ENABLE_RF1_CLK_2X_MSB = 24; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X
localparam ENABLE_RF1_CLK_2X = 24; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X
// RF_PLL_STATUS_REG Register (from x440_rfdc_regs.v)
localparam RF_PLL_STATUS_REG = 'h16008; // Register Offset
localparam RF_PLL_STATUS_REG_SIZE = 32; // register width in bits
localparam RF_PLL_STATUS_REG_MASK = 32'h110000;
localparam DATA_CLK_PLL_UNLOCKED_STICKY_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY_MSB = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_LOCKED_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED_MSB = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
// ADC_TILEMAP_REG Register (from x440_rfdc_regs.v)
localparam ADC_TILEMAP_REG = 'h17000; // Register Offset
localparam ADC_TILEMAP_REG_SIZE = 32; // register width in bits
// DAC_TILEMAP_REG Register (from x440_rfdc_regs.v)
localparam DAC_TILEMAP_REG = 'h17008; // Register Offset
localparam DAC_TILEMAP_REG_SIZE = 32; // register width in bits
// RFDC_INFO_REG Register (from x440_rfdc_regs.v)
localparam RFDC_INFO_REG = 'h18000; // Register Offset
localparam RFDC_INFO_REG_SIZE = 32; // register width in bits
top/x400/regmap/versioning_regs_regmap_utils.vh → top/x400/regmap/x440/versioning_regs_regmap_utils.vh
+15 -25
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@@ -1,5 +1,5 @@
//
// Copyright 2022 Ettus Research, A National Instruments Company
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -75,37 +75,27 @@
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
localparam DB_GPIO_IFC_CURRENT_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MAJOR
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME = 'h20110616; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME
localparam DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME = 'h22070116; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME
// Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_CURRENT_VERSION_MINOR = 'hA; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22121609; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_100M_VERSION
localparam RF_CORE_100M_VERSION_SIZE = 7;
localparam RF_CORE_100M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MINOR
localparam RF_CORE_100M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_BUILD
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD
localparam RF_CORE_100M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MAJOR
localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam RF_CORE_100M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_100M_VERSION:RF_CORE_100M_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_400M_VERSION
localparam RF_CORE_400M_VERSION_SIZE = 7;
localparam RF_CORE_400M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MINOR
localparam RF_CORE_400M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_BUILD
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD
localparam RF_CORE_400M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MAJOR
localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam RF_CORE_400M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_400M_VERSION:RF_CORE_400M_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_FULL_VERSION
localparam RF_CORE_FULL_VERSION_SIZE = 7;
localparam RF_CORE_FULL_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MINOR
localparam RF_CORE_FULL_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_BUILD
localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR
localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD
localparam RF_CORE_FULL_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MAJOR
localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME = 'h22062900; // RF_CORE_FULL_VERSION:RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME
//===============================================================================
// Register Group VERSIONING_REGS
top/x400/regmap/x440/x440_rfdc_mapping.v
+39
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@@ -0,0 +1,39 @@
//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x440_rfdc_mapping
// Description:
// Auxiliary register map to provide a single source for RFDC mapping information
//XmlParse xml_on
//
//<regmap name="RFDC_MAPPING_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="CHANNEL_SWAPPING">
//
// <enumeratedtype name="RFDC_ADC_MAPPING" showhex="true">
// <value name="CH0_RX_MAPPING" integer="3"> Located in Tile 225, Channel 1 </value>
// <value name="CH1_RX_MAPPING" integer="1"> Located in Tile 224, Channel 1 </value>
// <value name="CH2_RX_MAPPING" integer="0"> Located in Tile 224, Channel 0 </value>
// <value name="CH3_RX_MAPPING" integer="2"> Located in Tile 225, Channel 0 </value>
// <value name="CH4_RX_MAPPING" integer="7"> Located in Tile 227, Channel 1 </value>
// <value name="CH5_RX_MAPPING" integer="5"> Located in Tile 226, Channel 1 </value>
// <value name="CH6_RX_MAPPING" integer="4"> Located in Tile 226, Channel 0 </value>
// <value name="CH7_RX_MAPPING" integer="6"> Located in Tile 227, Channel 0 </value>
// </enumeratedtype>
//
// <enumeratedtype name="RFDC_DAC_MAPPING" showhex="true">
// <value name="CH0_TX_MAPPING" integer="0"> Located in Tile 228, Channel 0 </value>
// <value name="CH1_TX_MAPPING" integer="2"> Located in Tile 228, Channel 2 </value>
// <value name="CH2_TX_MAPPING" integer="3"> Located in Tile 228, Channel 3 </value>
// <value name="CH3_TX_MAPPING" integer="1"> Located in Tile 228, Channel 1 </value>
// <value name="CH4_TX_MAPPING" integer="4"> Located in Tile 229, Channel 0 </value>
// <value name="CH5_TX_MAPPING" integer="6"> Located in Tile 229, Channel 2 </value>
// <value name="CH6_TX_MAPPING" integer="7"> Located in Tile 229, Channel 3 </value>
// <value name="CH7_TX_MAPPING" integer="5"> Located in Tile 229, Channel 1 </value>
// </enumeratedtype>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/rf/common/Makefile.srcs
+1
View File
@@ -6,6 +6,7 @@
RF_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/common/, \
PkgRf.vhd \
adc_iq_repacker.v \
axis_mux.vhd \
capture_sysref.v \
gpio_to_axis_mux.vhd \
top/x400/rf/common/adc_iq_repacker.v
+115
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@@ -0,0 +1,115 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: adc_iq_repacker
//
// Description:
//
// This component repacks IQ from independent vectors into a single
// output signal, and implements data swapping when requested.
//
// The parameters for this component describe the expected amount of
// data to be received as well as the data to be generated.
//
// - SPC = Samples per cycle: amount of samples to be expected
// on each I and Q input vector on each "clk" cycle.
// - SAMPLE_WIDTH = Amount of bits composing each sample
//
// This modules incurs in two clk cycles of delay on the data and valid
// signals from input to output.
//
// Example case : SPC = 2, SAMPLE_WIDTH = 16
//
// adc_x_in size(for I and Q) = 2 x 16 = 32
// adc_out size = 2 x 2 x 16 = 64
//
// _______ _______ _______ ______
// clk _| |_______| |_______| |_______|
// _ _______________ _______________ _______________ ______
// adc_i_in _X_____I1,I0_____X_____I3,I2_____X____32{'X'}____X______
// _ _______________ _______________ _______________ ______
// adc_q_in _X_____Q1,Q0_____X_____Q3,Q2_____X____32{'X'}____X______
// _______________________________
// valid_in _| |______________________
// _ _______________ _______________ _______________ ______
// adc_out _X____64{'X'}____X____64{'X'}____X__Q1,I1,Q0,I0__X__Q3,..
// ______________________
// valid_out _________________________________|
//
// When the swap input is high, the order in which Q and I samples
// appear on the output vector is inverted
//
// _______ _______ _______ ______
// clk _| |_______| |_______| |_______|
// _ _______________ _______________ _______________ ______
// adc_i_in _X_____I1,I0_____X_____I3,I2_____X____32{'X'}____X______
// _ _______________ _______________ _______________ ______
// adc_q_in _X_____Q1,Q0_____X_____Q3,Q2_____X____32{'X'}____X______
// _______________________________
// valid_in _| |______________________
// _ _______________ _______________ _______________ ______
// adc_out _X____64{'X'}____X____64{'X'}____X__I1,Q1,I0,Q0__X__I3,..
// ______________________
// valid_out _________________________________|
//
// Parameters:
// SPC = Samples per cycle
// SAMPLE_WIDTH = width of i/q sample inputs. Output will be 2*SAMPLE_WIDTH
//
module adc_iq_repacker #(
parameter SPC = 1,
parameter SAMPLE_WIDTH = 16
)
(
input wire clk,
// Data in
input wire [SPC*SAMPLE_WIDTH-1:0] adc_q_in,
input wire [SPC*SAMPLE_WIDTH-1:0] adc_i_in,
input wire valid_in,
// This signal is currently driven in a related clock, and even though it runs at half the rate is should be fine
// to handle it in this clock domain(in nature it will also stay high one asserted until the next reset.)
input wire enable,
// Data is packed [Q,I] (I in LSBs) when swap_iq is '0', and [I,Q] otherwise
input wire swap_iq,
// Data out
output reg [SPC*SAMPLE_WIDTH*2-1:0] data_out_tdata,
output reg data_out_tvalid
);
localparam IQ_WIDTH = SAMPLE_WIDTH*2;
reg valid = 1'b0, valid_dly = 1'b0;
reg [SPC*SAMPLE_WIDTH-1:0] adc_q_data_in = {SPC*SAMPLE_WIDTH{1'b0}};
reg [SPC*SAMPLE_WIDTH-1:0] adc_i_data_in = {SPC*SAMPLE_WIDTH{1'b0}};
integer sample_num;
// It is safe to not reset this domain because all of the input signals will be cleared
// by a synchronous reset. Safe default values are assigned to all these registers.
always @(posedge clk) begin
adc_q_data_in <= adc_q_in;
adc_i_data_in <= adc_i_in;
// Place Q in the MSBs, I in the LSBs by default, unless swapped = 1.
for (sample_num=0; sample_num < (SPC); sample_num = sample_num + 1)
begin : data_out_gen
if (swap_iq) begin
data_out_tdata[sample_num*(IQ_WIDTH) +: IQ_WIDTH] <=
{adc_i_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH],
adc_q_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH]};
end else begin
data_out_tdata[sample_num*(IQ_WIDTH) +: IQ_WIDTH] <=
{adc_q_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH],
adc_i_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH]};
end
end
// Valid is simply a transferred version of the 1x clock's valid. Delay it one
// more cycle to align outputs.
valid <= valid_in && enable;
data_out_tvalid <= valid;
end
endmodule
top/x400/rf/full/Makefile.srcs
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#
# Copyright 2023 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
RF_FULL_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/full/, \
rf_core_full.v \
))
top/x400/rf/full/rf_core_full.v
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//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rf_core_full
//
// Description:
//
// Top-level wrapper for the ADC/DAC processing logic. One of these wrappers
// exists for every supported Data Rate. An instance of this core should
// exist per dboard.
//
// Data/RF Specs:
// DBs: 1
// RX/DB: 4
// TX/DB: 4
// Data Rate: rfdc_clk @ 8 SPC
//
// Input Clocks, all aligned to one another and coming from same MMCM
// rfdc_clk: 15.625 to 250 MHz
// rfdc_clk_2x: 2 * rfdc_clk
//
`default_nettype none
module rf_core_full # (
parameter NUM_ADC_CHANNELS = 4,
parameter NUM_DAC_CHANNELS = 4
) (
//---------------------------------------------------------------------------
// Clocking
//---------------------------------------------------------------------------
// Main Clock Inputs
input wire rfdc_clk,
input wire rfdc_clk_2x,
// AXI4-Lite Config Clock
// This clock is used to synchronize status bits for the RFDC
// registers in the AXI-S clock domain.
input wire s_axi_config_clk,
//---------------------------------------------------------------------------
// RFDC Data Interfaces
//---------------------------------------------------------------------------
// All ports here are in the rfdc_clk domain.
// ADC
input wire [127:0] adc_data_in_i_tdata_0,
output wire adc_data_in_i_tready_0,
input wire adc_data_in_i_tvalid_0,
input wire [127:0] adc_data_in_q_tdata_0,
output wire adc_data_in_q_tready_0,
input wire adc_data_in_q_tvalid_0,
input wire [127:0] adc_data_in_i_tdata_1,
output wire adc_data_in_i_tready_1,
input wire adc_data_in_i_tvalid_1,
input wire [127:0] adc_data_in_q_tdata_1,
output wire adc_data_in_q_tready_1,
input wire adc_data_in_q_tvalid_1,
input wire [127:0] adc_data_in_i_tdata_2,
output wire adc_data_in_i_tready_2,
input wire adc_data_in_i_tvalid_2,
input wire [127:0] adc_data_in_q_tdata_2,
output wire adc_data_in_q_tready_2,
input wire adc_data_in_q_tvalid_2,
input wire [127:0] adc_data_in_i_tdata_3,
output wire adc_data_in_i_tready_3,
input wire adc_data_in_i_tvalid_3,
input wire [127:0] adc_data_in_q_tdata_3,
output wire adc_data_in_q_tready_3,
input wire adc_data_in_q_tvalid_3,
// DAC
output wire [255:0] dac_data_out_tdata_0,
input wire dac_data_out_tready_0,
output wire dac_data_out_tvalid_0,
output wire [255:0] dac_data_out_tdata_1,
input wire dac_data_out_tready_1,
output wire dac_data_out_tvalid_1,
output wire [255:0] dac_data_out_tdata_2,
input wire dac_data_out_tready_2,
output wire dac_data_out_tvalid_2,
output wire [255:0] dac_data_out_tdata_3,
input wire dac_data_out_tready_3,
output wire dac_data_out_tvalid_3,
//---------------------------------------------------------------------------
// User Data Interfaces
//---------------------------------------------------------------------------
// All ports here are in the rfdc_clk domain on the X440.
// ADC
output wire [255:0] adc_data_out_tdata_0, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
output wire adc_data_out_tvalid_0,
output wire [255:0] adc_data_out_tdata_1, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
output wire adc_data_out_tvalid_1,
output wire [255:0] adc_data_out_tdata_2, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
output wire adc_data_out_tvalid_2,
output wire [255:0] adc_data_out_tdata_3, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
output wire adc_data_out_tvalid_3,
// DAC
input wire [255:0] dac_data_in_tdata_0, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
output wire dac_data_in_tready_0,
input wire dac_data_in_tvalid_0,
input wire [255:0] dac_data_in_tdata_1, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
output wire dac_data_in_tready_1,
input wire dac_data_in_tvalid_1,
input wire [255:0] dac_data_in_tdata_2, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
output wire dac_data_in_tready_2,
input wire dac_data_in_tvalid_2,
input wire [255:0] dac_data_in_tdata_3, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
output wire dac_data_in_tready_3,
input wire dac_data_in_tvalid_3,
//---------------------------------------------------------------------------
// Miscellaneous
//---------------------------------------------------------------------------
// Invert I/Q control signals from RFDC to DSP chain.
input wire [3:0] invert_adc_iq_rclk2,
input wire [3:0] invert_dac_iq_rclk2,
// Control/status vectors from/to RFDC.
// Notice these are all in the s_axi_config_clk domain.
output wire [9:0] dsp_info_sclk,
output wire [15:0] axi_status_sclk,
output wire [15:0] rfdc_info_sclk,
// Resets.
input wire adc_enable_data_rclk,
input wire adc_rfdc_axi_resetn_rclk,
// Version (Constant)
output wire [95:0] version_info
);
`include "../../regmap/x440/rfdc_regs_regmap_utils.vh"
`include "../../regmap/x440/versioning_regs_regmap_utils.vh"
`include "../../regmap/versioning_utils.vh"
// ADC data interface from RFDC.
wire [127:0] adc_data_in_i_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (I)
wire [127:0] adc_data_in_q_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (Q)
wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tready;
wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tready;
wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tvalid;
wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tvalid;
// DAC data interface to RFDC.
wire [255:0] dac_data_out_tdata [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q)
wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tready;
wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tvalid;
// ADC data interface to user.
wire [255:0] adc_data_out_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (I + Q)
wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tready;
wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tvalid;
// DAC data interface from user.
wire [255:0] dac_data_in_tdata_preswap [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q)
wire [255:0] dac_data_in_tdata [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q)
wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tready;
wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tvalid;
wire [15:0] axi_status;
//---------------------------------------------------------------------------
// Resets, Debug and Misc.
//---------------------------------------------------------------------------
// Group all these status bits together. They don't toggle frequently so data
// coherency is not an issue here.
// Using constants for DB0 since the bits are the 16 LSBs in a 32-bit vector.
// DB1 simply uses the 16 MSBs when wiring the status vector.
assign axi_status[USER_ADC_TREADY_MSB :USER_ADC_TREADY ] = adc_data_out_tready[1:0];
assign axi_status[USER_ADC_TVALID_MSB :USER_ADC_TVALID ] = adc_data_out_tvalid[1:0];
assign axi_status[RFDC_ADC_I_TVALID_MSB:RFDC_ADC_I_TVALID] = adc_data_in_i_tvalid[1:0];
assign axi_status[RFDC_ADC_Q_TVALID_MSB:RFDC_ADC_Q_TVALID] = adc_data_in_q_tvalid[1:0];
assign axi_status[RFDC_ADC_I_TREADY_MSB:RFDC_ADC_I_TREADY] = adc_data_in_i_tready[1:0];
assign axi_status[RFDC_ADC_Q_TREADY_MSB:RFDC_ADC_Q_TREADY] = adc_data_in_q_tready[1:0];
assign axi_status[RFDC_DAC_TVALID_MSB :RFDC_DAC_TVALID ] = dac_data_out_tvalid[1:0];
assign axi_status[RFDC_DAC_TREADY_MSB :RFDC_DAC_TREADY ] = dac_data_out_tready[1:0];
synchronizer #(
.WIDTH (16),
.STAGES (2),
.INITIAL_VAL (0),
.FALSE_PATH_TO_IN (1)
) synchronizer_axis_status (
.clk (s_axi_config_clk),
.rst (1'b0),
.in (axi_status),
.out (axi_status_sclk)
);
// Drive the DSP info vector with information on this specific DSP chain.
assign dsp_info_sclk[FABRIC_DSP_RX_CNT_MSB:FABRIC_DSP_RX_CNT] = NUM_ADC_CHANNELS;
assign dsp_info_sclk[FABRIC_DSP_TX_CNT_MSB:FABRIC_DSP_TX_CNT] = NUM_DAC_CHANNELS;
// This RF core always consumes 8 SPC from the gearbox per I/Q signal
assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8);
assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16);
// This RF core module contains no additional resampling
assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd1;
//---------------------------------------------------------------------------
// ADC Post-Processing
//---------------------------------------------------------------------------
// Data comes from the RFDC as 8 SPC, separate streams for each channel and
// I/Q.
assign adc_data_in_i_tdata[0] = adc_data_in_i_tdata_0;
assign adc_data_in_q_tdata[0] = adc_data_in_q_tdata_0;
assign adc_data_in_i_tdata[1] = adc_data_in_i_tdata_1;
assign adc_data_in_q_tdata[1] = adc_data_in_q_tdata_1;
assign adc_data_in_i_tdata[2] = adc_data_in_i_tdata_2;
assign adc_data_in_q_tdata[2] = adc_data_in_q_tdata_2;
assign adc_data_in_i_tdata[3] = adc_data_in_i_tdata_3;
assign adc_data_in_q_tdata[3] = adc_data_in_q_tdata_3;
assign adc_data_in_i_tready_0 = adc_data_in_i_tready[0];
assign adc_data_in_i_tvalid[0] = adc_data_in_i_tvalid_0;
assign adc_data_in_q_tready_0 = adc_data_in_q_tready[0];
assign adc_data_in_q_tvalid[0] = adc_data_in_q_tvalid_0;
assign adc_data_in_i_tready_1 = adc_data_in_i_tready[1];
assign adc_data_in_i_tvalid[1] = adc_data_in_i_tvalid_1;
assign adc_data_in_q_tready_1 = adc_data_in_q_tready[1];
assign adc_data_in_q_tvalid[1] = adc_data_in_q_tvalid_1;
assign adc_data_in_i_tready_2 = adc_data_in_i_tready[2];
assign adc_data_in_i_tvalid[2] = adc_data_in_i_tvalid_2;
assign adc_data_in_q_tready_2 = adc_data_in_q_tready[2];
assign adc_data_in_q_tvalid[2] = adc_data_in_q_tvalid_2;
assign adc_data_in_i_tready_3 = adc_data_in_i_tready[3];
assign adc_data_in_i_tvalid[3] = adc_data_in_i_tvalid_3;
assign adc_data_in_q_tready_3 = adc_data_in_q_tready[3];
assign adc_data_in_q_tvalid[3] = adc_data_in_q_tvalid_3;
// ADC Data from the RFDC arrives here as 8 SPC with separate I and Q
// streams. It leaves the adc_full_rate_bd as 8 SPC with I and Q packed into
// a single 256 bit word.
genvar adc_num;
generate
for (adc_num=0; adc_num < (NUM_ADC_CHANNELS); adc_num = adc_num + 1)
begin : adc_gen
adc_full_bd adc_full_bd_gen (
.enable_data_to_repacker_rclk (adc_enable_data_rclk),
.rfdc_adc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk),
.rfdc_clk (rfdc_clk),
.swap_iq_rclk (invert_adc_iq_rclk2 [adc_num]),
.adc_q_data_in_tvalid (adc_data_in_q_tvalid[adc_num]),
.adc_q_data_in_tready (adc_data_in_q_tready[adc_num]),
.adc_q_data_in_tdata (adc_data_in_q_tdata [adc_num]),
.adc_i_data_in_tvalid (adc_data_in_i_tvalid[adc_num]),
.adc_i_data_in_tready (adc_data_in_i_tready[adc_num]),
.adc_i_data_in_tdata (adc_data_in_i_tdata [adc_num]),
.adc_data_out_tvalid (adc_data_out_tvalid [adc_num]),
.adc_data_out_tdata (adc_data_out_tdata [adc_num])
);
end
endgenerate
// Data is released to the user as 8 SPC, separate streams for each channel.
assign adc_data_out_tdata_0 = adc_data_out_tdata[0];
assign adc_data_out_tdata_1 = adc_data_out_tdata[1];
assign adc_data_out_tdata_2 = adc_data_out_tdata[2];
assign adc_data_out_tdata_3 = adc_data_out_tdata[3];
// There is no tready going to the ADC (one has to be always ready for ADC
// data), but it is still a component of the axi_status vector as a generic
// AXI stream status. Report 1'b1 to the status vector consistent with being
// always ready
assign adc_data_out_tready[0] = 1'b1;
assign adc_data_out_tvalid_0 = adc_data_out_tvalid[0];
assign adc_data_out_tready[1] = 1'b1;
assign adc_data_out_tvalid_1 = adc_data_out_tvalid[1];
assign adc_data_out_tready[2] = 1'b1;
assign adc_data_out_tvalid_2 = adc_data_out_tvalid[2];
assign adc_data_out_tready[3] = 1'b1;
assign adc_data_out_tvalid_3 = adc_data_out_tvalid[3];
//---------------------------------------------------------------------------
// DAC Pre-Processing
//---------------------------------------------------------------------------
// Data comes from the user as 8 SPC, separate streams for each channel.
assign dac_data_in_tdata_preswap[0] = dac_data_in_tdata_0;
assign dac_data_in_tdata_preswap[1] = dac_data_in_tdata_1;
assign dac_data_in_tdata_preswap[2] = dac_data_in_tdata_2;
assign dac_data_in_tdata_preswap[3] = dac_data_in_tdata_3;
assign dac_data_in_tready_0 = dac_data_in_tready[0];
assign dac_data_in_tvalid[0] = dac_data_in_tvalid_0;
assign dac_data_in_tready_1 = dac_data_in_tready[1];
assign dac_data_in_tvalid[1] = dac_data_in_tvalid_1;
assign dac_data_in_tready_2 = dac_data_in_tready[2];
assign dac_data_in_tvalid[2] = dac_data_in_tvalid_2;
assign dac_data_in_tready_3 = dac_data_in_tready[3];
assign dac_data_in_tvalid[3] = dac_data_in_tvalid_3;
genvar dac_num;
generate
for (dac_num=0; dac_num < (NUM_DAC_CHANNELS); dac_num = dac_num + 1)
begin : dac_swap_gen
//IO and Q0 swap
assign dac_data_in_tdata[dac_num][15:00] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][31:16]) : (dac_data_in_tdata_preswap[dac_num][15:0]);
assign dac_data_in_tdata[dac_num][31:16] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][15:00]) : (dac_data_in_tdata_preswap[dac_num][31:16]);
//I1 and Q1 swap
assign dac_data_in_tdata[dac_num][47:32] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][63:48]) : (dac_data_in_tdata_preswap[dac_num][47:32]);
assign dac_data_in_tdata[dac_num][63:48] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][47:32]) : (dac_data_in_tdata_preswap[dac_num][63:48]);
//I2 and Q2 swap
assign dac_data_in_tdata[dac_num][79:64] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][95:80]) : (dac_data_in_tdata_preswap[dac_num][79:64]);
assign dac_data_in_tdata[dac_num][95:80] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][79:64]) : (dac_data_in_tdata_preswap[dac_num][95:80]);
//I3 and Q3 swap
assign dac_data_in_tdata[dac_num][111:96] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][127:112]) : (dac_data_in_tdata_preswap[dac_num][111:96]);
assign dac_data_in_tdata[dac_num][127:112] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][111:96]) : (dac_data_in_tdata_preswap[dac_num][127:112]);
//I4 and Q4 swap
assign dac_data_in_tdata[dac_num][143:128] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][159:144]) : (dac_data_in_tdata_preswap[dac_num][143:128]);
assign dac_data_in_tdata[dac_num][159:144] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][143:128]) : (dac_data_in_tdata_preswap[dac_num][159:144]);
//I5 and Q5 swap
assign dac_data_in_tdata[dac_num][175:160] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][191:176]) : (dac_data_in_tdata_preswap[dac_num][175:160]);
assign dac_data_in_tdata[dac_num][191:176] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][175:160]) : (dac_data_in_tdata_preswap[dac_num][191:176]);
//I6 and Q6 swap
assign dac_data_in_tdata[dac_num][207:192] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][223:208]) : (dac_data_in_tdata_preswap[dac_num][207:192]);
assign dac_data_in_tdata[dac_num][223:208] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][207:192]) : (dac_data_in_tdata_preswap[dac_num][223:208]);
//I7 and Q7 swap
assign dac_data_in_tdata[dac_num][239:224] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][255:240]) : (dac_data_in_tdata_preswap[dac_num][239:224]);
assign dac_data_in_tdata[dac_num][255:240] = invert_dac_iq_rclk2[dac_num] ?
(dac_data_in_tdata_preswap[dac_num][239:224]) : (dac_data_in_tdata_preswap[dac_num][255:240]);
end
endgenerate
// These streams are then connected to data out, no need for a bd, and form a single
// stream per channel, 8 SPC, packed: MSB [Sample7Q, Sample7I, ... ,
// Sample0Q, Sample0I] LSB.
generate
for (dac_num=0; dac_num < (NUM_DAC_CHANNELS); dac_num = dac_num + 1)
begin : dac_gen
assign dac_data_out_tdata[dac_num] = dac_data_in_tdata[dac_num];
assign dac_data_out_tvalid[dac_num] = dac_data_in_tvalid[dac_num];
assign dac_data_in_tready[dac_num] = dac_data_out_tready[dac_num];
end
endgenerate
// Data is released to the RFDC as 8 SPC, separate streams per channel (I/Q
// together).
assign dac_data_out_tdata_0 = dac_data_out_tdata[0];
assign dac_data_out_tdata_1 = dac_data_out_tdata[1];
assign dac_data_out_tdata_2 = dac_data_out_tdata[2];
assign dac_data_out_tdata_3 = dac_data_out_tdata[3];
assign dac_data_out_tready[0] = dac_data_out_tready_0;
assign dac_data_out_tvalid_0 = dac_data_out_tvalid[0];
assign dac_data_out_tready[1] = dac_data_out_tready_1;
assign dac_data_out_tvalid_1 = dac_data_out_tvalid[1];
assign dac_data_out_tready[2] = dac_data_out_tready_2;
assign dac_data_out_tvalid_2 = dac_data_out_tvalid[2];
assign dac_data_out_tready[3] = dac_data_out_tready_3;
assign dac_data_out_tvalid_3 = dac_data_out_tvalid[3];
//---------------------------------------------------------------------------
// Version
//---------------------------------------------------------------------------
// Version metadata, constants come from auto-generated
// versioning_regs_regmap_utils.vh
assign version_info = build_component_versions(
RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME,
build_version(
RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR,
RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR,
RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD
),
build_version(
RF_CORE_FULL_CURRENT_VERSION_MAJOR,
RF_CORE_FULL_CURRENT_VERSION_MINOR,
RF_CORE_FULL_CURRENT_VERSION_BUILD
)
);
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="VERSIONING_REGS_REGMAP">
// <group name="VERSIONING_CONSTANTS">
// <enumeratedtype name="RF_CORE_FULL_VERSION" showhex="true">
// <info>
// Full BW RF core.{BR/}
// For guidance on when to update these revision numbers,
// please refer to the register map documentation accordingly:
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
// </info>
// <value name="RF_CORE_FULL_CURRENT_VERSION_MAJOR" integer="1"/>
// <value name="RF_CORE_FULL_CURRENT_VERSION_MINOR" integer="0"/>
// <value name="RF_CORE_FULL_CURRENT_VERSION_BUILD" integer="0"/>
// <value name="RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
// <value name="RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
// <value name="RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
// <value name="RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME" integer="0x22062900"/>
// </enumeratedtype>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/rf/sim/Makefile
+1
View File
@@ -80,6 +80,7 @@ $(abspath tb_ddc_400m_saturate.vhd ) \
$(abspath tb_duc_400m_saturate.vhd ) \
$(abspath tb_rf_nco_reset.vhd ) \
$(abspath tb_x410_rf_reset_controller.vhd ) \
$(abspath tb_adc_iq_repacker.sv ) \
$(abspath rf_all_tb.sv ) \
#-------------------------------------------------
top/x400/rf/sim/rf_all_tb.sv
+3 -1
View File
@@ -26,6 +26,7 @@ module rf_all_tb;
tb_duc_400m_saturate tb_duc_400m_saturate_i ();
tb_rf_nco_reset tb_rf_nco_reset_i ();
tb_x410_rf_reset_controller tb_x410_rf_reset_controller_i ();
tb_adc_iq_repacker tb_adc_iq_repacker_i ();
initial begin
test.start_tb("rf_all_tb", 1ms);
@@ -44,7 +45,8 @@ module rf_all_tb;
tb_ddc_400m_saturate_i.StopSim &&
tb_duc_400m_saturate_i.StopSim &&
tb_rf_nco_reset_i.StopSim &&
tb_x410_rf_reset_controller_i.StopSim
tb_x410_rf_reset_controller_i.StopSim &&
tb_adc_iq_repacker_i.StopSim
) break;
end
test.end_test();
top/x400/rf/sim/tb_adc_iq_repacker.sv
+109
View File
@@ -0,0 +1,109 @@
//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: tb_adc_iq_repacker
//
// Description:
//
// This testbench mainly tests tb_adc_iq_repacker. It runs
// 3 different tests:
// - test data propagation when not swapping data
// - test data propagation when swapping data
// - check that data valid does not propagate when block
// is not enabled.
//
`timescale 1ns/1ps
`define NS_PER_TICK 1
`define NUM_TEST_CASES 3
`include "sim_clks_rsts.vh"
`include "sim_exec_report.vh"
module tb_adc_iq_repacker();
import PkgRandom::*;
`TEST_BENCH_INIT("tb_adc_iq_repacker", `NUM_TEST_CASES, `NS_PER_TICK);
//sets up clock
localparam CLK_PERIOD = $ceil(1e9/100.0e6);
`DEFINE_CLK(clk, CLK_PERIOD, 50);
//declare parameters
localparam SPC = 1;
localparam SAMPLE_WIDTH = 16;
//declare wires and regs
reg enable;
reg valid_in;
reg swap_iq;
reg [SPC*SAMPLE_WIDTH-1:0] adc_q_in;
reg [SPC*SAMPLE_WIDTH-1:0] adc_i_in;
reg StopSim;
wire [SPC*SAMPLE_WIDTH*2-1:0] data_out_tdata;
wire data_out_tvalid;
PkgRandom::Rand #(SPC*SAMPLE_WIDTH) rand_i;
PkgRandom::Rand #(SPC*SAMPLE_WIDTH) rand_q;
// instance adc_iq_repacker
adc_iq_repacker #(
.SPC(SPC),
.SAMPLE_WIDTH(SAMPLE_WIDTH)
) adc_iq_repacker_inst (
.clk(clk),
// Data in
.adc_q_in(adc_q_in),
.adc_i_in(adc_i_in),
.valid_in(valid_in),
.enable(enable),
// Data is packed [Q,I] (I in LSBs) when swap_iq is '0', and [I,Q] otherwise
.swap_iq(swap_iq),
// Data out
.data_out_tdata(data_out_tdata),
.data_out_tvalid(data_out_tvalid)
);
// initial statement with test cases
initial begin : tb_main
// test data propagation when not swapping data
`TEST_CASE_START("test data propagation, no swap, core enabled");
repeat (10) @(posedge clk);
swap_iq = 0;
enable = 1;
StopSim = 0;
valid_in = 1;
for (int i = 0; i < 10; i++) begin
adc_q_in = rand_q.rand_bit();
adc_i_in = rand_i.rand_bit();
repeat (3) @(posedge clk);
`ASSERT_ERROR(data_out_tdata[SAMPLE_WIDTH*2-1:0] == {adc_q_in[SAMPLE_WIDTH-1:0], adc_i_in[SAMPLE_WIDTH-1:0]}, "Output data is wrong");
`ASSERT_ERROR(data_out_tvalid == 1, "output valid not asserted");
end
`TEST_CASE_DONE(1);
// test data propagation when swapping data
`TEST_CASE_START("test data propagation w/ swap_iq=1");
swap_iq = 1;
for (int i = 0; i < 10; i++) begin
adc_q_in = rand_q.rand_bit();
adc_i_in = rand_i.rand_bit();
repeat (3) @(posedge clk);
`ASSERT_ERROR(data_out_tdata[SAMPLE_WIDTH*2-1:0] == {adc_i_in[SAMPLE_WIDTH-1:0], adc_q_in[SAMPLE_WIDTH-1:0]}, "Output data is wrong");
`ASSERT_ERROR(data_out_tvalid == 1, "output valid not asserted");
end
`TEST_CASE_DONE(1);
// check that data valid does not propagate when block
// is not enabled.
`TEST_CASE_START("test data valid when enable = 0");
enable = 0;
repeat (10) @(posedge clk);
`ASSERT_ERROR(data_out_tvalid == 0, "block should be disabled");
`TEST_CASE_DONE(1);
StopSim = 1;
end
endmodule : tb_adc_iq_repacker
top/x400/rf/sim/xvhdl.pb
BIN
View File
Binary file not shown.
top/x400/rf/common/clock_gates.vhd → top/x400/rf/x440/x440_clock_gates.vhd
+47 -86
View File
@@ -1,13 +1,13 @@
--
-- Copyright 2021 Ettus Research, a National Instruments Brand
-- Copyright 2022 Ettus Research, a National Instruments Brand
--
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: clock_gates
-- Module: x440_clock_gates
--
-- Description:
--
-- Gate propagation of DataClk and RfdcClk instances until the PLL lock
-- Gate propagation of RfdcClk instances until the PLL lock
-- status signal is stable and software has acknowledged it by asserting the
-- pertinent controls.
--
@@ -16,9 +16,10 @@
-- explicitly instantiated in the Block Design. Therefore, we only generate
-- the buffer enable signals for these clocks within this component.
--
-- Since DataClk are only used in other Custom IP blocks within the Block
-- design, it is possible to instantiate the clock buffers within this block
-- for without running into IP generation failures.
-- This file heavily leverages the code from '../x410/x410_clock_gates.vhd'.
-- The main changes when comparing against that file are:
-- - One RFDC Clock pair per radio.
-- - No DataClk buffer instantiations (since DataClk is removed from BD).
--
-- Parameters:
--
@@ -36,7 +37,7 @@ library WORK;
use WORK.PkgRFDC_REGS_REGMAP.all;
entity clock_gates is
entity x440_clock_gates is
generic (
kReliableClkPeriodNs : integer := 25
);
@@ -51,18 +52,14 @@ entity clock_gates is
-- Input Clocks (from MMCM)
ReliableClk : in std_logic;
DataClk1xPll : in std_logic;
DataClk2xPll : in std_logic;
-- Buffered Clock Outputs (to design)
DataClk1x : out std_logic;
DataClk2x : out std_logic;
-- Buffers for these signals must be instantiated on Block design for clock
-- rates to be identified. The Utility Buffers instantiated on the Block
-- Design require signals to be of type std_logic_vector.
aEnableRfBufg1x : out std_logic_vector(0 downto 0);
aEnableRfBufg2x : out std_logic_vector(0 downto 0);
aEnableRf0Bufg1x : out std_logic_vector(0 downto 0);
aEnableRf0Bufg2x : out std_logic_vector(0 downto 0);
aEnableRf1Bufg1x : out std_logic_vector(0 downto 0);
aEnableRf1Bufg2x : out std_logic_vector(0 downto 0);
-- PLL Status Signals
rPllLocked : out std_logic;
@@ -75,9 +72,9 @@ entity clock_gates is
rSoftwareControl : in std_logic_vector(31 downto 0);
rSoftwareStatus : out std_logic_vector(31 downto 0)
);
end clock_gates;
end x440_clock_gates;
architecture STRUCT of clock_gates is
architecture STRUCT of x440_clock_gates is
component sync_wrapper
generic (
@@ -92,15 +89,6 @@ architecture STRUCT of clock_gates is
signal_out : out std_logic_vector((WIDTH-1) downto 0));
end component;
component BUFGCE
generic(
CE_TYPE : string);
port (
O : out std_ulogic;
CE : in std_ulogic;
I : in std_ulogic);
end component;
-- UltraScale MMCM max lock time = 100 us / 25 ns = 4,000 clk cycles. If the
-- division kPllLockTimeNs / kReliableClkPeriodNs does not evaluate to an
-- integer, Vivado could either round up or down. In case they round down, we
@@ -126,15 +114,15 @@ architecture STRUCT of clock_gates is
signal rPllUnlockedSticky : std_logic := '0';
-- Safe BUFG enable signals
signal rEnableDataClk1x,
rEnableDataClk2x,
rEnableRfdcClk1x,
rEnableRfdcClk2x : std_logic;
signal rEnableRfdc0Clk1x,
rEnableRfdc0Clk2x,
rEnableRfdc1Clk1x,
rEnableRfdc1Clk2x : std_logic;
signal rEnableDataBufg1x : std_logic := '0';
signal rEnableDataBufg2x : std_logic := '0';
signal rEnableRfdcBufg1xLcl : std_logic := '0';
signal rEnableRfdcBufg2xLcl : std_logic := '0';
signal rEnableRfdc0Bufg1xLcl : std_logic := '0';
signal rEnableRfdc0Bufg2xLcl : std_logic := '0';
signal rEnableRfdc1Bufg1xLcl : std_logic := '0';
signal rEnableRfdc1Bufg2xLcl : std_logic := '0';
-- Active high version of reset required for synchronizer blocks.
signal rPllReset : std_logic;
@@ -143,18 +131,10 @@ architecture STRUCT of clock_gates is
-- a dont_touch attribute to preserve the signals through both synthesis and
-- P&R. Implementation of "dont_touch" has been confirmed after P&R.
attribute dont_touch : string;
attribute dont_touch of rEnableDataBufg1x : signal is "TRUE";
attribute dont_touch of rEnableDataBufg2x : signal is "TRUE";
attribute dont_touch of aEnableRfBufg1x : signal is "TRUE";
attribute dont_touch of aEnableRfBufg2x : signal is "TRUE";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_INFO of DataClk1xPll : signal is
"xilinx.com:signal:clock:1.0 DataClk1xPll CLK";
attribute X_INTERFACE_INFO of DataClk2xPll : signal is
"xilinx.com:signal:clock:1.0 DataClk2xPll CLK";
attribute dont_touch of aEnableRf0Bufg1x : signal is "TRUE";
attribute dont_touch of aEnableRf0Bufg2x : signal is "TRUE";
attribute dont_touch of aEnableRf1Bufg1x : signal is "TRUE";
attribute dont_touch of aEnableRf1Bufg2x : signal is "TRUE";
begin
@@ -168,57 +148,38 @@ begin
begin
if rising_edge(ReliableClk) then
if rPllReset_n = '0' then
rEnableDataBufg1x <= '0';
rEnableDataBufg2x <= '0';
rEnableRfdcBufg1xLcl <= '0';
rEnableRfdcBufg2xLcl <= '0';
rEnableRfdc0Bufg1xLcl <= '0';
rEnableRfdc0Bufg2xLcl <= '0';
rEnableRfdc1Bufg1xLcl <= '0';
rEnableRfdc1Bufg2xLcl <= '0';
else
rEnableDataBufg1x <=
rEnableRfdc0Bufg1xLcl <=
rSafeToEnableGatedClks and
rEnableDataClk1x and
rEnableRfdc0Clk1x and
(not rPllUnlockedSticky);
rEnableDataBufg2x <=
rEnableRfdc0Bufg2xLcl <=
rSafeToEnableGatedClks and
rEnableDataClk2x and
rEnableRfdc0Clk2x and
(not rPllUnlockedSticky);
rEnableRfdcBufg1xLcl <=
rEnableRfdc1Bufg1xLcl <=
rSafeToEnableGatedClks and
rEnableRfdcClk1x and
rEnableRfdc1Clk1x and
(not rPllUnlockedSticky);
rEnableRfdcBufg2xLcl <=
rEnableRfdc1Bufg2xLcl <=
rSafeToEnableGatedClks and
rEnableRfdcClk2x and
rEnableRfdc1Clk2x and
(not rPllUnlockedSticky);
end if;
end if;
end process DataClkEnables;
aEnableRfBufg1x(0) <= rEnableRfdcBufg1xLcl;
aEnableRfBufg2x(0) <= rEnableRfdcBufg2xLcl;
DataClk1xSafeBufg: BUFGCE
generic map(
CE_TYPE => "ASYNC"
)
port map (
I => DataClk1xPll,
CE => rEnableDataBufg1x,
O => DataClk1x
);
DataClk2xSafeBufg: BUFGCE
generic map(
CE_TYPE => "ASYNC"
)
port map (
I => DataClk2xPll,
CE => rEnableDataBufg2x,
O => DataClk2x
);
aEnableRf0Bufg1x(0) <= rEnableRfdc0Bufg1xLcl;
aEnableRf0Bufg2x(0) <= rEnableRfdc0Bufg2xLcl;
aEnableRf1Bufg1x(0) <= rEnableRfdc1Bufg1xLcl;
aEnableRf1Bufg2x(0) <= rEnableRfdc1Bufg2xLcl;
-----------------------------------------------------------------------------
-- Create PLL Lock Signal
@@ -288,11 +249,11 @@ begin
rPllLocked <= rPllLockedLcl;
-- AXI transaction decoding
rClearDataClkUnlockedSticky <= rSoftwareControl(kCLEAR_DATA_CLK_UNLOCKED);
rEnableDataClk1x <= rSoftwareControl(kENABLE_DATA_CLK);
rEnableDataClk2x <= rSoftwareControl(kENABLE_DATA_CLK_2X);
rEnableRfdcClk1x <= rSoftwareControl(kENABLE_RF_CLK);
rEnableRfdcClk2x <= rSoftwareControl(kENABLE_RF_CLK_2X);
rClearDataClkUnlockedSticky <= rSoftwareControl(kCLEAR_DATA_CLK_UNLOCKED);
rEnableRfdc0Clk1x <= rSoftwareControl(kENABLE_RF0_CLK);
rEnableRfdc0Clk2x <= rSoftwareControl(kENABLE_RF0_CLK_2X);
rEnableRfdc1Clk1x <= rSoftwareControl(kENABLE_RF1_CLK);
rEnableRfdc1Clk2x <= rSoftwareControl(kENABLE_RF1_CLK_2X);
rSoftwareStatus(kDATA_CLK_PLL_LOCKED) <= rPllLockedLcl;
rSoftwareStatus(kDATA_CLK_PLL_UNLOCKED_STICKY) <= rPllUnlockedSticky;
top/x400/rf/common/rf_reset_controller.vhd → top/x400/rf/x440/x440_rf_reset_controller.vhd
+51 -70
View File
@@ -1,13 +1,18 @@
--
-- Copyright 2021 Ettus Research, a National Instruments Brand
-- Copyright 2022 Ettus Research, a National Instruments Brand
--
-- SPDX-License-Identifier: LGPL-3.0-or-later
--
-- Module: rf_reset_controller
-- Module: x440_rf_reset_controller
--
-- Description:
--
-- Control RFDC, ADC, and DAC resets.
-- This file contains a similar structure to '../x410/x410_rf_reset_controller',
-- with the main difference of not having to support a complex reset chain.
-- This means that the instantiations of 'rf_reset' can be taken out in favor
-- having a simple combination of the incoming pulses and the software triggers
-- to generate the different outputs.
--
library IEEE;
@@ -17,45 +22,38 @@ library IEEE;
library WORK;
use WORK.PkgRFDC_REGS_REGMAP.all;
entity rf_reset_controller is
entity x440_rf_reset_controller is
port(
-- Clocks
-- Config clock is async to all the others.
ConfigClk : in std_logic;
DataClk : in std_logic;
PllRefClk : in std_logic;
RfClk : in std_logic;
RfClk2x : in std_logic;
DataClk2x : in std_logic;
-- Master resets from the Radio
dAdcResetPulse : in std_logic;
dDacResetPulse : in std_logic;
rAdcResetPulse : in std_logic;
rDacResetPulse : in std_logic;
-- ADC Resets
dAdcDataOutReset_n : out std_logic;
r2AdcFirReset_n : out std_logic;
rAdcRfdcAxiReset_n : out std_logic;
r2AdcReset_n : out std_logic;
rAdcEnableData : out std_logic;
rAdcGearboxReset_n : out std_logic;
rAdcReset_n : out std_logic;
-- DAC Resets
dDacDataInReset_n : out std_logic;
r2DacFirReset_n : out std_logic;
d2DacFirReset_n : out std_logic;
rDacRfdcAxiReset_n : out std_logic;
rDacGearboxReset_n : out std_logic;
r2DacReset_n : out std_logic;
rDacReset_n : out std_logic;
-- SW Control and Status
-- Control to initiate resets to RFDC and decimation block including the
-- gearboxes. The reset status is a sticky status of both ADC and DAC.
-- Control to initiate resets to RFDC.
-- The reset status is a sticky status of both ADC and DAC.
cSoftwareControl : in std_logic_vector(31 downto 0);
cSoftwareStatus : out std_logic_vector(31 downto 0)
);
end rf_reset_controller;
end x440_rf_reset_controller;
architecture RTL of rf_reset_controller is
architecture RTL of x440_rf_reset_controller is
-- POR value for all resets are high.
signal cTriggerAdcReset : std_logic := '1';
@@ -63,10 +61,10 @@ architecture RTL of rf_reset_controller is
signal cTriggerDacReset : std_logic := '1';
signal cTriggerDacResetDlyd : std_logic := '1';
signal dTriggerAdcReset_ms : std_logic := '1';
signal dTriggerAdcReset : std_logic := '1';
signal dTriggerDacReset_ms : std_logic := '1';
signal dTriggerDacReset : std_logic := '1';
signal rTriggerAdcReset_ms : std_logic := '1';
signal rTriggerAdcReset : std_logic := '1';
signal rTriggerDacReset_ms : std_logic := '1';
signal rTriggerDacReset : std_logic := '1';
-- POR value of all reset done signals are set to low.
signal cTriggerAdcResetDone_ms : std_logic := '0';
@@ -77,12 +75,12 @@ architecture RTL of rf_reset_controller is
signal cDacResetDoneSticky : std_logic := '0';
attribute ASYNC_REG : string;
attribute ASYNC_REG of dTriggerAdcReset : signal is "TRUE";
attribute ASYNC_REG of dTriggerDacReset : signal is "TRUE";
attribute ASYNC_REG of rTriggerAdcReset : signal is "TRUE";
attribute ASYNC_REG of rTriggerDacReset : signal is "TRUE";
attribute ASYNC_REG of cTriggerAdcResetDone : signal is "TRUE";
attribute ASYNC_REG of cTriggerDacResetDone : signal is "TRUE";
attribute ASYNC_REG of dTriggerAdcReset_ms : signal is "TRUE";
attribute ASYNC_REG of dTriggerDacReset_ms : signal is "TRUE";
attribute ASYNC_REG of rTriggerAdcReset_ms : signal is "TRUE";
attribute ASYNC_REG of rTriggerDacReset_ms : signal is "TRUE";
attribute ASYNC_REG of cTriggerAdcResetDone_ms : signal is "TRUE";
attribute ASYNC_REG of cTriggerDacResetDone_ms : signal is "TRUE";
@@ -108,14 +106,14 @@ begin
-- prove all your clocks are toggling to some extent.
-----------------------------------------------------------------------------
SeqResetDataClk : process(DataClk)
SeqResetRfClk : process(RfClk)
begin
if rising_edge(DataClk) then
if rising_edge(RfClk) then
-- double-syncs have no sync reset!
dTriggerAdcReset_ms <= cTriggerAdcReset;
dTriggerAdcReset <= dTriggerAdcReset_ms;
dTriggerDacReset_ms <= cTriggerDacReset;
dTriggerDacReset <= dTriggerDacReset_ms;
rTriggerAdcReset_ms <= cTriggerAdcReset;
rTriggerAdcReset <= rTriggerAdcReset_ms;
rTriggerDacReset_ms <= cTriggerDacReset;
rTriggerDacReset <= rTriggerDacReset_ms;
end if;
end process;
@@ -123,18 +121,18 @@ begin
-- Reset Sequence Done Status
-----------------------------------------------------------------------------
-- Now back to ConfigClk! We provide the status for all software controlled
-- resets. We move the signal from ConfigClk to DataClk domain and move it
-- back to ConfigClk domain. This just proves that DataClk is toggling and
-- the reset requested by software is sampled in the DataClk.
-- resets. We move the signal from ConfigClk to RfClk domain and move it
-- back to ConfigClk domain. This just proves that RfClk is toggling and
-- the reset requested by software is sampled in the RfClk.
-----------------------------------------------------------------------------
SeqResetDone : process(ConfigClk)
begin
if rising_edge(ConfigClk) then
-- double-syncs have no sync reset!
cTriggerAdcResetDone_ms <= dTriggerAdcReset;
cTriggerAdcResetDone_ms <= rTriggerAdcReset;
cTriggerAdcResetDone <= cTriggerAdcResetDone_ms;
cTriggerDacResetDone_ms <= dTriggerDacReset;
cTriggerDacResetDone_ms <= rTriggerDacReset;
cTriggerDacResetDone <= cTriggerDacResetDone_ms;
end if;
end process;
@@ -172,37 +170,20 @@ begin
-----------------------------------------------------------------------------
-- rf_reset Instances
-----------------------------------------------------------------------------
RfClkResets: process(RfClk)
begin
if rising_edge(RfClk) then
rAdcReset_n <= not (rAdcResetPulse or rTriggerAdcReset);
rDacReset_n <= not (rDacResetPulse or rTriggerDacReset);
end if;
end process RfClkResets;
AdcResets: entity work.rf_reset (RTL)
port map (
DataClk => DataClk,
PllRefClk => PllRefClk,
RfClk => RfClk,
RfClk2x => RfClk2x,
DataClk2x => DataClk2x,
dTimedReset => dAdcResetPulse,
dSwReset => dTriggerAdcReset,
dReset_n => dAdcDataOutReset_n,
d2Reset_n => open,
r2Reset_n => r2AdcFirReset_n,
rAxiReset_n => rAdcRfdcAxiReset_n,
rReset_n => rAdcGearboxReset_n
);
DacResets: entity work.rf_reset (RTL)
port map (
DataClk => DataClk,
PllRefClk => PllRefClk,
RfClk => RfClk,
RfClk2x => RfClk2x,
DataClk2x => DataClk2x,
dTimedReset => dDacResetPulse,
dSwReset => dTriggerDacReset,
dReset_n => dDacDataInReset_n,
d2Reset_n => d2DacFirReset_n,
r2Reset_n => r2DacFirReset_n,
rAxiReset_n => rDacRfdcAxiReset_n,
rReset_n => rDacGearboxReset_n
);
RfClk2xResets: process(RfClk2x)
begin
if rising_edge(RfClk2x) then
r2AdcReset_n <= not (rAdcResetPulse or rTriggerAdcReset);
r2DacReset_n <= not (rDacResetPulse or rTriggerDacReset);
end if;
end process RfClk2xResets;
end RTL;
top/x400/rf/x440/x440_rfdc_tx_control_remap.v
+35
View File
@@ -0,0 +1,35 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x440_rfdc_tx_control_remap.v
// Description:
// Allows for remapping control signals to the correct tile on X440.
// This file targets the DAC tiles specifically
//
`default_nettype none
module x440_rfdc_tx_control_remap (
// Input control (Front-Panel ordering)
input wire [7:0] input_controls,
// output_control (DAC Tile ordering)
output wire [7:0] output_controls
);
`include "../../regmap/x440/rfdc_mapping_regmap_utils.vh"
// Decode TX Channel mapping
assign output_controls[CH0_TX_MAPPING] = input_controls[0];
assign output_controls[CH1_TX_MAPPING] = input_controls[1];
assign output_controls[CH2_TX_MAPPING] = input_controls[2];
assign output_controls[CH3_TX_MAPPING] = input_controls[3];
assign output_controls[CH4_TX_MAPPING] = input_controls[4];
assign output_controls[CH5_TX_MAPPING] = input_controls[5];
assign output_controls[CH6_TX_MAPPING] = input_controls[6];
assign output_controls[CH7_TX_MAPPING] = input_controls[7];
endmodule
`default_nettype wire
top/x400/setupenv.sh
+1
View File
@@ -12,6 +12,7 @@ REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)
declare -A PRODUCT_ID_MAP
PRODUCT_ID_MAP["X410"]="zynquplusRFSOC/xczu28dr/ffvg1517/-1/e"
PRODUCT_ID_MAP["X440"]="zynquplusRFSOC/xczu28dr/ffvg1517/-2/e"
# Set default part for simulation
export ARCH=zynquplusRFSOC
top/x400/x410_400_128_static_router.hex
-17
View File
@@ -1,17 +0,0 @@
00000010
00400240
02400040
00800241
02410080
00c00280
028000c0
01000281
02810100
014002c0
02c00140
018002c1
02c10180
01c002c2
02c201c0
020002c3
02c30200
top/x400/x440_1600_d_rfnoc_image_core.v
+1126
View File
File diff suppressed because it is too large Load Diff
top/x400/x440_1600_d_rfnoc_image_core.vh
+19
View File
@@ -0,0 +1,19 @@
//
// Copyright 2023 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x440)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// Source: x440_1600_d_rfnoc_image_core.yml
//
`define CHDR_WIDTH 512
`define RFNOC_PROTOVER { 8'd1, 8'd0 }

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