5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
530 lines
21 KiB
Verilog
530 lines
21 KiB
Verilog
//
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// Copyright 2019 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_block_replay
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//
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// Description:
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//
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// RFNoC data record and playback block. This block has the ability to
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// capture all of the data that is sent to it and store it into an attached
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// memory using an AXI memory-mapped interface. It can then play back any
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// part of the data on demand or continuously. Timed playback is also
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// supported. See axis_replay.v for details of replay operation.
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//
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// Parameters:
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//
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// THIS_PORTID : Control crossbar port to which this block is connected
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// CHDR_W : AXIS-CHDR data bus width
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// MTU : Maximum transmission unit (i.e., maximum packet size in
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// CHDR words is 2**MTU).
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// NUM_PORTS : Number of replay instances to instantiate. Each one will
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// have its own register set and memory interface.
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// MEM_DATA_W : Data width to use for the memory interface.
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// MEM_ADDR_W : Byte address width to use for the memory interface.
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// BURST_LENGTH : Burst length to use in bytes. Must not exceed 256 words. It
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// can be larger than the 4096-byte limit of AXI, but this
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// might not be compatible with all memories.
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//
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`default_nettype none
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module rfnoc_block_replay #(
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parameter [9:0] THIS_PORTID = 10'd0,
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parameter CHDR_W = 64,
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parameter [5:0] MTU = 10,
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parameter NUM_PORTS = 1,
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parameter MEM_DATA_W = 64,
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parameter MEM_ADDR_W = 30,
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parameter BURST_LENGTH = MEM_DATA_W/8 * 256
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) (
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//---------------------------------------------------------------------------
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// AXIS-CHDR Port
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//---------------------------------------------------------------------------
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// RFNoC Framework Clocks and Resets
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input wire rfnoc_chdr_clk,
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// AXIS-CHDR Input Ports (from framework)
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input wire [(0+NUM_PORTS)*CHDR_W-1:0] s_rfnoc_chdr_tdata,
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input wire [ (0+NUM_PORTS)-1:0] s_rfnoc_chdr_tlast,
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input wire [ (0+NUM_PORTS)-1:0] s_rfnoc_chdr_tvalid,
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output wire [ (0+NUM_PORTS)-1:0] s_rfnoc_chdr_tready,
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// AXIS-CHDR Output Ports (to framework)
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output wire [(0+NUM_PORTS)*CHDR_W-1:0] m_rfnoc_chdr_tdata,
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output wire [ (0+NUM_PORTS)-1:0] m_rfnoc_chdr_tlast,
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output wire [ (0+NUM_PORTS)-1:0] m_rfnoc_chdr_tvalid,
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input wire [ (0+NUM_PORTS)-1:0] m_rfnoc_chdr_tready,
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// RFNoC Backend Interface
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input wire [511:0] rfnoc_core_config,
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output wire [511:0] rfnoc_core_status,
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//---------------------------------------------------------------------------
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// AXIS-Ctrl Port
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//---------------------------------------------------------------------------
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input wire rfnoc_ctrl_clk,
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// AXIS-Ctrl Input Port (from framework)
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input wire [31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// AXIS-Ctrl Output Port (to framework)
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output wire [31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready,
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//---------------------------------------------------------------------------
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// AXI Memory Mapped Interface
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//---------------------------------------------------------------------------
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// AXI Interface Clock and Reset
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input wire mem_clk,
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input wire axi_rst,
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// AXI Write address channel
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output wire [ (NUM_PORTS*1)-1:0] m_axi_awid,
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output wire [ (NUM_PORTS*MEM_ADDR_W)-1:0] m_axi_awaddr,
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output wire [ (NUM_PORTS*8)-1:0] m_axi_awlen,
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output wire [ (NUM_PORTS*3)-1:0] m_axi_awsize,
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output wire [ (NUM_PORTS*2)-1:0] m_axi_awburst,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_awlock,
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output wire [ (NUM_PORTS*4)-1:0] m_axi_awcache,
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output wire [ (NUM_PORTS*3)-1:0] m_axi_awprot,
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output wire [ (NUM_PORTS*4)-1:0] m_axi_awqos,
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output wire [ (NUM_PORTS*4)-1:0] m_axi_awregion,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_awuser,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_awvalid,
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input wire [ (NUM_PORTS*1)-1:0] m_axi_awready,
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// AXI Write data channel
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output wire [ (NUM_PORTS*MEM_DATA_W)-1:0] m_axi_wdata,
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output wire [(NUM_PORTS*MEM_DATA_W/8)-1:0] m_axi_wstrb,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_wlast,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_wuser,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_wvalid,
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input wire [ (NUM_PORTS*1)-1:0] m_axi_wready,
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// AXI Write response channel signals
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input wire [ (NUM_PORTS*1)-1:0] m_axi_bid,
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input wire [ (NUM_PORTS*2)-1:0] m_axi_bresp,
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input wire [ (NUM_PORTS*1)-1:0] m_axi_buser,
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input wire [ (NUM_PORTS*1)-1:0] m_axi_bvalid,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_bready,
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// AXI Read address channel
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output wire [ (NUM_PORTS*1)-1:0] m_axi_arid,
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output wire [ (NUM_PORTS*MEM_ADDR_W)-1:0] m_axi_araddr,
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output wire [ (NUM_PORTS*8)-1:0] m_axi_arlen,
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output wire [ (NUM_PORTS*3)-1:0] m_axi_arsize,
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output wire [ (NUM_PORTS*2)-1:0] m_axi_arburst,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_arlock,
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output wire [ (NUM_PORTS*4)-1:0] m_axi_arcache,
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output wire [ (NUM_PORTS*3)-1:0] m_axi_arprot,
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output wire [ (NUM_PORTS*4)-1:0] m_axi_arqos,
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output wire [ (NUM_PORTS*4)-1:0] m_axi_arregion,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_aruser,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_arvalid,
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input wire [ (NUM_PORTS*1)-1:0] m_axi_arready,
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// AXI Read data channel
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input wire [ (NUM_PORTS*1)-1:0] m_axi_rid,
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input wire [ (NUM_PORTS*MEM_DATA_W)-1:0] m_axi_rdata,
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input wire [ (NUM_PORTS*2)-1:0] m_axi_rresp,
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input wire [ (NUM_PORTS*1)-1:0] m_axi_rlast,
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input wire [ (NUM_PORTS*1)-1:0] m_axi_ruser,
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input wire [ (NUM_PORTS*1)-1:0] m_axi_rvalid,
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output wire [ (NUM_PORTS*1)-1:0] m_axi_rready
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);
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`include "rfnoc_block_replay_regs.vh"
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//---------------------------------------------------------------------------
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// Signal Declarations
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//---------------------------------------------------------------------------
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// CtrlPort Master
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wire ctrlport_req_wr;
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wire ctrlport_req_rd;
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wire [19:0] ctrlport_req_addr;
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wire [31:0] ctrlport_req_data;
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wire ctrlport_resp_ack;
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wire [31:0] ctrlport_resp_data;
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// Data Stream to User Logic: in
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wire [NUM_PORTS*MEM_DATA_W*1-1:0] in_axis_tdata;
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wire [ NUM_PORTS-1:0] in_axis_tlast;
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wire [ NUM_PORTS-1:0] in_axis_tvalid;
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wire [ NUM_PORTS-1:0] in_axis_tready;
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// Data Stream to User Logic: out
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wire [NUM_PORTS*MEM_DATA_W*1-1:0] out_axis_tdata;
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wire [ NUM_PORTS-1:0] out_axis_tlast;
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wire [ NUM_PORTS-1:0] out_axis_tvalid;
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wire [ NUM_PORTS-1:0] out_axis_tready;
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wire [ NUM_PORTS*64-1:0] out_axis_ttimestamp;
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wire [ NUM_PORTS-1:0] out_axis_thas_time;
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wire [ NUM_PORTS-1:0] out_axis_teob;
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//---------------------------------------------------------------------------
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// NoC Shell
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//---------------------------------------------------------------------------
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wire mem_rst_noc_shell;
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noc_shell_replay #(
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.THIS_PORTID (THIS_PORTID),
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.CHDR_W (CHDR_W),
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.MEM_DATA_W (MEM_DATA_W),
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.MTU (MTU),
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.NUM_PORTS (NUM_PORTS)
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) noc_shell_replay_i (
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//---------------------
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// Framework Interface
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//---------------------
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// Clock Inputs
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.mem_clk (mem_clk),
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// Reset Outputs
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.rfnoc_chdr_rst (),
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.rfnoc_ctrl_rst (),
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.mem_rst (mem_rst_noc_shell),
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// RFNoC Backend Interface
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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// CHDR Input Ports (from framework)
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.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
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.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
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.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
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.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
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// CHDR Output Ports (to framework)
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.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
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.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
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.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
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.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
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// AXIS-Ctrl Input Port (from framework)
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
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// AXIS-Ctrl Output Port (to framework)
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
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//---------------------
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// Client Interface
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//---------------------
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// CtrlPort Clock and Reset
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.ctrlport_clk (),
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.ctrlport_rst (),
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// CtrlPort Master
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.m_ctrlport_req_wr (ctrlport_req_wr),
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.m_ctrlport_req_rd (ctrlport_req_rd),
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.m_ctrlport_req_addr (ctrlport_req_addr),
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.m_ctrlport_req_data (ctrlport_req_data),
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.m_ctrlport_resp_ack (ctrlport_resp_ack),
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.m_ctrlport_resp_data (ctrlport_resp_data),
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// AXI-Stream Payload Context Clock and Reset
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.axis_data_clk (),
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.axis_data_rst (),
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// Data Stream to User Logic: in
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.m_in_axis_tdata (in_axis_tdata),
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.m_in_axis_tkeep (),
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.m_in_axis_tlast (in_axis_tlast),
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.m_in_axis_tvalid (in_axis_tvalid),
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.m_in_axis_tready (in_axis_tready),
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.m_in_axis_ttimestamp (),
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.m_in_axis_thas_time (),
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.m_in_axis_tlength (),
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.m_in_axis_teov (),
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.m_in_axis_teob (),
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// Data Stream from User Logic: out
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.s_out_axis_tdata (out_axis_tdata),
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.s_out_axis_tkeep ({NUM_PORTS*MEM_DATA_W/32{1'b1}}),
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.s_out_axis_tlast (out_axis_tlast),
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.s_out_axis_tvalid (out_axis_tvalid),
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.s_out_axis_tready (out_axis_tready),
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.s_out_axis_ttimestamp (out_axis_ttimestamp),
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.s_out_axis_thas_time (out_axis_thas_time),
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.s_out_axis_tlength ({NUM_PORTS{16'b0}}), // Not used when SIDEBAND_AT_END = 1
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.s_out_axis_teov ({NUM_PORTS{1'b0}}),
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.s_out_axis_teob (out_axis_teob)
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);
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reg mem_rst;
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// Combine the NoC Shell and AXI resets
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always @(posedge mem_clk) begin
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mem_rst <= axi_rst | mem_rst_noc_shell;
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end
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//---------------------------------------------------------------------------
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// CtrlPort Splitter
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//---------------------------------------------------------------------------
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wire [ 1*NUM_PORTS-1:0] dec_ctrlport_req_wr;
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wire [ 1*NUM_PORTS-1:0] dec_ctrlport_req_rd;
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wire [20*NUM_PORTS-1:0] dec_ctrlport_req_addr;
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wire [32*NUM_PORTS-1:0] dec_ctrlport_req_data;
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wire [ 1*NUM_PORTS-1:0] dec_ctrlport_resp_ack;
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wire [32*NUM_PORTS-1:0] dec_ctrlport_resp_data;
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generate
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if (NUM_PORTS > 1) begin : gen_ctrlport_decoder
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ctrlport_decoder #(
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.NUM_SLAVES (NUM_PORTS),
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.BASE_ADDR (0),
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.SLAVE_ADDR_W (REPLAY_ADDR_W)
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) ctrlport_decoder_i (
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.ctrlport_clk (mem_clk),
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.ctrlport_rst (mem_rst),
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.s_ctrlport_req_wr (ctrlport_req_wr),
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.s_ctrlport_req_rd (ctrlport_req_rd),
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.s_ctrlport_req_addr (ctrlport_req_addr),
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.s_ctrlport_req_data (ctrlport_req_data),
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.s_ctrlport_req_byte_en (4'hF),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'b0),
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.s_ctrlport_resp_ack (ctrlport_resp_ack),
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.s_ctrlport_resp_status (),
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.s_ctrlport_resp_data (ctrlport_resp_data),
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.m_ctrlport_req_wr (dec_ctrlport_req_wr),
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.m_ctrlport_req_rd (dec_ctrlport_req_rd),
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.m_ctrlport_req_addr (dec_ctrlport_req_addr),
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.m_ctrlport_req_data (dec_ctrlport_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (dec_ctrlport_resp_ack),
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.m_ctrlport_resp_status ({NUM_PORTS{2'b0}}),
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.m_ctrlport_resp_data (dec_ctrlport_resp_data)
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);
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end else begin : gen_no_decoder
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assign dec_ctrlport_req_wr = ctrlport_req_wr;
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assign dec_ctrlport_req_rd = ctrlport_req_rd;
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assign dec_ctrlport_req_addr = {{20-REPLAY_ADDR_W{1'b0}},
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ctrlport_req_addr[REPLAY_ADDR_W-1:0]};
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assign dec_ctrlport_req_data = ctrlport_req_data;
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assign ctrlport_resp_ack = dec_ctrlport_resp_ack;
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assign ctrlport_resp_data = dec_ctrlport_resp_data;
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end
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endgenerate
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//---------------------------------------------------------------------------
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// Replay Block Instances
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//---------------------------------------------------------------------------
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// Width of memory transfer count. This controls the maximum burst length
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// supported by the Replay block. For AXI, it must not exceed 8 and it should
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// be no more than 4096 unless supported by the memory being used.
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localparam DESIRED_MEM_COUNT_W = $clog2(BURST_LENGTH / (MEM_DATA_W/8));
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localparam MEM_COUNT_W = (DESIRED_MEM_COUNT_W > 8) ? 8 : DESIRED_MEM_COUNT_W;
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genvar i;
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generate
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for (i = 0; i < NUM_PORTS; i = i+1) begin : gen_replay_blocks
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wire [ MEM_ADDR_W-1:0] write_addr;
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wire [MEM_COUNT_W-1:0] write_count;
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wire write_ctrl_valid;
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wire write_ctrl_ready;
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wire [ MEM_DATA_W-1:0] write_data;
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wire write_data_valid;
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wire write_data_ready;
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wire [ MEM_ADDR_W-1:0] read_addr;
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wire [MEM_COUNT_W-1:0] read_count;
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wire read_ctrl_valid;
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wire read_ctrl_ready;
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wire [ MEM_DATA_W-1:0] read_data;
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wire read_data_valid;
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wire read_data_ready;
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//-----------------------------------------------------------------------
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// Replay Handler
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//-----------------------------------------------------------------------
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//
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// This block implements the state machine and control logic for
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// recording and playback of data.
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//
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//-----------------------------------------------------------------------
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axis_replay #(
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.MEM_DATA_W (MEM_DATA_W),
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.MEM_ADDR_W (MEM_ADDR_W),
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.MEM_COUNT_W (MEM_COUNT_W)
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) axis_replay_i (
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.clk (mem_clk),
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.rst (mem_rst),
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// CtrlPort Interface
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.s_ctrlport_req_wr (dec_ctrlport_req_wr [ 1*i +: 1]),
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.s_ctrlport_req_rd (dec_ctrlport_req_rd [ 1*i +: 1]),
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.s_ctrlport_req_addr (dec_ctrlport_req_addr [20*i +: 20]),
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.s_ctrlport_req_data (dec_ctrlport_req_data [32*i +: 32]),
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.s_ctrlport_resp_ack (dec_ctrlport_resp_ack [ 1*i +: 1]),
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.s_ctrlport_resp_data (dec_ctrlport_resp_data [32*i +: 32]),
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// AXI Stream Interface
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//
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// Input
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.i_tdata (in_axis_tdata [MEM_DATA_W*i +: MEM_DATA_W]),
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.i_tvalid (in_axis_tvalid[ 1*i +: 1]),
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.i_tlast (in_axis_tlast [ 1*i +: 1]),
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.i_tready (in_axis_tready[ 1*i +: 1]),
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//
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// Output
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.o_tdata (out_axis_tdata [MEM_DATA_W*i +: MEM_DATA_W]),
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.o_ttimestamp (out_axis_ttimestamp[ 64*i +: 64]),
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.o_thas_time (out_axis_thas_time [ 1*i +: 1]),
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.o_teob (out_axis_teob [ 1*i +: 1]),
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.o_tvalid (out_axis_tvalid [ 1*i +: 1]),
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.o_tlast (out_axis_tlast [ 1*i +: 1]),
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.o_tready (out_axis_tready [ 1*i +: 1]),
|
|
|
|
// Memory Interface
|
|
//
|
|
// Write interface
|
|
.write_addr (write_addr),
|
|
.write_count (write_count),
|
|
.write_ctrl_valid (write_ctrl_valid),
|
|
.write_ctrl_ready (write_ctrl_ready),
|
|
.write_data (write_data),
|
|
.write_data_valid (write_data_valid),
|
|
.write_data_ready (write_data_ready),
|
|
//
|
|
// Read interface
|
|
.read_addr (read_addr),
|
|
.read_count (read_count),
|
|
.read_ctrl_valid (read_ctrl_valid),
|
|
.read_ctrl_ready (read_ctrl_ready),
|
|
.read_data (read_data),
|
|
.read_data_valid (read_data_valid),
|
|
.read_data_ready (read_data_ready)
|
|
);
|
|
|
|
//-----------------------------------------------------------------------
|
|
// AXI DMA Master
|
|
//-----------------------------------------------------------------------
|
|
//
|
|
// This block translates simple read and write requests to AXI4
|
|
// memory-mapped reads and writes for the RAM interface.
|
|
//
|
|
//-----------------------------------------------------------------------
|
|
|
|
// Resize the count signals, in case they are not 8 bit.
|
|
wire [7:0] write_count_8 = write_count;
|
|
wire [7:0] read_count_8 = read_count;
|
|
|
|
axi_dma_master #(
|
|
.AWIDTH (MEM_ADDR_W),
|
|
.DWIDTH (MEM_DATA_W)
|
|
) axi_dma_master_i (
|
|
//
|
|
// AXI4 Memory Mapped Interface to DRAM
|
|
//
|
|
.aclk (mem_clk),
|
|
.areset (mem_rst),
|
|
|
|
// Write control
|
|
.m_axi_awid (m_axi_awid [ 1*i +: 1]),
|
|
.m_axi_awaddr (m_axi_awaddr [MEM_ADDR_W*i +: MEM_ADDR_W]),
|
|
.m_axi_awlen (m_axi_awlen [ 8*i +: 8]),
|
|
.m_axi_awsize (m_axi_awsize [ 3*i +: 3]),
|
|
.m_axi_awburst (m_axi_awburst [ 2*i +: 2]),
|
|
.m_axi_awvalid (m_axi_awvalid [ 1*i +: 1]),
|
|
.m_axi_awready (m_axi_awready [ 1*i +: 1]),
|
|
.m_axi_awlock (m_axi_awlock [ 1*i +: 1]),
|
|
.m_axi_awcache (m_axi_awcache [ 4*i +: 4]),
|
|
.m_axi_awprot (m_axi_awprot [ 3*i +: 3]),
|
|
.m_axi_awqos (m_axi_awqos [ 4*i +: 4]),
|
|
.m_axi_awregion (m_axi_awregion[ 4*i +: 4]),
|
|
.m_axi_awuser (m_axi_awuser [ 1*i +: 1]),
|
|
|
|
// Write Data
|
|
.m_axi_wdata (m_axi_wdata [ MEM_DATA_W*i +: MEM_DATA_W]),
|
|
.m_axi_wstrb (m_axi_wstrb [(MEM_DATA_W/8)*i +: (MEM_DATA_W/8)]),
|
|
.m_axi_wlast (m_axi_wlast [ 1*i +: 1]),
|
|
.m_axi_wvalid (m_axi_wvalid[ 1*i +: 1]),
|
|
.m_axi_wready (m_axi_wready[ 1*i +: 1]),
|
|
.m_axi_wuser (m_axi_wuser [ 1*i +: 1]),
|
|
|
|
// Write Response
|
|
.m_axi_bid (m_axi_bid [1*i +: 1]),
|
|
.m_axi_bresp (m_axi_bresp [2*i +: 2]),
|
|
.m_axi_buser (m_axi_buser [1*i +: 1]),
|
|
.m_axi_bvalid (m_axi_bvalid[1*i +: 1]),
|
|
.m_axi_bready (m_axi_bready[1*i +: 1]),
|
|
|
|
// Read Control
|
|
.m_axi_arid (m_axi_arid [ 1*i +: 1]),
|
|
.m_axi_araddr (m_axi_araddr [MEM_ADDR_W*i +: MEM_ADDR_W]),
|
|
.m_axi_arlen (m_axi_arlen [ 8*i +: 8]),
|
|
.m_axi_arsize (m_axi_arsize [ 3*i +: 3]),
|
|
.m_axi_arburst (m_axi_arburst [ 2*i +: 2]),
|
|
.m_axi_arvalid (m_axi_arvalid [ 1*i +: 1]),
|
|
.m_axi_arready (m_axi_arready [ 1*i +: 1]),
|
|
.m_axi_arlock (m_axi_arlock [ 1*i +: 1]),
|
|
.m_axi_arcache (m_axi_arcache [ 4*i +: 4]),
|
|
.m_axi_arprot (m_axi_arprot [ 3*i +: 3]),
|
|
.m_axi_arqos (m_axi_arqos [ 4*i +: 4]),
|
|
.m_axi_arregion (m_axi_arregion[ 4*i +: 4]),
|
|
.m_axi_aruser (m_axi_aruser [ 1*i +: 1]),
|
|
|
|
// Read Data
|
|
.m_axi_rid (m_axi_rid [ 1*i +: 1]),
|
|
.m_axi_rdata (m_axi_rdata [MEM_DATA_W*i +: MEM_DATA_W]),
|
|
.m_axi_rresp (m_axi_rresp [ 2*i +: 2]),
|
|
.m_axi_rlast (m_axi_rlast [ 1*i +: 1]),
|
|
.m_axi_ruser (m_axi_ruser [ 1*i +: 1]),
|
|
.m_axi_rvalid (m_axi_rvalid[ 1*i +: 1]),
|
|
.m_axi_rready (m_axi_rready[ 1*i +: 1]),
|
|
|
|
//
|
|
// Interface for Write transactions
|
|
//
|
|
.write_addr (write_addr),
|
|
.write_count (write_count_8),
|
|
.write_ctrl_valid (write_ctrl_valid),
|
|
.write_ctrl_ready (write_ctrl_ready),
|
|
.write_data (write_data),
|
|
.write_data_valid (write_data_valid),
|
|
.write_data_ready (write_data_ready),
|
|
|
|
//
|
|
// Interface for Read transactions
|
|
//
|
|
.read_addr (read_addr),
|
|
.read_count (read_count_8),
|
|
.read_ctrl_valid (read_ctrl_valid),
|
|
.read_ctrl_ready (read_ctrl_ready),
|
|
.read_data (read_data),
|
|
.read_data_valid (read_data_valid),
|
|
.read_data_ready (read_data_ready),
|
|
|
|
//
|
|
// Debug
|
|
//
|
|
.debug ()
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
|
|
endmodule // rfnoc_block_replay
|
|
|
|
|
|
`default_nettype wire
|