diff --git a/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/sim_axi_ram.sv b/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/sim_axi_ram.sv index efe3c2f..556269e 100644 --- a/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/sim_axi_ram.sv +++ b/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/sim_axi_ram.sv @@ -1,34 +1,44 @@ // -// Copyright 2019 Ettus Research, A National Instruments Company +// Copyright 2023 Ettus Research, a National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // // Module: sim_axi_ram // -// Description: +// Description: // -// Simulation model for a basic AXI4 memory mapped memory. A few notes on its +// Simulation model for a basic AXI4 memory mapped memory. A few notes on its // behavior: // -// - This model does not reorder requests (regardless of WID/RID). All +// - This model does not reorder requests (regardless of WID/RID). All // requests are evaluated strictly in order. // - The only supported response is OKAY -// - This model supports misaligned memory accesses, which cause a +// - This model supports misaligned memory accesses, which cause a // simulation warning. // - A reset does not clear the memory contents -// - The memory itself is implemented using an associative array (sparse +// - The memory itself is implemented using an associative array (sparse // matrix) so that large memories can be supported. // - This model is half duplex, meaning read and write data transfers won't // happen at the same time. A new data transfer won't begin until the // previous one has completed. // +// Parameters: +// +// - AWIDTH : Address width of the memory to model +// - DWIDTH : Data width of the memory to model +// - IDWIDTH : Width of ID ports of the AXI bus +// - BIG_ENDIAN : Endianness of the memory model (0 = little, 1 = big) +// - STALL_PROB : Default probability of a channel stalling (0 to 99) +// - NO_4KB_LIMIT : Allow bursts to cross 4 KiB boundaries +// module sim_axi_ram #( - parameter AWIDTH = 32, - parameter DWIDTH = 64, - parameter IDWIDTH = 2, - parameter BIG_ENDIAN = 0, - parameter STALL_PROB = 25 + parameter AWIDTH = 32, + parameter DWIDTH = 64, + parameter IDWIDTH = 2, + parameter BIG_ENDIAN = 0, + parameter STALL_PROB = 25, + parameter NO_4KB_LIMIT = 0 ) ( input logic s_aclk, input logic s_aresetn, @@ -82,7 +92,7 @@ module sim_axi_ram #( //--------------------------------------------------------------------------- // Data Types //--------------------------------------------------------------------------- - + typedef enum logic [1:0] { FIXED, INCR, WRAP } burst_t; typedef enum logic [1:0] { OKAY, EXOKAY, SLVERR, DECERR } resp_t; @@ -95,7 +105,7 @@ module sim_axi_ram #( burst_t burst; } req_t; - // Make the address type an extra bit wide so that we can detect + // Make the address type an extra bit wide so that we can detect // out-of-bounds accesses easily. typedef bit [AWIDTH:0] addr_t; @@ -160,7 +170,7 @@ module sim_axi_ram #( rdata_stall_prob = probability; endfunction : set_read_stall_prob - // Set Write Address Channel stall probability + // Set Write Address Channel stall probability function void set_waddr_stall_prob(int probability); assert(probability >= 0 && probability <= 100) else begin $error("Probability must be from 0 to 100"); @@ -200,7 +210,7 @@ module sim_axi_ram #( rdata_stall_prob = probability; endfunction : set_rdata_stall_prob - // Get Write Address Channel stall probability + // Get Write Address Channel stall probability function int get_waddr_stall_prob(); return waddr_stall_prob; endfunction : get_waddr_stall_prob @@ -313,13 +323,13 @@ module sim_axi_ram #( assert ($cast(burst, s_axi_awburst)) else begin $fatal(1, "Invalid AWBURST value"); end - assert ((s_axi_awaddr & MASK_4K) == - ((s_axi_awaddr + (s_axi_awlen+1)*(2**s_axi_awsize) - 1) & MASK_4K)) else begin + assert (NO_4KB_LIMIT || ((s_axi_awaddr & MASK_4K) == + ((s_axi_awaddr + (s_axi_awlen+1)*(2**s_axi_awsize) - 1) & MASK_4K))) else begin $fatal(1, "Memory write burst crosses 4 KiB boundary"); end if (DEBUG) begin - $display("WRITE REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m", + $display("WRITE REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m", req.id, req.addr, req.len, req.size, req.burst.name, $realtime); end @@ -370,13 +380,13 @@ module sim_axi_ram #( assert ($cast(burst, s_axi_awburst)) else begin $fatal(1, "Invalid ARBURST value"); end - assert ((s_axi_araddr & MASK_4K) == - ((s_axi_araddr + (s_axi_arlen+1)*(2**s_axi_arsize) - 1) & MASK_4K)) else begin + assert (NO_4KB_LIMIT || ((s_axi_araddr & MASK_4K) == + ((s_axi_araddr + (s_axi_arlen+1)*(2**s_axi_arsize) - 1) & MASK_4K))) else begin $fatal(1, "Memory read burst crosses 4 KiB boundary"); end if (DEBUG) begin - $display("READ REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m", + $display("READ REQ: id=%X, addr=%X, len=%X, size=%X, burst=%s, %t, %m", req.id, req.addr, req.len, req.size, req.burst.name, $realtime); end @@ -437,7 +447,7 @@ module sim_axi_ram #( addr = req.addr; end INCR : begin - // If the address rolls over, we've reached the end of the + // If the address rolls over, we've reached the end of the // memory and we should stop here. addr = req.addr + i*req.size; if (addr < req.addr) break; @@ -451,7 +461,7 @@ module sim_axi_ram #( write_mem(addr, req.size, s_axi_wdata, s_axi_wstrb); if (DEBUG) begin - $display("WRITE: count=%3X, ADDR=%X, DATA=%X, SIZE=%X, STRB=%X, %t, %m", + $display("WRITE: count=%3X, ADDR=%X, DATA=%X, SIZE=%X, STRB=%X, %t, %m", i, addr, s_axi_wdata, req.size, s_axi_wstrb, $realtime); end @@ -474,9 +484,9 @@ module sim_axi_ram #( // Enqueue write response write_resp.put(req); - // Make sure WLAST asserted for the last word. If not we report an error. - // Per the AXI4 standard, "a slave is not required to use the WLAST - // signal" because "a slave can calculate the last write data transfer + // Make sure WLAST asserted for the last word. If not we report an error. + // Per the AXI4 standard, "a slave is not required to use the WLAST + // signal" because "a slave can calculate the last write data transfer // from the burst length AWLEN". if (s_axi_wlast != 1'b1) begin $error("WLAST not asserted on last word of burst"); @@ -598,7 +608,7 @@ module sim_axi_ram #( addr = req.addr; end INCR : begin - // If the address rolls over, we've reached the end of the memory + // If the address rolls over, we've reached the end of the memory // and we should stop here. addr = req.addr + i*req.size; if (addr < req.addr) break; diff --git a/lib/rfnoc/blocks/rfnoc_block_replay/axis_replay.v b/lib/rfnoc/blocks/rfnoc_block_replay/axis_replay.v index 38d9eb0..96ae5f1 100644 --- a/lib/rfnoc/blocks/rfnoc_block_replay/axis_replay.v +++ b/lib/rfnoc/blocks/rfnoc_block_replay/axis_replay.v @@ -168,8 +168,12 @@ module axis_replay #( // The lower MEM_ALIGN bits for all memory byte addresses should be 0. localparam MEM_ALIGN = $clog2(MEM_DATA_W / 8); // - // AXI alignment requirement (4096 bytes) in MEM_DATA_W-bit words - localparam AXI_ALIGNMENT = 4096 / BYTES_PER_WORD; + // Burst length in bytes + localparam BURST_LENGTH = 2**MEM_COUNT_W * BYTES_PER_WORD; + // + // AXI alignment requirement (normally 4096 bytes) in MEM_DATA_W-bit words + localparam AXI_ALIGNMENT = (BURST_LENGTH <= 4096) ? 4096 / BYTES_PER_WORD : + BURST_LENGTH / BYTES_PER_WORD; // Memory Buffering Parameters // diff --git a/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay.v b/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay.v index 119b371..fd9b781 100644 --- a/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay.v +++ b/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay.v @@ -15,26 +15,30 @@ // // Parameters: // -// THIS_PORTID : Control crossbar port to which this block is connected -// CHDR_W : AXIS-CHDR data bus width -// MTU : Maximum transmission unit (i.e., maximum packet size in -// CHDR words is 2**MTU). -// NUM_PORTS : Number of replay instances to instantiate. Each one will -// have its own register set and memory interface. -// MEM_DATA_W : Data width to use for the memory interface. -// MEM_ADDR_W : Byte address width to use for the memory interface. +// THIS_PORTID : Control crossbar port to which this block is connected +// CHDR_W : AXIS-CHDR data bus width +// MTU : Maximum transmission unit (i.e., maximum packet size in +// CHDR words is 2**MTU). +// NUM_PORTS : Number of replay instances to instantiate. Each one will +// have its own register set and memory interface. +// MEM_DATA_W : Data width to use for the memory interface. +// MEM_ADDR_W : Byte address width to use for the memory interface. +// BURST_LENGTH : Burst length to use in bytes. Must not exceed 256 words. It +// can be larger than the 4096-byte limit of AXI, but this +// might not be compatible with all memories. // `default_nettype none module rfnoc_block_replay #( - parameter [9:0] THIS_PORTID = 10'd0, - parameter CHDR_W = 64, - parameter [5:0] MTU = 10, - parameter NUM_PORTS = 1, - parameter MEM_DATA_W = 64, - parameter MEM_ADDR_W = 30 + parameter [9:0] THIS_PORTID = 10'd0, + parameter CHDR_W = 64, + parameter [5:0] MTU = 10, + parameter NUM_PORTS = 1, + parameter MEM_DATA_W = 64, + parameter MEM_ADDR_W = 30, + parameter BURST_LENGTH = MEM_DATA_W/8 * 256 ) ( //--------------------------------------------------------------------------- // AXIS-CHDR Port @@ -323,11 +327,10 @@ module rfnoc_block_replay #( //--------------------------------------------------------------------------- // Width of memory transfer count. This controls the maximum burst length - // supported by the Replay block. For AXI compatibility, it must be 8 or less - // and should not represent more than 4 KiB. Here we set it to 2 KiB by - // default. - localparam MEM_COUNT_W = (MEM_DATA_W <= 64) ? 8 : // Max width allowed - $clog2(2048 / (MEM_DATA_W/8)); // 2 KiB + // supported by the Replay block. For AXI, it must not exceed 8 and it should + // be no more than 4096 unless supported by the memory being used. + localparam DESIRED_MEM_COUNT_W = $clog2(BURST_LENGTH / (MEM_DATA_W/8)); + localparam MEM_COUNT_W = (DESIRED_MEM_COUNT_W > 8) ? 8 : DESIRED_MEM_COUNT_W; genvar i; generate diff --git a/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_tb.sv b/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_tb.sv index d4cb071..bee3300 100644 --- a/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_tb.sv +++ b/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_tb.sv @@ -209,7 +209,8 @@ module rfnoc_block_replay_tb#( .DWIDTH (MEM_DATA_W), .IDWIDTH (1), .BIG_ENDIAN (0), - .STALL_PROB (STALL_PROB) + .STALL_PROB (STALL_PROB), + .NO_4KB_LIMIT(MEM_DATA_W/8 * 256 > 4096) ) sim_axi_ram_i ( .s_aclk (mem_clk), .s_aresetn (~mem_rst), diff --git a/tools/utils/image_package_mapping.py b/tools/utils/image_package_mapping.py index ab09250..365a533 100644 --- a/tools/utils/image_package_mapping.py +++ b/tools/utils/image_package_mapping.py @@ -95,6 +95,31 @@ PACKAGE_MAPPING = { "usrp_x410_fpga_CG_400.rpt", ] }, + "x440": { + "type": "x4xx", + "package_name": "x4xx_x440_fpga_default-g{}.zip", + "files": ["usrp_x440_fpga_CG_400.bit", + "usrp_x440_fpga_CG_400.bit.md5", + "usrp_x440_fpga_CG_400.dts", + "usrp_x440_fpga_CG_400.dts.md5", + "usrp_x440_fpga_CG_400.rpt", + "usrp_x440_fpga_X4_400.bit", + "usrp_x440_fpga_X4_400.bit.md5", + "usrp_x440_fpga_X4_400.dts", + "usrp_x440_fpga_X4_400.dts.md5", + "usrp_x440_fpga_X4_400.rpt", + "usrp_x440_fpga_CG_1600.bit", + "usrp_x440_fpga_CG_1600.bit.md5", + "usrp_x440_fpga_CG_1600.dts", + "usrp_x440_fpga_CG_1600.dts.md5", + "usrp_x440_fpga_CG_1600.rpt", + "usrp_x440_fpga_X4_1600.bit", + "usrp_x440_fpga_X4_1600.bit.md5", + "usrp_x440_fpga_X4_1600.dts", + "usrp_x440_fpga_X4_1600.dts.md5", + "usrp_x440_fpga_X4_1600.rpt", + ] + }, "x410_cpld": { "type": "x4xx", "package_name": "x4xx_x410_cpld_default-g{}.zip", @@ -107,6 +132,18 @@ PACKAGE_MAPPING = { "usrp_x410_cpld_10m08.svf", "usrp_x410_cpld_10m08.svf.md5"] }, + "x440_cpld": { + "type": "x4xx", + "package_name": "x4xx_x440_cpld_default-g{}.zip", + "files": ["usrp_x440_cpld_10m04.rpd", + "usrp_x440_cpld_10m04.rpd.md5", + "usrp_x440_cpld_10m04.svf", + "usrp_x440_cpld_10m04.svf.md5", + "usrp_x440_cpld_10m08.rpd", + "usrp_x440_cpld_10m08.rpd.md5", + "usrp_x440_cpld_10m08.svf", + "usrp_x440_cpld_10m08.svf.md5"] + }, "zbx_cpld": { "type": "x4xx", "package_name": "x4xx_zbx_cpld_default-g{}.zip", diff --git a/top/x400/Makefile b/top/x400/Makefile index 00a52fa..efe6c46 100644 --- a/top/x400/Makefile +++ b/top/x400/Makefile @@ -62,6 +62,14 @@ X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_40 X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_CH=0 +X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128 +X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=8*$(DRAM) DRAM_W=128 +X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0 +X440_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_CH=0 +X440_X1_1600: DEFS += $(QSFP0_10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=2*$(DRAM) DRAM_W=512 +X440_X4_1600: DEFS += $(QSFP0_4X10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=2*$(DRAM) DRAM_W=512 +X440_C1_1600: DEFS += $(QSFP0_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=0 +X440_CG_1600: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_CH=0 # DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to # exclude it. Note that some targets exclude it regardless of this setting. @@ -79,6 +87,10 @@ X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_ X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex) X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex) X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex) +X440_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_static_router.hex) +X440_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_d_static_router.hex) +X440_1600_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_static_router.hex) +X440_1600_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_d_static_router.hex) # Option to stop after RTL elaboration. Use this flag as a synthesis check. ifndef TARGET @@ -132,7 +144,15 @@ endif ##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused ##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused ##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused -##* Note: Not all targets are shipped with UHD. +##X440_X1_400 | 400 MHz | 8 | 10 GbE (Lane 0) | Unused | 128b x 8 Ch +##X440_X4_400 | 400 MHz | 8 | 4 x 10 GbE | Unused | 128b x 8 Ch +##X440_C1_400 | 400 MHz | 8 | 100 GbE | Unused | Unused +##X440_CG_400 | 400 MHz | 8 | 100 GbE | 100 GbE | Unused +##X440_X1_1600 | 1.6 GHz | 2 | 10 GbE (Lane 0) | Unused | 512b x 2 Ch +##X440_X4_1600 | 1.6 GHz | 2 | 4 x 10 GbE | Unused | 512b x 2 Ch +##X440_C1_1600 | 1.6 GHz | 2 | 100 GbE | Unused | Unused +##X440_CG_1600 | 1.6 GHz | 2 | 100 GbE | 100 GbE | Unused +##* Note: Not all targets are shipped with UHD ##* Note: Some YAML configurations might not use all available DRAM channels. X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts @@ -207,6 +227,38 @@ X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts $(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS)) $(call post_build,X410,CG_400) +X440_X1_400: X440_IP build/usrp_x440_fpga_X1_400.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS)) + $(call post_build,X440,X1_400) + +X440_X4_400: X440_IP build/usrp_x440_fpga_X4_400.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS)) + $(call post_build,X440,X4_400) + +X440_C1_400: X440_IP build/usrp_x440_fpga_C1_400.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS)) + $(call post_build,X440,C1_400) + +X440_CG_400: X440_IP build/usrp_x440_fpga_CG_400.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS)) + $(call post_build,X440,CG_400) + +X440_X1_1600: X440_IP build/usrp_x440_fpga_X1_1600.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS)) + $(call post_build,X440,X1_1600) + +X440_X4_1600: X440_IP build/usrp_x440_fpga_X4_1600.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS)) + $(call post_build,X440,X4_1600) + +X440_C1_1600: X440_IP build/usrp_x440_fpga_C1_1600.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS)) + $(call post_build,X440,C1_1600) + +X440_CG_1600: X440_IP build/usrp_x440_fpga_CG_1600.dts + $(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS)) + $(call post_build,X440,CG_1600) + ## ##Experimental Targets ##-------------|-----------|----|-----------------|-----------------|------------ @@ -229,6 +281,9 @@ all: X410_X4_200 X410_CG_400 X410_UC_200 ##(Default targets) X410_IP: ##Build IP only. +$(call vivado_ip,X410,$(DEFS) X410=1) +X440_IP: ##Build IP only. + +$(call vivado_ip,X440,$(DEFS) X440=1) + build/usrp_x410%.dts: dts/*.dts dts/*.dtsi -mkdir -p build tools/parse_versions_for_dts.py \ @@ -238,6 +293,15 @@ build/usrp_x410%.dts: dts/*.dts dts/*.dtsi ${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \ $$(python3 tools/get_dts_input.py --target $@) +build/usrp_x440%.dts: dts/*.dts dts/*.dtsi + -mkdir -p build + tools/parse_versions_for_dts.py \ + --input regmap/x440/versioning_regs_regmap_utils.vh \ + --output dts/x440-version-info.dtsi \ + --components fpga,cpld_ifc,db_gpio_ifc,rf_core_full + ${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \ + $$(python3 tools/get_dts_input.py --target $@) + clean: ##Clean up all target build outputs. @echo "Cleaning targets..." @rm -rf build-X4* diff --git a/top/x400/Makefile.x4xx.inc b/top/x400/Makefile.x4xx.inc index 69ac999..773e77f 100644 --- a/top/x400/Makefile.x4xx.inc +++ b/top/x400/Makefile.x4xx.inc @@ -100,11 +100,36 @@ rf/x410/x410_rf_reset_controller.vhd \ dboards/zbx/db_gpio_interface.v endif +ifdef X440 +TOP_SRCS += \ +rf/100m/rf_core_100m.v \ +rf/full/rf_core_full.v \ +rf/x440/x440_rf_reset_controller.vhd \ +dboards/fbx/db_gpio_interface.v \ +dboards/fbx/ctrlport_to_i2c_sync_ctrl.v \ +dboards/fbx/led_atr_control.v \ +dboards/fbx/clock_en_control.v \ +dboards/fbx/rf_atr_control.v +endif + ifdef X410 MB_XDC += \ constraints/timing/x410_clocks.xdc endif +ifdef X440 +ifeq ($(RF_BW), 400) +MB_XDC += \ +constraints/timing/x440_clocks_400.xdc +endif +ifeq ($(RF_BW), 1600) +MB_XDC += \ +constraints/timing/x440_clocks_1600.xdc +endif +MB_XDC += \ +constraints/timing/x440_clocks.xdc +endif + MB_XDC += \ constraints/pins/common.xdc \ constraints/timing/shared_constants.sdc \ @@ -119,6 +144,13 @@ constraints/pins/x410/db_gpio.xdc \ constraints/timing/x410.xdc endif +ifdef X440 +MB_XDC += \ +constraints/pins/rfdc_4x4.xdc \ +constraints/pins/x440/db_gpio.xdc \ +constraints/timing/x440.xdc +endif + # Definitions # MGT Types from x4xx_mgt_type.vh MGT_100GbE = 5 diff --git a/top/x400/constraints/pins/qsfp1_0.xdc b/top/x400/constraints/pins/qsfp1_0.xdc index 2c68bf7..ea319a2 100644 --- a/top/x400/constraints/pins/qsfp1_0.xdc +++ b/top/x400/constraints/pins/qsfp1_0.xdc @@ -26,4 +26,3 @@ set_property PACKAGE_PIN Y36 [get_ports {QSFP1_0_TX_N}] set_property PACKAGE_PIN Y31 [get_ports {GTY_RCV_CLK_P}] set_property PACKAGE_PIN Y32 [get_ports {GTY_RCV_CLK_N}] -set_property IOSTANDARD DIFF_SSTL12 [get_ports {GTY_RCV_CLK_*}] diff --git a/top/x400/constraints/pins/rfdc_4x4.xdc b/top/x400/constraints/pins/rfdc_4x4.xdc new file mode 100644 index 0000000..25e4991 --- /dev/null +++ b/top/x400/constraints/pins/rfdc_4x4.xdc @@ -0,0 +1,87 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# RF data converters pin constraints for X440. +# Converter pin mapping can be found at(redirected from UG1075): +# https://www.xilinx.com/support/packagefiles/zuppackages/xczu28drffvg1517pkg.txt +# + +# SYSREF input for data converters. +set_property PACKAGE_PIN U4 [get_ports {SYSREF_RF_N}] +set_property PACKAGE_PIN U5 [get_ports {SYSREF_RF_P}] + +############################################################################### +# Pin constraints for the ADCs +############################################################################### + +# ADC Reference Clocks for Slot 0 (DBA) +set_property PACKAGE_PIN AF5 [get_ports {ADC_CLK_P[0]}] +set_property PACKAGE_PIN AF4 [get_ports {ADC_CLK_N[0]}] +set_property PACKAGE_PIN AD5 [get_ports {ADC_CLK_P[1]}] +set_property PACKAGE_PIN AD4 [get_ports {ADC_CLK_N[1]}] + +# ADC Reference Clocks for Slot 1 (DBB) +set_property PACKAGE_PIN AB5 [get_ports {ADC_CLK_P[2]}] +set_property PACKAGE_PIN AB4 [get_ports {ADC_CLK_N[2]}] +set_property PACKAGE_PIN Y5 [get_ports {ADC_CLK_P[3]}] +set_property PACKAGE_PIN Y4 [get_ports {ADC_CLK_N[3]}] + +# ADC Inputs for Slot 0 (DBA) +# Note: numbering here does NOT match schematic, but it is the right order +# according to RF BD Connection spec. +set_property PACKAGE_PIN AH2 [get_ports {DB0_RX_P[3]}] +set_property PACKAGE_PIN AH1 [get_ports {DB0_RX_N[3]}] +set_property PACKAGE_PIN AK2 [get_ports {DB0_RX_P[2]}] +set_property PACKAGE_PIN AK1 [get_ports {DB0_RX_N[2]}] +set_property PACKAGE_PIN AM2 [get_ports {DB0_RX_P[1]}] +set_property PACKAGE_PIN AM1 [get_ports {DB0_RX_N[1]}] +set_property PACKAGE_PIN AP2 [get_ports {DB0_RX_P[0]}] +set_property PACKAGE_PIN AP1 [get_ports {DB0_RX_N[0]}] + +# ADC Inputs for Slot 1 (DBB) +# Note: numbering here does NOT match schematic, but it is the right order +# according to RF BD Connection spec. +set_property PACKAGE_PIN Y2 [get_ports {DB1_RX_P[3]}] +set_property PACKAGE_PIN Y1 [get_ports {DB1_RX_N[3]}] +set_property PACKAGE_PIN AB2 [get_ports {DB1_RX_P[2]}] +set_property PACKAGE_PIN AB1 [get_ports {DB1_RX_N[2]}] +set_property PACKAGE_PIN AD2 [get_ports {DB1_RX_P[1]}] +set_property PACKAGE_PIN AD1 [get_ports {DB1_RX_N[1]}] +set_property PACKAGE_PIN AF2 [get_ports {DB1_RX_P[0]}] +set_property PACKAGE_PIN AF1 [get_ports {DB1_RX_N[0]}] + + +############################################################################### +# Pin constraints for the DACs +############################################################################### + +# DAC Reference Clock for Slot 0 (DBA) +set_property PACKAGE_PIN R5 [get_ports {DAC_CLK_P[0]}] +set_property PACKAGE_PIN R4 [get_ports {DAC_CLK_N[0]}] + +# DAC Reference Clock for Slot 1 (DBB) +set_property PACKAGE_PIN N5 [get_ports {DAC_CLK_P[1]}] +set_property PACKAGE_PIN N4 [get_ports {DAC_CLK_N[1]}] + +# DAC Outputs for Slot 0 (DBA) +set_property PACKAGE_PIN U2 [get_ports {DB0_TX_P[0]}] +set_property PACKAGE_PIN U1 [get_ports {DB0_TX_N[0]}] +set_property PACKAGE_PIN R2 [get_ports {DB0_TX_P[1]}] +set_property PACKAGE_PIN R1 [get_ports {DB0_TX_N[1]}] +set_property PACKAGE_PIN N2 [get_ports {DB0_TX_P[2]}] +set_property PACKAGE_PIN N1 [get_ports {DB0_TX_N[2]}] +set_property PACKAGE_PIN L2 [get_ports {DB0_TX_P[3]}] +set_property PACKAGE_PIN L1 [get_ports {DB0_TX_N[3]}] + +# DAC Outputs for Slot 1 (DBB) +set_property PACKAGE_PIN J2 [get_ports {DB1_TX_P[0]}] +set_property PACKAGE_PIN J1 [get_ports {DB1_TX_N[0]}] +set_property PACKAGE_PIN G2 [get_ports {DB1_TX_P[1]}] +set_property PACKAGE_PIN G1 [get_ports {DB1_TX_N[1]}] +set_property PACKAGE_PIN E2 [get_ports {DB1_TX_P[2]}] +set_property PACKAGE_PIN E1 [get_ports {DB1_TX_N[2]}] +set_property PACKAGE_PIN C2 [get_ports {DB1_TX_P[3]}] +set_property PACKAGE_PIN C1 [get_ports {DB1_TX_N[3]}] diff --git a/top/x400/constraints/pins/x440/db_gpio.xdc b/top/x400/constraints/pins/x440/db_gpio.xdc new file mode 100644 index 0000000..70754ab --- /dev/null +++ b/top/x400/constraints/pins/x440/db_gpio.xdc @@ -0,0 +1,180 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# DB GPIO pin constraints for X440. +# + +############################################################################### +# Pin constraints for the other PL pins (1.8 V) +############################################################################### +set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}] +set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}] +set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}] +set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}] +set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}] +set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}] +set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}] +set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}] +set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}] +set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}] +set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}] +set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}] +set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}] +set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}] +set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}] +set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}] +set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}] +set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}] +set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}] +set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}] + +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[0]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[0]}] +set_property IOB TRUE [get_ports {DB1_GPIO[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[1]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[1]}] +set_property IOB TRUE [get_ports {DB1_GPIO[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[2]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[2]}] +set_property IOB TRUE [get_ports {DB1_GPIO[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[3]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[3]}] +set_property IOB TRUE [get_ports {DB1_GPIO[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[4]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[4]}] +set_property IOB TRUE [get_ports {DB1_GPIO[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[5]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[5]}] +set_property IOB TRUE [get_ports {DB1_GPIO[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[6]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[6]}] +set_property IOB TRUE [get_ports {DB1_GPIO[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[7]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[7]}] +set_property IOB TRUE [get_ports {DB1_GPIO[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[8]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[8]}] +set_property IOB TRUE [get_ports {DB1_GPIO[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[9]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[9]}] +set_property IOB TRUE [get_ports {DB1_GPIO[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[10]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[10]}] +set_property IOB TRUE [get_ports {DB1_GPIO[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[11]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[11]}] +set_property IOB TRUE [get_ports {DB1_GPIO[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[12]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[12]}] +set_property IOB TRUE [get_ports {DB1_GPIO[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[13]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[13]}] +set_property IOB TRUE [get_ports {DB1_GPIO[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[14]}] +set_property PULLUP TRUE [get_ports {DB1_GPIO[14]}] +set_property IOB TRUE [get_ports {DB1_GPIO[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[15]}] +set_property PULLUP TRUE [get_ports {DB1_GPIO[15]}] +set_property IOB TRUE [get_ports {DB1_GPIO[15]}] +# DB1_GPIO[17] connects to D, DB1_GPIO[16] connects to D# +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[16]}] +set_property PULLDOWN FALSE [get_ports {DB1_GPIO[16]}] +set_property SLEW SLOW [get_ports {DB1_GPIO[16]}] +set_property DRIVE 16 [get_ports {DB1_GPIO[16]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[17]}] +set_property PULLDOWN FALSE [get_ports {DB1_GPIO[17]}] +set_property SLEW SLOW [get_ports {DB1_GPIO[17]}] +set_property DRIVE 16 [get_ports {DB1_GPIO[17]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[18]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[18]}] +set_property IOB TRUE [get_ports {DB1_GPIO[18]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[19]}] +set_property PULLDOWN TRUE [get_ports {DB1_GPIO[19]}] +set_property IOB TRUE [get_ports {DB1_GPIO[19]}] + +set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}] +set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}] +set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}] +set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}] +set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}] +set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}] +set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}] +set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}] +set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}] +set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}] +set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}] +set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}] +set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}] +set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}] +set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}] +set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}] +set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}] +set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}] +set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}] +set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[0]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[0]}] +set_property IOB TRUE [get_ports {DB0_GPIO[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[1]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[1]}] +set_property IOB TRUE [get_ports {DB0_GPIO[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[2]}] +set_property PULLUP TRUE [get_ports {DB0_GPIO[2]}] +set_property IOB TRUE [get_ports {DB0_GPIO[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[3]}] +set_property PULLUP TRUE [get_ports {DB0_GPIO[3]}] +set_property IOB TRUE [get_ports {DB0_GPIO[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[4]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[4]}] +set_property IOB TRUE [get_ports {DB0_GPIO[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[5]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[5]}] +set_property IOB TRUE [get_ports {DB0_GPIO[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[6]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[6]}] +set_property IOB TRUE [get_ports {DB0_GPIO[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[7]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[7]}] +set_property IOB TRUE [get_ports {DB0_GPIO[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[8]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[8]}] +set_property IOB TRUE [get_ports {DB0_GPIO[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[9]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[9]}] +set_property IOB TRUE [get_ports {DB0_GPIO[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[10]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[10]}] +set_property IOB TRUE [get_ports {DB0_GPIO[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[11]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[11]}] +set_property IOB TRUE [get_ports {DB0_GPIO[11]}] +# DB0_GPIO[13] connects to D, DB0_GPIO[12] connects to D# +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[12]}] +set_property PULLDOWN FALSE [get_ports {DB0_GPIO[12]}] +set_property SLEW SLOW [get_ports {DB0_GPIO[12]}] +set_property DRIVE 16 [get_ports {DB0_GPIO[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[13]}] +set_property PULLDOWN FALSE [get_ports {DB0_GPIO[13]}] +set_property SLEW SLOW [get_ports {DB0_GPIO[13]}] +set_property DRIVE 16 [get_ports {DB0_GPIO[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[14]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[14]}] +set_property IOB TRUE [get_ports {DB0_GPIO[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[15]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[15]}] +set_property IOB TRUE [get_ports {DB0_GPIO[15]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[16]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[16]}] +set_property IOB TRUE [get_ports {DB0_GPIO[16]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[17]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[17]}] +set_property IOB TRUE [get_ports {DB0_GPIO[17]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[18]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[18]}] +set_property IOB TRUE [get_ports {DB0_GPIO[18]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[19]}] +set_property PULLDOWN TRUE [get_ports {DB0_GPIO[19]}] +set_property IOB TRUE [get_ports {DB0_GPIO[19]}] diff --git a/top/x400/constraints/timing/x440.xdc b/top/x400/constraints/timing/x440.xdc new file mode 100644 index 0000000..a5482b2 --- /dev/null +++ b/top/x400/constraints/timing/x440.xdc @@ -0,0 +1,124 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# Timing constraints exclusive to X440. These should be used +# in conjunction with ./common.xdc +# + +############################################################################### +# DB GPIO +# This interface is defined as system synchronous to pll_ref_clk. +# Some timing constants in this section are declared in +# /fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc +############################################################################### + +# In the current db_gpio_interface implementation, all GPIOs are received asynchronously +# by the DB, so we add a very relax constraint for these signals. +set db_gpio_min 0 +set db_gpio_max [expr {$pll_ref_clk_period/2}] +set db_gpio_sync_max 3.500 + +# Set constraints for all ports. +set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}] +set db_gpio_sync_ports [get_ports {DB0_GPIO[12] DB0_GPIO[13] DB1_GPIO[16] DB1_GPIO[17]}] + +set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_min $db_gpio_ports +set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_max $db_gpio_ports +# Should just overwrite the setting for the sync clock ports that are also in db_gpio_ports +set_output_delay -clock [get_clocks ref_clk] -max $db_gpio_sync_max $db_gpio_sync_ports + +set_input_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_min $db_gpio_ports +set_input_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_max $db_gpio_ports + +# Use multi cycle path constraint to relax timing on these pins. +set_multicycle_path -setup 2 -from [get_pins db_gpio_gen[*].db_gpio_interface_i/ctrlport_to_i2c_inst/i2c_master/byte_controller/bit_controller/*_oen_reg/C] +set_multicycle_path -end -hold 7 -from [get_pins db_gpio_gen[*].db_gpio_interface_i/ctrlport_to_i2c_inst/i2c_master/byte_controller/bit_controller/*_oen_reg/C] +############################################################################### +# x440_ps_rfdc_bd +############################################################################### + +# This property tells Vivado that we require these clocks to be well aligned. +# We have synchronous clock domain crossings between these clocks that can have +# large hold violations after placement due to uneven clock loading. +set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk_2x ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk ||\ + NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk_2x \ +}] + +# We treat rfdc_clk buffers as asynchronous, with knowledge that +# code clocked in this domain will be reset after this clocked is enabled. This +# will make timing easier to meet on these clock domains. +set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg1x*/C}] \ + -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_1x_buf/*BUFGCE*/CE}] + +set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg2x*/C}] \ + -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_2x_buf/*BUFGCE*/CE}] + +set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg1x*/C}] \ + -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_1x_buf/*BUFGCE*/CE}] + +set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg2x*/C}] \ + -to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_2x_buf/*BUFGCE*/CE}] + + +############################################################################### +# SPLL SYSREF Capture +############################################################################### + +# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces +# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both +# SYSREF and PLL reference clock are directly fed into the RFSoC. +# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC +# output) with a double synchronizer and then transfered to the RFDC clock +# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for +# sync. purposes. +# SYSREF is a continuous signal intentionally shifted in the LMK chip to align +# it closer to the PRC's falling edge. +# The highest PRC frequency supported in MPM (64 MHz) is used for +# timing constraints. Therefore, SYSREF LMK's delay = (1/64e6)/2. +set sysref_lmk_delay 7.8125 +# +# These are the signals' lengths and corresponding delays (assuming 170 ps/in): +# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns +# - PRC --> 5668 mils (5.668 inches) = 0.964 ns +# +# For min/max input delay calculations, it is assumed min prop. delay of 0 ns, +# which essentially over-constrains SYSREF. +# +# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is +# calculated as follows: +# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max) +# - PRC prop. delay (min) +set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}] +# +# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it +# is calculated as follows: +# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min) +# - PRC prop. delay (min) +set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}] + +set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}] +set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}] + +############################################################################### +# SPI to MB CPLD (PL) +# This interface is defined as system synchronous to pll_ref_clk. +############################################################################### + +# The output delays are chosen to allow a large time window of valid data for +# the MB CPLD logic. +set spi_min_out_delay -1.500 +set spi_max_out_delay 9.500 + +# Set output constraints for all ports. +set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}] +set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports +set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports diff --git a/top/x400/constraints/timing/x440_clocks.xdc b/top/x400/constraints/timing/x440_clocks.xdc new file mode 100644 index 0000000..62faaf6 --- /dev/null +++ b/top/x400/constraints/timing/x440_clocks.xdc @@ -0,0 +1,37 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# Clock definition constraints for X440 +# + +############################################################################### +# MMCM-Related Clocks +# +# Note: Vivado will create generated clocks based on the default MMCM settings +# configured in the clocking wizard, but we are going to dynamically change +# those clocks, and so we need to provide worst-case values in here. +############################################################################### + +# PLL Reference Clock (PRC) input. This goes from the LMK straight to the MMCM +# input, and is used to generate the internal PRC as well as RFDC/data clocks. +set pll_ref_clk_in_period 15.625 +create_clock -name pll_ref_in_clk -period $pll_ref_clk_in_period [get_ports PLL_REFCLK_FPGA_P] + +# Internal PLL Reference Clock (PRC). Used to derive data clocks. Constrain to +# the fastest possible clock rate supported in the driver. +set pll_ref_clk_period 15.625 +create_clock -name pll_ref_clk \ + -period $pll_ref_clk_period \ + [get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT0] + +############################################################################### +# Generated Clocks +############################################################################### + +create_generated_clock -name sync_ref_clk \ + -source [get_ports BASE_REFCLK_FPGA_P] \ + -divide_by 2 [get_pins clock_div_5mhz/clk_out_reg/Q] + diff --git a/top/x400/constraints/timing/x440_clocks_1600.xdc b/top/x400/constraints/timing/x440_clocks_1600.xdc new file mode 100644 index 0000000..b5bac95 --- /dev/null +++ b/top/x400/constraints/timing/x440_clocks_1600.xdc @@ -0,0 +1,20 @@ +# +# Copyright 2023 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# Clock definition constraints for X440 1600 type images +# + +# Data clocks: Generated by the MMCM, used for data paths between the RFDC output +# and RFNoC. Maximum supported master clock rate is 2.048 Gsps @8SPC => 256 MHz. +set rfdc_data_clk_period 3.906 + +create_clock -name rfdc_r0_clk -add \ + -period $rfdc_data_clk_period \ + [get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2] +create_clock -name rfdc_r1_clk -add \ + -period $rfdc_data_clk_period \ + [get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5] + diff --git a/top/x400/constraints/timing/x440_clocks_400.xdc b/top/x400/constraints/timing/x440_clocks_400.xdc new file mode 100644 index 0000000..52a7bdf --- /dev/null +++ b/top/x400/constraints/timing/x440_clocks_400.xdc @@ -0,0 +1,21 @@ +# +# Copyright 2023 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# Clock definition constraints for X440 400 type images +# + +# Data clocks: Generated by the MMCM, used for data paths between the RFDC output +# and RFNoC. Maximum supported master clock rate is 500 Msps @8SPC => 62.5 MHz. +# Theoretical maximum converter rate is 4.096 GSps, so really, 512 Msps @ 8SPC => 64 MHz. +set rfdc_data_clk_period 15.625 + +create_clock -name rfdc_r0_clk -add \ + -period $rfdc_data_clk_period \ + [get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2] +create_clock -name rfdc_r1_clk -add \ + -period $rfdc_data_clk_period \ + [get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5] + diff --git a/top/x400/cpld/Makefile b/top/x400/cpld/Makefile index 4224d11..eef3037 100644 --- a/top/x400/cpld/Makefile +++ b/top/x400/cpld/Makefile @@ -22,11 +22,14 @@ 10M08_ID = "10M08SAU169I7G" # Project directories +X440_DIR = $(abspath ./x440) X410_DIR = $(abspath ./x410) # Target specific variables X410_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 PROJECT_DIR=$(X410_DIR) X410=1 X410_CPLD_10M08: DEFS = VARIANT_`echo $(10M08_ID) | cut -c1-5`=1 PROJECT_DIR=$(X410_DIR) X410=1 +X440_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 PROJECT_DIR=$(X440_DIR) X440=1 +X440_CPLD_10M08: DEFS = VARIANT_`echo $(10M08_ID) | cut -c1-5`=1 PROJECT_DIR=$(X440_DIR) X440=1 X410_CPLD_MFG_10M08: DEFS = VARIANT_`echo $(10M08_ID) | cut -c1-5`=1 MFG_SUPPORT=1 PROJECT_DIR=$(X410_DIR) @@ -61,7 +64,7 @@ endif ##Supported Targets ##----------------- -all: X410_CPLD_10M04 X410_CPLD_10M08 ##(Default target) +all: X410_CPLD_10M04 X410_CPLD_10M08 X440_CPLD_10M04 X440_CPLD_10M08 ##(Default target) ##X410_CPLD_10M04: Motherboard CPLD targeted to 10M04SAU169I7G. X410_CPLD_10M04: @@ -73,6 +76,16 @@ X410_CPLD_10M08: $(call quartus_build,$(10M08_ID),$(DEFS)) $(call post_build,"usrp_x410_cpld_`echo $(10M08_ID) | cut -c1-5 | tr A-Z a-z`") +##X440_CPLD_10M08: Motherboard CPLD targeted to 10M04SAU169I7G. +X440_CPLD_10M04: + $(call quartus_build,$(10M04_ID),$(DEFS)) + $(call post_build,"usrp_x440_cpld_`echo $(10M04_ID) | cut -c1-5 | tr A-Z a-z`") + +##X440_CPLD_10M08: Motherboard CPLD targeted to 10M08SAU169I7G. +X440_CPLD_10M08: + $(call quartus_build,$(10M08_ID),$(DEFS)) + $(call post_build,"usrp_x440_cpld_`echo $(10M08_ID) | cut -c1-5 | tr A-Z a-z`") + X410_CPLD_IP: ##Build IPs only, needed for simulation. @# Building only X410_CPLD_10M04 IP $(call quartus_ip,$(10M04_ID),$(DEFS)) diff --git a/top/x400/cpld/common/pl_cpld_regs.v b/top/x400/cpld/common/pl_cpld_regs.v index 0640b50..96e5a1b 100644 --- a/top/x400/cpld/common/pl_cpld_regs.v +++ b/top/x400/cpld/common/pl_cpld_regs.v @@ -47,6 +47,8 @@ module pl_cpld_regs #( `ifdef X410 `include "../regmap/x410/constants_regmap_utils.vh" + `else + `include "../regmap/x440/constants_regmap_utils.vh" `endif `include "../regmap/pl_cpld_base_regmap_utils.vh" `include "../../../../lib/rfnoc/core/ctrlport.vh" diff --git a/top/x400/cpld/common/ps_cpld_regs.v b/top/x400/cpld/common/ps_cpld_regs.v index d09c499..88e1697 100644 --- a/top/x400/cpld/common/ps_cpld_regs.v +++ b/top/x400/cpld/common/ps_cpld_regs.v @@ -47,6 +47,8 @@ module ps_cpld_regs #( ); `ifdef X410 `include "../regmap/x410/constants_regmap_utils.vh" +`else +`include "../regmap/x440/constants_regmap_utils.vh" `endif `include "../regmap/ps_cpld_base_regmap_utils.vh" `include "../../../../lib/rfnoc/core/ctrlport.vh" diff --git a/top/x400/cpld/ctrlport_to_jtag.v b/top/x400/cpld/ctrlport_to_jtag.v deleted file mode 100644 index dedc66e..0000000 --- a/top/x400/cpld/ctrlport_to_jtag.v +++ /dev/null @@ -1,275 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: ctrlport_to_jtag -// -// Description: -// -// This module wraps a JTAG master and provides a ControlPort slave -// interface. -// -// Parameters: -// -// BASE_ADDRESS : Base address for CtrlPort registers -// DEFAULT_PRESCALAR : Default clock divider to use -// - -`default_nettype none - - -module ctrlport_to_jtag #( - parameter BASE_ADDRESS = 0, - parameter DEFAULT_PRESCALAR = 0 -) ( - //--------------------------------------------------------------------------- - // ControlPort Slave - //--------------------------------------------------------------------------- - - input wire ctrlport_clk, - input wire ctrlport_rst, - - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [31:0] s_ctrlport_req_data, - output reg s_ctrlport_resp_ack, - - output reg [ 1:0] s_ctrlport_resp_status = 0, - output reg [31:0] s_ctrlport_resp_data = 0, - - //--------------------------------------------------------------------------- - // JTAG Signals - //--------------------------------------------------------------------------- - - output wire tck, - output wire tdi, - input wire tdo, - output wire tms -); - - `include "../../../lib/rfnoc/core/ctrlport.vh" - `include "./regmap/jtag_regmap_utils.vh" - - //--------------------------------------------------------------------------- - // Local Registers - //--------------------------------------------------------------------------- - - reg [ TX_DATA_SIZE-1:0] tx_data_reg; - reg [ STB_DATA_SIZE-1:0] stb_data_reg; - reg [PRESCALAR_SIZE-1:0] prescalar_reg = DEFAULT_PRESCALAR; - reg [ LENGTH_SIZE-1:0] length_reg; - reg start_reg; - reg soft_rst_stb_reg; - - //--------------------------------------------------------------------------- - // Readback Signals from JTAG Master - //--------------------------------------------------------------------------- - - wire [31:0] rd_data; - wire ready; - - //--------------------------------------------------------------------------- - // Handling of CtrlPort - //--------------------------------------------------------------------------- - - localparam NUM_ADDRESSES = 32; - wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && - (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES); - wire soft_rst_requested = (s_ctrlport_req_addr == BASE_ADDRESS + CONTROL) && - (s_ctrlport_req_data[RESET] == 1'b1); - - always @(posedge ctrlport_clk) begin - // Reset internal registers and responses - if (ctrlport_rst) begin - tx_data_reg <= {TX_DATA_SIZE {1'b0}}; - stb_data_reg <= {STB_DATA_SIZE {1'b0}}; - prescalar_reg <= DEFAULT_PRESCALAR; - length_reg <= {LENGTH_SIZE {1'b0}}; - start_reg <= 1'b0; - soft_rst_stb_reg <= 1'b0; - s_ctrlport_resp_ack <= 1'b0; - - end else begin - // Request independent default assignments - start_reg <= 1'b0; - soft_rst_stb_reg <= 1'b0; // self-clearing strobe - - // Write requests - if (s_ctrlport_req_wr) begin - // Always issue an ack and no data - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_data <= {CTRLPORT_DATA_W{1'bx}}; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - // Process write requests only in case ready is asserted because JTAG - // module requires these values to be stable when it is not ready. - // - // The one exception is when a soft-reset is requested to reset the - // bitq_fsm, in that case that is a valid write. - if (soft_rst_requested) begin - soft_rst_stb_reg <= 1'b1; - - end else if (ready) begin - case (s_ctrlport_req_addr) - BASE_ADDRESS + TX_DATA: begin - tx_data_reg <= s_ctrlport_req_data; - end - - BASE_ADDRESS + STB_DATA: begin - stb_data_reg <= s_ctrlport_req_data; - end - - BASE_ADDRESS + CONTROL: begin - length_reg <= s_ctrlport_req_data[LENGTH_MSB:LENGTH]; - prescalar_reg <= s_ctrlport_req_data[PRESCALAR_MSB:PRESCALAR]; - // When the RESET bit is high, a soft-reset (i.e. no start strobe) - // must take place, which is handled by the default assignment. - // Otherwise, if the RESET bit is low, a start strobe should be - // issued, triggering a transaction. - start_reg <= (s_ctrlport_req_data[RESET] == 1'b0); - end - - // Error on undefined address - default: begin - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // Error in case ready is not asserted - end else begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - end - - // Read requests - end else if (s_ctrlport_req_rd) begin - // Default assumption: valid request - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + RX_DATA: begin - s_ctrlport_resp_data <= rd_data; - end - - BASE_ADDRESS + CONTROL: begin - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}}; - s_ctrlport_resp_data[LENGTH_MSB:LENGTH] <= length_reg; - s_ctrlport_resp_data[PRESCALAR_MSB:PRESCALAR] <= prescalar_reg; - s_ctrlport_resp_data[READY] <= ready; - end - - // Error on undefined address - default: begin - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}}; - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // No request - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - end - - //--------------------------------------------------------------------------- - // JTAG Master - //--------------------------------------------------------------------------- - - // bitq_fsm reset is asserted by either the ctrlport_rst or the soft-reset - // strobe triggered through software. - wire bitq_resetn = ~(ctrlport_rst | soft_rst_stb_reg); - - bitq_fsm #( - .IDLE_VALUE (1'b0) - ) jtag_master ( - .clk (ctrlport_clk), - .rstn (bitq_resetn), - .prescalar (prescalar_reg), - .bit_clk (tck), - .bit_in (tdo), - .bit_out (tdi), - .bit_stb (tms), - .start (start_reg), - .ready (ready), - .len (length_reg), - .wr_data (tx_data_reg), - .stb_data (stb_data_reg), - .rd_data (rd_data) - ); - -endmodule - - -`default_nettype wire - - -//XmlParse xml_on -// -// -// -// -// This register map is present for each JTAG module. -// -// Basic operation would be: -// -// - poll @.ready until asserted -// - write / read data -// - write @.CONTROL register along with @.reset deasserted to start a transaction -// -// For resetting the BITQ FSM, simply assert @.reset. -// -// This operation seems a little strange, but it is what the axi_bitq driver -// expects. This behavior has been implemented in previous products. -// -// -// -// -// Data to be transmitted (TDI) -// -// -// -// Data to be transmitted (TMS) -// -// -// -// JTAG module status and control -// -// Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value. -// -// -// (Number of bits - 1) to be transferred -// -// -// When asserted ('1') a soft-reset for the bitq FSM is triggered, -// preventing any transactions to take place. -// -// Deassert this bit, along with values for @.prescalar and @.length -// to trigger a new transaction (start strobe). -// -// -// Bitq FSM is ready for input (no data transmission in progress). -// -// -// -// -// Received data (TDO) -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/cpld/ctrlport_to_spi.v b/top/x400/cpld/ctrlport_to_spi.v deleted file mode 100644 index d4b72a7..0000000 --- a/top/x400/cpld/ctrlport_to_spi.v +++ /dev/null @@ -1,276 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: ctrlport_to_spi -// -// Description: -// -// This module wraps a SPI master and provides a ControlPort interface. -// -// Parameters: -// -// BASE_ADDRESS : Base address for CtrlPort registers. -// - -`default_nettype none - - -module ctrlport_to_spi #( - parameter BASE_ADDRESS = 0 -) ( - //--------------------------------------------------------------- - // ControlPort Slave - //--------------------------------------------------------------- - - input wire ctrlport_clk, - input wire ctrlport_rst, - - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [31:0] s_ctrlport_req_data, - - output reg s_ctrlport_resp_ack, - output reg [ 1:0] s_ctrlport_resp_status = 0, - output reg [31:0] s_ctrlport_resp_data = 0, - - //--------------------------------------------------------------- - // SPI Signals - //--------------------------------------------------------------- - - output wire sclk, - output wire mosi, - output wire [15:0] ss, - input wire miso -); - - `include "../../../lib/rfnoc/core/ctrlport.vh" - `include "./regmap/spi_regmap_utils.vh" - - //--------------------------------------------------------------- - // Translating CtrlPort <-> Wishbone - //--------------------------------------------------------------- - - reg wb_cyc_i; // Active bus cycle - reg wb_we_i = 1'b0; // Write access - reg [ 4:0] wb_adr_i = 5'b0; - reg [31:0] wb_dat_i = 32'b0; - wire wb_ack_o; - wire [31:0] wb_dat_o; - wire wb_err_o; - - // Check for address to be in range [base_addr..base_addr+32) - localparam NUM_ADDRESSES = 32; - wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && - (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES); - - // Following chapter 3.2.3 (classic standard SINGLE WRITE cycle) of - // https://cdn.opencores.org/downloads/wbspec_b4.pdf - always @(posedge ctrlport_clk) begin - // Reset internal registers and responses - if (ctrlport_rst) begin - wb_cyc_i <= 1'b0; - s_ctrlport_resp_ack <= 1'b0; - - end else begin - // Request independent default assignments - s_ctrlport_resp_ack <= 1'b0; - - // Wait for ack on active bus transactions - if (wb_cyc_i) begin - if (wb_ack_o) begin - // End bus cycle and generate response - wb_cyc_i <= 1'b0; - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_data <= wb_dat_o; - - if (wb_err_o) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - end else begin - s_ctrlport_resp_status <= CTRL_STS_OKAY; - end - end - - // Write requests - end else if (s_ctrlport_req_wr) begin - // Assume there is a valid address - wb_cyc_i <= 1'b1; - wb_we_i <= 1'b1; - wb_dat_i <= s_ctrlport_req_data; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + TX_DATA_LOW: begin - wb_adr_i <= 5'h00; - end - - BASE_ADDRESS + TX_DATA_HIGH: begin - wb_adr_i <= 5'h04; - end - - BASE_ADDRESS + CONTROL: begin - wb_adr_i <= 5'h10; - end - - BASE_ADDRESS + CLOCK_DIVIDER: begin - wb_adr_i <= 5'h14; - end - - BASE_ADDRESS + SLAVE_SELECT: begin - wb_adr_i <= 5'h18; - end - - // Error on undefined address - default: begin - wb_cyc_i <= 1'b0; - - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // Read requests - end else if (s_ctrlport_req_rd) begin - // Assume there is a valid address - wb_cyc_i <= 1'b1; - wb_we_i <= 1'b0; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + RX_DATA_LOW: begin - wb_adr_i <= 5'h00; - end - - BASE_ADDRESS + RX_DATA_HIGH: begin - wb_adr_i <= 5'h04; - end - - BASE_ADDRESS + CONTROL: begin - wb_adr_i <= 5'h10; - end - - BASE_ADDRESS + CLOCK_DIVIDER: begin - wb_adr_i <= 5'h14; - end - - BASE_ADDRESS + SLAVE_SELECT: begin - wb_adr_i <= 5'h18; - end - - // Error on undefined address - default: begin - wb_cyc_i <= 1'b0; - - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // No request - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - end - - //--------------------------------------------------------------- - // SPI Master - //--------------------------------------------------------------- - - spi_top spi_master ( - .wb_clk_i (ctrlport_clk), - .wb_rst_i (ctrlport_rst), - .wb_adr_i (wb_adr_i), - .wb_dat_i (wb_dat_i), - .wb_dat_o (wb_dat_o), - .wb_sel_i (4'hF), - .wb_we_i (wb_we_i), - .wb_stb_i (wb_cyc_i), - .wb_cyc_i (wb_cyc_i), - .wb_ack_o (wb_ack_o), - .wb_err_o (wb_err_o), - .wb_int_o (), - .ss_pad_o (ss), - .sclk_pad_o (sclk), - .mosi_pad_o (mosi), - .miso_pad_i (miso) - ); - -endmodule - - -`default_nettype wire - - -//XmlParse xml_on -// -// -// -// -// This register map is present for each SPI master. -// -// For information about the register content and the way to interact with the core see the -// documentation -// of the SPI master from opencores used internally. -// -// The core is configured to operate with 16 slave signal signals, up to 128 bits per transmission and 8 bit clock divider. -// Only 64 bits of data are available via this register interface. -// -// For the different SPI modes use the following table to derive the bits in @.CONTROL register. Only option 0 (CPOL=0, CPHA=0) has been tested. -// -//| CPOL | CPHA | TX_NEG | RX_NEG | -//| ------- | -------- | -------- | ------- | -//| 0 | 0 | 1 | 0 | -//| 0 | 1 | 0 | 1 | -//| 1 | 0 | 0 | 1 | -//| 1 | 1 | 1 | 0 | -// -// -// -// Lower 32 bits of the received word. (RxWord[31:0]) -// -// -// -// Higher 32 bits of the received word. (RxWord[63:32]) -// -// -// -// Lower 32 bits of the received word. (TxWord[31:0]) -// -// -// -// Higher 32 bits of the received word. (TxWord[63:32]) -// -// -// -// Control register -// - -// -// -// -// Clock Divider. -// -// -// -// -// -// -// Slave select. -// -// -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/cpld/db_spi_shared_constants.sdc b/top/x400/cpld/db_spi_shared_constants.sdc deleted file mode 100644 index 21935c2..0000000 --- a/top/x400/cpld/db_spi_shared_constants.sdc +++ /dev/null @@ -1,20 +0,0 @@ -# -# Copyright 2021 Ettus Research, a National Instruments Brand -# -# SPDX-License-Identifier: LGPL-3.0-or-later -# -# Description: -# -# Timing constants for the MB CPLD <-> DB CPLD SPI interface -# - -# Delays are rounded to integer values which leave a slack of >1ns on each setup -# and hold path without requirement for adding hold delays (as reported -# by Quartus fitter report). -# The signal might change before the SCLK edge as the internal -# registers are driven by PLL reference clock rather than the SPI clock used -# for the port timing constaints. -set db_cpld_spi_max_out 14.000 -set db_cpld_spi_min_out 2.000 -set db_cpld_spi_max_in 2.000 -set db_cpld_spi_min_in -2.000 diff --git a/top/x400/cpld/mb_cpld.sdc b/top/x400/cpld/mb_cpld.sdc deleted file mode 100644 index af291a9..0000000 --- a/top/x400/cpld/mb_cpld.sdc +++ /dev/null @@ -1,689 +0,0 @@ -# -# Copyright 2021 Ettus Research, a National Instruments Brand -# -# SPDX-License-Identifier: LGPL-3.0-or-later -# -# Description: -# -# Timing constraints for the X4xx's motherboard CPLD. -# - -set_time_format -unit ns -decimal_places 3 - -##################################################################### -# General -##################################################################### -# For a couple of 3.3V interfaces the buffer SN74AVC4T774RSVR is used to -# increase the drive strength. For reuse we define the timings constants here. -# For direction A to B and B to A the maximum timing varies by 0.1 ns. Taking -# the maximum of both. -set buffer_prop_min 0.100 -set buffer_prop_max 2.400 - -##################################################################### -# Main Clocks -##################################################################### -## Input clocks. -# Reliable clock: 100.0 MHz -set CLK_100_period 10.000 -create_clock -name CLK_100 -period $CLK_100_period [get_ports CLK_100] - -# internal PLL derived clock -derive_pll_clocks -# provide name for derived clocks -set CLK_250 [get_clocks {*clk[1]}] - -# PLL output pins of the generated 50 MHz clock for internal processing -set clk50_period 20.000 -set pll_clk_out_pin [get_pins {pll_inst|altpll_component|auto_generated|pll1|clk[0]}] - -set clk250_period 4.000 - -# PLL reference clock: 64 MHz (maximum) -set prc_clock_period 15.625 -create_clock -name PLL_REF_CLK -period $prc_clock_period [get_ports PLL_REF_CLK] - -##################################################################### -# Timing exceptions -##################################################################### -## SPI slaves -# Delay path for all synchronizers is based on the period of the -# faster clock domain (50 MHz derived by the PLL from 100 MHz reliable clock). -set clk50_period [expr {$CLK_100_period * 2}] - -set_max_delay -to [get_registers *synchronizer_false_path\|value\[0\]\[*\]] \ - $clk50_period - -# sclk data to CLK_100 -set_max_delay -from [get_registers *spi_slave_async\|received_word\[*\]] \ - -to [get_registers *spi_slave_async\|data_out\[*\]] \ - $clk50_period -# PLL driven data to sclk -set_max_delay -from [get_clocks {pll_inst*}] \ - -to [get_registers *spi_slave_async\|transmit_bits\[*\]] \ - $clk50_period - -##################################################################### -# JTAG to daughterboards -##################################################################### -# Use the worst-case board propagation delays. -# Assuming 170.0 ps/in and usage of X410 DB. -# Longest trace | Trace length | Trace delay -# TDI to DB 0 | 7.625 in | 1.296 ns -# -------------------------------------------- - -# JTAG parameters -# see https://www.intel.com/content/www/us/en/programmable/documentation/mcn1397700832153.html#mcn1399899915639 -set db_jtag_board_delay 1.296 -set db_jtag_setup 3.000 -set db_jtag_hold 10.000 -set db_jtag_clk_to_out 20.000 - -set db0_jtag_outputs [get_ports {DB_JTAG_TDI[0] DB_JTAG_TMS[0]}] -set db0_jtag_inputs [get_ports {DB_JTAG_TDO[0]}] -set db1_jtag_outputs [get_ports {DB_JTAG_TDI[1] DB_JTAG_TMS[1]}] -set db1_jtag_inputs [get_ports {DB_JTAG_TDO[1]}] - -##### DB 0 ##### -# generated jtag clock is at least divided by 4 -# max JTAG clock rate = 20 MHz -# source clock rate = 50 MHz -# only even dividers -> minimum value = 4 -set db0_jtag_clk_register [get_registers {ctrlport_to_jtag:db0_jtag|bitq_fsm:jtag_master|bitq_state.HIGH}] -create_generated_clock -source $pll_clk_out_pin \ - -name db0_jtag_clk $db0_jtag_clk_register \ - -divide_by 4 - -# see White Rabbit DAC for futher explanation -set_false_path -from $db0_jtag_clk_register -to $db0_jtag_clk_register - -create_generated_clock \ - -source $db0_jtag_clk_register \ - -name db0_jtag_out_clk [get_ports {DB_JTAG_TCK[0]}] - -set_output_delay -clock db0_jtag_out_clk \ - -max [expr {$db_jtag_setup + $db_jtag_board_delay + $buffer_prop_max}] \ - $db0_jtag_outputs -set_output_delay -clock db0_jtag_out_clk \ - -min [expr {-$db_jtag_hold - $db_jtag_board_delay - $buffer_prop_min}] \ - $db0_jtag_outputs -# data is driven on CPLD on falling edge, which is 2 clock cycles ahead -# of the latch edge -set_multicycle_path -setup -start -to $db0_jtag_outputs 2 -set_multicycle_path -hold -start -to $db0_jtag_outputs 3 - -# maximum delay accounts for slow clock and data propagation as -# well as clock to out time -set_input_delay -clock_fall -clock db0_jtag_out_clk \ - -max [expr {$db_jtag_clk_to_out + 2*$db_jtag_board_delay + 2*$buffer_prop_max}] \ - $db0_jtag_inputs -# worst-case everything changes immediatelly -set_input_delay -clock_fall -clock db0_jtag_out_clk \ - -min [expr {2*$buffer_prop_min}] \ - $db0_jtag_inputs -set_multicycle_path -setup -end -from $db0_jtag_inputs 2 -set_multicycle_path -hold -end -from $db0_jtag_inputs 3 - -##### DB 1 ##### -# generated jtag clock is at least divided by 4 -set db1_jtag_clk_register [get_registers {ctrlport_to_jtag:db1_jtag|bitq_fsm:jtag_master|bitq_state.HIGH}] -create_generated_clock -source $pll_clk_out_pin \ - -name db1_jtag_clk $db1_jtag_clk_register \ - -divide_by 4 -# see White Rabbit DAC for futher explanation -set_false_path -from $db1_jtag_clk_register -to $db1_jtag_clk_register -create_generated_clock \ - -source $db1_jtag_clk_register \ - -name db1_jtag_out_clk [get_ports {DB_JTAG_TCK[1]}] - -set_output_delay -clock db1_jtag_out_clk \ - -max [expr {$db_jtag_setup + $db_jtag_board_delay + $buffer_prop_max}] \ - $db1_jtag_outputs -set_output_delay -clock db1_jtag_out_clk \ - -min [expr {-$db_jtag_hold - $db_jtag_board_delay - $buffer_prop_min}] \ - $db1_jtag_outputs -set_multicycle_path -setup -start -to $db1_jtag_outputs 2 -set_multicycle_path -hold -start -to $db1_jtag_outputs 3 - -# maximum delay accounts for slow clock and data propagation as -# well as clock to out time -set_input_delay -clock_fall -clock db1_jtag_out_clk \ - -max [expr {$db_jtag_clk_to_out + 2*$db_jtag_board_delay + 2*$buffer_prop_max}] \ - $db1_jtag_inputs -# ideally everything changes immediatelly -set_input_delay -clock_fall -clock db1_jtag_out_clk \ - -min [expr {2*$buffer_prop_min}] \ - $db1_jtag_inputs -set_multicycle_path -setup -end -from $db1_jtag_inputs 2 -set_multicycle_path -hold -end -from $db1_jtag_inputs 3 - -##################################################################### -# FPGA <-> MB CPLD PL SPI interface -##################################################################### -# Create clock for the PL's SPI interface. -# PRC at least divided by 2 by the SPI Master on FPGA -set pl_sclk_period [expr {2 * $prc_clock_period}] -create_clock -name pl_sclk -period $pl_sclk_period [get_registers mb_cpld_sclk] - -# The SPI PL master (on the FPGA) is designed as a system synchronous -# interface using PLL_REF_CLK. -# The FPGA output constraints are required to calculate the windows -# at CPLD of valid data -# They are derived iteratively from the FPGA design ensuring a large -# valid data period. -set pl_spi_fpga_min_out 0.000 -set pl_spi_fpga_max_out 11.000 - -# The longest trace on the PL SPI interface is (sssuming 170.0 ps/in) -# Longest trace | Trace length | Trace delay -# CS_0 | 7.143 in | 1.215 ns -set pl_spi_board_delay 1.215 - -# This path also contains a level translator which has a typical -# switching time of 2.7 ns. Let's add a margin of 1 ns as worst -# case estimation -set pl_level_trans_delay 3.700 - -# CPLD and FPGA both use PLL reference clock from a common clock chip. -# The traces from that clock chip to the ICs are not length matched -# Assume a worst case clock difference of 0.5 ns at the IC inputs. -# There is no direction defined. The clock can arrive faster or slower -# on one IC. -set pl_clock_diff 0.500 - -set pl_slave_inputs [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS_N[*]}] -# calculate output delays back from capturing edge, add board delay, level translator and clock difference -set_input_delay -clock PLL_REF_CLK \ - -max [expr {$prc_clock_period - $pl_spi_fpga_max_out + $pl_spi_board_delay + $pl_level_trans_delay + $pl_clock_diff}] \ - $pl_slave_inputs -# Assuming data is going without any delay, clock is arriving early at CPLD. -# Negate minimum output delay as it is defined from the change to the start clock edge. -set_input_delay -clock PLL_REF_CLK \ - -min [expr {- $pl_spi_fpga_min_out - $pl_clock_diff}] \ - $pl_slave_inputs - -# ensure large data valid window for the FPGA -# those values are used in the FPGA / DB CPLDs -# to calculate the input delay -# those values are maximum integer values to still meet timing -set pl_spi_cpld_min_out -1.000 -set pl_spi_cpld_max_out 8.000 - -set pl_slave_outputs [get_ports {PL_CPLD_MISO}] -set_output_delay -clock PLL_REF_CLK -max $pl_spi_cpld_max_out $pl_slave_outputs -set_output_delay -clock PLL_REF_CLK -min $pl_spi_cpld_min_out $pl_slave_outputs - -##################################################################### -# DB clock and reset -##################################################################### -# Output clocks for the daughterboards (SPI control) -create_generated_clock -source $pll_clk_out_pin \ - -name db0_ref_clk [get_ports {DB_REF_CLK[0]}] -create_generated_clock -source $pll_clk_out_pin \ - -name db1_ref_clk [get_ports {DB_REF_CLK[1]}] - -# output reset within one clock period -set_max_delay -to [get_ports {DB_ARST[0] DB_ARST[1]}] $CLK_100_period -set_min_delay -to [get_ports {DB_ARST[0] DB_ARST[1]}] 0 - -##################################################################### -# DB SPI interfaces -##################################################################### -# --------- ----------------- ----------------- -# FPGA | CS/SCLK/ | MB CPLD | | DB | -# |-- MOSI ->|--------> R1 ->|--------->| | -# SPI | | | | SPI | -# master |<- MISO --|<- R2 <--------|<---------| slave | -# --------- ----------------- ----------------- -# -# The output clocks are derived from the PLL reference clock (PRC). The SCLK -# edges are aligned with the rising edge of PLL reference clock. There are two -# registers R1 and R2 in the SPI path between FPGA and DB. -# For the transmission of data from master to slave those registers are -# transparent. The overall reception is just delayed by 1 PLL reference clock -# cycle. In the other direction the MISO timing is different. The falling edge -# of SCLK is used for changing the data signals. The propagation of this signal -# to the DB is delayed by 1 PLL reference clock period because of register R1. -# The MISO signal is captured on the rising edge of SCLK on the FPGA. Register -# R2 in the MB CPLD changes the timing in a way that MISO has to be stable on -# the rising edge of PLL reference clock before the SCLK rising edge. -# Additionally a minimum of two PLL reference clock cycles are required for -# processing in the SPI slave. The number of processing cycles is denoted by n. - -# Here is an example for n=2 and SPI bus with CPHA=0 and CPOL=0. -# Data is driven on the falling edge and captured on the rising edge of the -# clock signal. The falling edge of the SCLK@DB is delayed by a clock cycle -# because of R1. The FPGA as SPI master is capturing the data on the rising edge -# of SCLK. The register R2 on the MB CPLD is capturing the data one clock cycle -# earlier. Therefore MISO has to be stable one clock cycle earlier then the -# original SCLK at the MB CPLD input. The effective SCLK signal to use for the -# timing constraints of the DB therefore has a low period which is reduced by 2 -# clock cycles (R1 + R2) of PLL reference clock. It still has the same period as -# SCLK. In this example the low period would be 2 PRC cycles and the high period -# would be 6 PRC cycles. -# The following waveform illustrates the timing for n=2. Based on the defined -# delays denotes the time when the signal is not stable. -# -# <--- R1 --->|<-------- n=2 -------->|<--- R2 ---> -# PRC ___/-----\_____/-----\_____/-----\_____/-----\_____/---- -# SCLK ---\_______________________________________________/---- -# SCLK @ DB (ideal) ---------------\________________________________________ -# SCLK @ DB (effective) ---------------\_______________________/---------------- -# MOSI output @ MB CPLD -------------------------------------------------- -# MISO input @ MB CPLD -------------------------------------------------- -# DB propagation and processing <---------> -# MOSI change @ FPGA ^ -# MOSI change @ MB CPLD ^ -# MISO capture @ MB CPLD ^ -# MISO capture @ FPGA ^ -# -# Although the delays are defined based on PLL reference clock the SPI bus clock -# must be divided by at least n+2, where n>1 to be functional. Increase n in -# case the DB propagation and processing time does not fit into n PLL reference -# clock cycles taking the delays from below into account (see waveform above). -# Make sure you defined the SPI bus clock frequency for the slave to n*PLL clock -# period (effective SPI clock). Set the required SPI DB clock divider on the -# FPGA before starting data transfer. -# -# The constants for this interface are defined in db_spi_shared_constants.sdc - -#### DB 0 #### -create_generated_clock -source [get_ports {PLL_REF_CLK}] \ - -name db0_ctrl_clk_int [get_registers {DB_CTRL_SCLK[0]~reg0}] -create_generated_clock -source [get_registers {DB_CTRL_SCLK[0]~reg0}] \ - -name db0_ctrl_clk [get_ports {DB_CTRL_SCLK[0]}] - -set db0_ctrl_outputs [get_ports {DB_CTRL_MOSI[0] DB_CTRL_CS_N[0]}] -set_output_delay -clock db0_ctrl_clk -max $db_cpld_spi_max_out $db0_ctrl_outputs -set_output_delay -clock db0_ctrl_clk -min $db_cpld_spi_min_out $db0_ctrl_outputs - -set db0_ctrl_inputs [get_ports {DB_CTRL_MISO[0]}] -set_input_delay -clock db0_ctrl_clk -max $db_cpld_spi_max_in $db0_ctrl_inputs -set_input_delay -clock db0_ctrl_clk -min $db_cpld_spi_min_in $db0_ctrl_inputs - -#### DB 1 #### -create_generated_clock -source [get_ports {PLL_REF_CLK}] \ - -name db1_ctrl_clk_int [get_registers {DB_CTRL_SCLK[1]~reg0}] -create_generated_clock -source [get_registers {DB_CTRL_SCLK[1]~reg0}] \ - -name db1_ctrl_clk [get_ports DB_CTRL_SCLK[1]] - -set db1_ctrl_outputs [get_ports {DB_CTRL_MOSI[1] DB_CTRL_CS_N[1]}] -set_output_delay -clock db1_ctrl_clk -max $db_cpld_spi_max_out $db1_ctrl_outputs -set_output_delay -clock db1_ctrl_clk -min $db_cpld_spi_min_out $db1_ctrl_outputs - -set db1_ctrl_inputs [get_ports {DB_CTRL_MISO[1]}] -set_input_delay -clock db1_ctrl_clk -max $db_cpld_spi_max_in $db1_ctrl_inputs -set_input_delay -clock db1_ctrl_clk -min $db_cpld_spi_min_in $db1_ctrl_inputs - -##################################################################### -# Power supply clocks, LEDs, DIO direction -##################################################################### -# Change all output signals in this section within one clock period of the -# driving clocks. - -# Power supply clocks -set power_supply_clocks_outputs [get_ports {PWR_SUPPLY_CLK_*}] -set_min_delay -to $power_supply_clocks_outputs 0 -set_max_delay -to $power_supply_clocks_outputs $CLK_100_period - -# LED signals -set led_outputs [get_ports {QSFP0_LED_ACTIVE[*] QSFP0_LED_LINK[*] \ - QSFP1_LED_ACTIVE[*] QSFP1_LED_LINK[*]}] -set_min_delay -to $led_outputs 0 -set_max_delay -to $led_outputs $prc_clock_period - -# DIO direction -set dio_outputs [get_ports {DIO_DIRECTION_A[*] DIO_DIRECTION_B[*]}] -set_min_delay -to $dio_outputs 0 -set_max_delay -to $dio_outputs $clk50_period - -# Power control -set pwr_ctrl_outputs [get_ports {IPASS_POWER_DISABLE PWR_EN_5V_OSC_100 PWR_EN_5V_OSC_122_88}] -set_min_delay -to $pwr_ctrl_outputs 0 -set_max_delay -to $pwr_ctrl_outputs $clk50_period - -# Power fault inputs -# Virtual clocks for constraining inputs. Using an odd clock period to -# make sure any uncovered paths will result in timing errors due to short setup -# or hold path. -set power_fault_inputs [get_ports {IPASS_POWER_EN_FAULT[*]}] -create_clock -name virtual_async_in_clk -period 4.567 -set_input_delay -clock virtual_async_in_clk 0 $power_fault_inputs - -##################################################################### -# FPGA <-> MB CPLD PS SPI interface -##################################################################### -# Assume the PS SPI clock is maximum 5 MHz. -# It is driven from another source and provided with the data. -set ps_sclk_period 200.000 -create_clock -name ps_sclk -period $ps_sclk_period [get_ports PS_CPLD_SCLK] - -# The SPI PS master (on the FPGA) is wired through the MIO (Multiplexed I/O) -# pins, meaning that the timing characteristics of the interface come from -# the controller itself (i.e. no timed routing through PL). -# Based on the SPI master controller specification (DS925: Table 48), -# one may define the min/max input/output delay constraints. -set ps_spi_tco_min -2.000 -set ps_spi_tco_max 5.000 -set ps_spi_miso_setup -2.000 -set ps_spi_miso_hold [expr {0.3 * $ps_sclk_period}] - -# Use the worst-case board propagation delays. -# Assuming 170.0 ps/in. -# Longest trace | Trace length | Trace delay -# CS0_n | 4.735 in | 0.805 ns -# -------------------------------------------- -set ps_spi_board_delay 0.805 - -set ps_slave_inputs [get_ports {PS_CPLD_MOSI PS_CPLD_CS_N[*]}] -# clock is immediately available, data is taking maximum time -# SPI data in CPOL=CPHA=1 is driven on the falling sclk edge -set ps_sclk_max_in_delay [expr {$ps_spi_tco_max + $ps_spi_board_delay}] -set_input_delay -clock ps_sclk -clock_fall \ - -max $ps_sclk_max_in_delay \ - $ps_slave_inputs -# fast data and clock delayed (reducing data delay) -set_input_delay -clock ps_sclk -clock_fall \ - -min [expr {$ps_spi_tco_min - $ps_spi_board_delay}] \ - $ps_slave_inputs - -set ps_slave_outputs [get_ports {PS_CPLD_MISO}] -# use only half the frequency because falling edge is driving data -set_output_delay -clock ps_sclk \ - -max [expr {$ps_spi_miso_setup + 2*$ps_spi_board_delay}] \ - $ps_slave_outputs -# use hold requirement only as clock and data propagation further -# delay the signal -set_output_delay -clock ps_sclk \ - -min [expr {-$ps_spi_miso_hold}] \ - $ps_slave_outputs - -# Chip select signals are captured for binary decoding in 250 MHz clock domain. -# To be able to specify a maximum delay for the data path only a second set of -# input delays is added to the root clock of the 250 MHz domain. -set_input_delay -add_delay -clock CLK_100 0 [get_ports {PS_CPLD_CS_N[*]}] -# Declare paths between the 2 clock domains as false paths -set_false_path -from [get_clocks {CLK_100}] -to [get_ports {PS_CPLD_MISO}] -set_false_path -from [get_clocks {ps_sclk}] -to [get_registers {synchronizer:ps_spi_input_sync_inst*}] -# Specify maximum data path delay -set_max_delay -from [get_ports {PS_CPLD_CS_N[*]}] -to $CLK_250 $clk250_period - -##################################################################### -# MB CPLD PS SPI passthrough -##################################################################### -###### Binary CS decoding ###### -# The CS outputs for the external SPI slaves are driven from a 250 MHz clock to -# ensure glitch free switching after binary encoding. Additionally those signals -# have to meet the setup and hold requirements of the SPI slaves operating at -# ps_sclk (5 MHz). CS lines typically are asserted half a clock period of sclk -# before any active edge of sclk. The constraints below are using multi-cycle -# paths to provide the placer with information about the clock multiplier from -# ps_sclk to 250 MHz. Furthermore they incorporate the time required for -# decoding by lowering the clock multiplier as shown in the waveform below -# (multiplier is not shown correctly). -# -# ps_sclk -\__________________________________________________/-------- -# 250 MHz _/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\- -# CS @ CPLD input X>--------------- stable ------------------------------------ -# CS @ CPLD output ----------------------- stable --------------------- -# |<----->| min decoding delay -# |<----->| change window -# --------------->| SPI slave hold requirement -# SPI slave setup requirement |<-------------------------------->| -# -# Get port to apply the multi-cycle constraint. -set binary_cs_ports [get_ports {LMK32_CS_N TPM_CS_N PHASE_DAC_CS_N DB_CALEEPROM_CS_N[*] CLK_DB_CS_N}] -# Determine number of full 250 MHz periods within half a period of ps_sclk. -set ps_spi_clock_divider [expr {int($ps_sclk_period/$clk250_period/2)}] -# Setup multi-cycle accounts for -# - one clock cycle data path delay from port to first register stage -# - one clock cycle to resolve meta-stability -# - up to 3 register stages internally (port to ps_cpld_cs_n_shift3) -# - one output register stage (registers on each $binary_cs_ports) -# Static timing analysis will take the data path from register to output port -# into account. -# The number of 250 MHz periods is reduced by a total of 7 clock cycles (listed -# above) to match the SPI slave setup requirement time shown in the waveform -# above. The slave's setup time in ps_sclk domain is specified below for each -# individual slave. -set ps_spi_setup_multicycle [expr {$ps_spi_clock_divider - 7}] -set_multicycle_path -setup -start -to $binary_cs_ports $ps_spi_setup_multicycle -# Hold multicycle accounts for -# - min 2 synchronization register stages internally (ps_cpld_cs_n_shift2) -# (= min one clock cycle delay as data could arrive just before setup -# requirement of first register stages assuming no data delay) -# - one output register stage -# Static timing analysis will take the data path from register to output port -# into account. -# As the clock edge for hold analysis is shifted with the setup edge the number -# of multi cycles has to be increased by this amount of cycles to get back to -# the falling edge of ps_sclk. Furthermore CS lines are released one half -# ps_sclk period after the last data transfer. So hold delay is increased by an -# additional half clock cycle. -set ps_spi_hold_multicycle [expr {$ps_spi_clock_divider + $ps_spi_setup_multicycle - 2}] -set_multicycle_path -hold -start -to $binary_cs_ports $ps_spi_hold_multicycle - -###### local SPI slave ###### -# The chip select path for the MB CPLD itself is driven in the 250 MHz clock -# domain and captured by registers operating at ps_sclk. Therefore setting the -# path as false path preventing the placer from adding additional routing delay -# to ensure hold timing. The setup path is limited to a maximum extend of one -# clock period. As this path crosses clock domains clock propagation is included -# in this path during static timing analysis. The TCL analysis in -# scripts/ps_cs_analysis.tcl ensures a maximum value for data excluding the -# clocking network. -set_false_path -from [get_registers {ps_spi_cs_n_decoded[0]}] -hold -set_max_delay -from [get_registers {ps_spi_cs_n_decoded[0]}] $clk250_period - -###### LMK04832 ###### -create_generated_clock -source [get_ports PS_CPLD_SCLK] \ - -name lmk_spi_sclk [get_ports LMK32_SCLK] - -# Use the worst-case board propagation delays. -# Assuming 170.0 ps/in. -# Longest trace | Trace length | Trace delay -# LMK32_SCLK | 8.259 in | 1.404 ns -# -------------------------------------------- -set lmk_board_delay 1.404 - -# setup and hold dominated by CS <-> SCK relationship -set lmk_setup 20.000 -set lmk_hold 20.000 -set lmk_tco_max 60.000 - -set lmk_outputs [get_ports {LMK32_MOSI LMK32_CS_N}] -set_output_delay -clock lmk_spi_sclk \ - -max [expr {$lmk_setup + $lmk_board_delay + $buffer_prop_max}] \ - $lmk_outputs -set_output_delay -clock lmk_spi_sclk \ - -min [expr {-$lmk_hold - $lmk_board_delay - $buffer_prop_min}] \ - $lmk_outputs - -set lmk_inputs [get_ports {LMK32_MISO}] -set_input_delay -clock lmk_spi_sclk -clock_fall \ - -max [expr {$lmk_tco_max + 2*$lmk_board_delay + 2*$buffer_prop_max}] \ - $lmk_inputs -set_input_delay -clock lmk_spi_sclk -clock_fall \ - -min [expr {2*$buffer_prop_min}] \ - $lmk_inputs - -###### Phase DAC ###### -create_generated_clock -source [get_ports PS_CPLD_SCLK] \ - -name phase_dac_spi_sclk [get_ports PHASE_DAC_SCLK] - -# Use the worst-case board propagation delays. -# Assuming 170.0 ps/in. -# Longest trace | Trace length | Trace delay -# SpiDCs3v3_n | 8.322 in | 1.415 ns -# -------------------------------------------- -set phase_dac_board_delay 1.415 - -#setup dominated by SYNC signal -set phase_dac_setup 13.000 -set phase_dac_hold 5.000 - -# device captures data on falling clock edge (CPOL = 1) -# constraining it as it would be like all the other SPI modules -# PS SPI master is responsible for changing SPI mode when talking -# to this device -set phase_dac_outputs [get_ports {PHASE_DAC_MOSI PHASE_DAC_CS_N}] -set_output_delay -clock phase_dac_spi_sclk -clock_fall \ - -max [expr {$phase_dac_setup + $phase_dac_board_delay}] \ - $phase_dac_outputs -set_output_delay -clock phase_dac_spi_sclk -clock_fall \ - -min [expr {-$phase_dac_hold - $phase_dac_board_delay}] \ - $phase_dac_outputs - -###### TPM ###### -create_generated_clock -source [get_ports PS_CPLD_SCLK] \ - -name tpm_spi_sclk [get_ports TPM_SCLK] - -# Use the worst-case board propagation delays. -# Assuming 170.0 ps/in. -# Longest trace | Trace length | Trace delay -# TPM_CS_n | 1.128 in | 0.196 ns -# -------------------------------------------- -set tpm_board_delay 0.196 - -#tco dominated by NSS signal -set tpm_setup 5.000 -set tpm_hold 5.000 -set tpm_tco_max 25.000 - -set tpm_outputs [get_ports {TPM_MOSI TPM_CS_N}] -set_output_delay -clock tpm_spi_sclk \ - -max [expr {$tpm_setup + $tpm_board_delay}] \ - $tpm_outputs -set_output_delay -clock tpm_spi_sclk \ - -min [expr {-$tpm_hold - $tpm_board_delay}] \ - $tpm_outputs - -set tpm_inputs [get_ports {TPM_MISO}] -set_input_delay -clock tpm_spi_sclk -clock_fall \ - -max [expr {$tpm_tco_max + 2*$tpm_board_delay}] \ - $tpm_inputs -set_input_delay -clock tpm_spi_sclk -clock_fall \ - -min 0 \ - $tpm_inputs - -###### DB Calibration EEPROM ###### -# Use worst case board propagation delays to estimate input and output -# timing. The longest path assuming 170 ps/in is: -# db0_caleeprom_spi_cs_n | 4.387 in | 0.746 ns -set eeprom_board_prop_delay 0.746 -# Within the path to the EEPROM on the DB there is a level-transistor. -# The maximum propagation delays are 0.1..3.3 ns to the DB and 3.7 ns from the DB. -set eeprom_lvl_trans_to_db_delay_min 0.1 -set eeprom_lvl_trans_to_db_delay_max 3.3 -set eeprom_lvl_trans_from_db_delay_max 3.7 -# Data in setup and hold times of the EEPROM are 5ns (based on the -# CS_N setup and hold times). -set db_eeprom_setup 5 -set db_eeprom_hold 5 -# Ouput valid from SCK is min 0 ns and max 8 ns. -set db_eeprom_output_valid 8 - -# max out path assuming clock delay is 0 and data delay is maximum value -set eeprom_max_out [expr {$eeprom_board_prop_delay + $eeprom_lvl_trans_to_db_delay_max + $db_eeprom_setup}] -# min out path assuming clock delay is maximal and data delay is 0 -set eeprom_min_out [expr {-($eeprom_board_prop_delay + $eeprom_lvl_trans_to_db_delay_min + $db_eeprom_hold)}] -# board propagation to eeprom and back + lvl_translator back and forth + clock to data on eeprom -set eeprom_max_in [expr {$eeprom_board_prop_delay*2 + $eeprom_lvl_trans_to_db_delay_max + $eeprom_lvl_trans_from_db_delay_max + $db_eeprom_output_valid}] -# assuming no delay for everything -set eeprom_min_in 0 - -### DB 0 -create_generated_clock -source [get_ports PS_CPLD_SCLK] \ - -name db0_eeprom_clk [get_ports {DB_CALEEPROM_SCLK[0]}] - -set db0_eeprom_outputs [get_ports {DB_CALEEPROM_MOSI[0] DB_CALEEPROM_CS_N[0]}] -set_output_delay -clock db0_eeprom_clk -max $eeprom_max_out $db0_eeprom_outputs -set_output_delay -clock db0_eeprom_clk -min $eeprom_min_out $db0_eeprom_outputs - -set db0_eeprom_inputs [get_ports {DB_CALEEPROM_MISO[0]}] -# data is changed on the falling edge -set_input_delay -clock db0_eeprom_clk -clock_fall -max $eeprom_max_in $db0_eeprom_inputs -set_input_delay -clock db0_eeprom_clk -clock_fall -min $eeprom_min_in $db0_eeprom_inputs - -### DB 1 -create_generated_clock -source [get_ports PS_CPLD_SCLK] \ - -name db1_eeprom_clk [get_ports {DB_CALEEPROM_SCLK[1]}] - -set db1_eeprom_outputs [get_ports {DB_CALEEPROM_MOSI[1] DB_CALEEPROM_CS_N[1]}] -set_output_delay -clock db1_eeprom_clk -max $eeprom_max_out $db1_eeprom_outputs -set_output_delay -clock db1_eeprom_clk -min $eeprom_min_out $db1_eeprom_outputs - -set db1_eeprom_inputs [get_ports {DB_CALEEPROM_MISO[1]}] -# data is changed on the falling edge -set_input_delay -clock db1_eeprom_clk -clock_fall -max $eeprom_max_in $db1_eeprom_inputs -set_input_delay -clock db1_eeprom_clk -clock_fall -min $eeprom_min_in $db1_eeprom_inputs - -#### Clocking AUX board SPI interface #### -# Rev B clocking aux board uses a LMK05318 connected to this interface -# Using its timing for this interface. -create_generated_clock -source [get_ports PS_CPLD_SCLK] \ - -name clk_db_clk_out [get_ports CLK_DB_SCLK] -set clk_db_setup 10.000 -set clk_db_hold 10.000 -set clk_db_tco_max 20.000 -# Just a worst case assumption based on 2 times the MB trace length CLK_DB_MOSI. -# The multiplier 2 accounts for any traces on the CLK AUX board. -set clk_db_board_delay 4.000 - -set clk_db_outputs [get_ports {CLK_DB_CS_N CLK_DB_MOSI}] -# Output signals have to stable for max setup and propagation time. Clock delay -# to device is expected to be 0 in this equation. -set_output_delay -clock clk_db_clk_out \ - -max [expr {$clk_db_setup + $clk_db_board_delay + $buffer_prop_max}] $clk_db_outputs -# The min output delay is comprised of: -# - device required hold time ($clk_db_hold) -# - max clock propagation delay ($clk_db_board_delay) -# - min data propagation time (0) -# All terms have to be negated as min output delay is defined in opposite -# direction (positive into the past). -set_output_delay -clock clk_db_clk_out \ - -min [expr {-$clk_db_hold - $clk_db_board_delay - $buffer_prop_min}] $clk_db_outputs - -set clk_db_inputs [get_ports {CLK_DB_MISO}] -# Max delay calculated is based on -# - max clock delay ($clk_db_board_delay) -# - max clock to out LMK ($clk_db_tco_max) -# - max data path delay ($clk_db_board_delay) -set_input_delay -clock clk_db_clk_out -clock_fall \ - -max [expr {$clk_db_tco_max + $clk_db_board_delay*2 + 2*$buffer_prop_max}] $clk_db_inputs -# Min delay assumes clock propagates to device and data propagates to CPLD -# without any delays. -set_input_delay -clock clk_db_clk_out -clock_fall \ - -min [expr {2*$buffer_prop_min}] $clk_db_inputs - -##################################################################### -# PCIe signals -##################################################################### -# I²C bus is operated at 100kHz. Constraints would not improve timing -# significantly (typically in the order of nanoseconds, which is negligible -# given the SCL period of 10 us). -# PCI-Express reset signal is not timing critical as it is received -# asynchronously by the FPGA. -set_false_path -to [get_ports {IPASS_SDA[0] IPASS_SCL[0] PCIE_RESET}] -# I²C inputs are only consumed by synchronizers. -# Add exceptions for all known consumers. -set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|I2cTop:CableI2cx|I2cMonitor:I2cMonitorx|I2cFilter:I2cFilterx|I2cSigFilter:SclFilterx|fSig_ms}] -set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|I2cTop:CableI2cx|I2cMonitor:I2cMonitorx|I2cFilter:I2cFilterx|I2cSigFilter:SdaFilterx|fSig_ms}] -set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|StuckBusFixer:StuckBusFixerx|DoubleSyncSlAsyncIn:DoubleSclkx|DoubleSyncAsyncInBase:DoubleSyncAsyncInBasex|DFlopAsync:oSig_msx|lpm_ff:LPM_FFx|dffs[0]}] -set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|StuckBusFixer:StuckBusFixerx|DoubleSyncSlAsyncIn:DoubleSdax|DoubleSyncAsyncInBase:DoubleSyncAsyncInBasex|DFlopAsync:oSig_msx|lpm_ff:LPM_FFx|dffs[0]}] - -##################################################################### -# Known Issue of On-Chip Flash -##################################################################### -# see https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2016/warning--332060---node---alteraonchipflash-onchipflash-alteraonc.html -create_generated_clock -name flash_se_neg_reg \ - -source [get_pins { on_chip_flash:flash_inst|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk }] \ - -divide_by 2 [get_pins { on_chip_flash:flash_inst|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q } ] - -##################################################################### -# Clock uncertainty -##################################################################### -# Assign some uncertainty to all clocks -set clock_uncertainty 0.150 -set_clock_uncertainty -to [get_clocks *] $clock_uncertainty -derive_clock_uncertainty diff --git a/top/x400/cpld/pl_cpld_regs.v b/top/x400/cpld/pl_cpld_regs.v deleted file mode 100644 index 19acdea..0000000 --- a/top/x400/cpld/pl_cpld_regs.v +++ /dev/null @@ -1,297 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: pl_cpld_regs -// -// Description: -// -// Basic Registers to inform software about version and capabilities. -// -// Parameters: -// -// BASE_ADDRESS : Base address for CtrlPort registers -// - -`default_nettype none - - -module pl_cpld_regs #( - parameter BASE_ADDRESS = 0 -) ( - input wire ctrlport_clk, - input wire ctrlport_rst, - - // Request - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [31:0] s_ctrlport_req_data, - // Response - output reg s_ctrlport_resp_ack, - output reg [ 1:0] s_ctrlport_resp_status, - output reg [31:0] s_ctrlport_resp_data, - - // QSFP LEDs - // Port 0 - output wire [ 3:0] qsfp0_led_active, - output wire [ 3:0] qsfp0_led_link, - // Port 1 - output wire [ 3:0] qsfp1_led_active, - output wire [ 3:0] qsfp1_led_link, - - // iPass status - output wire [ 1:0] ipass_cable_present -); - - `include "regmap/constants_regmap_utils.vh" - `include "regmap/pl_cpld_base_regmap_utils.vh" - `include "../../../lib/rfnoc/core/ctrlport.vh" - - //--------------------------------------------------------------------------- - // Address Calculation - //--------------------------------------------------------------------------- - - localparam NUM_ADDRESSES = 64; - wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && - (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES); - - //--------------------------------------------------------------------------- - // Internal Registers - //--------------------------------------------------------------------------- - - reg [SCRATCH_REGISTER_SIZE-1:0] scratch_reg; - reg [LED_REGISTER_SIZE-1:0] led_reg; - reg [CABLE_PRESENT_REG_SIZE-1:0] ipass_reg; - - //--------------------------------------------------------------------------- - // Assign Outputs - //--------------------------------------------------------------------------- - - assign qsfp0_led_active = led_reg[QSFP0_LED_ACTIVE+:QSFP0_LED_ACTIVE_SIZE]; - assign qsfp0_led_link = led_reg[QSFP0_LED_LINK+:QSFP0_LED_LINK_SIZE]; - - assign qsfp1_led_active = led_reg[QSFP1_LED_ACTIVE+:QSFP1_LED_ACTIVE_SIZE]; - assign qsfp1_led_link = led_reg[QSFP1_LED_LINK+:QSFP1_LED_LINK_SIZE]; - - assign ipass_cable_present = ipass_reg; - - //--------------------------------------------------------------------------- - // Handling of ControlPort Requests - //--------------------------------------------------------------------------- - - always @(posedge ctrlport_clk) begin - // Reset internal registers and responses - if (ctrlport_rst) begin - scratch_reg <= 0; - led_reg <= 0; - ipass_reg <= 0; - s_ctrlport_resp_ack <= 1'b0; - - // Write requests - end else if (s_ctrlport_req_wr) begin - // Always issue an ack and no data - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}}; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + SCRATCH_REGISTER: - scratch_reg <= s_ctrlport_req_data; - - BASE_ADDRESS + LED_REGISTER: - led_reg <= s_ctrlport_req_data[LED_REGISTER_SIZE-1:0]; - - BASE_ADDRESS + CABLE_PRESENT_REG: begin - ipass_reg[0] <= s_ctrlport_req_data[IPASS0_CABLE_PRESENT]; - ipass_reg[1] <= s_ctrlport_req_data[IPASS1_CABLE_PRESENT]; - end - - // Error on undefined address - default: begin - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // Read request - end else if (s_ctrlport_req_rd) begin - // Default assumption: valid request - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + SIGNATURE_REGISTER: - s_ctrlport_resp_data <= PL_CPLD_SIGNATURE; - - BASE_ADDRESS + REVISION_REGISTER: - s_ctrlport_resp_data <= CPLD_REVISION; - - BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER: - s_ctrlport_resp_data <= OLDEST_CPLD_REVISION; - - BASE_ADDRESS + SCRATCH_REGISTER: - s_ctrlport_resp_data <= scratch_reg; - - BASE_ADDRESS + GIT_HASH_REGISTER: - `ifdef GIT_HASH - s_ctrlport_resp_data <= `GIT_HASH; - `else - s_ctrlport_resp_data <= 32'hDEADBEEF; - `endif - - BASE_ADDRESS + LED_REGISTER: - s_ctrlport_resp_data <= {{(CTRLPORT_DATA_W - LED_REGISTER_SIZE){1'b0}}, led_reg}; - - BASE_ADDRESS + CABLE_PRESENT_REG: begin - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}}; - s_ctrlport_resp_data[IPASS0_CABLE_PRESENT] <= ipass_reg[0]; - s_ctrlport_resp_data[IPASS1_CABLE_PRESENT] <= ipass_reg[1]; - end - - // Error on undefined address - default: begin - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}}; - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // No request - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - -endmodule - - -`default_nettype wire - - -//XmlParse xml_on -// -// -// -// Basic registers containing version and capabilities information. -// -// -// -// Contains the product's signature. -// -// Fixed value PL_CPLD_SIGNATURE of @.CONSTANTS_REGMAP -// -// -// -// -// Contains the CPLD revision (see CPLD_REVISION of @.CONSTANTS_REGMAP) -// -// Contains revision hour code. -// -// -// Contains revision day code. -// -// -// Contains revision month code. -// -// -// Contains revision year code. -// -// -// -// -// -// This register returns (in YYMMDDHH format) the oldest revision -// that is still compatible with this one. Compatible means that -// registers or register bits may have been added, but not -// modified or deleted (see OLDEST_CPLD_REVISION of @.CONSTANTS_REGMAP). -// -// -// Contains revision hour code. -// -// -// Contains revision day code. -// -// -// Contains revision month code. -// -// -// Contains revision year code. -// -// -// -// -// Read/write register for general software use. -// -// -// -// -// Git hash of commit used to build this image.{br} -// Value equals 0xDEADBEEF if the git hash was not used during synthesis. -// -// -// -// 0x0 in case the git status was clean{br} -// 0xF in case there were uncommitted changes -// -// -// -// 7 hex digit hash code of the commit -// -// -// -// -// -// -// Register Map to control QSFP LEDs. -// -// -// -// Provides to the LEDs of the QSFP ports. -// Write access will directly change the LED status. -// The LED lights up if the corresponding bit is set. -// -// -// Link LEDs of QSFP port 0 -// -// -// Active LEDs of QSFP port 0 -// -// -// Link LEDs of QSFP port 1 -// -// -// Active LEDs of QSFP port 1 -// -// -// -// -// -// -// Cable present status register. -// -// -// -// Information from FPGA about the cable present status. -// -// -// Set to 1 if cable present in iPass 0 connector. -// -// -// Set to 1 if cable present in iPass 1 connector. -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/cpld/ps_cpld_regs.v b/top/x400/cpld/ps_cpld_regs.v deleted file mode 100644 index d5f9b1d..0000000 --- a/top/x400/cpld/ps_cpld_regs.v +++ /dev/null @@ -1,404 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: ps_cpld_regs -// -// Description: -// -// Basic registers to inform software about version and capabilities. -// -// Parameters: -// -// BASE_ADDRESS : Base address for CtrlPort registers -// - -`default_nettype none - - -module ps_cpld_regs #( - parameter BASE_ADDRESS = 0 -) ( - input wire ctrlport_clk, - input wire ctrlport_rst, - - // Request - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [31:0] s_ctrlport_req_data, - // Response - output reg s_ctrlport_resp_ack, - output reg [ 1:0] s_ctrlport_resp_status, - output reg [31:0] s_ctrlport_resp_data, - - // Configuration outputs - output reg [ 1:0] db_clk_enable = 2'b00, - output reg [ 1:0] db_reset = 2'b11, - output reg pll_ref_clk_enable = 1'b0, - - output reg [11:0] dio_direction_a = 12'b0, - output reg [11:0] dio_direction_b = 12'b0, - - output reg [39:0] serial_num = 40'b0, - output reg cmi_ready = 1'b0, - input wire cmi_other_side_detected -); - -`include "regmap/constants_regmap_utils.vh" -`include "regmap/ps_cpld_base_regmap_utils.vh" -`include "../../../lib/rfnoc/core/ctrlport.vh" - -//----------------------------------------------------------------------------- -// Address Calculation -//----------------------------------------------------------------------------- - -localparam NUM_ADDRESSES = 64; -wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && - (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES); - -//----------------------------------------------------------------------------- -// Internal Registers -//----------------------------------------------------------------------------- - -reg [SCRATCH_REGISTER_SIZE-1:0] scratch_reg; - -//----------------------------------------------------------------------------- -// Handling of ControlPort Requests -//----------------------------------------------------------------------------- - -always @(posedge ctrlport_clk) begin - // Reset internal registers and responses - if (ctrlport_rst) begin - scratch_reg <= 0; - db_clk_enable <= 2'b00; - db_reset <= 2'b11; - pll_ref_clk_enable <= 1'b0; - dio_direction_a <= {DIO_DIRECTION_A_SIZE{1'b0}}; - dio_direction_b <= {DIO_DIRECTION_B_SIZE{1'b0}}; - s_ctrlport_resp_ack <= 1'b0; - s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}}; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - // Write requests - end else begin - if (s_ctrlport_req_wr) begin - // Always issue an ack and no data - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}}; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + SCRATCH_REGISTER: - scratch_reg <= s_ctrlport_req_data; - - BASE_ADDRESS + PL_DB_REGISTER: begin - if (s_ctrlport_req_data[DISABLE_CLOCK_DB0]) begin - db_clk_enable[0] <= 1'b0; - end else if (s_ctrlport_req_data[ENABLE_CLOCK_DB0]) begin - db_clk_enable[0] <= 1'b1; - end - if (s_ctrlport_req_data[DISABLE_CLOCK_DB1]) begin - db_clk_enable[1] <= 1'b0; - end else if (s_ctrlport_req_data[ENABLE_CLOCK_DB1]) begin - db_clk_enable[1] <= 1'b1; - end - if (s_ctrlport_req_data[DISABLE_PLL_REF_CLOCK]) begin - pll_ref_clk_enable <= 1'b0; - end else if (s_ctrlport_req_data[ENABLE_PLL_REF_CLOCK]) begin - pll_ref_clk_enable <= 1'b1; - end - if (s_ctrlport_req_data[ASSERT_RESET_DB0]) begin - db_reset[0] <= 1'b1; - end else if (s_ctrlport_req_data[RELEASE_RESET_DB0]) begin - db_reset[0] <= 1'b0; - end - if (s_ctrlport_req_data[ASSERT_RESET_DB1]) begin - db_reset[1] <= 1'b1; - end else if (s_ctrlport_req_data[RELEASE_RESET_DB1]) begin - db_reset[1] <= 1'b0; - end - end - - BASE_ADDRESS + DIO_DIRECTION_REGISTER: begin - dio_direction_a <= s_ctrlport_req_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A]; - dio_direction_b <= s_ctrlport_req_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B]; - end - - BASE_ADDRESS + SERIAL_NUM_LOW_REG: begin - serial_num[31:0] <= s_ctrlport_req_data; - end - - BASE_ADDRESS + SERIAL_NUM_HIGH_REG: begin - serial_num[39:32] <= s_ctrlport_req_data[SERIAL_NUM_HIGH_REG_SIZE-1:0]; - end - - BASE_ADDRESS + CMI_CONTROL_STATUS: begin - cmi_ready <= s_ctrlport_req_data[CMI_READY]; - end - - // Error on undefined address - default: begin - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // Read request - end else if (s_ctrlport_req_rd) begin - // Default assumption: valid request - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}}; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + SIGNATURE_REGISTER: - s_ctrlport_resp_data <= PS_CPLD_SIGNATURE; - - BASE_ADDRESS + REVISION_REGISTER: - s_ctrlport_resp_data <= CPLD_REVISION; - - BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER: - s_ctrlport_resp_data <= OLDEST_CPLD_REVISION; - - BASE_ADDRESS + SCRATCH_REGISTER: - s_ctrlport_resp_data <= scratch_reg; - - BASE_ADDRESS + GIT_HASH_REGISTER: - `ifdef GIT_HASH - s_ctrlport_resp_data <= `GIT_HASH; - `else - s_ctrlport_resp_data <= 32'hDEADBEEF; - `endif - - BASE_ADDRESS + PL_DB_REGISTER: begin - s_ctrlport_resp_data[DB0_CLOCK_ENABLED] <= db_clk_enable[0]; - s_ctrlport_resp_data[DB1_CLOCK_ENABLED] <= db_clk_enable[1]; - s_ctrlport_resp_data[PLL_REF_CLOCK_ENABLED] <= pll_ref_clk_enable; - s_ctrlport_resp_data[DB0_RESET_ASSERTED] <= db_reset[0]; - s_ctrlport_resp_data[DB1_RESET_ASSERTED] <= db_reset[1]; - end - - BASE_ADDRESS + DIO_DIRECTION_REGISTER: begin - s_ctrlport_resp_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A] <= dio_direction_a; - s_ctrlport_resp_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B] <= dio_direction_b; - end - - BASE_ADDRESS + SERIAL_NUM_LOW_REG: begin - s_ctrlport_resp_data <= serial_num[31:0]; - end - - BASE_ADDRESS + SERIAL_NUM_HIGH_REG: begin - s_ctrlport_resp_data[SERIAL_NUM_HIGH_REG_SIZE-1:0] <= serial_num[39:32]; - end - - BASE_ADDRESS + CMI_CONTROL_STATUS: begin - s_ctrlport_resp_data[CMI_READY] <= cmi_ready; - s_ctrlport_resp_data[OTHER_SIDE_DETECTED] <= cmi_other_side_detected; - end - - // Error on undefined address - default: begin - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}}; - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // No request - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end -end - -endmodule - - -`default_nettype wire - - -//XmlParse xml_on -// -// -// -// Basic registers containing version and capabilites information. -// -// -// -// Contains the product's signature. -// -// Fixed value PS_CPLD_SIGNATURE of @.CONSTANTS_REGMAP -// -// -// -// -// Contains the CPLD revision (see CPLD_REVISION of @.CONSTANTS_REGMAP). -// -// Contains revision hour code. -// -// -// Contains revision day code. -// -// -// Contains revision month code. -// -// -// Contains revision year code. -// -// -// -// -// -// This register returns (in YYMMDDHH format) the oldest revision -// that is still compatible with this one. Compatible means that -// registers or register bits may have been added, but not -// modified or deleted (see OLDEST_CPLD_REVISION of @.CONSTANTS_REGMAP). -// -// -// Contains revision hour code. -// -// -// Contains revision day code. -// -// -// Contains revision month code. -// -// -// Contains revision year code. -// -// -// -// -// Read/write register for general software use. -// -// -// -// -// Git hash of commit used to build this image.{br} -// Value equals 0xDEADBEEF if the git hash was not used during synthesis. -// -// -// -// 0x0 in case the git status was clean{br} -// 0xF in case there were uncommitted changes -// -// -// -// 7 hex digit hash code of the commit -// -// -// -// -// -// -// Register Map to control MB CPLD functions. -// -// -// -// Register to control the PL part DB SPI connection and reset generation. -// The DB connection is clocked with PLL reference clock. Ensure this clock is stable -// and enabled before starting any SPI request. -// The PLL reference clock can be disabled if both DB connections are disabled or inactive. -// To enable the DB connection, enable clock with one write access and release -// reset with the next write access. -// To disable the DB connection, assert reset with one write access and -// disable clocks with the next write access. -// -// -// Indicates if a clock is forwarded to DB 0. -// -// -// Indicates if a clock is forwarded to DB 1. -// -// -// Indicates if the PLL reference clock for the PL interface is enabled. -// -// -// Indicates that reset is asserted for DB 0. -// -// -// Indicates that reset is asserted for DB 1. -// -// -// Writing with this flag set enables DB 0 clock forwarding. (may be overwritten by @.DISABLE_CLOCK_DB0) -// -// -// Writing with this flag set enables DB 1 clock forwarding. (may be overwritten by @.DISABLE_CLOCK_DB1) -// -// -// Writing with this flag set enables the PLL reference clock. Assert this flag after PLL reference clock is stable. (may be overwritten by @.DISABLE_PLL_REF_CLOCK) -// -// -// Writing with this flag set disables DB 0 clock forwarding (overrides @.ENABLE_CLOCK_DB0) -// -// -// Writing with this flag set disables DB 1 clock forwarding (overrides @.ENABLE_CLOCK_DB1) -// -// -// Writing with this flag set disables the PLL reference clock (overrides @.ENABLE_PLL_REF_CLOCK). Assert this flag to reconfigure the clock. -// -// -// Writing with this flag set releases DB 0 reset. (may be overwritten by @.ASSERT_RESET_DB0) -// -// -// Writing with this flag set releases DB 1 reset. (may be overwritten by @.ASSERT_RESET_DB1) -// -// -// Writing with this flag set asserts reset for DB 0 (overrides @.RELEASE_RESET_DB0) -// -// -// Writing with this flag set asserts reset for DB 1 (overrides @.RELEASE_RESET_DB1) -// -// -// -// -// -// -// Registers to control the GPIO buffer direction on the DIO board connected to the FPGA. -// Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers. -// Set the direction in the FPGA's DIO register appropriately. -// -// -// -// Set the direction of FPGA buffer connected to DIO ports on the DIO board.{br/} -// Each bit represents one signal line. 0 = line is an input to the FPGA, 1 = line is an output driven by the FPGA. -// -// -// -// -// -// -// -// -// Cable present status register. -// -// -// Least significant bytes of 5 byte serial number. -// -// -// Most significant byte of 5 byte serial number. -// -// -// Control CMI communication and delivers information on the CMI link status. -// -// Set if the device is ready to establish a PCI-Express link (affects CMI_CLP_READY bit). -// -// -// 1 if an upstream CMI device has been detected. -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/cpld/ps_power_regs.v b/top/x400/cpld/ps_power_regs.v deleted file mode 100644 index 3e1a252..0000000 --- a/top/x400/cpld/ps_power_regs.v +++ /dev/null @@ -1,231 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: ps_power_regs -// -// Description: -// -// Registers to control power supplies on the motherboard. -// -// Parameters: -// -// BASE_ADDRESS : Base address for CtrlPort registers. -// NUM_ADDRESSES : Number of bytes of address space to use. -// - -`default_nettype none - - -module ps_power_regs #( - parameter BASE_ADDRESS = 0, - parameter NUM_ADDRESSES = 32 -) ( - input wire ctrlport_clk, - input wire ctrlport_rst, - - // Request - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [31:0] s_ctrlport_req_data, - // Response - output reg s_ctrlport_resp_ack, - output reg [ 1:0] s_ctrlport_resp_status, - output reg [31:0] s_ctrlport_resp_data, - - // iPass - output reg ipass_power_disable = 1'b0, - input wire [ 1:0] ipass_power_fault_n, - - // Oscillators - output reg osc_100_en, - output reg osc_122_88_en -); - - `include "regmap/ps_power_regmap_utils.vh" - `include "../../../lib/rfnoc/core/ctrlport.vh" - - //---------------------------------------------------------- - // Address Calculation - //---------------------------------------------------------- - - wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && - (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES); - - //---------------------------------------------------------- - // Internal Registers - //---------------------------------------------------------- - - reg [1:0] ipass_power_sticky = 2'b00; - reg [1:0] ipass_clear_sticky = 2'b00; - - //---------------------------------------------------------- - // Handling of ControlPort Requests - //---------------------------------------------------------- - - always @(posedge ctrlport_clk) begin - // Reset internal registers and responses - if (ctrlport_rst) begin - ipass_power_disable <= 1'b0; - s_ctrlport_resp_ack <= 1'b0; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}}; - - osc_100_en <= 1'b0; - osc_122_88_en <= 1'b0; - - end else begin - // Default assignments - ipass_clear_sticky <= 2'b00; - - // Write requests - if (s_ctrlport_req_wr) begin - // Always issue an ack and no data - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - s_ctrlport_resp_data <= {CTRLPORT_ADDR_W {1'bx}}; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + IPASS_POWER_REG: begin - ipass_power_disable <= s_ctrlport_req_data[IPASS_DISABLE_POWER_BIT]; - ipass_clear_sticky[0] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT0]; - ipass_clear_sticky[1] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT1]; - end - - BASE_ADDRESS + OSC_POWER_REG: begin - osc_100_en <= s_ctrlport_req_data[OSC_100]; - osc_122_88_en <= s_ctrlport_req_data[OSC_122_88]; - end - - // Error on undefined address - default: begin - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // Read request - end else if (s_ctrlport_req_rd) begin - // Default assumption: valid request - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}}; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + IPASS_POWER_REG: begin - s_ctrlport_resp_data[IPASS_DISABLE_POWER_BIT] <= ipass_power_disable; - s_ctrlport_resp_data[IPASS_POWER_FAULT0] <= ipass_power_sticky[0]; - s_ctrlport_resp_data[IPASS_POWER_FAULT1] <= ipass_power_sticky[1]; - end - - BASE_ADDRESS + OSC_POWER_REG: begin - s_ctrlport_resp_data[OSC_100] <= osc_100_en; - s_ctrlport_resp_data[OSC_122_88] <= osc_122_88_en; - end - - // Error on undefined address - default: begin - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}}; - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // No request - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - end - - //---------------------------------------------------------- - // Sticky Logic of Power Registers - //---------------------------------------------------------- - - // Synchronize asynchronous inputs - wire [1:0] ipass_power_fault_lcl_n; - synchronizer #( - .WIDTH (2), - .STAGES (2), - .INITIAL_VAL (1'b0), - .FALSE_PATH_TO_IN (1) - ) power_fault_sync ( - .clk (ctrlport_clk), - .rst (ctrlport_rst), - .in (ipass_power_fault_n), - .out (ipass_power_fault_lcl_n) - ); - - always @(posedge ctrlport_clk) begin - if (ctrlport_rst) begin - ipass_power_sticky <= 2'b00; - end else begin - // Keep value if not cleared or set in case of fault - ipass_power_sticky <= (ipass_power_sticky & ~ipass_clear_sticky) | ~ipass_power_fault_lcl_n; - end - end - -endmodule - - -`default_nettype wire - - -//XmlParse xml_on -// -// -// -// Registers to control power supplies on the motherboard. -// -// -// -// Controls the power supplies for the iPass connectors. -// -// Set to 1 to disable power for both iPass connectors. -// -// -// Clear @.IPASS_POWER_FAULT0. -// -// -// Clear @.IPASS_POWER_FAULT1. -// -// -// -// Asserted signal indicates a power fault in power switch for iPass -// connector 0. Sticky bit. Asserted on occurrence. Reset using -// @.IPASS_CLEAR_POWER_FAULT0. -// -// -// -// -// Asserted signal indicates a power fault in power switch for iPass -// connector 1. Sticky bit. Asserted on occurrence. Reset using -// @.IPASS_CLEAR_POWER_FAULT1. -// -// -// -// -// -// Controls the power supplies for the oscillators. -// -// Enables 5V power switch for the 100 MHz oscillator. -// -// -// Enables 5V power switch for the 122.88 MHz oscillator. -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/cpld/pwr_supply_clk_gen.v b/top/x400/cpld/pwr_supply_clk_gen.v deleted file mode 100644 index e69db9d..0000000 --- a/top/x400/cpld/pwr_supply_clk_gen.v +++ /dev/null @@ -1,73 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: pwr_supply_clk_gen -// -// Description: -// -// Generates a clock for one motherboard power supply. -// -// Parameters: -// -// BASE_ADDRESS : Base address for CtrlPort registers. -// NUM_ADDRESSES : Number of bytes of address space to use. -// - -`default_nettype none - - -module pwr_supply_clk_gen#( - parameter SOURCE_CLK_FREQ = 100_000_000, - parameter TARGET_CLK_FREQ = 100_000 -) ( - // Base clock and reset - input wire clk, - input wire rst, - - // Power supply clocks - output reg pwr_supply_clk -); - -//----------------------------------------------------------------------------- -// Counter Calculation / Definition -//----------------------------------------------------------------------------- -// Counter to generate the power supply switching clock - -// Assumption: the ratio between the generated clock and the source clock is -// even, therefore we can produce a 50% DC clock output. -localparam MAX_COUNT = SOURCE_CLK_FREQ / TARGET_CLK_FREQ / 2; -localparam COUNTER_W = $clog2(MAX_COUNT); -reg [COUNTER_W-1:0] counter = 0; - -//----------------------------------------------------------------------------- -// Clock Generation -//----------------------------------------------------------------------------- -// This process implements a simple clock divider for the power supply -// switcher. - -// SAFE COUNTER START! rst is a synchronous reset generated in the -// clk domain; therefore, inherently safe. -always @(posedge clk) begin - if (rst) begin - counter <= 0; - pwr_supply_clk <= 1'b0; - end - else begin - // Add one every cycle to the counter - counter <= counter + 1'b1; - - // When the counter reaches its mid value, it is reset and the output clock - // output is toggled. - if (counter == MAX_COUNT-1) begin - counter <= 0; - pwr_supply_clk <= ~pwr_supply_clk; - end - end -end - -endmodule - - -`default_nettype wire diff --git a/top/x400/cpld/quartus/ps_cs_analysis.tcl b/top/x400/cpld/quartus/ps_cs_analysis.tcl deleted file mode 100644 index 03ff77d..0000000 --- a/top/x400/cpld/quartus/ps_cs_analysis.tcl +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright 2021 Ettus Research, a National Instruments Brand -# -# SPDX-License-Identifier: LGPL-3.0-or-later -# -# Module: ps_cs_analysis -# -# Description: -# -# Analyze false path in PS SPI logic to ensure an upper delay boundary. -# - -# get project to a working state -project_open -force "mb_cpld.qpf" -create_timing_netlist -update_timing_netlist - -# Determine data path delay from MB CPLD chip select signal to MB CPLD internal -# SPI slave -set paths [report_path -from [get_registers {ps_spi_cs_n_decoded[0]}] -multi_corner] -set spiSlaveCsPathDelay [lindex $paths 1] - -# clock period at 250 MHz (clock driving the decoding registers) -set maxDelay 4 - -# compare path from above with maximum delay -if ([expr {$maxDelay < $spiSlaveCsPathDelay}]) { - puts "MB CPLD SPI CS line longer than expected." - exit 1 -} - -exit 0 diff --git a/top/x400/cpld/quartus/raw_conversion.cof b/top/x400/cpld/quartus/raw_conversion.cof deleted file mode 100644 index 87ecb15..0000000 --- a/top/x400/cpld/quartus/raw_conversion.cof +++ /dev/null @@ -1,39 +0,0 @@ - - - output_files/mb_cpld_converted.pof - 1 - 1 - 14 - - Page_0 - 1 - - output_files/mb_cpld.sof1 - - - 10 - 0 - 0 - 1 - 1 - - 1 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - - - 1 - 2 - 0 - -1 - -1 - 1 - - \ No newline at end of file diff --git a/top/x400/cpld/reconfig_engine.v b/top/x400/cpld/reconfig_engine.v deleted file mode 100644 index 6674cc6..0000000 --- a/top/x400/cpld/reconfig_engine.v +++ /dev/null @@ -1,1065 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: reconfig_engine -// -// Description: -// -// This file implements the registers and the state machine to interface with -// Intel's IP for the Max 10 FPGA that allows in-field updates to the primary -// FPGA image. This state machine has been designed to provide a level of -// abstraction between the register interface provided to user and the -// details of interfacing with Intel's On-Chip Flash IP block. The user -// simply needs to instruct this state machine to enable/disable write -// protection and perform read/write/erase operations accordingly to load and -// verify a new primary FPGA image. Since the purpose of this file is to -// allow modification to an FPGA image care has been taken to mitigate data -// corruption. -// -// The interface to Intel's On-Chip Flash IP block implemented in this file -// is based on the information found in the Max 10 User Flash Memory User -// Guide found at the link below. -// -// https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_ufm.pdf -// -// Parameters: -// -// BASE_ADDRESS : Base address for CtrlPort registers. -// NUM_ADDRESSES : Number of bytes of address space to use. -// MEM_INIT : Memory initialization enabled. Set to 0 if MAX10 internal -// configuration set to single compressed image. Set to 1 if -// MAX10 internal configuration set to single compressed -// image with memory initialization. -// - -`default_nettype none - - -module reconfig_engine #( - parameter BASE_ADDRESS = 0, - parameter NUM_ADDRESSES = 32, - parameter MEM_INIT = 0 -) ( - input wire ctrlport_clk, - input wire ctrlport_rst, - - /// Request - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [31:0] s_ctrlport_req_data, - // Response - output reg s_ctrlport_resp_ack, - output reg [ 1:0] s_ctrlport_resp_status, - output reg [31:0] s_ctrlport_resp_data, - - // Interface to On-Chip Flash IP - output reg csr_addr, - output reg csr_read, - output reg [31:0] csr_writedata, - output reg csr_write, - input wire [31:0] csr_readdata, - output reg [16:0] data_addr, - output reg data_read, - output reg [31:0] data_writedata, - output reg data_write, - input wire [31:0] data_readdata, - input wire data_waitrequest, - input wire data_readdatavalid -); - - `include "regmap/reconfig_regmap_utils.vh" - `include "../../../lib/rfnoc/core/ctrlport.vh" - - // Check MAX10 variant target (10M04, 10M08 or XO3) - `ifdef VARIANT_10M04 - localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04; - localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M04; - localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M04; - localparam CFM0_WP_OFFSET_MSB = 26; // From Max 10 Flash Memory User Guide. - localparam CFM0_WP_OFFSET_LSB = 24; // From Max 10 Flash Memory User Guide. - `elsif VARIANT_10M08 - localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08; - localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M08; - localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M08; - localparam CFM0_WP_OFFSET_MSB = 27; // From Max 10 Flash Memory User Guide. - localparam CFM0_WP_OFFSET_LSB = 25; // From Max 10 Flash Memory User Guide. - // The reconfiguration engine via flash is not supported in the XO3 variant. - `elsif VARIANT_XO3 - localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = 0; - localparam FLASH_PRIMARY_IMAGE_START_ADDR = 0; - localparam FLASH_PRIMARY_IMAGE_END_ADDR = 0; - localparam CFM0_WP_OFFSET_MSB = 0; - localparam CFM0_WP_OFFSET_LSB = 0; - `else - ERROR_MAX10_variant_must_be_defined(); - localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04; - localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M04; - localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M04; - localparam CFM0_WP_OFFSET_MSB = 26; // From Max 10 Flash Memory User Guide. - localparam CFM0_WP_OFFSET_LSB = 24; // From Max 10 Flash Memory User Guide. - `endif - - - //---------------------------------------------------------- - // Flash Interface between Registers and State Machine - //---------------------------------------------------------- - - // Flash Data Interface - reg [16:0] flash_addr = 0; - reg [31:0] flash_write_data = 0; - reg [31:0] flash_read_data; - - // Flash Control Interface - Control - reg flash_read_stb = 1'b0; - reg flash_write_stb = 1'b0; - reg flash_erase_stb = 1'b0; - reg flash_enable_wp_stb = 1'b0; - reg flash_disable_wp_stb = 1'b0; - reg [2:0] flash_sector = 3'b0; - - // Flash Control Interface - Status - reg flash_wp_enabled; - reg flash_read_idle; - reg flash_write_idle; - reg flash_erase_idle; - reg flash_read_err; - reg flash_write_err; - reg flash_erase_err; - reg clear_flash_read_err_stb = 1'b0; - reg clear_flash_write_err_stb = 1'b0; - reg clear_flash_erase_err_stb = 1'b0; - - //---------------------------------------------------------- - // Address Calculation - //---------------------------------------------------------- - - wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && - (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES); - - //---------------------------------------------------------- - // Handling of ControlPort Requests - //---------------------------------------------------------- - - always @(posedge ctrlport_clk) begin - // Default assignments - s_ctrlport_resp_ack <= 1'b0; - - flash_read_stb <= 1'b0; - flash_write_stb <= 1'b0; - flash_erase_stb <= 1'b0; - flash_enable_wp_stb <= 1'b0; - flash_disable_wp_stb <= 1'b0; - clear_flash_read_err_stb <= 1'b0; - clear_flash_write_err_stb <= 1'b0; - clear_flash_erase_err_stb <= 1'b0; - - // Do not acknowledge on reset - if (ctrlport_rst) begin - s_ctrlport_resp_ack <= 1'b0; - s_ctrlport_resp_data <= {32{1'bx}}; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - // Write requests - end else begin - if (s_ctrlport_req_wr) begin - // Always issue an ack and no data - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_data <= {32{1'bx}}; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + FLASH_CONTROL_REG: begin - flash_read_stb <= s_ctrlport_req_data[FLASH_READ_STB]; - flash_write_stb <= s_ctrlport_req_data[FLASH_WRITE_STB]; - flash_erase_stb <= s_ctrlport_req_data[FLASH_ERASE_STB]; - flash_enable_wp_stb <= s_ctrlport_req_data[FLASH_ENABLE_WP_STB]; - flash_disable_wp_stb <= s_ctrlport_req_data[FLASH_DISABLE_WP_STB]; - clear_flash_read_err_stb <= s_ctrlport_req_data[CLEAR_FLASH_READ_ERROR_STB]; - clear_flash_write_err_stb <= s_ctrlport_req_data[CLEAR_FLASH_WRITE_ERROR_STB]; - clear_flash_erase_err_stb <= s_ctrlport_req_data[CLEAR_FLASH_ERASE_ERROR_STB]; - flash_sector <= s_ctrlport_req_data[FLASH_ERASE_SECTOR_MSB:FLASH_ERASE_SECTOR]; - end - - BASE_ADDRESS + FLASH_ADDR_REG: begin - flash_addr <= s_ctrlport_req_data[FLASH_ADDR_MSB:FLASH_ADDR]; - end - - BASE_ADDRESS + FLASH_WRITE_DATA_REG: begin - flash_write_data <= s_ctrlport_req_data[FLASH_WRITE_DATA_MSB:FLASH_WRITE_DATA]; - end - - // Error on undefined address - default: begin - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - - // Read request - end else if (s_ctrlport_req_rd) begin - // Default assumption: valid request - s_ctrlport_resp_ack <= 1'b1; - s_ctrlport_resp_status <= CTRL_STS_OKAY; - - case (s_ctrlport_req_addr) - BASE_ADDRESS + FLASH_STATUS_REG: begin - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}}; - s_ctrlport_resp_data[FLASH_WP_ENABLED] <= flash_wp_enabled; - s_ctrlport_resp_data[FLASH_READ_IDLE] <= flash_read_idle; - s_ctrlport_resp_data[FLASH_READ_ERR] <= flash_read_err; - s_ctrlport_resp_data[FLASH_ERASE_IDLE] <= flash_erase_idle; - s_ctrlport_resp_data[FLASH_ERASE_ERR] <= flash_erase_err; - s_ctrlport_resp_data[FLASH_WRITE_IDLE] <= flash_write_idle; - s_ctrlport_resp_data[FLASH_WRITE_ERR] <= flash_write_err; - s_ctrlport_resp_data[FLASH_MEM_INIT_ENABLED] <= MEM_INIT ? 1'b1 : 1'b0; - end - - BASE_ADDRESS + FLASH_ADDR_REG: begin - s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'b0}}; - s_ctrlport_resp_data[FLASH_ADDR_MSB:FLASH_ADDR] <= flash_addr; - end - - BASE_ADDRESS + FLASH_READ_DATA_REG: begin - s_ctrlport_resp_data <= flash_read_data; - end - - BASE_ADDRESS + FLASH_CFM0_START_ADDR_REG: begin - s_ctrlport_resp_data <= MEM_INIT ? FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT : - FLASH_PRIMARY_IMAGE_START_ADDR; - end - - BASE_ADDRESS + FLASH_CFM0_END_ADDR_REG: begin - s_ctrlport_resp_data <= FLASH_PRIMARY_IMAGE_END_ADDR; - end - - // Error on undefined address - default: begin - s_ctrlport_resp_data <= {32{1'bx}}; - if (address_in_range) begin - s_ctrlport_resp_status <= CTRL_STS_CMDERR; - - // No response if out of range - end else begin - s_ctrlport_resp_ack <= 1'b0; - end - end - endcase - end - end - end - - //---------------------------------------------------------- - // State Machine Constants - //---------------------------------------------------------- - - // Local state - localparam IDLE = 4'h0; - localparam WP_DISABLED = 4'h1; - localparam WAIT_FOR_READ_DATA_VALID = 4'h2; - localparam GET_READ_STATUS = 4'h3; - localparam CHECK_READ_STATUS = 4'h4; - localparam WAIT_FOR_WRITE_COMPLETE = 4'h5; - localparam GET_WRITE_STATUS = 4'h6; - localparam CHECK_WRITE_STATUS = 4'h7; - localparam ERASE_SECTOR = 4'h8; - localparam GET_ERASE_BUSY = 4'h9; - localparam CHECK_ERASE_BUSY = 4'hA; - localparam GET_ERASE_IDLE = 4'hB; - localparam CHECK_ERASE_IDLE = 4'hC; - - // The Intel on-chip flash control interface has two registers, a Status - // Register at address 0 and a Control Register at address 1. The constants - // defined below identify fields and values of interest in each register. - // These are taken directly from the Max 10 Flash Memory User Guide. - localparam STATUS_REG_ADDR = 1'b0; - localparam STATUS_REG_BUSY_STATUS_MSB = 1; - localparam STATUS_REG_BUSY_STATUS_LSB = 0; - localparam STATUS_REG_IDLE = 2'b00; - localparam STATUS_REG_ERASE_BUSY = 2'b01; - localparam STATUS_REG_WRITE_BUSY = 2'b10; - localparam STATUS_REG_READ_BUSY = 2'b11; - localparam STATUS_REG_READ_STATUS = 2; - localparam STATUS_REG_WRITE_STATUS = 3; - localparam STATUS_REG_ERASE_STATUS = 4; - localparam OPERATION_FAILED = 0; - - localparam CONTROL_REG_ADDR = 1'b1; - localparam SECTOR_ERASE_ADDR_MSB = 22; - localparam SECTOR_ERASE_ADDR_LSB = 20; - // CFM0_WP_OFFSET_MSB and CFM0_WP_OFFSET_LSB are MAX10 variant dependent. - localparam ENABLE_WP = MEM_INIT ? 3'b111 : 3'b100; - localparam DISABLE_WP = 3'b000; - - //---------------------------------------------------------- - // State Machine - //---------------------------------------------------------- - - reg [3:0] state = IDLE; - wire flash_no_errors_detected; - - assign flash_no_errors_detected = ~(flash_read_err | flash_write_err | flash_erase_err); - - always @(posedge ctrlport_clk) begin - if (ctrlport_rst) begin - state <= IDLE; - - // Signals to config registers - flash_wp_enabled <= 1'b1; - flash_read_idle <= 1'b1; - flash_write_idle <= 1'b1; - flash_erase_idle <= 1'b1; - flash_read_err <= 1'b0; - flash_write_err <= 1'b0; - flash_erase_err <= 1'b0; - flash_read_data <= 32'b0; - - // Signals to flash control interface - csr_addr <= 1'b0; - csr_writedata <= {32 {1'b1}}; - csr_read <= 1'b0; - csr_write <= 1'b0; - - // Signals to flash data interface - data_addr <= 17'b0; - data_writedata <= 32'b0; - data_read <= 1'b0; - data_write <= 1'b0; - end - // Rising edge clock - else begin - // Default values - csr_read <= 1'b0; - csr_write <= 1'b0; - csr_addr <= STATUS_REG_ADDR; - csr_writedata <= {32 {1'b1}}; - - data_read <= 1'b0; - data_write <= 1'b0; - - // State handling - case(state) - - // When in IDLE: - // * No operations are in progress and write protection is enabled. - // * Allowed transitions are to either read data from flash or - // disable write protection. - // * Transitions are only allowed if no error bits are asserted. - // * In the event both the *read_stb and *disable_wp_stb bits are - // asserted read operations take priority as these do not open the - // flash to modification. - // * Attempts to both enable and disable write protection - // simultaneously result in the state machine remaining in IDLE - // write protection enabled. - IDLE: begin - flash_wp_enabled <= 1'b1; - - if (flash_read_stb && flash_no_errors_detected) begin - state <= WAIT_FOR_READ_DATA_VALID; - flash_read_idle <= 1'b0; - data_read <= 1'b1; - data_addr <= flash_addr; - end else if (flash_disable_wp_stb && ~flash_enable_wp_stb && flash_no_errors_detected) begin - state <= WP_DISABLED; - csr_write <= 1'b1; - csr_addr <= CONTROL_REG_ADDR; - csr_writedata[CFM0_WP_OFFSET_MSB:CFM0_WP_OFFSET_LSB] <= DISABLE_WP; - end - end - - // Transition from WP_DISABLED when write protection is enabled or when - // write/erase operations are initiated. A few things to note: - // * Enabling write protection takes priority, regardless of what - // other control bits may be asserted simultaneously, followed by - // writes, and lastly erases. - // * The user should not strobe both the *write_stb and *erase_stb - // bits simultaneously, but if they do the state machine returns to - // IDLE (thereby enabling write protection) and the *write_err and - // *erase_err bits are asserted. - // * Performing a write or erase operation is only allowed from - // WP_DISABLED. This allows some mitigation against data corruption - // as multiple steps are required to change the data in the flash. - // First write protection must be disabled, and only then can the - // flash be erased or written. - WP_DISABLED: begin - flash_wp_enabled <= 1'b0; - - if (flash_erase_stb && flash_write_stb) begin - flash_erase_err <= 1'b1; - flash_write_err <= 1'b1; - end - - if (flash_enable_wp_stb || (flash_erase_stb && flash_write_stb)) begin - state <= IDLE; - csr_write <= 1'b1; - csr_addr <= CONTROL_REG_ADDR; - csr_writedata[CFM0_WP_OFFSET_MSB:CFM0_WP_OFFSET_LSB] <= ENABLE_WP; - end else if (flash_write_stb) begin - state <= WAIT_FOR_WRITE_COMPLETE; - flash_write_idle <= 1'b0; - data_write <= 1'b1; - data_writedata <= flash_write_data; - data_addr <= flash_addr; - end else if (flash_erase_stb) begin - state <= ERASE_SECTOR; - flash_erase_idle <= 1'b0; - csr_write <= 1'b1; - csr_addr <= CONTROL_REG_ADDR; - csr_writedata[CFM0_WP_OFFSET_MSB:CFM0_WP_OFFSET_LSB] <= DISABLE_WP; - csr_writedata[SECTOR_ERASE_ADDR_MSB:SECTOR_ERASE_ADDR_LSB] <= flash_sector; - end - end - - - // Read Flash - // -------------- - // Per Intel's Max 10 User Flash Memory User Guide, the Read bit of the - // flash data interface should be pulsed for one clock cycle to start - // the read process from flash. This pulse occurs upon transition from - // IDLE to WAIT_FOR_READ_DATA_VALID. The state machine then waits in - // WAIT_FOR_READ_DATA_VALID until the flash data interface - // data_readdatavalid signal asserts, indicating the data is now valid. - // Intel's documentation does not provide guidance on the expected time - // for data_readdatavalid to assert. From simulation, however, - // data_readdatavalid asserts four clock cycles after the Read pulse - // ends. The data_readdatavalid signal from the flash data interface - // pulses for one clock cycle. Only during this pulse is the data valid. - WAIT_FOR_READ_DATA_VALID: begin - if (data_readdatavalid) begin - state <= GET_READ_STATUS; - flash_read_data <= data_readdata; - csr_read <= 1'b1; - end - end - - // The data_readdatavalid signal determines when the read operation has - // completed in the flash data interface, but Intel's documentation - // does not indicate the relation of this bit to the 'busy' field in - // the flash control interface Status Register. To verify that the read - // operation is complete, the StatusRegister is polled until the 'busy' - // field indicates the flash is idle. This polling operation is - // implemented with CHECK_READ_STATUS below. GET_READ_STATUS exists to - // set the address of the flash control interface to the Status - // Register and pulse the read bit of the flash control interface. - // CHECK_READ_STATUS evaluates the resulting Status Register data and - // steer the state machine accordingly. See Figure 6 in Intel's Max 10 - // User Flash Memory User Guide for a waveform on this request and - // check mechanism. Successful read operations result in the state - // machine returning to IDLE. Failing read operations assert the - // flash_read_err bit before returning to IDLE. From simulation, the - // 'busy' field returns to IDLE on the third read. - GET_READ_STATUS: begin - state <= CHECK_READ_STATUS; - // csr_read set in transactions into this state - // CSR address set as default assignment - end - CHECK_READ_STATUS: begin - if (csr_readdata[STATUS_REG_BUSY_STATUS_MSB:STATUS_REG_BUSY_STATUS_LSB] == STATUS_REG_IDLE) begin - state <= IDLE; - flash_read_idle <= 1'b1; - flash_read_err <= (csr_readdata[STATUS_REG_READ_STATUS] == OPERATION_FAILED) ? 1'b1 : 1'b0; - end else if (csr_readdata[STATUS_REG_BUSY_STATUS_MSB:STATUS_REG_BUSY_STATUS_LSB] == STATUS_REG_READ_BUSY) begin - state <= GET_READ_STATUS; - csr_read <= 1'b1; - end - end - - - // Write Flash - //--------------- - // Per Intel's Max 10 User Flash Memory User Guide, the Write bit of - // the flash data interface should be asserted while maintaining - // address and data until the flash interface deasserts the - // data_waitrequest bit. Transition from WP_DISABLED to - // WAIT_FOR_WRITE_COMPLETE causes the write bit to assert and address - // and data to be set. The state machine remains in this state until - // the data_waitrequest bit deasserts. Per Intel's Max 10 User Flash - // Memory User Guide, the data_waitrequest signal is expected to - // deassert within 555 usec. - WAIT_FOR_WRITE_COMPLETE: begin - if (~data_waitrequest) begin - state <= GET_WRITE_STATUS; - csr_read <= 1'b1; - end else begin - // Flash writes require asserting the Write bit of the flash data - // interface until the write is complete. - data_write <= 1'b1; - end - end - - // The data_waitrequest signal determines when the write operation has - // completed in the flash data interface, but Intel's documentation does - // not indicate the relation of this bit to the 'busy' field in the flash - // control interface Status Register. To verify that the write operation - // is complete the StatusRegister is polled until the 'busy' field - // indicates the flash is idle. This polling operation is implemented with - // GET_WRITE_STATUS and CHECK_WRITE_STATUS below, and follows the same - // methodology as the polling operation for reads described above with the - // following two changes: - // * Upon successful completion of a write operation the state - // machine returns to WP_DISABLED. This allows repeated writes of - // new data without having to disable/enable for each write. - // * When a failure is detected the state machine transitions to to - // IDLE thereby enabling write protection. Failure of a write is - // not expected. Write protection is enabled in the event of a - // failure to mitigate further data corruption. - GET_WRITE_STATUS: begin - state <= CHECK_WRITE_STATUS; - // csr_read set in transactions into this state - // CSR address set as default assignment - end - CHECK_WRITE_STATUS: begin - if (csr_readdata[STATUS_REG_BUSY_STATUS_MSB:STATUS_REG_BUSY_STATUS_LSB] == STATUS_REG_IDLE) begin - if (csr_readdata[STATUS_REG_WRITE_STATUS] == OPERATION_FAILED) begin - state <= IDLE; - csr_write <= 1'b1; - csr_addr <= CONTROL_REG_ADDR; - csr_writedata[CFM0_WP_OFFSET_MSB:CFM0_WP_OFFSET_LSB] <= ENABLE_WP; - end else begin // SUCCESS - state <= WP_DISABLED; - end - flash_write_idle <= 1'b1; - flash_write_err <= (csr_readdata[STATUS_REG_WRITE_STATUS] == OPERATION_FAILED) ? 1'b1 : 1'b0; - end else if (csr_readdata[STATUS_REG_BUSY_STATUS_MSB:STATUS_REG_BUSY_STATUS_LSB] == STATUS_REG_WRITE_BUSY) begin - state <= GET_WRITE_STATUS; - csr_read <= 1'b1; - end - end - - // Erase Flash - //------------- - // Erasing the primary configuration image requires a single write to - // the flash control interface Control Register. Only one sector needs - // to be erased to erase the entire primary configuration image. - // Transition from WP_DISABLED to ERASE_SECTOR causes data to be - // written to the Control Register to erase this sector and pulse the - // flash control interface write bit. - ERASE_SECTOR: begin - state <= GET_ERASE_BUSY; - csr_read <= 1'b1; - end - - // There is some latency between writing the Control Register and the - // 'busy' field of the flash control interface Status Register - // indicating the erase operation is in progress. After initiating the - // erase operation, GET_ERASE_BUSY and CHECK_ERASE_BUSY implement a - // polling operation to determine when the erase operation has started. - // GET_ERASE_BUSY exists to set the address of the flash control - // interface to the Status Register and pulse the read bit of the flash - // control interface. CHECK_ERASE_BUSY exists to evaluate the resulting - // Status Register data and steer the state machine accordingly. The - // polling operation continues until the 'busy' field indicates the - // erase operation is in progress. Intel's documentation does not - // indicate how long it takes for the Status Register to indicate the - // erase is in progress, but simulation shows the erase is in progress - // after the second read. - GET_ERASE_BUSY: begin - state <= CHECK_ERASE_BUSY; - // csr_read set in transactions into this state - // CSR address set as default assignment - end - CHECK_ERASE_BUSY: begin - if (csr_readdata[STATUS_REG_BUSY_STATUS_MSB:STATUS_REG_BUSY_STATUS_LSB] == STATUS_REG_ERASE_BUSY) begin - state <= GET_ERASE_IDLE; - csr_read <= 1'b1; - end else if (csr_readdata[STATUS_REG_BUSY_STATUS_MSB:STATUS_REG_BUSY_STATUS_LSB] == STATUS_REG_IDLE) begin - state <= GET_ERASE_BUSY; - csr_read <= 1'b1; - end - end - - // Once the erase operation is in progress a second polling operation - // defined by GET_ERASE_IDLE and CHECK_ERASE_IDLE is implemented to - // determine when the operation has completed. This polling operation - // follows the same methodology as the polling operation for erase busy - // described above. Intel's documentation indicates that erase - // operations take a maximum of 350 msec. - GET_ERASE_IDLE: begin - state <= CHECK_ERASE_IDLE; - // csr_read set in transactions into this state - // CSR address set as default assignment - end - CHECK_ERASE_IDLE: begin - if (csr_readdata[STATUS_REG_BUSY_STATUS_MSB:STATUS_REG_BUSY_STATUS_LSB] == STATUS_REG_IDLE) begin - if (csr_readdata[STATUS_REG_ERASE_STATUS] == OPERATION_FAILED) begin - state <= IDLE; - csr_write <= 1'b1; - csr_addr <= CONTROL_REG_ADDR; - csr_writedata[CFM0_WP_OFFSET_MSB:CFM0_WP_OFFSET_LSB] <= ENABLE_WP; - end else begin // SUCCESS - state <= WP_DISABLED; - end - flash_erase_idle <= 1'b1; - flash_erase_err <= (csr_readdata[STATUS_REG_ERASE_STATUS] == OPERATION_FAILED) ? 1'b1 : 1'b0; - end else if (csr_readdata[STATUS_REG_BUSY_STATUS_MSB:STATUS_REG_BUSY_STATUS_LSB] == STATUS_REG_ERASE_BUSY) begin - state <= GET_ERASE_IDLE; - csr_read <= 1'b1; - end - end - - // Default to IDLE in other cases - default: begin - state <= IDLE; - end - endcase - - // Reset errors - if (clear_flash_read_err_stb) begin - flash_read_err <= 1'b0; - end - if (clear_flash_write_err_stb) begin - flash_write_err <= 1'b0; - end - if (clear_flash_erase_err_stb) begin - flash_erase_err <= 1'b0; - end - end - end - -endmodule - - -`default_nettype wire - - -//XmlParse xml_on -// -// -// -// These registers are used to upload and verify a new primary image to the -// Max 10 FPGA on-chip flash when configured to support dual configuration -// images. The steps below outline the process of verifying/preparing the -// new image to be written, erasing the current image, writing the new -// image, and verifying the new image was successfully written. -// {p}{b}Prepare the data...{/b} -// {ol}{li}{p}The Max 10 FPGA build should generate a *cfm0_auto.rpd -// file The *.rpd file is a "raw programming -// data" file holding all data related to the -// configuration image (CFM0). There are two -// important items to note regarding the addresses. -// First the *rpd data uses {b}byte{/b} addresses. -// Second, the start/end addresses defined by -// FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses{/p}{/li} -// {li}{p}As a sanity check, verify the size of the raw -// programming data for CFM0 correspond to the address -// range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by -// reading the values from FLASH_CFM0_START_ADDR_REG and -// FLASH_CFM0_END_ADDR, subtract both values, add one and -// multiply by four. -// {/p}{/li} -// {li}{p}Having passed the sanity check the *.rpd data must -// now be manipulated into the form required by Altera's -// on-chip flash IP. Two operations must be performed. -// First the data must be converted from bytes to 32-bit -// words. Second the bit order must be reversed. This is -// illustrated in in the following table which shows byte -// address and data from the *.rpd file compared to the -// word address and data to be written to the on-chip -// flash. -// {table border=1} -// {tr}{td}.Map Addr{/td}{td}.Map Data{/td}{td}Flash Addr{/td}{td}Flash Data{/td}{/tr} -// {tr}{td}0x2B800{/td}{td}0x01{/td}{td rowspan=4}0xAC00{/td}{td rowspan=4}0x8040C020{/td}{/tr} -// {tr}{td}0x2B801{/td}{td}0x02{/td}{/tr} -// {tr}{td}0x2B802{/td}{td}0x03{/td}{/tr} -// {tr}{td}0x2B803{/td}{td}0x04{/td}{/tr} -// {tr}{td}0x2B804{/td}{td}0x05{/td}{td rowspan=4}0xAC01{/td}{td rowspan=4}0xA060E010{/td}{/tr} -// {tr}{td}0x2B805{/td}{td}0x06{/td}{/tr} -// {tr}{td}0x2B806{/td}{td}0x07{/td}{/tr} -// {tr}{td}0x2B807{/td}{td}0x08{/td}{/tr} -// {/table} -// {/p}{/li} -// {li}{p}The resulting set of flash address data pairs should -// be used when writing FLASH_ADDR_REG and -// FLASH_WRITE_DATA_REG to update the CFM0 image. -// However, prior to writing the new image the old image -// must be erased. -// {/p}{/li} -// {/ol} -// {/p} -// {p}{b}Erase the current primary flash image...{/b} -// {ol}{p}{li}Read FLASH_STATUS_REG and verify no error bits are -// asserted and that all read, write, and erase operations -// are idle.{/p}{/li} -// {p}{li}Disable write protection of the flash by strobing the -// FLASH_DISABLE_WP_STB bit of FLASH_CONTROL_REG. -// {/p}{/li} -// {p}{li}Verify write protection is disabled and no errors are -// present by reading FLASH_STATUS_REG.{/p}{/li} -// {p}{li}Initiate the erase operation by setting -// @.FLASH_ERASE_SECTOR and strobing FLASH_ERASE_STB of -// FLASH_CONTROL_REG.{/p}{/li} -// {p}{li}Poll the FLASH_ERASE_IDLE bit of -// FLASH_STATUS_REG until it de-asserts indicating the -// erase operation is complete, then verify the operation -// was successful by checking that the FLASH_ERASE_ERR -// bit is de-asserted. Erase operations are expected to -// take a maximum of 350 msec. Upon completion of the erase -// operation write protection will remain disabled. -// {/p}{/li} -// {p}{li}Erase additional sectors as required (see -// @.FLASH_ERASE_SECTOR for details) by restarting with first -// step.{/p}{/li} -// {/ol} -// {/p} -// {p}{b}Write the new primary flash image...{/b} -// {ol}{p}{li}Read FLASH_STATUS_REG and verify no error bits are -// asserted, all read, write, and erase operations are -// idle, and write protection is disabled.{/li} -// {p}{li}Set the target address for the write to the Max 10 -// on-chip flash by writing value from -// FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.{/li}{/p} -// {p}{li}Set the data to be written to this address by writing -// the new 32-bit word of the new image to -// FLASH_WRITE_DATA_REG.{/li}{/p} -// {p}{li}Initiate the write by strobing FLASH_WRITE_STB of -// FLASH_CONTROL_REG.{/li}{/p} -// {p}{li}Poll the FLASH_WRITE_IDLE bit of -// FLASH_STATUS_REG until it de-asserts indicating the -// write operation is complete, then verify the operation -// was successful by checking that the FLASH_WRITE_ERR -// bit is de-asserted. Write operations are expected to -// take a maximum of 550 usec.{/li}{/p} -// {p}{li}Upon completion of the write operation return to step -// 2, incrementing the target address by one, and writing -// the next 32-bit word to Max10FlashWriteDatReg. If this -// was the last write, indicated by writing to -// FLASH_PRIMARY_IMAGE_END_ADDR, proceed to the next step -// to enable write protection.{/li}{/p} -// {p}{li}After writing the new image enable write protection -// by strobing the FLASH_ENABLE_WP_STB bit of -// FLASH_CONTROL_REG.{/li}{/p} -// {/ol} -// {/p} -// {p}{b}Verify the new primary flash image...{/b} -// {ol}{p}{li}Read FLASH_STATUS_REG and verify no error bits are -// asserted and that all read, write, and erase operations -// are idle.{/li}{/p} -// {p}{li}Set the target address for the read in the Max 10 -// on-chip flash by writing value from -// FLASH_CFM0_START_ADDR_REG to FLASH_ADDR_REG.{/li}{/p} -// {p}{li}Initiate the read by strobing FLASH_READ_STB of -// FLASH_CONTROL_REG.{/li}{/p} -// {p}{li}Poll the FLASH_READ_IDLE bit of -// FLASH_STATUS_REG until it de-asserts indicating the -// read operation is complete, then verify the operation -// was successful by checking that the FLASH_READ_ERR -// bit is de-asserted. There is no guidance on exactly how -// long reads take to complete, but they are expected to be -// fairly quick. A very conservative timeout on this -// polling would be similar to that used for write -// operations.{/li}{/p} -// {p}{li}Upon completion of the read operation the resulting -// data returned by the on-chip flash will be available in -// Max10FlashReadDatReg. Read this register, compare to -// expected value previously written, and ensure they -// match.{/li}{/p} -// {p}{li}Return to step 2, incrementing the target -// address by one. If this was the last read verification -// is complete and no further action is required.{/li}{/p} -// {/ol} -// {/p} -// {p}After the flash has been erased, programmed, and verified, a power -// cycle is required for the new image to become active. -// {/p} -// -// -// -// These values are the start and end address of the CFM image flash -// sector from Intel's On-Chip Flash IP Generator. -// Be aware that three different values exist per each of the two -// supported MAX10 variants: 10M04 and 10M08 -// Note that the values given in the IP generator are byte based where -// the values of this enum are U32 based (divided by 4). -// -// -// -// -// -// -// -// -// -// -// -// -// This bit is asserted when the flash is write protected and -// de-asserted when write protection is disabled. -// {li}Write protection must be enabled prior to performing read -// operations.{/li} -// {li}Write protection must be disabled prior to performing write and -// erase operations.{/li} -// -// -// -// -// This bit is de-asserted when a read operation is in progress. Poll -// this bit after strobing the FLASH_READ_STB bit of -// FLASH_CONTROL_REG to determine when the read operation has -// completed, then check the FLASH_READ_ERR bit to verify the -// operation was successful. -// -// -// -// -// This bit is asserted when a read operation fails. Clear this error -// by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the -// event of a read error... -// {li}the data in FLASH_READ_DATA_REG is invalid.{/li} -// {li}attempts to disable write protection will be ignored.{/li} -// {li}attempts to read/write/erase the flash will be ignored.{/li} -// -// -// -// -// This bit is de-asserted when an erase operation is in progress. Poll -// this bit after strobing the FLASH_ERASE_STB bit of -// FLASH_CONTROL_REG to determine when the erase operation has -// completed, then check the FLASH_ERASE_ERR bit to verify the -// operation was successful. -// -// -// -// -// This bit is asserted when an erase operation fails. Clear this -// error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In -// the event of an erase error... -// {li}{b}the primary configuration image may be corrupted,{/b} and -// power cycling the board may result in unknown behavior.{/li} -// {li}write protection of the flash will automatically be -// re-enabled.{/li} -// {li}attempts to disable write protection will be ignored.{/li} -// {li}attempts to read/write/erase the flash will be ignored.{/li} -// -// -// -// -// This bit is de-asserted when a write operation is in progress. Poll -// this bit after strobing the FLASH_WRITE_STB bit of -// FLASH_CONTROL_REG to determine when the write operation has -// completed, then check the FLASH_WRITE_ERR bit to verify the -// operation was successful. -// -// -// -// -// This bit is asserted when write operation fails. Clear this error -// by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In -// the event of a write error... -// {li}{b}the primary configuration image may be corrupted,{/b} and -// power cycling the board may result unknown behavior.{/li} -// {li}write protection of the flash will automatically be -// re-enabled.{/li} -// {li}attempts to disable write protection will be ignored.{/li} -// {li}attempts to read/write/erase the flash will be ignored.{/li} -// -// -// -// -// This bit is asserted when the flash can hold an image with memory -// initialization. -// -// -// -// -// -// -// Strobe this bit to enable write protection to the section of the -// Max 10 on-chip flash storing the primary configuration image -// (CFM0). -// {li}Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to -// determine the current state of write protection.{/li} -// {li}Prior to strobing this bit verify no write or erase operations -// are in progress and no error bits are asserted by reading -// FLASH_STATUS_REG.{/li} -// {li}Attempts to enable write protection while erase or write -// operations are in progress will be ignored.{/li} -// {li}Write protection must be enabled prior to performing -// read operations.{/li} -// {li}Write protection should be enabled after completing -// write or erase operations to prevent data corruption.{/li} -// -// -// -// -// Strobe this bit to disable write protection to the section of the -// Max 10 on-chip flash storing the primary configuration image -// (CFM0). -// {li}Read the FLASH_WP_ENABLED bit of FLASH_STATUS_REG to -// determine the current state of write protection.{/li} -// {li}Prior to strobing this bit verify no read operations are in -// progress and no error bits are asserted by reading -// FLASH_STATUS_REG.{/li} -// {li}Attempts to disable write protection while a read is in -// progress will be ignored.{/li} -// {li}Attempts to disable write protection will be ignored if -// this bit is strobed simultaneously with either FLASH_READ_STB -// or FLASH_ENABLE_WP_STB.{/li} -// {li}Write protection must be disabled prior to performing erase or -// write operations.{/li} -// {li}Upon completion of erase/write operations write protection -// will remain disabled. When not actively erasing or writing a new -// image write protection should be enabled to avoid data -// corruption.{/li} -// -// -// -// -// Strobe this bit to read data from the flash address identified in -// FLASH_ADDR_REG. -// {li}Prior to strobing this bit verify no read, write, or erase -// operations are in progress, no error bits are asserted, and -// write protection is enabled by reading FLASH_STATUS_REG.{/li} -// {li}Attempts to read data while other operations are in progress -// or while write protection is disabled will be ignored.{/li} -// {li}After strobing this bit poll the FLASH_READ_IDLE and -// FLASH_READ_ERR bits of FLASH_STATUS_REG to determine when -// the read operation is complete and if it was successful.{/li} -// {li}Upon successful completion the data read from flash will be -// available in FLASH_READ_DATA_REG.{/li} -// -// -// -// -// Strobe this bit to write the data contained in -// FLASH_WRITE_DATA_REG to the flash address identified in -// FLASH_ADDR_REG. -// {li}The flash must be erased before writing new data.{/li} -// {li}Prior to strobing this bit verify write protection is -// disabled, no other write or erase operations are in progress, and -// no error bits are asserted by reading FLASH_STATUS_REG.{/li} -// {li}Attempts to write data while other write or erase operations -// are in progress will be ignored.{/li} -// {li}Attempts to write data with write protection enabled will be -// ignored.{/li} -// {li}Strobing this bit and FLASH_ERASE_STB simultaneously will -// result in both the write and erase operation being ignored, -// both corresponding error bits being set, and write protection -// being re-enabled.{/li} -// {li}After strobing this bit poll theMax10FlashWriteIdle and -// FLASH_WRITE_ERR bits of FLASH_STATUS_REG to determine when -// the write operation is complete and if it was successful.{/li} -// -// -// -// -// Strobe this bit to erase the primary Max10 configuration image -// (CFM0). -// {li}Prior to strobing this bit verify no other write or erase -// operations are in progress, write protection is disabled, and no -// error bits are asserted by reading FLASH_STATUS_REG.{/li} -// {li}Attempts to erase the primary image while other write or erase -// operations are in progress will be ignored. -// {li}Attempts to erase the primary image when write protection is -// enabled will be ignored.{/li} -// {li}Strobing this bit and FLASH_WRITE_STB simultaneously will -// result both the erase and the write operation being ignored, both -// corresponding error bits being set, and write protection being -// re-enabled.{/li} -// {li}After strobing this bit poll the FLASH_ERASE_IDLE and -// FLASH_ERASE_ERR bits of FLASH_STATUS_REG to determine when -// the erase operation is complete and if it was successful.{/li} -// -// -// -// -// Defines the sector to be erased. Has to be set latest with the -// write access which starts the erase operation by strobing -// @.FLASH_ERASE_STB.{br} -// With 10M04 variants, if the flash is configured to support memory -// initialization (see @.FLASH_MEM_INIT_ENABLED flag) the sectors 2 -// to 4 have to be erased. If the flag is not asserted only sector 4 -// has to be erased. -// With 10M08 variants, the sectors to be erased are 3 to 5 when -// using memory initialization or only sector 5 otherwise. -// -// -// -// -// Strobe this bit to clear a read error. -// -// -// -// -// Strobe this bit to clear a write error. -// -// -// -// -// Strobe this bit to clear an erase error. -// -// -// -// -// -// -// This field holds the target address for the next read or -// write operation. Set this field prior to strobing the -// FLASH_WRITE_STB and FLASH_READ_STB bits of -// FLASH_CONTROL_REG. Valid addresses are defined by the -// FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration. -// -// -// -// -// -// -// Data in this register will be written to the flash at the address -// identified in FLASH_ADDR_REG when a successful write operation -// is executed. -// -// -// -// -// -// -// This register contains data read from the flash address identified -// in FLASH_ADDR_REG after a successful read operation is executed. -// -// -// -// -// -// -// Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM). -// -// -// -// -// -// -// Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM). -// -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/cpld/regmap/mb_cpld_pl_regmap_utils.vh b/top/x400/cpld/regmap/mb_cpld_pl_regmap_utils.vh deleted file mode 100644 index d4f2135..0000000 --- a/top/x400/cpld/regmap/mb_cpld_pl_regmap_utils.vh +++ /dev/null @@ -1,36 +0,0 @@ -// -// Copyright 2022 Ettus Research, A National Instruments Company -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: mb_cpld_pl_regmap_utils.vh -// Description: -// The constants in this file are autogenerated by XmlParse. - -//=============================================================================== -// A numerically ordered list of registers and their HDL source files -//=============================================================================== - - // PL_REGISTERS : 0x0 (mb_cpld.v) - // JTAG_DB0 : 0x60 (mb_cpld.v) - // JTAG_DB1 : 0x80 (mb_cpld.v) - -//=============================================================================== -// RegTypes -//=============================================================================== - -//=============================================================================== -// Register Group MB_CPLD_PL_WINDOWS -//=============================================================================== - - // PL_REGISTERS Window (from mb_cpld.v) - localparam PL_REGISTERS = 'h0; // Window Offset - localparam PL_REGISTERS_SIZE = 'h40; // size in bytes - - // JTAG_DB0 Window (from mb_cpld.v) - localparam JTAG_DB0 = 'h60; // Window Offset - localparam JTAG_DB0_SIZE = 'h20; // size in bytes - - // JTAG_DB1 Window (from mb_cpld.v) - localparam JTAG_DB1 = 'h80; // Window Offset - localparam JTAG_DB1_SIZE = 'h20; // size in bytes diff --git a/top/x400/cpld/reset_generator.v b/top/x400/cpld/reset_generator.v deleted file mode 100644 index dd3a560..0000000 --- a/top/x400/cpld/reset_generator.v +++ /dev/null @@ -1,93 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: reset_generator -// -// Description: -// -// Generates a power-on reset signal that is asserted at startup and stays -// asserted for at least CYCLES_IN_RESET clock cycles. -// -// Internally, it generates a 1-bit synchronous signal (initialize) to safely -// initialize the power_on_reset_counter incremental counter to 0's. -// -// A delayed version of the initializing signal is also generated -// (counter_enable) to start counting. -// -// 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ 9_ -// clk _| |_| |_| |_| |_| |_| |_| |_| |_| -// _____________________ -// initialize _____________| -// _________ -// counter_enable _________________________| -// - -`default_nettype none - - -module reset_generator ( - input wire clk, - output reg power_on_reset = 1'b1 -); - - wire [0:0] counter_enable; - wire [0:0] initialize; - - synchronizer #( - .WIDTH (1), - .STAGES (3), - .INITIAL_VAL (1'b0), - .FALSE_PATH_TO_IN (0) - ) init_sync_inst ( - .clk (clk), - .rst (1'b0), - .in (1'b1), - .out (initialize) - ); - - synchronizer #( - .WIDTH (1), - .STAGES (3), - .INITIAL_VAL (1'b0), - .FALSE_PATH_TO_IN (0) - ) counter_en_sync_inst ( - .clk (clk), - .rst (1'b0), - .in (initialize), - .out (counter_enable) - ); - - // Internal synchronous reset generator. - localparam CYCLES_IN_RESET = 20; - reg [7:0] power_on_reset_counter = 8'b0; - - // This block generates a synchronous reset in the clk domain that can be - // used by downstream logic. - // - // power_on_reset_counter is first initialized to 0's upon assertion of - // initialize. Some cycles later (3), upon assertion if counter_enable, - // power_on_reset_counter starts to increment. - // - // power_on_reset will remain asserted until power_on_reset_counter reaches - // cycles_in_reset, resulting in the deassertion of power_on_reset. - always @(posedge clk) begin : power_on_reset_gen - if (counter_enable) begin - if (power_on_reset_counter == CYCLES_IN_RESET-1) begin - power_on_reset <= 1'b0; - end else begin - power_on_reset_counter <= power_on_reset_counter + 1'b1; - power_on_reset <= 1'b1; - end - end - else if (initialize) begin - power_on_reset_counter <= 8'b0; - power_on_reset <= 1'b1; - end - end - -endmodule - - -`default_nettype wire diff --git a/top/x400/cpld/spi_slave.v b/top/x400/cpld/spi_slave.v deleted file mode 100644 index ab2f16f..0000000 --- a/top/x400/cpld/spi_slave.v +++ /dev/null @@ -1,288 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: spi_slave -// -// Description: -// -// SPI slave for configuration CPOL = CPHA = 0. -// Transfers 8 bit = 1 byte MSB first. Parallel data has to be -// provided and consumed immediately when flags are asserted. -// -// Limitation: clk frequency <= 2*sclk frequency -// -// Data request from sclk domain is triggered towards the clk domain ahead of -// time. This is due to the clock domain crossing using the synchronizer and -// processing pipeline stages. -// -// The worst case propagation delay of the used synchronizer is: -// -// 4 'clk' clock cycles: -// 1 clock cycle of signal propagation to synchronizer -// (data_request_sclk assertion) -// 1 clock cycle to capture data with instability in first stage -// 1 clock cycle to stabilize first stage -// 1 clock cycle to capture data in second stage -// (data_request_clk available in 'clk' domain) -// -// Once synchronized in 'clk' domain, there is one additional clock cycle to -// derive data_out_valid and data_in_required. To ensure that transmit data -// is registered a 'clk' cycle ahead of the actual transmission we need 2 -// more 'clk' clock cycles. This ensures that transmit_word has changed and -// is stable for at least one 'clk' cycle before 'sclk' asserts again. Any -// additional time required externally to respond to the control port -// requests should be considered in this crossing as well. This is a total of -// 7 clock cycles (+ctrlport response margin) @ clk domain. The minimum -// required time in sclk domain to issue the request is calculated based on -// the clock frequencies. -// -// Parameters: -// -// CLK_FREQUENCY : Frequency of "clk" -// SPI_FREQUENCY : Frequency of "sclk" -// - -`default_nettype none - - -module spi_slave #( - parameter CLK_FREQUENCY = 50000000, - parameter SPI_FREQUENCY = 10000000 -) ( - //--------------------------------------------------------------- - // SPI Interface - //--------------------------------------------------------------- - - input wire sclk, - input wire cs_n, - input wire mosi, - output wire miso, - - //--------------------------------------------------------------- - // Parallel Interface - //--------------------------------------------------------------- - - input wire clk, - input wire rst, - - output reg data_in_required, - input wire data_in_valid, - input wire [7:0] data_in, - - output reg data_out_valid, - output reg [7:0] data_out, - - output wire active -); - - wire [0:0] data_request_clk; - wire [0:0] reception_complete_clk; - - //--------------------------------------------------------------- - // SPI Receiver @ sclk - //--------------------------------------------------------------- - - reg [7:0] receiver_reg; - reg [2:0] current_bit_index; - reg reception_complete_sclk = 1'b0; - reg [7:0] received_word; - - always @(posedge sclk or posedge cs_n) begin - // Reset logic on positive cs_n edge = slave idle - if (cs_n) begin - receiver_reg <= 8'b0; - end - // Rising edge of sclk - else begin - // Capture bits into shift register MSBs first - receiver_reg <= {receiver_reg[6:0], mosi}; - end - end - - // Reset with cs_n might occur too early during clk sync. - // Reset half way through the reception. - always @(posedge sclk) begin - // Complete word was received - if (current_bit_index == 7) begin - reception_complete_sclk <= 1'b1; - received_word <= {receiver_reg[6:0], mosi}; - - // Reset after half transaction - end else if (current_bit_index == 3) begin - reception_complete_sclk <= 1'b0; - end - end - - //--------------------------------------------------------------- - // Handover of data sclk -> clk - //--------------------------------------------------------------- - - synchronizer #( - .WIDTH (1), - .STAGES (2), - .INITIAL_VAL (1'b0), - .FALSE_PATH_TO_IN (1) - ) data_sync_inst ( - .clk (clk), - .rst (1'b0), - .in (reception_complete_sclk), - .out (reception_complete_clk) - ); - - //--------------------------------------------------------------- - // Parallel interface data output @ clk - //--------------------------------------------------------------- - - reg reception_complete_clk_delayed = 1'b0; - - // Propagate toggling signal without reset to ensure stability on reset - always @(posedge clk) begin - // Capture last state of reception - reception_complete_clk_delayed <= reception_complete_clk; - end - - // Derive data and control signal - always @(posedge clk) begin - if (rst) begin - data_out_valid <= 1'b0; - data_out <= 8'b0; - end - else begin - // Default assignment - data_out_valid <= 1'b0; - - // Provide data to output on rising_edge - if (reception_complete_clk & ~reception_complete_clk_delayed) begin - // Data can simply be captured as the reception complete signal - // indicates stable values in received_word. - data_out <= received_word; - data_out_valid <= 1'b1; - end - end - end - - //--------------------------------------------------------------- - // SPI Transmitter @ sclk - //--------------------------------------------------------------- - - // Data request calculation: - // SCLK_CYCLES_DURING_DATA_REQ = 8 clk period / sclk period - // Clock periods are expressed by reciprocal of frequencies. - // Term "+CLK_FREQUENCY-1" is used to round up the result in integer logic. - localparam SCLK_CYCLES_DURING_DATA_REQ = (8*SPI_FREQUENCY + CLK_FREQUENCY-1)/CLK_FREQUENCY; - // subtract from 8 bits per transfer to get target index - localparam DATA_REQ_BIT_INDEX = 8 - SCLK_CYCLES_DURING_DATA_REQ; - - reg [7:0] transmit_bits; - reg [7:0] transmit_word; - reg data_request_sclk = 1'b0; - - always @(negedge sclk or posedge cs_n) begin - // Reset logic on positive cs_n edge = slave idle - if (cs_n) begin - current_bit_index <= 3'b0; - data_request_sclk <= 1'b0; - transmit_bits <= 8'b0; - end - // Falling edge of sclk - else begin - // Fill or move shift register for byte transmissions - if (current_bit_index == 7) begin - transmit_bits <= transmit_word; - end else begin - transmit_bits <= {transmit_bits[6:0], 1'b0}; - end - - // Update bit index - current_bit_index <= current_bit_index + 1'b1; - - // Trigger request for new word at start of calculated index - if (current_bit_index == DATA_REQ_BIT_INDEX-1) begin - data_request_sclk <= 1'b1; - // Reset after half the reception in case cs_n is not changed in between - // two transactions. - end else if (current_bit_index == (DATA_REQ_BIT_INDEX+4-1)%8) begin - data_request_sclk <= 1'b0; - end - end - end - - // Drive miso output with data when cs_n low - assign miso = cs_n ? 1'bz : transmit_bits[7]; - - //--------------------------------------------------------------- - // Handover of Data Request sclk -> clk - //--------------------------------------------------------------- - - synchronizer #( - .WIDTH (1), - .STAGES (2), - .INITIAL_VAL (1'b0), - .FALSE_PATH_TO_IN (1) - ) request_sync_inst ( - .clk (clk), - .rst (rst), - .in (data_request_sclk), - .out (data_request_clk) - ); - - //--------------------------------------------------------------- - // Parallel Interface Data Input Control - //--------------------------------------------------------------- - - reg data_request_clk_delayed; - - always @(posedge clk) begin - if (rst) begin - data_request_clk_delayed <= 1'b0; - data_in_required <= 1'b0; - transmit_word <= 8'b0; - end - else begin - // Default assignment - data_in_required <= 1'b0; - - // Capture last state of data request - data_request_clk_delayed <= data_request_clk; - - // Request data from input - if (~data_request_clk_delayed & data_request_clk) begin - data_in_required <= 1'b1; - end - - // Capture new data if valid data available, 0 otherwise. - if (data_in_required) begin - if (data_in_valid) begin - transmit_word <= data_in; - end else begin - transmit_word <= 8'b0; - end - end - end - end - - //--------------------------------------------------------------- - // Chip Select - //--------------------------------------------------------------- - // Driven as active signal in parallel clock domain - - wire cs_n_clk; - assign active = ~cs_n_clk; - synchronizer #( - .WIDTH (1), - .STAGES (2), - .INITIAL_VAL (1'b1), - .FALSE_PATH_TO_IN (1) - ) active_sync_inst ( - .clk (clk), - .rst (rst), - .in (cs_n), - .out (cs_n_clk) - ); - -endmodule - - -`default_nettype wire diff --git a/top/x400/cpld/spi_slave_to_ctrlport_master.v b/top/x400/cpld/spi_slave_to_ctrlport_master.v deleted file mode 100644 index 6f624fe..0000000 --- a/top/x400/cpld/spi_slave_to_ctrlport_master.v +++ /dev/null @@ -1,238 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: spi_slave_to_ctrlport_master -// -// Description: -// -// SPI slave to ContolPort master conversion in order to tunnel control port -// request through an SPI bus. -// -// The request format on SPI is defined as: -// -// Write request: -// 1'b1 = write, 15 bit address, 32 bit data (MOSI), 8 bit processing gap, -// 5 bit padding, 1 bit ack, 2 bit status -// -// Read request: -// 1'b0 = read, 15 bit address, 8 bit processing gap, 32 bit data (MISO), -// 5 bit padding, 1 bit ack, 2 bit status -// -// Parameters: -// -// CLK_FREQUENCY : Frequency of "clk" -// SPI_FREQUENCY : Frequency of "sclk" -// - -`default_nettype none - - -module spi_slave_to_ctrlport_master #( - parameter CLK_FREQUENCY = 50000000, - parameter SPI_FREQUENCY = 10000000 -) ( - //--------------------------------------------------------------- - // ControlPort Master - //--------------------------------------------------------------- - - input wire ctrlport_clk, - input wire ctrlport_rst, - - output wire m_ctrlport_req_wr, - output wire m_ctrlport_req_rd, - output wire [19:0] m_ctrlport_req_addr, - output wire [31:0] m_ctrlport_req_data, - - input wire m_ctrlport_resp_ack, - input wire [ 1:0] m_ctrlport_resp_status, - input wire [31:0] m_ctrlport_resp_data, - - //--------------------------------------------------------------- - // SPI Slave - //--------------------------------------------------------------- - - input wire sclk, - input wire cs_n, - input wire mosi, - output wire miso -); - - `include "../../../lib/rfnoc/core/ctrlport.vh" - - //--------------------------------------------------------------- - // SPI Slave - //--------------------------------------------------------------- - - wire [7:0] data_in; - wire [7:0] data_out; - wire data_in_valid; - wire data_out_valid; - wire data_in_required; - wire spi_slave_active; - - spi_slave #( - .CLK_FREQUENCY (CLK_FREQUENCY), - .SPI_FREQUENCY (SPI_FREQUENCY) - ) spi_slave_async ( - .sclk (sclk), - .cs_n (cs_n), - .mosi (mosi), - .miso (miso), - .clk (ctrlport_clk), - .rst (ctrlport_rst), - .data_in_required (data_in_required), - .data_in_valid (data_in_valid), - .data_in (data_in), - .data_out_valid (data_out_valid), - .data_out (data_out), - .active (spi_slave_active) - ); - - //--------------------------------------------------------------- - // Reset Generation from SPI Slave - //--------------------------------------------------------------- - - reg spi_slave_active_delayed = 1'b0; - always @(posedge ctrlport_clk) begin - if (ctrlport_rst) begin - spi_slave_active_delayed <= 1'b0; - end - else begin - spi_slave_active_delayed <= spi_slave_active; - end - end - - // Trigger reset on falling edge of active signal (rising edge of cs_n) - wire spi_slave_reset; - assign spi_slave_reset = spi_slave_active_delayed & (~spi_slave_active); - - //--------------------------------------------------------------- - // Transfer Constants - //--------------------------------------------------------------- - - localparam NUM_BYTES_TRANSACTION = 8; - localparam NUM_BYTES_WRITE_REQUEST_PAYLOAD = 6; - localparam NUM_BYTES_READ_REQUEST_PAYLOAD = 2; - localparam MAX_BYTES_RESPONSE_PAYLOAD = 5; - - //--------------------------------------------------------------- - // Data Receiver - //--------------------------------------------------------------- - - reg [3:0] num_bytes_received; - reg request_received; - reg write_request; - reg provide_response; - reg [NUM_BYTES_WRITE_REQUEST_PAYLOAD*8-1:0] request_reg = {NUM_BYTES_WRITE_REQUEST_PAYLOAD*8 {1'b0}}; - - always @(posedge ctrlport_clk) begin - if (ctrlport_rst || spi_slave_reset) begin - num_bytes_received <= 4'b0; - request_received <= 1'b0; - write_request <= 1'b0; - provide_response <= 1'b0; - end - else begin - // Counter number of received bytes - if (data_out_valid) begin - // Increment counter - num_bytes_received <= num_bytes_received + 1'b1; - - if (num_bytes_received == NUM_BYTES_TRANSACTION-1) begin - num_bytes_received <= 4'b0; - end - end - - // Check for read / write on first received byte's MSB - if (data_out_valid && (num_bytes_received == 0)) begin - write_request <= data_out[7]; - end - - // Detect complete request - request_received <= 1'b0; - if (data_out_valid) begin - if (write_request && (num_bytes_received == NUM_BYTES_WRITE_REQUEST_PAYLOAD-1)) begin - request_received <= 1'b1; - provide_response <= 1'b1; - end else if (~write_request && (num_bytes_received == NUM_BYTES_READ_REQUEST_PAYLOAD-1)) begin - request_received <= 1'b1; - provide_response <= 1'b1; - end - end - - // Detect end of response on last received byte - if (num_bytes_received == NUM_BYTES_TRANSACTION-1) begin - provide_response <= 1'b0; - end - - // Capture data into shift register - if (data_out_valid) begin - request_reg <= {request_reg[NUM_BYTES_WRITE_REQUEST_PAYLOAD*8-8-1:0], data_out}; - end - end - end - - // Drive ControlPort - localparam SPI_TRANSFER_ADDRESS_WIDTH = 15; - assign m_ctrlport_req_wr = request_received && write_request; - assign m_ctrlport_req_rd = request_received && ~write_request; - assign m_ctrlport_req_data = request_reg[CTRLPORT_DATA_W-1:0]; - assign m_ctrlport_req_addr = (write_request) ? - {5'b0, request_reg[CTRLPORT_DATA_W+:SPI_TRANSFER_ADDRESS_WIDTH]} : - {5'b0, request_reg[0+:SPI_TRANSFER_ADDRESS_WIDTH]}; - - //--------------------------------------------------------------- - // Response Handling - //--------------------------------------------------------------- - - reg [MAX_BYTES_RESPONSE_PAYLOAD*8-1:0] response_reg; - reg ready_for_response; // active during processing gap - wire write_response_byte; - - always @(posedge ctrlport_clk) begin - if (ctrlport_rst || spi_slave_reset) begin - response_reg <= {8*MAX_BYTES_RESPONSE_PAYLOAD {1'b0}}; - ready_for_response <= 1'b0; - end - else begin - // Reset response on new request - if (request_received) begin - ready_for_response <= 1'b1; - if (write_request) begin - // Just last byte -> padding, ack flag, CMDERR, padding (data length) - response_reg <= {5'b0, 1'b1, CTRL_STS_CMDERR, {CTRLPORT_DATA_W{1'b0}}}; - end else begin - // Last 5 bytes -> data = 0, Padding, ack flag, CMDERR - response_reg <= {{CTRLPORT_DATA_W{1'b0}}, 5'b0, 1'b1, CTRL_STS_CMDERR}; - end - - // Capture response within processing gap, leave default response from above otherwise - end else if (m_ctrlport_resp_ack && ready_for_response) begin - if (write_request) begin - response_reg <= {5'b0, m_ctrlport_resp_ack, m_ctrlport_resp_status, {CTRLPORT_DATA_W{1'b0}}}; - end else begin - response_reg <= {m_ctrlport_resp_data, 5'b0, m_ctrlport_resp_ack, m_ctrlport_resp_status}; - end - end - - // Shift data after writing to slave - if (write_response_byte) begin - response_reg <= {response_reg[0+:(MAX_BYTES_RESPONSE_PAYLOAD-1)*8], 8'b0}; - ready_for_response <= 1'b0; - end - end - end - - // Response is written after request part has been transferred - assign write_response_byte = data_in_required && provide_response; - - // Assign SPI slave inputs - assign data_in = response_reg[(MAX_BYTES_RESPONSE_PAYLOAD-1)*8+:8]; - assign data_in_valid = write_response_byte; - -endmodule - - -`default_nettype wire diff --git a/top/x400/cpld/x440/led_control.v b/top/x400/cpld/x440/led_control.v new file mode 100644 index 0000000..c43a526 --- /dev/null +++ b/top/x400/cpld/x440/led_control.v @@ -0,0 +1,222 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: led_control +// +// Description: +// Implements control over LED state via CtrlPort. The default state +// has the LEDs disabled. +// + +`default_nettype none + +module led_control #( + parameter BASE_ADDRESS = 0, + parameter REGMAP_SIZE = 8'h1 +) ( + // Clock and reset + input wire ctrlport_clk, + input wire ctrlport_rst, + + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status, + output reg [31:0] s_ctrlport_resp_data, + + // LED Control (domain: ctrlport_clk) + output reg ch0_rx2_led, + output reg ch0_tx_led, + output reg ch0_rx_led, + output reg ch1_rx2_led, + output reg ch1_tx_led, + output reg ch1_rx_led, + output reg ch2_rx2_led, + output reg ch2_tx_led, + output reg ch2_rx_led, + output reg ch3_rx2_led, + output reg ch3_tx_led, + output reg ch3_rx_led + +); + + `include "../regmap/x440/led_setup_regmap_utils.vh" + `include "../../../../lib/rfnoc/core/ctrlport.vh" + + //--------------------------------------------------------------- + // ATR memory signals + //--------------------------------------------------------------- + reg [31:0] led_ctrl_reg; + + //--------------------------------------------------------------- + // Handling of CtrlPort + //--------------------------------------------------------------- + // Check of request address is targeted for this module. + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + REGMAP_SIZE); + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_status <= 2'b0; + s_ctrlport_resp_data <= 32'b0; + + end else begin + // write requests + if (s_ctrlport_req_wr) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + LED_CONTROL: begin + led_ctrl_reg <= s_ctrlport_req_data; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + //req_rd not delayed + end else if (s_ctrlport_req_rd) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (s_ctrlport_req_addr) + BASE_ADDRESS : begin + s_ctrlport_resp_data <= led_ctrl_reg & LED_CONTROL_MASK; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + always @(posedge ctrlport_clk) begin + //outputs + ch0_rx2_led <= led_ctrl_reg[CH0_RX2_LED_EN]; + ch0_tx_led <= led_ctrl_reg[CH0_TRX1_LED_RED_EN]; + ch0_rx_led <= led_ctrl_reg[CH0_TRX1_LED_GR_EN]; + + ch1_rx2_led <= led_ctrl_reg[CH1_RX2_LED_EN]; + ch1_tx_led <= led_ctrl_reg[CH1_TRX1_LED_RED_EN]; + ch1_rx_led <= led_ctrl_reg[CH1_TRX1_LED_GR_EN]; + + ch2_rx2_led <= led_ctrl_reg[CH2_RX2_LED_EN]; + ch2_tx_led <= led_ctrl_reg[CH2_TRX1_LED_RED_EN]; + ch2_rx_led <= led_ctrl_reg[CH2_TRX1_LED_GR_EN]; + + ch3_rx2_led <= led_ctrl_reg[CH3_RX2_LED_EN]; + ch3_tx_led <= led_ctrl_reg[CH3_TRX1_LED_RED_EN]; + ch3_rx_led <= led_ctrl_reg[CH3_TRX1_LED_GR_EN]; + end + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// Contains registers that control the LEDs. +// +// +// +// This register configures RF Frontend LEDs. +// +// +// +// Enables the Ch0 Rx2 Green LED +// +// +// +// +// Enables the Ch0 TRX (TX) Red LED +// +// +// +// +// Enables the Ch0 TRX (RX) Green LED +// +// +// +// +// Enables the Ch1 Rx2 Green LED +// +// +// +// +// Enables the Ch1 TRX (TX) Red LED +// +// +// +// +// Enables the Ch1 TRX (RX) Green LED +// +// +// +// +// Enables the Ch2 Rx2 Green LED +// +// +// +// +// Enables the Ch2 TRX (TX) Red LED +// +// +// +// +// Enables the Ch2 TRX (RX) Green LED +// +// +// +// +// Enables the Ch3 Rx2 Green LED +// +// +// +// +// Enables the Ch3 TRX (TX) Red LED +// +// +// +// +// Enables the Ch3 TRX (RX) Green LED +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/cpld/x440/mb_cpld.sdc b/top/x400/cpld/x440/mb_cpld.sdc new file mode 100644 index 0000000..da3aa1f --- /dev/null +++ b/top/x400/cpld/x440/mb_cpld.sdc @@ -0,0 +1,21 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# +# Timing constraints for the x440's motherboard CPLD. +# + + +##################################################################### +# DB specific LED constraints +##################################################################### + +# LED signals +set led_outputs [get_ports {QSFP0_LED_ACTIVE[*] QSFP0_LED_LINK[*] \ + QSFP1_LED_ACTIVE[*] QSFP1_LED_LINK[*] CH*_RX2_LED[*] CH*_TX_LED[*] CH*_RX_LED[*] } ] +set_min_delay -to $led_outputs 0 +set_max_delay -to $led_outputs $prc_clock_period + diff --git a/top/x400/cpld/mb_cpld.v b/top/x400/cpld/x440/mb_cpld.v similarity index 82% rename from top/x400/cpld/mb_cpld.v rename to top/x400/cpld/x440/mb_cpld.v index e9e21ac..43d6272 100644 --- a/top/x400/cpld/mb_cpld.v +++ b/top/x400/cpld/x440/mb_cpld.v @@ -1,5 +1,5 @@ // -// Copyright 2021 Ettus Research, A National Instruments Brand +// Copyright 2022 Ettus Research, A National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -7,7 +7,7 @@ // // Description: // -// Top level file for the X4xx motherboard CPLD. +// Top level file for the X440 motherboard CPLD. // // Parameters: // @@ -90,22 +90,20 @@ module mb_cpld #( output wire [3:0] QSFP1_LED_ACTIVE, output wire [3:0] QSFP1_LED_LINK, - // Daughterboard control interface + // Daughterboard LED GPIO // 1 -> DB1 / 0 -> DB0 - output reg [1:0] DB_CTRL_SCLK, - output reg [1:0] DB_CTRL_MOSI, - input wire [1:0] DB_CTRL_MISO, - output reg [1:0] DB_CTRL_CS_N, - output wire [1:0] DB_REF_CLK, - output wire [1:0] DB_ARST, - - // Daughterboards' JTAG master interfaces. - // 1 -> DB1 / 0 -> DB0 - output wire [1:0] DB_JTAG_TCK, - output wire [1:0] DB_JTAG_TDI, // from CPLD to DB - input wire [1:0] DB_JTAG_TDO, // from DB to CPLD - output wire [1:0] DB_JTAG_TMS, - + output wire [1:0] CH0_RX2_LED, + output wire [1:0] CH0_TX_LED, + output wire [1:0] CH0_RX_LED, + output wire [1:0] CH1_RX2_LED, + output wire [1:0] CH1_TX_LED, + output wire [1:0] CH1_RX_LED, + output wire [1:0] CH2_RX2_LED, + output wire [1:0] CH2_TX_LED, + output wire [1:0] CH2_RX_LED, + output wire [1:0] CH3_RX2_LED, + output wire [1:0] CH3_TX_LED, + output wire [1:0] CH3_RX_LED, //--------------------------------------------------------------------------- // PS Interfaces to/from Motherboard //--------------------------------------------------------------------------- @@ -132,13 +130,6 @@ module mb_cpld #( output wire [11:0] DIO_DIRECTION_A, output wire [11:0] DIO_DIRECTION_B, - // Daughterboard calibration EEPROM SPI - // 1 -> DB1 / 0 -> DB0 - output wire [1:0] DB_CALEEPROM_SCLK, - output wire [1:0] DB_CALEEPROM_MOSI, - input wire [1:0] DB_CALEEPROM_MISO, - output wire [1:0] DB_CALEEPROM_CS_N, - //--------------------------------------------------------------------------- // Miscellaneous //--------------------------------------------------------------------------- @@ -161,9 +152,9 @@ module mb_cpld #( // SPI masters (spi_top) are limited to 64 bit transmission length `define SPI_MAX_CHAR_64 - `include "../../../lib/rfnoc/core/ctrlport.vh" - `include "regmap/mb_cpld_ps_regmap_utils.vh" - `include "regmap/mb_cpld_pl_regmap_utils.vh" + `include "../../../../lib/rfnoc/core/ctrlport.vh" + `include "../regmap/mb_cpld_ps_regmap_utils.vh" + `include "../regmap/x440/mb_cpld_pl_regmap_utils.vh" //--------------------------------------------------------------------------- // Clocks and Resets @@ -346,24 +337,6 @@ module mb_cpld #( wire [1:0] db_reset; wire [1:0] ipass_cable_present; - // Clocks and reset - oddr db0_clk_out ( - .outclock (clk50), - .din ({1'b0, db_clk_enable[0]}), - .pad_out (DB_REF_CLK[0]), - .aclr (reset_clk50) - ); - - oddr db1_clk_out ( - .outclock (clk50), - .din ({1'b0, db_clk_enable[1]}), - .pad_out (DB_REF_CLK[1]), - .aclr (reset_clk50) - ); - - assign DB_ARST[0] = db_reset[0]; - assign DB_ARST[1] = db_reset[1]; - // PL SPI FPGA -> DB CPLD reg mb_cpld_sclk, mb_cpld_mosi, mb_cpld_cs_n; wire mb_cpld_miso; @@ -378,24 +351,8 @@ module mb_cpld #( // SW is expected to properly setup the DBs before issuing SPI transactions. always @(posedge pll_ref_clk_int) begin : to_db // Default chip selects - DB_CTRL_CS_N[0] <= 1'b1; - DB_CTRL_CS_N[1] <= 1'b1; mb_cpld_cs_n <= 1'b1; - // DB 0 - DB_CTRL_SCLK[0] <= PL_CPLD_SCLK; - DB_CTRL_MOSI[0] <= PL_CPLD_MOSI; - if (PL_CPLD_CS_N == PL_CS_DB0) begin - DB_CTRL_CS_N[0] <= 1'b0; - end - - // DB 1 - DB_CTRL_SCLK[1] <= PL_CPLD_SCLK; - DB_CTRL_MOSI[1] <= PL_CPLD_MOSI; - if (PL_CPLD_CS_N == PL_CS_DB1) begin - DB_CTRL_CS_N[1] <= 1'b0; - end - // MB CPLD mb_cpld_sclk <= PL_CPLD_SCLK; mb_cpld_mosi <= PL_CPLD_MOSI; @@ -408,8 +365,6 @@ module mb_cpld #( always @(posedge pll_ref_clk_int) begin : from_db case (PL_CPLD_CS_N) PL_CS_MB_CPLD : PL_CPLD_MISO <= mb_cpld_miso; // MB CPLD - PL_CS_DB1 : PL_CPLD_MISO <= DB_CTRL_MISO[1]; // DB 1 - PL_CS_DB0 : PL_CPLD_MISO <= DB_CTRL_MISO[0]; // DB 0 PL_CS_IDLE : PL_CPLD_MISO <= 1'bz; // Inactive endcase end @@ -450,6 +405,22 @@ module mb_cpld #( wire [31:0] pl_regs_ctrlport_resp_data; wire [ 1:0] pl_regs_ctrlport_resp_status; + wire [19:0] db0_led_ctrlport_req_addr; + wire [31:0] db0_led_ctrlport_req_data; + wire db0_led_ctrlport_req_rd; + wire db0_led_ctrlport_req_wr; + wire db0_led_ctrlport_resp_ack; + wire [31:0] db0_led_ctrlport_resp_data; + wire [ 1:0] db0_led_ctrlport_resp_status; + + wire [19:0] db1_led_ctrlport_req_addr; + wire [31:0] db1_led_ctrlport_req_data; + wire db1_led_ctrlport_req_rd; + wire db1_led_ctrlport_req_wr; + wire db1_led_ctrlport_resp_ack; + wire [31:0] db1_led_ctrlport_resp_data; + wire [ 1:0] db1_led_ctrlport_resp_status; + wire [19:0] pl_term_ctrlport_req_addr; wire [31:0] pl_term_ctrlport_req_data; wire pl_term_ctrlport_req_rd; @@ -458,22 +429,6 @@ module mb_cpld #( wire [31:0] pl_term_ctrlport_resp_data; wire [ 1:0] pl_term_ctrlport_resp_status; - wire pl_jtag0_ctrlport_req_rd; - wire pl_jtag0_ctrlport_req_wr; - wire pl_jtag0_ctrlport_resp_ack; - wire [31:0] pl_jtag0_ctrlport_resp_data; - wire [ 1:0] pl_jtag0_ctrlport_resp_status; - wire [19:0] pl_jtag0_ctrlport_req_addr; - wire [31:0] pl_jtag0_ctrlport_req_data; - - wire [19:0] pl_jtag1_ctrlport_req_addr; - wire [31:0] pl_jtag1_ctrlport_req_data; - wire pl_jtag1_ctrlport_req_rd; - wire pl_jtag1_ctrlport_req_wr; - wire pl_jtag1_ctrlport_resp_ack; - wire [31:0] pl_jtag1_ctrlport_resp_data; - wire [1:0] pl_jtag1_ctrlport_resp_status; - ctrlport_splitter #( .NUM_SLAVES (4) ) pl_ctrlport_splitter ( @@ -489,16 +444,16 @@ module mb_cpld #( .s_ctrlport_resp_ack (pl_ctrlport_resp_ack), .s_ctrlport_resp_status (pl_ctrlport_resp_status), .s_ctrlport_resp_data (pl_ctrlport_resp_data), - .m_ctrlport_req_wr ({pl_regs_ctrlport_req_wr, pl_term_ctrlport_req_wr, pl_jtag0_ctrlport_req_wr, pl_jtag1_ctrlport_req_wr}), - .m_ctrlport_req_rd ({pl_regs_ctrlport_req_rd, pl_term_ctrlport_req_rd, pl_jtag0_ctrlport_req_rd, pl_jtag1_ctrlport_req_rd}), - .m_ctrlport_req_addr ({pl_regs_ctrlport_req_addr, pl_term_ctrlport_req_addr, pl_jtag0_ctrlport_req_addr, pl_jtag1_ctrlport_req_addr}), - .m_ctrlport_req_data ({pl_regs_ctrlport_req_data, pl_term_ctrlport_req_data, pl_jtag0_ctrlport_req_data, pl_jtag1_ctrlport_req_data}), + .m_ctrlport_req_wr ({pl_regs_ctrlport_req_wr, db0_led_ctrlport_req_wr, db1_led_ctrlport_req_wr, pl_term_ctrlport_req_wr}), + .m_ctrlport_req_rd ({pl_regs_ctrlport_req_rd, db0_led_ctrlport_req_rd, db1_led_ctrlport_req_rd, pl_term_ctrlport_req_rd}), + .m_ctrlport_req_addr ({pl_regs_ctrlport_req_addr, db0_led_ctrlport_req_addr, db1_led_ctrlport_req_addr, pl_term_ctrlport_req_addr}), + .m_ctrlport_req_data ({pl_regs_ctrlport_req_data, db0_led_ctrlport_req_data, db1_led_ctrlport_req_data, pl_term_ctrlport_req_data}), .m_ctrlport_req_byte_en (), .m_ctrlport_req_has_time (), .m_ctrlport_req_time (), - .m_ctrlport_resp_ack ({pl_regs_ctrlport_resp_ack, pl_term_ctrlport_resp_ack, pl_jtag0_ctrlport_resp_ack, pl_jtag1_ctrlport_resp_ack}), - .m_ctrlport_resp_status ({pl_regs_ctrlport_resp_status, pl_term_ctrlport_resp_status, pl_jtag0_ctrlport_resp_status, pl_jtag1_ctrlport_resp_status}), - .m_ctrlport_resp_data ({pl_regs_ctrlport_resp_data, pl_term_ctrlport_resp_data, pl_jtag0_ctrlport_resp_data, pl_jtag1_ctrlport_resp_data}) + .m_ctrlport_resp_ack ({pl_regs_ctrlport_resp_ack, db0_led_ctrlport_resp_ack, db1_led_ctrlport_resp_ack, pl_term_ctrlport_resp_ack}), + .m_ctrlport_resp_status ({pl_regs_ctrlport_resp_status, db0_led_ctrlport_resp_status, db1_led_ctrlport_resp_status, pl_term_ctrlport_resp_status}), + .m_ctrlport_resp_data ({pl_regs_ctrlport_resp_data, db0_led_ctrlport_resp_data, db1_led_ctrlport_resp_data, pl_term_ctrlport_resp_data}) ); pl_cpld_regs #( @@ -520,47 +475,63 @@ module mb_cpld #( .ipass_cable_present (ipass_cable_present) ); - ctrlport_to_jtag #( - .BASE_ADDRESS (JTAG_DB0), - .DEFAULT_PRESCALAR (1) - ) db0_jtag ( - .ctrlport_clk (clk50), - .ctrlport_rst (reset_clk50), - .s_ctrlport_req_wr (pl_jtag0_ctrlport_req_wr), - .s_ctrlport_req_rd (pl_jtag0_ctrlport_req_rd), - .s_ctrlport_req_addr (pl_jtag0_ctrlport_req_addr), - .s_ctrlport_req_data (pl_jtag0_ctrlport_req_data), - .s_ctrlport_resp_ack (pl_jtag0_ctrlport_resp_ack), - .s_ctrlport_resp_status (pl_jtag0_ctrlport_resp_status), - .s_ctrlport_resp_data (pl_jtag0_ctrlport_resp_data), - .tck (DB_JTAG_TCK[0]), - .tdi (DB_JTAG_TDI[0]), - .tdo (DB_JTAG_TDO[0]), - .tms (DB_JTAG_TMS[0]) + led_control #( + .BASE_ADDRESS (PL_DB0_LED_REGISTERS), + .REGMAP_SIZE (PL_DB0_LED_REGISTERS_SIZE) + ) led_control_db0 ( + .ctrlport_clk (clk50), + .ctrlport_rst (reset_clk50), + .s_ctrlport_req_wr (db0_led_ctrlport_req_wr), + .s_ctrlport_req_rd (db0_led_ctrlport_req_rd), + .s_ctrlport_req_addr (db0_led_ctrlport_req_addr), + .s_ctrlport_req_data (db0_led_ctrlport_req_data), + .s_ctrlport_resp_ack (db0_led_ctrlport_resp_ack), + .s_ctrlport_resp_status (db0_led_ctrlport_resp_status), + .s_ctrlport_resp_data (db0_led_ctrlport_resp_data), + .ch0_rx2_led (CH0_RX2_LED[0]), + .ch0_tx_led (CH0_TX_LED[0]), + .ch0_rx_led (CH0_RX_LED[0]), + .ch1_rx2_led (CH1_RX2_LED[0]), + .ch1_tx_led (CH1_TX_LED[0]), + .ch1_rx_led (CH1_RX_LED[0]), + .ch2_rx2_led (CH2_RX2_LED[0]), + .ch2_tx_led (CH2_TX_LED[0]), + .ch2_rx_led (CH2_RX_LED[0]), + .ch3_rx2_led (CH3_RX2_LED[0]), + .ch3_tx_led (CH3_TX_LED[0]), + .ch3_rx_led (CH3_RX_LED[0]) ); - ctrlport_to_jtag #( - .BASE_ADDRESS (JTAG_DB1), - .DEFAULT_PRESCALAR (1) - ) db1_jtag ( - .ctrlport_clk (clk50), - .ctrlport_rst (reset_clk50), - .s_ctrlport_req_wr (pl_jtag1_ctrlport_req_wr), - .s_ctrlport_req_rd (pl_jtag1_ctrlport_req_rd), - .s_ctrlport_req_addr (pl_jtag1_ctrlport_req_addr), - .s_ctrlport_req_data (pl_jtag1_ctrlport_req_data), - .s_ctrlport_resp_ack (pl_jtag1_ctrlport_resp_ack), - .s_ctrlport_resp_status (pl_jtag1_ctrlport_resp_status), - .s_ctrlport_resp_data (pl_jtag1_ctrlport_resp_data), - .tck (DB_JTAG_TCK[1]), - .tdi (DB_JTAG_TDI[1]), - .tdo (DB_JTAG_TDO[1]), - .tms (DB_JTAG_TMS[1]) + led_control #( + .BASE_ADDRESS (PL_DB1_LED_REGISTERS), + .REGMAP_SIZE (PL_DB1_LED_REGISTERS_SIZE) + ) led_control_db1 ( + .ctrlport_clk (clk50), + .ctrlport_rst (reset_clk50), + .s_ctrlport_req_wr (db1_led_ctrlport_req_wr), + .s_ctrlport_req_rd (db1_led_ctrlport_req_rd), + .s_ctrlport_req_addr (db1_led_ctrlport_req_addr), + .s_ctrlport_req_data (db1_led_ctrlport_req_data), + .s_ctrlport_resp_ack (db1_led_ctrlport_resp_ack), + .s_ctrlport_resp_status (db1_led_ctrlport_resp_status), + .s_ctrlport_resp_data (db1_led_ctrlport_resp_data), + .ch0_rx2_led (CH0_RX2_LED[1]), + .ch0_tx_led (CH0_TX_LED[1]), + .ch0_rx_led (CH0_RX_LED[1]), + .ch1_rx2_led (CH1_RX2_LED[1]), + .ch1_tx_led (CH1_TX_LED[1]), + .ch1_rx_led (CH1_RX_LED[1]), + .ch2_rx2_led (CH2_RX2_LED[1]), + .ch2_tx_led (CH2_TX_LED[1]), + .ch2_rx_led (CH2_RX_LED[1]), + .ch3_rx2_led (CH3_RX2_LED[1]), + .ch3_tx_led (CH3_TX_LED[1]), + .ch3_rx_led (CH3_RX_LED[1]) ); // Termination of ctrlport request ctrlport_terminator #( - .START_ADDRESS (JTAG_DB1 + JTAG_DB1_SIZE), + .START_ADDRESS (PL_DB1_LED_REGISTERS + PL_DB1_LED_REGISTERS_SIZE), .LAST_ADDRESS (2**CTRLPORT_ADDR_W-1) ) pl_terminator ( .ctrlport_clk (clk50), @@ -682,16 +653,6 @@ module mb_cpld #( assign PHASE_DAC_MOSI = PS_CPLD_MOSI; assign PHASE_DAC_CS_N = ps_spi_cs_n_decoded[PS_CS_PHASE_DAC]; - // DB EEPROM 0 SPI signals - assign DB_CALEEPROM_SCLK[0] = PS_CPLD_SCLK; - assign DB_CALEEPROM_MOSI[0] = PS_CPLD_MOSI; - assign DB_CALEEPROM_CS_N[0] = ps_spi_cs_n_decoded[PS_CS_DB0_CAL_EEPROM]; - - // DB EEPROM 1 SPI signals - assign DB_CALEEPROM_SCLK[1] = PS_CPLD_SCLK; - assign DB_CALEEPROM_MOSI[1] = PS_CPLD_MOSI; - assign DB_CALEEPROM_CS_N[1] = ps_spi_cs_n_decoded[PS_CS_DB1_CAL_EEPROM]; - // CLK AUX DB SPI signals assign CLK_DB_SCLK = PS_CPLD_SCLK; assign CLK_DB_MOSI = PS_CPLD_MOSI; @@ -702,8 +663,6 @@ module mb_cpld #( assign PS_CPLD_MISO = (PS_CPLD_CS_N[2:0] == PS_CS_MB_CPLD) ? ps_spi_endpoint_miso : (PS_CPLD_CS_N[2:0] == PS_CS_LMK32) ? LMK32_MISO : (PS_CPLD_CS_N[2:0] == PS_CS_TPM) ? TPM_MISO : - (PS_CPLD_CS_N[2:0] == PS_CS_DB0_CAL_EEPROM) ? DB_CALEEPROM_MISO[0] : - (PS_CPLD_CS_N[2:0] == PS_CS_DB1_CAL_EEPROM) ? DB_CALEEPROM_MISO[1] : (PS_CPLD_CS_N[2:0] == PS_CS_CLK_AUX_DB) ? CLK_DB_MISO : 1'bz; // Default case and PHASE_DAC @@ -977,7 +936,7 @@ endmodule //XmlParse xml_on -// +// // // // @@ -1011,21 +970,9 @@ endmodule // All protocol masters controller by this register map are running with a clock frequency of 50 MHz. // // -// -// -// -// JTAG Master connected to first daugherboard's CPLD JTAG interface. -// -// **Use minimum value of 1 for @.JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.** -// -// -// -// -// JTAG Master connected to second daugherboard's CPLD JTAG interface. -// -// **Use minimum value of 1 for @.JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.** -// -// +// +// +// // // // @@ -1038,10 +985,10 @@ endmodule // // This enumeration is used to create the constants held in the basic registers. // -// +// // -// -// +// +// // // // diff --git a/top/x400/cpld/quartus/mb_cpld.qpf b/top/x400/cpld/x440/quartus/mb_cpld.qpf similarity index 100% rename from top/x400/cpld/quartus/mb_cpld.qpf rename to top/x400/cpld/x440/quartus/mb_cpld.qpf diff --git a/top/x400/cpld/quartus/mb_cpld.qsf b/top/x400/cpld/x440/quartus/mb_cpld.qsf similarity index 80% rename from top/x400/cpld/quartus/mb_cpld.qsf rename to top/x400/cpld/x440/quartus/mb_cpld.qsf index 001391c..65217b0 100644 --- a/top/x400/cpld/quartus/mb_cpld.qsf +++ b/top/x400/cpld/x440/quartus/mb_cpld.qsf @@ -293,74 +293,59 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_SCLK set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_MOSI set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_CS_N -# Daughterboards' JTAG master interfaces. -set_location_assignment PIN_J12 -to DB_JTAG_TCK[0] -set_location_assignment PIN_G9 -to DB_JTAG_TCK[1] -set_location_assignment PIN_K12 -to DB_JTAG_TDI[0] -set_location_assignment PIN_E13 -to DB_JTAG_TDI[1] -set_location_assignment PIN_H10 -to DB_JTAG_TDO[0] -set_location_assignment PIN_F13 -to DB_JTAG_TDO[1] -set_location_assignment PIN_K11 -to DB_JTAG_TMS[0] -set_location_assignment PIN_G10 -to DB_JTAG_TMS[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[1] - -# Daughterboards' Calibration EEPROM SPI interfaces. -set_location_assignment PIN_C9 -to DB_CALEEPROM_CS_N[0] -set_location_assignment PIN_B9 -to DB_CALEEPROM_MISO[0] -set_location_assignment PIN_B10 -to DB_CALEEPROM_MOSI[0] -set_location_assignment PIN_A10 -to DB_CALEEPROM_SCLK[0] - -set_location_assignment PIN_B5 -to DB_CALEEPROM_MOSI[1] -set_location_assignment PIN_B6 -to DB_CALEEPROM_SCLK[1] -set_location_assignment PIN_B4 -to DB_CALEEPROM_MISO[1] -set_location_assignment PIN_B3 -to DB_CALEEPROM_CS_N[1] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[0] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[1] - -# Daughterboards' Control interfaces. -set_location_assignment PIN_C10 -to DB_CTRL_SCLK[0] -set_location_assignment PIN_A9 -to DB_CTRL_MISO[0] -set_location_assignment PIN_A8 -to DB_ARST[0] -set_location_assignment PIN_A11 -to DB_CTRL_CS_N[0] -set_location_assignment PIN_E8 -to DB_CTRL_MOSI[0] -set_location_assignment PIN_D8 -to DB_REF_CLK[0] - -set_location_assignment PIN_A3 -to DB_REF_CLK[1] -set_location_assignment PIN_A4 -to DB_CTRL_MISO[1] -set_location_assignment PIN_D6 -to DB_CTRL_CS_N[1] -set_location_assignment PIN_E6 -to DB_CTRL_SCLK[1] -set_location_assignment PIN_A5 -to DB_CTRL_MOSI[1] -set_location_assignment PIN_B2 -to DB_ARST[1] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[0] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[1] +# DB0 TX/RX LEDS per chan +#------------------------------------------- +set_location_assignment PIN_A11 -to CH0_TX_LED[0] +set_location_assignment PIN_C10 -to CH0_RX_LED[0] +set_location_assignment PIN_A9 -to CH0_RX2_LED[0] +set_location_assignment PIN_E8 -to CH1_TX_LED[0] +set_location_assignment PIN_D8 -to CH1_RX_LED[0] +set_location_assignment PIN_A8 -to CH1_RX2_LED[0] +set_location_assignment PIN_C9 -to CH2_TX_LED[0] +set_location_assignment PIN_A10 -to CH2_RX_LED[0] +set_location_assignment PIN_B10 -to CH2_RX2_LED[0] +set_location_assignment PIN_K12 -to CH3_TX_LED[0] +set_location_assignment PIN_K11 -to CH3_RX_LED[0] +set_location_assignment PIN_J12 -to CH3_RX2_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_TX_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX2_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_TX_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX2_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_TX_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX_LED[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX2_LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_TX_LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX_LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX2_LED[0] +# DB0 TX/RX LEDS per chan +#------------------------------------------- +set_location_assignment PIN_D6 -to CH0_TX_LED[1] +set_location_assignment PIN_E6 -to CH0_RX_LED[1] +set_location_assignment PIN_A4 -to CH0_RX2_LED[1] +set_location_assignment PIN_A5 -to CH1_TX_LED[1] +set_location_assignment PIN_A3 -to CH1_RX_LED[1] +set_location_assignment PIN_B2 -to CH1_RX2_LED[1] +set_location_assignment PIN_B3 -to CH2_TX_LED[1] +set_location_assignment PIN_B6 -to CH2_RX_LED[1] +set_location_assignment PIN_B5 -to CH2_RX2_LED[1] +set_location_assignment PIN_E13 -to CH3_TX_LED[1] +set_location_assignment PIN_G10 -to CH3_RX_LED[1] +set_location_assignment PIN_G9 -to CH3_RX2_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_TX_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX2_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_TX_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX2_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_TX_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX_LED[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX2_LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_TX_LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX_LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX2_LED[1] # Miscellaneous. #------------------------------------------ @@ -395,19 +380,19 @@ set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmiWrapper.vhd set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmi.vhd set_global_assignment -name QSYS_FILE ../ip/clkctrl/clkctrl.qsys set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys -set_global_assignment -name SDC_FILE ../db_spi_shared_constants.sdc -set_global_assignment -name SDC_FILE ../mb_cpld.sdc -set_global_assignment -name VERILOG_FILE ../reconfig_engine.v -set_global_assignment -name VERILOG_FILE ../mb_cpld.v -set_global_assignment -name VERILOG_FILE ../ctrlport_to_spi.v -set_global_assignment -name VERILOG_FILE ../ctrlport_to_jtag.v -set_global_assignment -name VERILOG_FILE ../pl_cpld_regs.v -set_global_assignment -name VERILOG_FILE ../pwr_supply_clk_gen.v -set_global_assignment -name VERILOG_FILE ../ps_cpld_regs.v -set_global_assignment -name VERILOG_FILE ../ps_power_regs.v -set_global_assignment -name VERILOG_FILE ../reset_generator.v -set_global_assignment -name VERILOG_FILE ../spi_slave_to_ctrlport_master.v -set_global_assignment -name VERILOG_FILE ../spi_slave.v +set_global_assignment -name SDC_FILE ../common/common.sdc +set_global_assignment -name SDC_FILE ../x440/mb_cpld.sdc +set_global_assignment -name VERILOG_FILE ../x440/mb_cpld.v +set_global_assignment -name VERILOG_FILE ../x440/led_control.v +set_global_assignment -name VERILOG_FILE ../common/reconfig_engine.v +set_global_assignment -name VERILOG_FILE ../common/ctrlport_to_spi.v +set_global_assignment -name VERILOG_FILE ../common/pl_cpld_regs.v +set_global_assignment -name VERILOG_FILE ../common/pwr_supply_clk_gen.v +set_global_assignment -name VERILOG_FILE ../common/ps_cpld_regs.v +set_global_assignment -name VERILOG_FILE ../common/ps_power_regs.v +set_global_assignment -name VERILOG_FILE ../common/reset_generator.v +set_global_assignment -name VERILOG_FILE ../common/spi_slave_to_ctrlport_master.v +set_global_assignment -name VERILOG_FILE ../common/spi_slave.v set_global_assignment -name QIP_FILE ../ip/pll/pll.qip set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer_impl.v set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer.v @@ -421,12 +406,11 @@ set_global_assignment -name VERILOG_FILE ../../../../lib/control/pulse_synchroni set_global_assignment -name VERILOG_FILE ../../../../lib/control/handshake.v set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/axi_bitq.vhd -set_global_assignment -name QIP_FILE ../ip/oddr/oddr.qip set_global_assignment -name SOURCE_FILE db/mb_cpld.cmp.rdb set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id "PcieCmi:PcieCmix" set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "PcieCmi:PcieCmix" set_global_assignment -name PARTITION_COLOR 52377 -section_id "PcieCmi:PcieCmix" -set_global_assignment -name PARTITION_IMPORT_FILE ../ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" +set_global_assignment -name PARTITION_IMPORT_FILE ../../ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" set_global_assignment -name PARTITION_LAST_IMPORTED_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix" \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix" diff --git a/top/x400/cpld_interface.v b/top/x400/cpld_interface.v index 9168868..178687e 100644 --- a/top/x400/cpld_interface.v +++ b/top/x400/cpld_interface.v @@ -85,7 +85,11 @@ module cpld_interface ( `include "../../lib/rfnoc/core/ctrlport.vh" `include "regmap/pl_cpld_regmap_utils.vh" // Variant-dependent register map. - `include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh" + `ifdef X440 + `include "cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh" + `else // Use X410 as the default variant for regmap. + `include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh" + `endif `include "cpld/regmap/pl_cpld_base_regmap_utils.vh" //--------------------------------------------------------------------------- diff --git a/top/x400/cpld_interface_regs.v b/top/x400/cpld_interface_regs.v index a6d0dad..33baeb4 100644 --- a/top/x400/cpld_interface_regs.v +++ b/top/x400/cpld_interface_regs.v @@ -46,7 +46,11 @@ module cpld_interface_regs #( ); // Variant-dependent register map. - `include "regmap/x410/versioning_regs_regmap_utils.vh" + `ifdef X440 + `include "regmap/x440/versioning_regs_regmap_utils.vh" + `else // Use X410 as the default variant for regmap. + `include "regmap/x410/versioning_regs_regmap_utils.vh" + `endif `include "regmap/versioning_utils.vh" `include "regmap/cpld_interface_regmap_utils.vh" diff --git a/top/x400/dboards/db_gpio_interface.v b/top/x400/dboards/db_gpio_interface.v deleted file mode 100644 index d48650d..0000000 --- a/top/x400/dboards/db_gpio_interface.v +++ /dev/null @@ -1,275 +0,0 @@ -// -// Copyright 2021 Ettus Research, a National Instruments Brand -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: db_gpio_interface -// -// Description: -// Interface for GPIO interface towards daughterboards. -// -// A ControlPort interface is serialized into bytes along with a valid signal. -// The ControlPort supports write requests only. Byte enables are not supported. -// There is support for timed commands. -// Furthermore there are 4 state wires towards the DB. Ensure an appropriate -// hold time on the states as the transmission happens in pll_ref_clk, which is -// slower than radio_clk. Pulses of e.g. just a single clock cycle may not get -// transferred to the DB. -// -// The 20 available GPIO lines are assigned with -// - 5x empty -// - bytestream direction -// - bytestream valid -// - bytestream data (8 bits) -// - 1x empty -// - db_state (4 bits) -// - -`default_nettype none - -module db_gpio_interface ( - // Clocks and reset - input wire radio_clk, - input wire pll_ref_clk, - - // DB state lines (domain: radio_clk) - input wire [ 3:0] db_state, - // Request (domain: radio_clk) - input wire ctrlport_rst, - input wire s_ctrlport_req_wr, - input wire s_ctrlport_req_rd, - input wire [19:0] s_ctrlport_req_addr, - input wire [31:0] s_ctrlport_req_data, - - // Response (domain: radio_clk) - output wire s_ctrlport_resp_ack, - output reg [ 1:0] s_ctrlport_resp_status, - output reg [31:0] s_ctrlport_resp_data, - - // GPIO interface (domain: pll_ref_clk) - input wire [19:0] gpio_in, - output wire [19:0] gpio_out, - output wire [19:0] gpio_out_en, - - // Version (Constant) - output wire [95:0] version_info -); - - `include "../regmap/versioning_regs_regmap_utils.vh" - `include "../regmap/versioning_utils.vh" - - //---------------------------------------------------------------------------- - // Clock domain crossing (radio_clk -> pll_ref_clk) - //---------------------------------------------------------------------------- - // Radio_clk is derived from pll_ref_clk by an integer multiplier and - // originate from the same PLL. - // Therefore the clock crossing can be achieved by using simple registers. - // Static timing analysis will be able to meet setup and hold requirements on - // them. - - // holding read and write flags for multiple radio_clk cycles - reg ctrlport_req_wr_hold = 1'b0; - reg ctrlport_req_rd_hold = 1'b0; - - reg [19:0] ctrlport_req_addr_prc = 20'b0; - reg [31:0] ctrlport_req_data_prc = 32'b0; - reg ctrlport_req_rd_prc = 1'b0; - reg ctrlport_req_wr_prc = 1'b0; - - wire ctrlport_resp_ack_prc; - wire [31:0] ctrlport_resp_data_prc; - wire [ 1:0] ctrlport_resp_status_prc; - - reg ctrlport_req_rd_fall = 1'b0; - reg ctrlport_req_wr_fall = 1'b0; - reg [31:0] ctrlport_resp_data_fall = 32'b0; - reg [ 1:0] ctrlport_resp_status_fall = 2'b0; - reg ctrlport_resp_ack_fall = 1'b0; - - // Retime signals to falling edge of radio_clk. - // Because radio_clk is more heavily loaded than pll_ref_clk, it arrives at - // the FF's later, which leads to hold time violations when moving signals - // from pll_ref_clk to radio_clk. By sampling on the falling edge of - // radio_clk, we provide (nominally) half a radio_clk period of hold, while - // reducing setup time by half. The late arrival of radio_clk adds back some - // of the lost setup margin. - always @(negedge radio_clk) begin - ctrlport_req_rd_fall <= ctrlport_req_rd_prc; - ctrlport_req_wr_fall <= ctrlport_req_wr_prc; - ctrlport_resp_ack_fall <= ctrlport_resp_ack_prc; - ctrlport_resp_status_fall <= ctrlport_resp_status_prc; - ctrlport_resp_data_fall <= ctrlport_resp_data_prc; - end - - always @(posedge radio_clk) begin - if (ctrlport_req_wr_fall) begin - ctrlport_req_wr_hold <= 1'b0; - end else if (s_ctrlport_req_wr) begin - ctrlport_req_wr_hold <= 1'b1; - end - if (ctrlport_req_rd_fall) begin - ctrlport_req_rd_hold <= 1'b0; - end else if (s_ctrlport_req_rd) begin - ctrlport_req_rd_hold <= 1'b1; - end - - // capture request address and data - if (s_ctrlport_req_wr || s_ctrlport_req_rd) begin - ctrlport_req_addr_prc <= s_ctrlport_req_addr; - ctrlport_req_data_prc <= s_ctrlport_req_data; - end - end - - // capture extended flags in pll_ref_clk domain - always @(posedge pll_ref_clk) begin - ctrlport_req_wr_prc <= ctrlport_req_wr_hold; - ctrlport_req_rd_prc <= ctrlport_req_rd_hold; - end - - // search for rising edge in response - reg [1:0] ctrlport_resp_ack_reg = 2'b0; - always @(posedge radio_clk) begin - ctrlport_resp_ack_reg = {ctrlport_resp_ack_reg[0], ctrlport_resp_ack_fall}; - end - assign s_ctrlport_resp_ack = ctrlport_resp_ack_reg[0] & ~ctrlport_resp_ack_reg[1]; - - // capture response data - always @(posedge radio_clk) begin - if (ctrlport_resp_ack_fall) begin - s_ctrlport_resp_status <= ctrlport_resp_status_fall; - s_ctrlport_resp_data <= ctrlport_resp_data_fall; - end - end - - // transfer state lines - reg [3:0] db_state_prc = 4'b0; - reg [3:0] db_state_prc_fe = 4'b0; - always @(posedge pll_ref_clk) begin - db_state_prc <= db_state; - end - always @(negedge pll_ref_clk) begin - db_state_prc_fe <= db_state_prc; - end - - // transfer reset - reg ctrlport_rst_hold = 1'b0; - reg ctrlport_rst_prc = 1'b0; - reg ctrlport_rst_fall = 1'b0; - always @(posedge radio_clk) begin - if (ctrlport_rst) begin - ctrlport_rst_hold <= 1'b1; - end else if (ctrlport_rst_fall) begin - ctrlport_rst_hold <= 1'b0; - end - end - always @(posedge pll_ref_clk) begin - ctrlport_rst_prc <= ctrlport_rst_hold; - end - always @(negedge radio_clk) begin - ctrlport_rst_fall <= ctrlport_rst_prc; - end - - - //---------------------------------------------------------------------------- - // Ctrlport serializer - //---------------------------------------------------------------------------- - wire [7:0] bytestream_data_in; - wire [7:0] bytestream_data_out; - wire bytestream_direction; - wire bytestream_output_enable; - wire bytestream_valid_in; - wire bytestream_valid_out; - - ctrlport_byte_serializer serializer_i ( - .ctrlport_clk (pll_ref_clk), - .ctrlport_rst (ctrlport_rst_prc), - .s_ctrlport_req_wr (ctrlport_req_wr_prc), - .s_ctrlport_req_rd (ctrlport_req_rd_prc), - .s_ctrlport_req_addr (ctrlport_req_addr_prc), - .s_ctrlport_req_data (ctrlport_req_data_prc), - .s_ctrlport_resp_ack (ctrlport_resp_ack_prc), - .s_ctrlport_resp_status (ctrlport_resp_status_prc), - .s_ctrlport_resp_data (ctrlport_resp_data_prc), - .bytestream_data_in (bytestream_data_in), - .bytestream_valid_in (bytestream_valid_in), - .bytestream_data_out (bytestream_data_out), - .bytestream_valid_out (bytestream_valid_out), - .bytestream_direction (bytestream_direction), - .bytestream_output_enable (bytestream_output_enable) - ); - - // IOB registers to drive data on the falling edge - reg [7:0] bytestream_data_out_fe; - reg bytestream_direction_fe; - reg bytestream_output_enable_fe; - reg bytestream_valid_out_fe; - - // Signals are shifted into a falling edge domain to help meet - // hold requirements at CPLD - always @(negedge pll_ref_clk) begin - if (ctrlport_rst_prc) begin - bytestream_data_out_fe <= 8'b0; - bytestream_valid_out_fe <= 1'b0; - bytestream_direction_fe <= 1'b0; - bytestream_output_enable_fe <= 1'b1; - end else begin - bytestream_data_out_fe <= bytestream_data_out; - bytestream_valid_out_fe <= bytestream_valid_out; - bytestream_direction_fe <= bytestream_direction; - bytestream_output_enable_fe <= bytestream_output_enable; - end - end - - //---------------------------------------------------------------------------- - // wire assignment - //---------------------------------------------------------------------------- - // 5 unused, 10 used, 1 unused and 4 used signals - assign gpio_out = {5'b0, bytestream_direction_fe, bytestream_valid_out_fe, bytestream_data_out_fe, 1'b0, db_state_prc_fe}; - assign gpio_out_en = {5'b0, 1'b1, {9 {bytestream_output_enable_fe}}, 1'b0, {4 {1'b1}} }; - - assign bytestream_valid_in = gpio_in[13]; - assign bytestream_data_in = gpio_in[12:5]; - - //---------------------------------------------------------------------------- - // version_info - //---------------------------------------------------------------------------- - - // Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh - assign version_info = build_component_versions( - DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME, - build_version( - DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR, - DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR, - DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD), - build_version( - DB_GPIO_IFC_CURRENT_VERSION_MAJOR, - DB_GPIO_IFC_CURRENT_VERSION_MINOR, - DB_GPIO_IFC_CURRENT_VERSION_BUILD)); - -endmodule - -`default_nettype wire - -//XmlParse xml_on -// -// -// -// -// Daughterboard GPIO interface.{BR/} -// For guidance on when to update these revision numbers, -// please refer to the register map documentation accordingly: -//
  • Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION -//
  • Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION -//
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED -// -// -// -// -// -// -// -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/dboards/fbx/clock_en_control.v b/top/x400/dboards/fbx/clock_en_control.v new file mode 100644 index 0000000..d98de6b --- /dev/null +++ b/top/x400/dboards/fbx/clock_en_control.v @@ -0,0 +1,162 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: clock_en_control +// +// Description: +// Implements control over clock enable. clk_in is always active. +// The enable controls whether clk_out is active or not. +// +// Parameters: +// +// REG_BASE : Base address to use for registers. +// REG_SIZE : Register space size. +// + +`default_nettype none + +module clock_en_control #( + parameter BASE_ADDRESS = 0, + parameter REGMAP_SIZE = 8'h4 +) ( + // Clock and reset + input wire ctrlport_clk, + input wire ctrlport_rst, + + // Request + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + // Response + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status, + output reg [31:0] s_ctrlport_resp_data, + + // Clock Enable (domain: ctrlport_clk) + input wire clk_in, + output wire clk_out +); + + `include "../../../../lib/rfnoc/core/ctrlport.vh" + `include "regmap/clock_en_regmap_utils.vh" + + //--------------------------------------------------------------- + // ATR memory signals + //--------------------------------------------------------------- + reg [31:0] clk_ctrl_reg; + + //--------------------------------------------------------------- + // Handling of CtrlPort + //--------------------------------------------------------------- + // Check of request address is targeted for this module. + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + REGMAP_SIZE); + + always @(posedge ctrlport_clk) begin + // reset internal registers and responses + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_status <= 2'b0; + s_ctrlport_resp_data <= 32'b0; + clk_ctrl_reg <= 32'b0; + + end else begin + // write requests + if (s_ctrlport_req_wr) begin + // always issue an ack and no data + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_data <= {32{1'bx}}; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + CLK_EN_CONTROL: begin + clk_ctrl_reg <= s_ctrlport_req_data; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + //req_rd not delayed + end else if (s_ctrlport_req_rd) begin + // default assumption: valid request + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + s_ctrlport_resp_data <= {32{1'b0}}; + + case (s_ctrlport_req_addr) + BASE_ADDRESS + CLK_EN_CONTROL: begin + s_ctrlport_resp_data <= clk_ctrl_reg & CLK_EN_CONTROL_MASK; + end + + // error on undefined address + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // no response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + + // no request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + //--------------------------------------------------------------- + // Clock Enable + //--------------------------------------------------------------- + + wire clk_en; + + synchronizer synchronizer_i ( + .clk(clk_in ), + .rst(1'b0 ), + .in (clk_ctrl_reg[CLK_EN]), + .out(clk_en ) + ); + + BUFGCE BUFGCE_i ( + .O (clk_out), + .CE(clk_en ), + .I (clk_in ) + ); + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// Clock Enable Register +// +// +// +// This register configures Clock Enable. +// +// +// +// Enables the Clock. +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/dboards/fbx/ctrlport_to_i2c_sync_ctrl.v b/top/x400/dboards/fbx/ctrlport_to_i2c_sync_ctrl.v new file mode 100644 index 0000000..de8047a --- /dev/null +++ b/top/x400/dboards/fbx/ctrlport_to_i2c_sync_ctrl.v @@ -0,0 +1,618 @@ +// +// Copyright 2022 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ctrlport_to_i2c_sync_ctrl +// +// Description: +// +// This module wraps a I2C WB master and provides a ControlPort interface +// specific to the SYNC IO expander peripheral. +// Sync switch control sequence is as follows: +// 1. Setup core and IO expander: +// a. Write to SETUP_REG +// b. Poll/read from SETUP_STATUS_REG until bit SETUP_STATUS == 1 +// 2. Write sync switch configuration to SYNC_[1-5]_REG and RFS_EN_REG +// 3. Initiate io expander config +// a. Write to CONFIG_IO_REG +// b. Poll/read from CONFIG_IO_STATUS_REG until bit CONFIG_IO_STATUS == 1 +// Step 1 only needs to happen once after power up or core reset. +// Repeat steps 2 and 3 as needed. +// +// Parameters: +// +// BASE_ADDRESS : Base address for CtrlPort registers. +// PRESCALE : Scaling factor to determine clock speed of I2C SCL. +// Must be divisible by 5. +// + +`default_nettype wire + +module ctrlport_to_i2c_sync_ctrl #( + parameter BASE_ADDRESS = 0, + parameter [15:0] PRESCALE = 'd500 +) ( + //--------------------------------------------------------------- + // ControlPort Slave + //--------------------------------------------------------------- + + input wire ctrlport_clk, + input wire ctrlport_rst, + + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + + output reg s_ctrlport_resp_ack, + output reg [ 1:0] s_ctrlport_resp_status = 2'b0, + output reg [31:0] s_ctrlport_resp_data = 32'b0, + + //--------------------------------------------------------------- + // I2C signals + //--------------------------------------------------------------- + // i2c clock line + input wire scl_pad_i, // SCL-line input + output wire scl_pad_o, // SCL-line output + output wire scl_pad_en_o, // SCL-line output enable (active low) + + // i2c data line + input wire sda_pad_i, // SDA-line input + output wire sda_pad_o, // SDA-line output + output wire sda_pad_en_o // SDA-line output enable (active low) +); + + `include "../../../../lib/rfnoc/core/ctrlport.vh" + `include "../../../../lib/wishbone/i2c_master.vh" + `include "./regmap/rf_sync_regmap_utils.vh" + + + + //--------------------------------------------------------------- + // CtrlPort Interface Regs and Triggers to Initiate I2C + //--------------------------------------------------------------- + reg [2:0] sync1, sync2, sync3, sync4, sync5; + reg rfs_en; + reg setup_trig; // initiate setup + reg config_io_trig; // configure IO + reg setup_finished; + reg setup_finished_hold; + reg config_io_finished; + reg config_io_finished_hold; + + //--------------------------------------------------------------- + // WishBone interface + //--------------------------------------------------------------- + reg wb_cyc_i; // Active bus cycle + reg wb_we_i = 1'b0; // Write access + reg [2:0] wb_adr_i = 3'b0; + reg [7:0] wb_dat_i = 8'b0; + wire wb_ack_o; + wire [7:0] wb_dat_o; + + // Check for address to be in range [base_addr..base_addr+32) + localparam NUM_ADDRESSES = 32; + wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && + (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES); + + // The scaling factor (PRESCALE) of the input clock (ctrlport_clk) to SCL + // isn't direct but instead the relationship between the input clock and + // the state machine inside the i2c_master that controls SCL. + // This state machine has 5 repeated stages per SCL clock cycle so + // the scaling is divided by a factor of 5. The division here + // obscures a need for the user to do an extra step to calculate the + // PRESCALE parameter. + // For example, if a user wants to have an actual rescaling of 1:500 + // (SCL to ctrlpor_clk), the PRESCALE parameter is divided by 5 + // here so the i2c_master prescale value is set to 100. + if (PRESCALE % 5 != 0) begin : gen_assertion + ERROR_PRESCALE_must_be_div_by_5(); + end + + // constants to configure wb i2c master core + localparam PRESCALE_5 = PRESCALE/5; + localparam PRER_LO_CONST = PRESCALE_5[7:0]; + localparam PRER_HI_CONST = PRESCALE_5[15:8]; + + //constants for interfacing with i2c master core + localparam I2C_WR = 1'b0; + localparam I2C_RD = 1'b1; + localparam SYNC_IO_SLV_ADR = 7'h20; + + // CtrlPort Interface + // configure sync switch IO and trigger I2C transactions + always @(posedge ctrlport_clk) begin + // Reset internal registers and responses + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_status <= 2'b0; + s_ctrlport_resp_data <= 32'b0; + setup_trig <= 1'b0; + config_io_trig <= 1'b0; + setup_finished_hold <= 1'b0; + config_io_finished_hold <= 1'b0; + sync1 <= 3'b0; + sync2 <= 3'b0; + sync3 <= 3'b0; + sync4 <= 3'b0; + sync5 <= 3'b0; + rfs_en <= 1'b0; + end else begin + // Only ack under certain conditions + s_ctrlport_resp_ack <= 1'b0; + if (setup_finished) begin + setup_finished_hold <= 1'b1; + end + if (config_io_finished) begin + config_io_finished_hold <= 1'b1; + end + if (s_ctrlport_req_wr) begin // Write requests + // if address is normal ctrlport, immediately ack + if (address_in_range) begin + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + end + case (s_ctrlport_req_addr) + BASE_ADDRESS + SYNC_1_REG: begin + sync1 <= s_ctrlport_req_data[2:0]; + end + + BASE_ADDRESS + SYNC_2_REG: begin + sync2 <= s_ctrlport_req_data[2:0]; + end + + BASE_ADDRESS + SYNC_3_REG: begin + sync3 <= s_ctrlport_req_data[2:0]; + end + + BASE_ADDRESS + SYNC_4_REG: begin + sync4 <= s_ctrlport_req_data[2:0]; + end + + BASE_ADDRESS + SYNC_5_REG: begin + sync5 <= s_ctrlport_req_data[2:0]; + end + + BASE_ADDRESS + RFS_EN_REG: begin + rfs_en <= s_ctrlport_req_data[0]; + end + //initialize SYNC_IO peripheral + BASE_ADDRESS + SETUP_REG: begin + setup_trig <= 1'b1; + setup_finished_hold <= 1'b0; + end + //configure IO + BASE_ADDRESS + CONFIG_IO_REG: begin + config_io_trig <= 1'b1; + config_io_finished_hold <= 1'b0; + end + endcase + + // Read requests + end else if (s_ctrlport_req_rd) begin + // Acknowledge by default + if (address_in_range) begin + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + end + case (s_ctrlport_req_addr) + BASE_ADDRESS + SYNC_1_REG: begin + s_ctrlport_resp_data[2:0] <= sync1; + end + BASE_ADDRESS + SYNC_2_REG: begin + s_ctrlport_resp_data[2:0] <= sync2; + end + BASE_ADDRESS + SYNC_3_REG: begin + s_ctrlport_resp_data[2:0] <= sync3; + end + BASE_ADDRESS + SYNC_4_REG: begin + s_ctrlport_resp_data[2:0] <= sync4; + end + BASE_ADDRESS + SYNC_5_REG: begin + s_ctrlport_resp_data[2:0] <= sync5; + end + BASE_ADDRESS + RFS_EN_REG: begin + s_ctrlport_resp_data[2:0] <= {2'b00, rfs_en}; + end + BASE_ADDRESS + SETUP_STATUS_REG: begin + s_ctrlport_resp_data[2:0] <= {2'b00, setup_finished_hold}; + if(setup_finished_hold) begin + setup_trig <= 1'b0; + end + end + BASE_ADDRESS + CONFIG_IO_STATUS_REG: begin + s_ctrlport_resp_data[2:0] <= {2'b00, config_io_finished_hold}; + if(config_io_finished_hold) begin + config_io_trig <= 1'b0; + end + end + // Respond with 0 + default: begin + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + end + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_data <= 32'b0; + end + endcase + // No request + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end // always + + // state machine for I2C Write Transactions and WB Controls + localparam I2C_IDLE = 0; + localparam I2C_PRE_LO = 1; + localparam I2C_PRE_HI = 2; + localparam I2C_EN = 3; + localparam I2C_TXR = 4; + localparam I2C_CR = 5; + localparam I2C_TIP_START = 6; + localparam I2C_TIP = 7; + localparam I2C_TIP_FIN = 8; + + reg i2c_tip_fin; // indicates transfer is finished + reg i2c_master_en; // indicates i2c master setup and enabled + reg [3:0] i2c_state; + wire wb_cyc_valid; // determines what states wb_cyc_i should be high + reg i2c_wr; //trigger an i2c wr cmd + reg i2c_core_setup; //trigger i2c master setup + reg [7:0] wb_txr; + reg [7:0] wb_cr; + + assign wb_cyc_valid = (i2c_state >= I2C_PRE_LO ) && (i2c_state < I2C_TIP_FIN); + + always @(posedge ctrlport_clk) begin + if (ctrlport_rst) begin + i2c_state <= I2C_IDLE; + wb_cyc_i <= 1'b0; + wb_we_i <= 1'b0; + wb_adr_i <= 3'b0; + wb_dat_i <= 8'b0; + i2c_tip_fin <= 1'b0; + i2c_master_en <= 1'b0; + //more regs need to be set here. + end + else begin + //handle wb_cyc_i for all states. dependent on i2c transaction states + //and wb_ack_o + if (wb_cyc_i) begin + if (wb_ack_o) begin + wb_cyc_i <= 1'b0; + end + end else begin + if (wb_cyc_valid) begin + wb_cyc_i <= 1'b1; + end + end + case(i2c_state) + I2C_IDLE: begin + i2c_tip_fin <= 1'b0; + if (i2c_wr) begin + i2c_state <= I2C_TXR; + end + else if (i2c_core_setup) begin + i2c_state <= I2C_PRE_LO; + end + end //I2C_IDLE + //begin cases to setup i2c master core + I2C_PRE_LO: begin + wb_adr_i <= WB_PRER_LO; + wb_dat_i <= PRER_LO_CONST; + wb_we_i <= 1'b1; + if (wb_ack_o) begin + i2c_state <= I2C_PRE_HI; + end + end + I2C_PRE_HI: begin + wb_adr_i <= WB_PRER_HI; + wb_dat_i <= PRER_HI_CONST; + wb_we_i <= 1'b1; + if (wb_ack_o) begin + i2c_state <= I2C_EN; + end + end + I2C_EN: begin + wb_adr_i <= WB_CTR; + wb_dat_i <= WB_CORE_EN; + wb_we_i <= 1'b1; + i2c_master_en <= 1'b1; + if (wb_ack_o) begin + i2c_state <= I2C_IDLE; + end + end + //end cases to setup i2c master core + //begin cases to initiate i2c write transfer + I2C_TXR: begin + wb_adr_i <= WB_TXR; + wb_dat_i <= wb_txr; + wb_we_i <= 1'b1; + if (wb_ack_o) begin + i2c_state <= I2C_CR; + end + end + I2C_CR: begin + wb_adr_i <= WB_CR; + wb_dat_i <= wb_cr; + wb_we_i <= 1'b1; + if (wb_ack_o) begin + i2c_state <= I2C_TIP_START; + end + end + I2C_TIP_START: begin + wb_adr_i <= WB_SR; + wb_dat_i <= 8'b0; + wb_we_i <= 1'b0; + if (wb_ack_o && wb_dat_o[1]) begin + i2c_state <= I2C_TIP; + end + end + I2C_TIP: begin //TIP transfer in progress + wb_adr_i <= WB_SR; + wb_dat_i <= 8'b0; + wb_we_i <= 1'b0; + if (wb_ack_o && !wb_dat_o[1]) begin + i2c_state <= I2C_TIP_FIN; + i2c_tip_fin <= 1'b1; //pulse this as we transition to final state + end + end + I2C_TIP_FIN: begin + i2c_tip_fin <= 1'b0; + if (!i2c_wr) begin + i2c_state <= I2C_IDLE; + end + end + //end cases to initiate i2c write transfer + //default case, just go to I2C_IDLE + default : begin + i2c_state <= I2C_IDLE; + end + endcase + end + end //always + + + + // i2c master top controller state machine + localparam IDLE = 0; + localparam EN = 1; + localparam IO_EXP_CONFIG_1 = 2; + localparam IO_EXP_CONFIG_2 = 3; + localparam IO_EXP_CONFIG_3 = 4; + localparam IO_EXP_CONFIG_4 = 5; + localparam IO_EXP_FIN = 6; + + wire [15:0] io_config; + assign io_config = { rfs_en, sync5, sync4, sync3, sync2, sync1 }; + reg [2:0] master_state; + always @(posedge ctrlport_clk) begin + if (ctrlport_rst) begin + master_state <= IDLE; + wb_txr <= 8'b0; + wb_cr <= 8'b0; + i2c_wr <= 1'b0; + setup_finished <= 1'b0; + config_io_finished <= 1'b0; + i2c_core_setup <= 1'b0; + end + else begin + case(master_state) + IDLE: begin + i2c_wr <= 1'b0; + setup_finished <= 1'b0; + config_io_finished <= 1'b0; + i2c_core_setup <= 1'b0; + if (setup_trig) begin + master_state <= EN; + end + else if (config_io_trig) begin + master_state <= IO_EXP_CONFIG_1; + end + end + EN: begin //all the prescale and enable setup happens in i2c_state machine + i2c_core_setup <= 1'b1; //triggers setup sequence in i2c state machine. + i2c_wr <= 1'b0; + if (i2c_master_en) begin //indicates setup sequence finished + master_state <= IO_EXP_CONFIG_1; + end + end + IO_EXP_CONFIG_1: begin //first stage of setting up IO EXP with startup configurations + wb_txr <= { SYNC_IO_SLV_ADR, I2C_WR}; + wb_cr <= CR_START_AND_WRITE; + if (i2c_tip_fin) begin //when transfer is done, i2c_wr is disabled + i2c_wr <= 1'b0; + master_state <= IO_EXP_CONFIG_2; + end else begin + i2c_wr <= 1'b1; + end + end + IO_EXP_CONFIG_2: begin + if (setup_trig) begin + wb_txr <= IO_EXP_CONFIG0_REG; //CONFIG0 reg is what we set to configure I/O as output + end else if (config_io_trig) begin + wb_txr <= IO_EXP_OUTPUT_PORT0_REG; + end + wb_cr <= CR_WRITE; + if (i2c_tip_fin) begin //when transfer is done, i2c_wr is disabled + i2c_wr <= 1'b0; + master_state <= IO_EXP_CONFIG_3; + end else begin + i2c_wr <= 1'b1; + end + end + IO_EXP_CONFIG_3: begin + if (setup_trig) begin + wb_txr <= 1'b0; + end else if (config_io_trig) begin + wb_txr <= io_config[7:0]; + end + wb_cr <= CR_WRITE; + if (i2c_tip_fin) begin //when transfer is done, i2c_wr is disabled + i2c_wr <= 1'b0; + master_state <= IO_EXP_CONFIG_4; + end else begin + i2c_wr <= 1'b1; + end + end + IO_EXP_CONFIG_4: begin + if (setup_trig) begin + wb_txr <= 1'b0; + end else if (config_io_trig) begin + wb_txr <= io_config[15:8]; + end + wb_cr <= CR_WRITE_AND_STOP; + if (i2c_tip_fin) begin //when transfer is done, i2c_wr is disabled + i2c_wr <= 1'b0; + setup_finished <= setup_trig; + config_io_finished <= config_io_trig; + master_state <= IO_EXP_FIN; + end else begin + i2c_wr <= 1'b1; + end + end + IO_EXP_FIN : begin //final state to make sure triggers are unset before returning to IDLE; + i2c_wr <= 1'b0; + setup_finished <= 1'b0; + config_io_finished <= 1'b0; + if (!setup_trig && !config_io_trig) begin + master_state <= IDLE; + end + end + default : begin + master_state <= IDLE; + end + endcase + end + end //always + + //wishbone-based i2c core + i2c_master_top #( + .ARST_LVL(1) + ) i2c_master ( + .wb_clk_i(ctrlport_clk), + .wb_rst_i(ctrlport_rst), + .arst_i(1'b0), + .wb_adr_i(wb_adr_i), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_we_i(wb_we_i), + .wb_stb_i(wb_cyc_i), + .wb_cyc_i(wb_cyc_i), + .wb_ack_o(wb_ack_o), + .wb_inta_o(), + .scl_pad_i(scl_pad_i), + .scl_pad_o(scl_pad_o), + .scl_padoen_o(scl_pad_en_o), + .sda_pad_i(sda_pad_i), + .sda_pad_o(sda_pad_o), + .sda_padoen_o(sda_pad_en_o) + ); + +endmodule + + +//XmlParse xml_on +// +// +// +// Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1 +// switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for +// all four switches are not considered time critical controls, and are hence driven by a +// TCA6416A I/O expander controlled via I2C. +// This register map controls that I/O expander. The first 6 registers in +// this space set the values of the 5 3-pin sync switches and then an +// RFS enable bit. The 2 additional registers trigger a init sequence for +// the expander peripheral and configuring the I/O with the contents of +// the value registers both with a series of I2C commands. +// +// +// +// Sets I/O to control Sync Switch. +// +// +// +// +// +// +// +// Sets I/O state to control Sync Switch 1. +// +// +// +// +// Sets I/O state to control Sync Switch 2. +// +// +// +// +// Sets I/O state to control Sync Switch 3. +// +// +// +// +// Sets I/O state to control Sync Switch 4. +// +// +// +// +// Sets I/O state to control Sync Switch 5. +// +// +// +// +// Sets I/O state to control RFS Enable. +// +// +// +// +// +// Write to this register to trigger initialization sequence of +// I2C Master core and TCA6416A I/O expander peripheral. +// +// +// +// +// +// Read from this register to check the status of setup. +// +// +// +// +// +// Write to this register to trigger I/O configuration I2C sequence of +// TCA6416A I/O expander peripheral. +// Read from this register to check the status of reconfiguring the setup. +// +// +// +// +// +// Read from this register to check the status of reconfiguring the setup. +// +// +// +// +// +// +// This is not a register spaces for this ctrlport interface but +// instead register addresses on the TCA6416A. Therefore, we will just +// define an enum with these addresses so there is no clash with the +// above ctrlport regmap. +// +// +// +// +// +// +// +// +// +// +// +// + +//XmlParse xml_off + diff --git a/top/x400/dboards/fbx/db_gpio_interface.v b/top/x400/dboards/fbx/db_gpio_interface.v new file mode 100644 index 0000000..2c01bdc --- /dev/null +++ b/top/x400/dboards/fbx/db_gpio_interface.v @@ -0,0 +1,444 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: db_gpio_interface +// +// Description: +// Interface for GPIO interface towards FBX daughterboards. +// +// +// The 20 available GPIO lines are assigned with +// - 12x RF switches(3x per channel) +// - 2x I2C to Sync switches IO Expander +// - 6x empty +// + +`default_nettype none + +module db_gpio_interface #( + parameter LED_REGISTER_ADDRESS = 0 +) ( + // Clocks and reset + input wire radio_clk, + input wire pll_ref_clk, + input wire in_sync_clk, + output wire out_sync_clk, + + // DB state lines (domain: radio_clk) + input wire [ 7:0] db_state, + // Request (domain: radio_clk) + input wire ctrlport_rst, + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + + // Response (domain: radio_clk) + output wire s_ctrlport_resp_ack, + output wire [ 1:0] s_ctrlport_resp_status, + output wire [31:0] s_ctrlport_resp_data, + + // ControlPort request to CPLD (domain: radio_clk) + output wire m_ctrlport_req_wr, + output wire m_ctrlport_req_rd, + output wire [19:0] m_ctrlport_req_addr, + output wire [31:0] m_ctrlport_req_data, + output wire [ 3:0] m_ctrlport_req_byte_en, + + // ControlPort response from CPLD (domain: radio_clk) + input wire m_ctrlport_resp_ack, + input wire [ 1:0] m_ctrlport_resp_status, + input wire [31:0] m_ctrlport_resp_data, + + // GPIO interface (domain: pll_ref_clk) + input wire [19:0] gpio_in, + output wire [19:0] gpio_out, + output wire [19:0] gpio_out_en, + + // Version (Constant) + output wire [95:0] version_info +); + + `include "../../regmap/x440/versioning_regs_regmap_utils.vh" + `include "regmap/fbx_ctrl_regmap_utils.vh" + `include "../../regmap/versioning_utils.vh" + + //---------------------------------------------------------------------------- + // Radio_clk -> pll_ref_clk clock crossing + //---------------------------------------------------------------------------- + + wire ctrlport_rst_prc; + + wire ctrlport_req_wr_prc; + wire ctrlport_req_rd_prc; + wire [19:0] ctrlport_req_addr_prc; + wire [31:0] ctrlport_req_data_prc; + + wire ctrlport_resp_ack_prc; + wire [ 1:0] ctrlport_resp_status_prc; + wire [31:0] ctrlport_resp_data_prc; + + ctrlport_clk_cross core_clk_cross_slave ( + .rst (ctrlport_rst), + .s_ctrlport_clk (radio_clk), + .s_ctrlport_req_wr (s_ctrlport_req_wr), + .s_ctrlport_req_rd (s_ctrlport_req_rd), + .s_ctrlport_req_addr (s_ctrlport_req_addr), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (s_ctrlport_req_data), + .s_ctrlport_req_byte_en (), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (s_ctrlport_resp_ack), + .s_ctrlport_resp_status (s_ctrlport_resp_status), + .s_ctrlport_resp_data (s_ctrlport_resp_data), + .m_ctrlport_clk (pll_ref_clk), + .m_ctrlport_req_wr (ctrlport_req_wr_prc), + .m_ctrlport_req_rd (ctrlport_req_rd_prc), + .m_ctrlport_req_addr (ctrlport_req_addr_prc), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (ctrlport_req_data_prc), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (ctrlport_resp_ack_prc), + .m_ctrlport_resp_status (ctrlport_resp_status_prc), + .m_ctrlport_resp_data (ctrlport_resp_data_prc) + ); + + reset_sync reset_sync_prc ( + .clk (pll_ref_clk), + .reset_in (ctrlport_rst), + .reset_out (ctrlport_rst_prc) + ); + + wire [7:0] db_state_prc; + + handshake #( + .WIDTH (8) + ) synchronizer_db_state ( + .clk_a (radio_clk), + .rst_a (ctrlport_rst), + .valid_a (1'b1), + .data_a (db_state), + .busy_a (), + .clk_b (pll_ref_clk), + .valid_b (), + .data_b (db_state_prc) + ); + + //---------------------------------------------------------------------------- + // CtrlPort Splitter + //---------------------------------------------------------------------------- + + wire [19:0] rf_atr_ctrlport_req_addr; + wire [31:0] rf_atr_ctrlport_req_data; + wire rf_atr_ctrlport_req_rd; + wire rf_atr_ctrlport_req_wr; + wire rf_atr_ctrlport_resp_ack; + wire [31:0] rf_atr_ctrlport_resp_data; + wire [ 1:0] rf_atr_ctrlport_resp_status; + + wire [19:0] sync_ctrlport_req_addr; + wire [31:0] sync_ctrlport_req_data; + wire sync_ctrlport_req_rd; + wire sync_ctrlport_req_wr; + wire sync_ctrlport_resp_ack; + wire [31:0] sync_ctrlport_resp_data; + wire [ 1:0] sync_ctrlport_resp_status; + + wire [19:0] led_atr_ctrlport_req_addr; + wire [31:0] led_atr_ctrlport_req_data; + wire led_atr_ctrlport_req_rd; + wire led_atr_ctrlport_req_wr; + wire led_atr_ctrlport_resp_ack; + wire [31:0] led_atr_ctrlport_resp_data; + wire [ 1:0] led_atr_ctrlport_resp_status; + + wire [19:0] clk_en_ctrlport_req_addr; + wire [31:0] clk_en_ctrlport_req_data; + wire clk_en_ctrlport_req_rd; + wire clk_en_ctrlport_req_wr; + wire clk_en_ctrlport_resp_ack; + wire [31:0] clk_en_ctrlport_resp_data; + wire [ 1:0] clk_en_ctrlport_resp_status; + + ctrlport_splitter #( + .NUM_SLAVES (4) + ) fbx_ctrlport_splitter ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .s_ctrlport_req_wr (ctrlport_req_wr_prc), + .s_ctrlport_req_rd (ctrlport_req_rd_prc), + .s_ctrlport_req_addr (ctrlport_req_addr_prc), + .s_ctrlport_req_data (ctrlport_req_data_prc), + .s_ctrlport_req_byte_en (4'hF), + .s_ctrlport_req_has_time (1'b0), + .s_ctrlport_req_time (64'b0), + .s_ctrlport_resp_ack (ctrlport_resp_ack_prc), + .s_ctrlport_resp_status (ctrlport_resp_status_prc), + .s_ctrlport_resp_data (ctrlport_resp_data_prc), + .m_ctrlport_req_wr ({ clk_en_ctrlport_req_wr, led_atr_ctrlport_req_wr, sync_ctrlport_req_wr, rf_atr_ctrlport_req_wr }), + .m_ctrlport_req_rd ({ clk_en_ctrlport_req_rd, led_atr_ctrlport_req_rd, sync_ctrlport_req_rd, rf_atr_ctrlport_req_rd }), + .m_ctrlport_req_addr ({ clk_en_ctrlport_req_addr, led_atr_ctrlport_req_addr, sync_ctrlport_req_addr, rf_atr_ctrlport_req_addr }), + .m_ctrlport_req_data ({ clk_en_ctrlport_req_data, led_atr_ctrlport_req_data, sync_ctrlport_req_data, rf_atr_ctrlport_req_data }), + .m_ctrlport_req_byte_en (), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack ({ clk_en_ctrlport_resp_ack, led_atr_ctrlport_resp_ack, sync_ctrlport_resp_ack, rf_atr_ctrlport_resp_ack }), + .m_ctrlport_resp_status ({ clk_en_ctrlport_resp_status, led_atr_ctrlport_resp_status, sync_ctrlport_resp_status, rf_atr_ctrlport_resp_status }), + .m_ctrlport_resp_data ({ clk_en_ctrlport_resp_data, led_atr_ctrlport_resp_data, sync_ctrlport_resp_data, rf_atr_ctrlport_resp_data }) + ); + + //---------------------------------------------------------------------------- + // Switch Control + //---------------------------------------------------------------------------- + + wire rf0_tx_rx_rfs, rf0_rx_rfs, rf0_tdds; + wire rf1_tx_rx_rfs, rf1_rx_rfs, rf1_tdds; + wire rf2_tx_rx_rfs, rf2_rx_rfs, rf2_tdds; + wire rf3_tx_rx_rfs, rf3_rx_rfs, rf3_tdds; + + rf_atr_control #( + .REG_BASE (RF_ATR_REGS), + .REG_SIZE (RF_ATR_REGS_SIZE) + ) rf_atr_control_i ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .s_ctrlport_req_wr (rf_atr_ctrlport_req_wr), + .s_ctrlport_req_rd (rf_atr_ctrlport_req_rd), + .s_ctrlport_req_addr (rf_atr_ctrlport_req_addr), + .s_ctrlport_req_data (rf_atr_ctrlport_req_data), + .s_ctrlport_resp_ack (rf_atr_ctrlport_resp_ack), + .s_ctrlport_resp_status (rf_atr_ctrlport_resp_status), + .s_ctrlport_resp_data (rf_atr_ctrlport_resp_data), + .db_state (db_state_prc), + .rf0_tx_rx_rfs (rf0_tx_rx_rfs), + .rf0_rx_rfs (rf0_rx_rfs), + .rf0_tdds (rf0_tdds), + .rf1_tx_rx_rfs (rf1_tx_rx_rfs), + .rf1_rx_rfs (rf1_rx_rfs), + .rf1_tdds (rf1_tdds), + .rf2_tx_rx_rfs (rf2_tx_rx_rfs), + .rf2_rx_rfs (rf2_rx_rfs), + .rf2_tdds (rf2_tdds), + .rf3_tx_rx_rfs (rf3_tx_rx_rfs), + .rf3_rx_rfs (rf3_rx_rfs), + .rf3_tdds (rf3_tdds) + ); + + //---------------------------------------------------------------------------- + // LED Control + //---------------------------------------------------------------------------- + + wire cpld_ctrlport_req_wr; + wire cpld_ctrlport_req_rd; + wire [19:0] cpld_ctrlport_req_addr; + wire [31:0] cpld_ctrlport_req_data; + wire [ 3:0] cpld_ctrlport_req_byte_en; + + wire cpld_ctrlport_resp_ack; + wire [ 1:0] cpld_ctrlport_resp_status; + wire [31:0] cpld_ctrlport_resp_data; + + + led_atr_control #( + .LED_REGISTER_ADDRESS (LED_REGISTER_ADDRESS), + .REG_BASE (LED_ATR_REGS), + .REG_SIZE (LED_ATR_REGS_SIZE) + ) led_atr_control_i ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .s_ctrlport_req_wr (led_atr_ctrlport_req_wr), + .s_ctrlport_req_rd (led_atr_ctrlport_req_rd), + .s_ctrlport_req_addr (led_atr_ctrlport_req_addr), + .s_ctrlport_req_data (led_atr_ctrlport_req_data), + .s_ctrlport_resp_ack (led_atr_ctrlport_resp_ack), + .s_ctrlport_resp_status (led_atr_ctrlport_resp_status), + .s_ctrlport_resp_data (led_atr_ctrlport_resp_data), + .db_state (db_state_prc), + .m_ctrlport_req_wr (cpld_ctrlport_req_wr), + .m_ctrlport_req_rd (cpld_ctrlport_req_rd), + .m_ctrlport_req_addr (cpld_ctrlport_req_addr), + .m_ctrlport_req_data (cpld_ctrlport_req_data), + .m_ctrlport_req_byte_en (cpld_ctrlport_req_byte_en), + .m_ctrlport_resp_ack (cpld_ctrlport_resp_ack), + .m_ctrlport_resp_status (cpld_ctrlport_resp_status), + .m_ctrlport_resp_data (cpld_ctrlport_resp_data) + ); + + ctrlport_clk_cross core_clk_cross_cpld_master ( + .rst (ctrlport_rst_prc), + .s_ctrlport_clk (pll_ref_clk), + .s_ctrlport_req_wr (cpld_ctrlport_req_wr), + .s_ctrlport_req_rd (cpld_ctrlport_req_rd), + .s_ctrlport_req_addr (cpld_ctrlport_req_addr), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (cpld_ctrlport_req_data), + .s_ctrlport_req_byte_en (cpld_ctrlport_req_byte_en), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (cpld_ctrlport_resp_ack), + .s_ctrlport_resp_status (cpld_ctrlport_resp_status), + .s_ctrlport_resp_data (cpld_ctrlport_resp_data), + .m_ctrlport_clk (radio_clk), + .m_ctrlport_req_wr (m_ctrlport_req_wr), + .m_ctrlport_req_rd (m_ctrlport_req_rd), + .m_ctrlport_req_addr (m_ctrlport_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (m_ctrlport_req_data), + .m_ctrlport_req_byte_en (m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (m_ctrlport_resp_ack), + .m_ctrlport_resp_status (m_ctrlport_resp_status), + .m_ctrlport_resp_data (m_ctrlport_resp_data) + ); + + //---------------------------------------------------------------------------- + // I2C Control + //---------------------------------------------------------------------------- + + wire i2c_scl_i, i2c_scl_o, i2c_scl_en_o; + wire i2c_sda_i, i2c_sda_o, i2c_sda_en_o; + + ctrlport_to_i2c_sync_ctrl #( + .BASE_ADDRESS(RF_SYNC_REGS), + .PRESCALE(1000) + ) ctrlport_to_i2c_inst ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .s_ctrlport_req_wr (sync_ctrlport_req_wr), + .s_ctrlport_req_rd (sync_ctrlport_req_rd), + .s_ctrlport_req_addr (sync_ctrlport_req_addr), + .s_ctrlport_req_data (sync_ctrlport_req_data), + .s_ctrlport_resp_ack (sync_ctrlport_resp_ack), + .s_ctrlport_resp_status (sync_ctrlport_resp_status), + .s_ctrlport_resp_data (sync_ctrlport_resp_data), + .scl_pad_i (i2c_scl_i), + .scl_pad_o (i2c_scl_o), + .scl_pad_en_o (i2c_scl_en_o), + .sda_pad_i (i2c_sda_i), + .sda_pad_o (i2c_sda_o), + .sda_pad_en_o (i2c_sda_en_o) + ); + + //---------------------------------------------------------------------------- + // Sync Clock Enable + //---------------------------------------------------------------------------- + + clock_en_control #( + .BASE_ADDRESS(SYNC_CLK_EN_REGS) + ) clock_en_control_inst ( + .ctrlport_clk (pll_ref_clk), + .ctrlport_rst (ctrlport_rst_prc), + .s_ctrlport_req_wr (clk_en_ctrlport_req_wr), + .s_ctrlport_req_rd (clk_en_ctrlport_req_rd), + .s_ctrlport_req_addr (clk_en_ctrlport_req_addr), + .s_ctrlport_req_data (clk_en_ctrlport_req_data), + .s_ctrlport_resp_ack (clk_en_ctrlport_resp_ack), + .s_ctrlport_resp_status (clk_en_ctrlport_resp_status), + .s_ctrlport_resp_data (clk_en_ctrlport_resp_data), + .clk_in (in_sync_clk), + .clk_out (out_sync_clk) + ); + + //---------------------------------------------------------------------------- + // wire assignment + //---------------------------------------------------------------------------- + // RFS1, RFS2, RFS3, RFS4, RFS5, RFS6, RFS7, RFS8, TDDS1, TDDS2, TDDS3, TDDS4, + // 2 unused, 2 for I2C, 4 unused. + + assign i2c_sda_i = gpio_in[4]; + assign i2c_scl_i = gpio_in[5]; + + assign gpio_out = {rf0_tx_rx_rfs, rf0_rx_rfs, + rf1_tx_rx_rfs, rf1_rx_rfs, + rf2_tx_rx_rfs, rf2_rx_rfs, + rf3_tx_rx_rfs, rf3_rx_rfs, + rf0_tdds, rf1_tdds, + rf2_tdds, rf3_tdds, + 2'b0, // Unused + i2c_scl_o, i2c_sda_o, // I2C + 4'b0 // Unused + }; + + assign gpio_out_en = {12'hFFF, // Switches + 2'b0, // Unused + ~i2c_scl_en_o, ~i2c_sda_en_o, // I2C enables tri-state when HIGH + 4'b0 // Unused + }; + //---------------------------------------------------------------------------- + // version_info + //---------------------------------------------------------------------------- + + // Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh + assign version_info = build_component_versions( + DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME, + build_version( + DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR, + DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR, + DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD), + build_version( + DB_GPIO_IFC_CURRENT_VERSION_MAJOR, + DB_GPIO_IFC_CURRENT_VERSION_MINOR, + DB_GPIO_IFC_CURRENT_VERSION_BUILD)); + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// +// Daughterboard GPIO interface.{BR/} +// For guidance on when to update these revision numbers, +// please refer to the register map documentation accordingly: +//
  • Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION +//
  • Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION +//
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED +// +// +// +// +// +// +// +// +// +// +// + +// +// +// This map contains register windows for controlling the different sources +// that drive the state of FBX control lines. +// +// +// +// Control RF switches in FBX daughterboard based on the ATR state of the accessed radio +// +// +// I2C interface to FBX daughterboard IO Expander that controls SYNC switches and rfs en +// +// +// Control TX/RX LEDs based on the ATR state of the accessed radio +// +// +// Clock enable register for SYNC INJECT 5 MHz clock +// +// +// +//XmlParse xml_off diff --git a/top/x400/dboards/fbx/led_atr_control.v b/top/x400/dboards/fbx/led_atr_control.v new file mode 100644 index 0000000..6198b93 --- /dev/null +++ b/top/x400/dboards/fbx/led_atr_control.v @@ -0,0 +1,569 @@ +// +// Copyright 2022 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: led_atr_control +// +// Description: +// Translates db_status to implement control over RF LEDs via CtrlPort. +// Uses RAM to store multiple ATR configurations. Triggers CtrlPort +// requests to transfer changes to LEDs to MB CPLD. +// There are three supported control schemes for these switches: +// - ATR Disabled - Single persistent state. +// - Classic ATR - Each channel's LEDs depend on the transmission state +// of the respective channel. +// - DB State - Each channel's LEDs depend on the transmission state +// of all channels in this radio. +// +// Parameters: +// +// LED_REGISTER_ADDRESS : Address of LED register within CPLD. +// REG_BASE : Base address to use for registers. +// REG_SIZE : Register space size. +// + +`default_nettype none + +module led_atr_control #( + parameter LED_REGISTER_ADDRESS = 0, + parameter REG_BASE = 'h2000, + parameter REG_SIZE = 'h2000 + +) ( + // Common ControlPort signals + input wire ctrlport_clk, + input wire ctrlport_rst, + + // Slave ctrlport inteledace + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + output reg s_ctrlport_resp_ack = 1'b0, + output reg [ 1:0] s_ctrlport_resp_status = 2'b00, + output reg [31:0] s_ctrlport_resp_data = {32 {1'b0}}, + + // DB state lines + input wire [7:0] db_state, + + // ControlPort request + output reg m_ctrlport_req_wr, + output wire m_ctrlport_req_rd, + output wire [19:0] m_ctrlport_req_addr, + output wire [31:0] m_ctrlport_req_data, + output wire [ 3:0] m_ctrlport_req_byte_en, + + // ControlPort response + input wire m_ctrlport_resp_ack, + input wire [ 1:0] m_ctrlport_resp_status, + input wire [31:0] m_ctrlport_resp_data + +); + + `include "../../cpld/regmap/x440/led_setup_regmap_utils.vh" + `include "../../../../lib/rfnoc/core/ctrlport.vh" + `include "regmap/led_atr_regmap_utils.vh" + + + //--------------------------------------------------------------- + // ATR memory signals + //--------------------------------------------------------------- + reg ram_led0_wea; + wire [LED_SIZE-1:0] ram_led0_doa; + wire [LED_SIZE-1:0] ram_led0_dob; + + reg ram_led1_wea; + wire [LED_SIZE-1:0] ram_led1_doa; + wire [LED_SIZE-1:0] ram_led1_dob; + + reg ram_led2_wea; + wire [LED_SIZE-1:0] ram_led2_doa; + wire [LED_SIZE-1:0] ram_led2_dob; + + reg ram_led3_wea; + wire [LED_SIZE-1:0] ram_led3_doa; + wire [LED_SIZE-1:0] ram_led3_dob; + + + //--------------------------------------------------------------- + // ATR Scheme signals + //--------------------------------------------------------------- + reg [3:0] atr_disable = 4'b0; + + // DB state/Classic ATR selector + reg [3:0] atr_mode = 4'b0; + + //--------------------------------------------------------------------------- + // Control inteledace handling + //--------------------------------------------------------------------------- + + // Check that address is within this module's range. + wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE); + + // Check that address is targeting an ATR state. + wire address_is_atr = (s_ctrlport_req_addr >= REG_BASE + LED0_ATR_STATE(0)) && (s_ctrlport_req_addr <= REG_BASE + LED3_ATR_STATE(LED3_ATR_STATE_COUNT-1)); + + // Read request shift register to align memory read and response generation. + reg [ 1:0] read_req_shift_reg = 2'b0; + // Mask out 8 bits for ATR configurations to be able to compare all ATR + // configurations against the same base register address. + wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]}; + // Decode the ATR state being addressed. + wire [ 7:0] atr_address = s_ctrlport_req_addr[9:2]; + + always @ (posedge ctrlport_clk) begin + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_data <= 32'b0; + s_ctrlport_resp_status <= 2'b00; + + atr_disable <= 4'b0; + atr_mode <= 4'b0; + + ram_led0_wea <= 1'b0; + ram_led1_wea <= 1'b0; + ram_led2_wea <= 1'b0; + ram_led3_wea <= 1'b0; + + end else begin + // default assignments + read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd}; + + ram_led0_wea <= 1'b0; + ram_led1_wea <= 1'b0; + ram_led2_wea <= 1'b0; + ram_led3_wea <= 1'b0; + + // Write registers + if (s_ctrlport_req_wr) begin + // Acknowledge by default + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + // Address ATR state writes + if(address_is_atr) begin + + case (register_base_address) + REG_BASE + LED0_ATR_STATE(0): begin + ram_led0_wea <= 1'b1; + end + + REG_BASE + LED1_ATR_STATE(0): begin + ram_led1_wea <= 1'b1; + end + + REG_BASE + LED2_ATR_STATE(0): begin + ram_led2_wea <= 1'b1; + end + + REG_BASE + LED3_ATR_STATE(0): begin + ram_led3_wea <= 1'b1; + end + + // error on undefined address + default: begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + end + endcase + end else begin + + // Address writes to the rest of the register space + case (s_ctrlport_req_addr) + + REG_BASE + LED_ATR_OPTION_REGISTER: begin + atr_mode[0] <= s_ctrlport_req_data[LED0_ATR_OPTION]; + atr_mode[1] <= s_ctrlport_req_data[LED1_ATR_OPTION]; + atr_mode[2] <= s_ctrlport_req_data[LED2_ATR_OPTION]; + atr_mode[3] <= s_ctrlport_req_data[LED3_ATR_OPTION]; + end + + REG_BASE + LED_ATR_DISABLED: begin + atr_disable[0] <= s_ctrlport_req_data[LED0_ATR_DISABLED]; + atr_disable[1] <= s_ctrlport_req_data[LED1_ATR_DISABLED]; + atr_disable[2] <= s_ctrlport_req_data[LED2_ATR_DISABLED]; + atr_disable[3] <= s_ctrlport_req_data[LED3_ATR_DISABLED]; + end + + // No register implementation for provided address + default: begin + // Acknowledge and provide error status if address is in range + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // No response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + end + + // Read registers + end else if (read_req_shift_reg[1]) begin + // Acknowledge by default + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + // Address ATR state reads + if(address_is_atr) begin + + case (register_base_address) + REG_BASE + LED0_ATR_STATE(0): begin + s_ctrlport_resp_data <= ram_led0_doa & LED_ATR_STATE_MASK; + end + REG_BASE + LED1_ATR_STATE(0): begin + s_ctrlport_resp_data <= ram_led1_doa & LED_ATR_STATE_MASK; + end + REG_BASE + LED2_ATR_STATE(0): begin + s_ctrlport_resp_data <= ram_led2_doa & LED_ATR_STATE_MASK; + end + REG_BASE + LED3_ATR_STATE(0): begin + s_ctrlport_resp_data <= ram_led3_doa & LED_ATR_STATE_MASK; + end + + default: begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + end + endcase + + end else begin + + // Address reads to the rest of the register space + case (s_ctrlport_req_addr) + + REG_BASE + LED_ATR_OPTION_REGISTER: begin + s_ctrlport_resp_data[LED0_ATR_OPTION] <= atr_mode[0]; + s_ctrlport_resp_data[LED1_ATR_OPTION] <= atr_mode[1]; + s_ctrlport_resp_data[LED2_ATR_OPTION] <= atr_mode[2]; + s_ctrlport_resp_data[LED3_ATR_OPTION] <= atr_mode[3]; + end + + REG_BASE + LED_ATR_DISABLED: begin + s_ctrlport_resp_data[LED0_ATR_DISABLED] <= atr_disable[0]; + s_ctrlport_resp_data[LED1_ATR_DISABLED] <= atr_disable[1]; + s_ctrlport_resp_data[LED2_ATR_DISABLED] <= atr_disable[2]; + s_ctrlport_resp_data[LED3_ATR_DISABLED] <= atr_disable[3]; + end + + // No register implementation for provided address + default: begin + // Acknowledge and provide error status if address is in range + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // No response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + end + + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + // register without reset + reg [ 7:0] ram_addr = 8'b0; + reg [LED_SIZE-1:0] ram_datain = {LED_SIZE{1'b0}}; + always @(posedge ctrlport_clk) begin + // memories + ram_addr <= atr_address; + ram_datain <= s_ctrlport_req_data[LED_SIZE-1:0]; + end + + // ATR Scheme selection + reg [7:0] atr_config_led [3:0]; + + generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin: read_address_gen + + always @(posedge ctrlport_clk) begin + if (atr_disable[i]) begin + atr_config_led[i] <= 8'b0; + end else begin + if (atr_mode[i]) begin + atr_config_led[i] <= {6'b0, db_state[2*i+:2]}; + end else begin + atr_config_led[i] <= db_state; + end + end + end + + end + endgenerate + + reg [31:0] led_combined = 32'b0; + always @(posedge ctrlport_clk) begin + led_combined[CH0_RX2_LED_EN] <= ram_led0_dob[RX2_LED]; + led_combined[CH0_TRX1_LED_RED_EN] <= ram_led0_dob[TXRX_RED_LED]; + led_combined[CH0_TRX1_LED_GR_EN] <= ram_led0_dob[TXRX_GR_LED]; + + led_combined[CH1_RX2_LED_EN] <= ram_led1_dob[RX2_LED]; + led_combined[CH1_TRX1_LED_RED_EN] <= ram_led1_dob[TXRX_RED_LED]; + led_combined[CH1_TRX1_LED_GR_EN] <= ram_led1_dob[TXRX_GR_LED]; + + led_combined[CH2_RX2_LED_EN] <= ram_led2_dob[RX2_LED]; + led_combined[CH2_TRX1_LED_RED_EN] <= ram_led2_dob[TXRX_RED_LED]; + led_combined[CH2_TRX1_LED_GR_EN] <= ram_led2_dob[TXRX_GR_LED]; + + led_combined[CH3_RX2_LED_EN] <= ram_led3_dob[RX2_LED]; + led_combined[CH3_TRX1_LED_RED_EN] <= ram_led3_dob[TXRX_RED_LED]; + led_combined[CH3_TRX1_LED_GR_EN] <= ram_led3_dob[TXRX_GR_LED]; + + end + + + //--------------------------------------------------------------- + // ATR memory + //--------------------------------------------------------------- + ram_2port #( + .DWIDTH (LED_SIZE), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0) + ) ram_led0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_led0_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_led0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_led[0]), + .dib ({LED_SIZE{1'b0}}), + .dob (ram_led0_dob)); + + ram_2port #( + .DWIDTH (LED_SIZE), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0) + ) ram_led1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_led1_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_led1_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_led[1]), + .dib ({LED_SIZE{1'b0}}), + .dob (ram_led1_dob)); + + ram_2port #( + .DWIDTH (LED_SIZE), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0) + ) ram_led2_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_led2_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_led2_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_led[2]), + .dib ({LED_SIZE{1'b0}}), + .dob (ram_led2_dob)); + + ram_2port #( + .DWIDTH (LED_SIZE), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0) + ) ram_led3_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_led3_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_led3_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_led[3]), + .dib ({LED_SIZE{1'b0}}), + .dob (ram_led3_dob)); + + + //---------------------------------------------------------- + // Logic to wait for response after triggering request + //---------------------------------------------------------- + + reg transfer_in_progress; + reg [31:0] led_combined_delayed = 32'b0; + + always @(posedge ctrlport_clk) begin + if (ctrlport_rst) begin + m_ctrlport_req_wr <= 1'b0; + transfer_in_progress <= 1'b0; + led_combined_delayed <= 16'b0; + end else begin + // Default assignment + m_ctrlport_req_wr <= 1'b0; + + // Issue new request on change if no request is pending + if (led_combined != led_combined_delayed && ~transfer_in_progress) begin + transfer_in_progress <= 1'b1; + m_ctrlport_req_wr <= 1'b1; + led_combined_delayed <= led_combined; + end + + // Reset pending request + if (m_ctrlport_resp_ack) begin + transfer_in_progress <= 1'b0; + end + end + end + + //---------------------------------------------------------- + // Static ControlPort assignments + //---------------------------------------------------------- + + assign m_ctrlport_req_rd = 0; + assign m_ctrlport_req_byte_en = 4'b1111; + assign m_ctrlport_req_addr = LED_REGISTER_ADDRESS; + assign m_ctrlport_req_data = {led_combined_delayed}; + +endmodule + +//XmlParse xml_on +// +// +// +// Each channel in the FBX daughterboard has 3 LEDs. TXRX Red/Green LEDs and RX2 Green LED. +// This register map describes how to control the behavior of the 3 LEDs. +// There are three supported control schemes for these LEDs:
    +//
      +//
    • ATR Disabled - Single persistent state.
      • +//
    • Classic ATR - Each channel's LEDs depend on the transmission state +// of the respective channel.
      • +//
    • DB State - Each channel's LEDs depend on the transmission state +// of all channels in this radio.
      • +//
    +//     +// +// +// +// +// +// +// Holds the value for the control lines of each channel's LEDs +// for a particular ATR sate +// +// +// +// +// +// +// +// Describes led behavior for the different ATR states. When @.LED0_ATR_OPTION +// is set to use the DB states, TX and RX states for LED0-LED3 are +// combined to create a single vector. This creates 256 different +// combinations, each with its own register. When @.LED0_ATR_OPTION is set to +// classic ATR, the first 4 offsets in this register group will be driven +// in accordance with the state of RF0. +// CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1, +// TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1] +// +// +// +// +// +// Describes led behavior for the different ATR states. When @.LED1_ATR_OPTION +// is set to use the DB states, TX and RX states for LED0-LED3 are +// combined to create a single vector. This creates 256 different +// combinations, each with its own register. When @.LED1_ATR_OPTION is set to +// classic ATR, the first 4 offsets in this register group will be driven +// in accordance with the state of RF1. +// CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1, +// TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1] +// +// +// +// +// +// Describes led behavior for the different ATR states. When @.LED2_ATR_OPTION +// is set to use the DB states, TX and RX states for LED0-LED3 are +// combined to create a single vector. This creates 256 different +// combinations, each with its own register. When @.LED2_ATR_OPTION is set to +// classic ATR, the first 4 offsets in this register group will be driven +// in accordance with the state of RF2. +// CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1, +// TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1] +// +// +// +// +// +// Describes led behavior for the different ATR states. When @.LED3_ATR_OPTION +// is set to use the DB states, TX and RX states for LED0-LED3 are +// combined to create a single vector. This creates 256 different +// combinations, each with its own register. When @.LED3_ATR_OPTION is set to +// classic ATR, the first 4 offsets in this register group will be driven +// in accordance with the state of RF3. +// CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1, +// TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1] +// +// +// +// +// Controls whether switch control lines use the TX and RX state of +// their respective channel (Classic ATR) or the daughterboard state +// to select which state to use from values set in LED_ATR_STATE registers. +// For each particular bit:
    +// 0: Use DB state for ATR
    +// 1: Classic ATR mode. +//     +// +// +// Control ATR scheme for RF0. +// +// +// +// +// Control ATR scheme for RF1. +// +// +// +// +// Control ATR scheme for RF2. +// +// +// +// +// Control ATR scheme for RF3. +// +// +//     +// +// +// Disable ATR Control. DB state 0 will be reflected regardless of the ATR state. +// +// +// +// +// +// +//     +//     +//XmlParse xml_off + + +`default_nettype wire diff --git a/top/x400/cpld/regmap/constants_regmap_utils.vh b/top/x400/dboards/fbx/regmap/clock_en_regmap_utils.vh similarity index 60% rename from top/x400/cpld/regmap/constants_regmap_utils.vh rename to top/x400/dboards/fbx/regmap/clock_en_regmap_utils.vh index 374a104..c520aba 100644 --- a/top/x400/cpld/regmap/constants_regmap_utils.vh +++ b/top/x400/dboards/fbx/regmap/clock_en_regmap_utils.vh @@ -3,7 +3,7 @@ // // SPDX-License-Identifier: LGPL-3.0-or-later // -// Module: constants_regmap_utils.vh +// Module: clock_en_regmap_utils.vh // Description: // The constants in this file are autogenerated by XmlParse. @@ -11,18 +11,20 @@ // A numerically ordered list of registers and their HDL source files //=============================================================================== + // CLK_EN_CONTROL : 0x0 (clock_en_control.v) //=============================================================================== // RegTypes //=============================================================================== //=============================================================================== -// Register Group CONSTANTS_GROUP +// Register Group CLOCK_EN_REGISTERS //=============================================================================== - // Enumerated type CONSTANTS_ENUM - localparam CONSTANTS_ENUM_SIZE = 4; - localparam PS_CPLD_SIGNATURE = 'hA522D27; // CONSTANTS_ENUM:PS_CPLD_SIGNATURE - localparam OLDEST_CPLD_REVISION = 'h20122114; // CONSTANTS_ENUM:OLDEST_CPLD_REVISION - localparam CPLD_REVISION = 'h21111615; // CONSTANTS_ENUM:CPLD_REVISION - localparam PL_CPLD_SIGNATURE = 'h3FDC5C47; // CONSTANTS_ENUM:PL_CPLD_SIGNATURE + // CLK_EN_CONTROL Register (from clock_en_control.v) + localparam CLK_EN_CONTROL = 'h0; // Register Offset + localparam CLK_EN_CONTROL_SIZE = 32; // register width in bits + localparam CLK_EN_CONTROL_MASK = 32'h1; + localparam CLK_EN_SIZE = 1; //CLK_EN_CONTROL:CLK_EN + localparam CLK_EN_MSB = 0; //CLK_EN_CONTROL:CLK_EN + localparam CLK_EN = 0; //CLK_EN_CONTROL:CLK_EN diff --git a/top/x400/dboards/fbx/regmap/fbx_ctrl_regmap_utils.vh b/top/x400/dboards/fbx/regmap/fbx_ctrl_regmap_utils.vh new file mode 100644 index 0000000..ad480b0 --- /dev/null +++ b/top/x400/dboards/fbx/regmap/fbx_ctrl_regmap_utils.vh @@ -0,0 +1,41 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: fbx_ctrl_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // RF_ATR_REGS : 0x0 (db_gpio_interface.v) + // RF_SYNC_REGS : 0x2000 (db_gpio_interface.v) + // LED_ATR_REGS : 0x4000 (db_gpio_interface.v) + // SYNC_CLK_EN_REGS : 0x6000 (db_gpio_interface.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group FBX_CONTROLS +//=============================================================================== + + // RF_ATR_REGS Window (from db_gpio_interface.v) + localparam RF_ATR_REGS = 'h0; // Window Offset + localparam RF_ATR_REGS_SIZE = 'h2000; // size in bytes + + // RF_SYNC_REGS Window (from db_gpio_interface.v) + localparam RF_SYNC_REGS = 'h2000; // Window Offset + localparam RF_SYNC_REGS_SIZE = 'h2000; // size in bytes + + // LED_ATR_REGS Window (from db_gpio_interface.v) + localparam LED_ATR_REGS = 'h4000; // Window Offset + localparam LED_ATR_REGS_SIZE = 'h2000; // size in bytes + + // SYNC_CLK_EN_REGS Window (from db_gpio_interface.v) + localparam SYNC_CLK_EN_REGS = 'h6000; // Window Offset + localparam SYNC_CLK_EN_REGS_SIZE = 'h2000; // size in bytes diff --git a/top/x400/dboards/fbx/regmap/led_atr_regmap_utils.vh b/top/x400/dboards/fbx/regmap/led_atr_regmap_utils.vh new file mode 100644 index 0000000..383b615 --- /dev/null +++ b/top/x400/dboards/fbx/regmap/led_atr_regmap_utils.vh @@ -0,0 +1,110 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: led_atr_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // LED0_ATR_STATE : 0x0 (led_atr_control.v) + // LED1_ATR_STATE : 0x400 (led_atr_control.v) + // LED2_ATR_STATE : 0x800 (led_atr_control.v) + // LED3_ATR_STATE : 0xC00 (led_atr_control.v) + // LED_ATR_OPTION_REGISTER : 0x1000 (led_atr_control.v) + // LED_ATR_DISABLED : 0x1004 (led_atr_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // LED_ATR_STATE Type (from led_atr_control.v) + localparam LED_ATR_STATE_SIZE = 32; + localparam LED_ATR_STATE_MASK = 32'h7; + localparam RX2_LED_SIZE = 1; //LED_ATR_STATE:RX2_LED + localparam RX2_LED_MSB = 0; //LED_ATR_STATE:RX2_LED + localparam RX2_LED = 0; //LED_ATR_STATE:RX2_LED + localparam TXRX_RED_LED_SIZE = 1; //LED_ATR_STATE:TXRX_RED_LED + localparam TXRX_RED_LED_MSB = 1; //LED_ATR_STATE:TXRX_RED_LED + localparam TXRX_RED_LED = 1; //LED_ATR_STATE:TXRX_RED_LED + localparam TXRX_GR_LED_SIZE = 1; //LED_ATR_STATE:TXRX_GR_LED + localparam TXRX_GR_LED_MSB = 2; //LED_ATR_STATE:TXRX_GR_LED + localparam TXRX_GR_LED = 2; //LED_ATR_STATE:TXRX_GR_LED + +//=============================================================================== +// Register Group LED_ATR_REGISTERS +//=============================================================================== + + // Enumerated type LED_SIZE_TYPE + localparam LED_SIZE_TYPE_SIZE = 1; + localparam LED_SIZE = 'h3; // LED_SIZE_TYPE:LED_SIZE + + // LED0_ATR_STATE Register (from led_atr_control.v) + localparam LED0_ATR_STATE_COUNT = 256; // Number of elements in array + + // LED1_ATR_STATE Register (from led_atr_control.v) + localparam LED1_ATR_STATE_COUNT = 256; // Number of elements in array + + // LED2_ATR_STATE Register (from led_atr_control.v) + localparam LED2_ATR_STATE_COUNT = 256; // Number of elements in array + + // LED3_ATR_STATE Register (from led_atr_control.v) + localparam LED3_ATR_STATE_COUNT = 256; // Number of elements in array + + // LED_ATR_OPTION_REGISTER Register (from led_atr_control.v) + localparam LED_ATR_OPTION_REGISTER = 'h1000; // Register Offset + localparam LED_ATR_OPTION_REGISTER_SIZE = 32; // register width in bits + localparam LED_ATR_OPTION_REGISTER_MASK = 32'hF; + localparam LED0_ATR_OPTION_SIZE = 1; //LED_ATR_OPTION_REGISTER:LED0_ATR_OPTION + localparam LED0_ATR_OPTION_MSB = 0; //LED_ATR_OPTION_REGISTER:LED0_ATR_OPTION + localparam LED0_ATR_OPTION = 0; //LED_ATR_OPTION_REGISTER:LED0_ATR_OPTION + localparam LED1_ATR_OPTION_SIZE = 1; //LED_ATR_OPTION_REGISTER:LED1_ATR_OPTION + localparam LED1_ATR_OPTION_MSB = 1; //LED_ATR_OPTION_REGISTER:LED1_ATR_OPTION + localparam LED1_ATR_OPTION = 1; //LED_ATR_OPTION_REGISTER:LED1_ATR_OPTION + localparam LED2_ATR_OPTION_SIZE = 1; //LED_ATR_OPTION_REGISTER:LED2_ATR_OPTION + localparam LED2_ATR_OPTION_MSB = 2; //LED_ATR_OPTION_REGISTER:LED2_ATR_OPTION + localparam LED2_ATR_OPTION = 2; //LED_ATR_OPTION_REGISTER:LED2_ATR_OPTION + localparam LED3_ATR_OPTION_SIZE = 1; //LED_ATR_OPTION_REGISTER:LED3_ATR_OPTION + localparam LED3_ATR_OPTION_MSB = 3; //LED_ATR_OPTION_REGISTER:LED3_ATR_OPTION + localparam LED3_ATR_OPTION = 3; //LED_ATR_OPTION_REGISTER:LED3_ATR_OPTION + + // LED_ATR_DISABLED Register (from led_atr_control.v) + localparam LED_ATR_DISABLED = 'h1004; // Register Offset + localparam LED_ATR_DISABLED_SIZE = 32; // register width in bits + localparam LED_ATR_DISABLED_MASK = 32'hF; + localparam LED0_ATR_DISABLED_SIZE = 1; //LED_ATR_DISABLED:LED0_ATR_DISABLED + localparam LED0_ATR_DISABLED_MSB = 0; //LED_ATR_DISABLED:LED0_ATR_DISABLED + localparam LED0_ATR_DISABLED = 0; //LED_ATR_DISABLED:LED0_ATR_DISABLED + localparam LED1_ATR_DISABLED_SIZE = 1; //LED_ATR_DISABLED:LED1_ATR_DISABLED + localparam LED1_ATR_DISABLED_MSB = 1; //LED_ATR_DISABLED:LED1_ATR_DISABLED + localparam LED1_ATR_DISABLED = 1; //LED_ATR_DISABLED:LED1_ATR_DISABLED + localparam LED2_ATR_DISABLED_SIZE = 1; //LED_ATR_DISABLED:LED2_ATR_DISABLED + localparam LED2_ATR_DISABLED_MSB = 2; //LED_ATR_DISABLED:LED2_ATR_DISABLED + localparam LED2_ATR_DISABLED = 2; //LED_ATR_DISABLED:LED2_ATR_DISABLED + localparam LED3_ATR_DISABLED_SIZE = 1; //LED_ATR_DISABLED:LED3_ATR_DISABLED + localparam LED3_ATR_DISABLED_MSB = 3; //LED_ATR_DISABLED:LED3_ATR_DISABLED + localparam LED3_ATR_DISABLED = 3; //LED_ATR_DISABLED:LED3_ATR_DISABLED + + // Return the offset of an element of register array LED0_ATR_STATE + function integer LED0_ATR_STATE (input integer i); + LED0_ATR_STATE = (i * 'h4) + 'h0; + endfunction + + // Return the offset of an element of register array LED1_ATR_STATE + function integer LED1_ATR_STATE (input integer i); + LED1_ATR_STATE = (i * 'h4) + 'h400; + endfunction + + // Return the offset of an element of register array LED2_ATR_STATE + function integer LED2_ATR_STATE (input integer i); + LED2_ATR_STATE = (i * 'h4) + 'h800; + endfunction + + // Return the offset of an element of register array LED3_ATR_STATE + function integer LED3_ATR_STATE (input integer i); + LED3_ATR_STATE = (i * 'h4) + 'hC00; + endfunction diff --git a/top/x400/dboards/fbx/regmap/rf_atr_regmap_utils.vh b/top/x400/dboards/fbx/regmap/rf_atr_regmap_utils.vh new file mode 100644 index 0000000..7cb7a77 --- /dev/null +++ b/top/x400/dboards/fbx/regmap/rf_atr_regmap_utils.vh @@ -0,0 +1,110 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rf_atr_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // RF0_ATR_STATE : 0x0 (rf_atr_control.v) + // RF1_ATR_STATE : 0x400 (rf_atr_control.v) + // RF2_ATR_STATE : 0x800 (rf_atr_control.v) + // RF3_ATR_STATE : 0xC00 (rf_atr_control.v) + // ATR_OPTION_REGISTER : 0x1000 (rf_atr_control.v) + // RF_ATR_DISABLED : 0x1004 (rf_atr_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // RF_ATR_STATE Type (from rf_atr_control.v) + localparam RF_ATR_STATE_SIZE = 32; + localparam RF_ATR_STATE_MASK = 32'h7; + localparam TX_RX_RFS_SIZE = 1; //RF_ATR_STATE:TX_RX_RFS + localparam TX_RX_RFS_MSB = 0; //RF_ATR_STATE:TX_RX_RFS + localparam TX_RX_RFS = 0; //RF_ATR_STATE:TX_RX_RFS + localparam RX_RFS_SIZE = 1; //RF_ATR_STATE:RX_RFS + localparam RX_RFS_MSB = 1; //RF_ATR_STATE:RX_RFS + localparam RX_RFS = 1; //RF_ATR_STATE:RX_RFS + localparam TDDS_SIZE = 1; //RF_ATR_STATE:TDDS + localparam TDDS_MSB = 2; //RF_ATR_STATE:TDDS + localparam TDDS = 2; //RF_ATR_STATE:TDDS + +//=============================================================================== +// Register Group RF_ATR_REGISTERS +//=============================================================================== + + // Enumerated type RF_SWITCHES_SIZE_TYPE + localparam RF_SWITCHES_SIZE_TYPE_SIZE = 1; + localparam RFS_SIZE = 'h3; // RF_SWITCHES_SIZE_TYPE:RFS_SIZE + + // RF0_ATR_STATE Register (from rf_atr_control.v) + localparam RF0_ATR_STATE_COUNT = 256; // Number of elements in array + + // RF1_ATR_STATE Register (from rf_atr_control.v) + localparam RF1_ATR_STATE_COUNT = 256; // Number of elements in array + + // RF2_ATR_STATE Register (from rf_atr_control.v) + localparam RF2_ATR_STATE_COUNT = 256; // Number of elements in array + + // RF3_ATR_STATE Register (from rf_atr_control.v) + localparam RF3_ATR_STATE_COUNT = 256; // Number of elements in array + + // ATR_OPTION_REGISTER Register (from rf_atr_control.v) + localparam ATR_OPTION_REGISTER = 'h1000; // Register Offset + localparam ATR_OPTION_REGISTER_SIZE = 32; // register width in bits + localparam ATR_OPTION_REGISTER_MASK = 32'hF; + localparam RF0_ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTER:RF0_ATR_OPTION + localparam RF0_ATR_OPTION_MSB = 0; //ATR_OPTION_REGISTER:RF0_ATR_OPTION + localparam RF0_ATR_OPTION = 0; //ATR_OPTION_REGISTER:RF0_ATR_OPTION + localparam RF1_ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTER:RF1_ATR_OPTION + localparam RF1_ATR_OPTION_MSB = 1; //ATR_OPTION_REGISTER:RF1_ATR_OPTION + localparam RF1_ATR_OPTION = 1; //ATR_OPTION_REGISTER:RF1_ATR_OPTION + localparam RF2_ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTER:RF2_ATR_OPTION + localparam RF2_ATR_OPTION_MSB = 2; //ATR_OPTION_REGISTER:RF2_ATR_OPTION + localparam RF2_ATR_OPTION = 2; //ATR_OPTION_REGISTER:RF2_ATR_OPTION + localparam RF3_ATR_OPTION_SIZE = 1; //ATR_OPTION_REGISTER:RF3_ATR_OPTION + localparam RF3_ATR_OPTION_MSB = 3; //ATR_OPTION_REGISTER:RF3_ATR_OPTION + localparam RF3_ATR_OPTION = 3; //ATR_OPTION_REGISTER:RF3_ATR_OPTION + + // RF_ATR_DISABLED Register (from rf_atr_control.v) + localparam RF_ATR_DISABLED = 'h1004; // Register Offset + localparam RF_ATR_DISABLED_SIZE = 32; // register width in bits + localparam RF_ATR_DISABLED_MASK = 32'hF; + localparam RF0_ATR_DISABLED_SIZE = 1; //RF_ATR_DISABLED:RF0_ATR_DISABLED + localparam RF0_ATR_DISABLED_MSB = 0; //RF_ATR_DISABLED:RF0_ATR_DISABLED + localparam RF0_ATR_DISABLED = 0; //RF_ATR_DISABLED:RF0_ATR_DISABLED + localparam RF1_ATR_DISABLED_SIZE = 1; //RF_ATR_DISABLED:RF1_ATR_DISABLED + localparam RF1_ATR_DISABLED_MSB = 1; //RF_ATR_DISABLED:RF1_ATR_DISABLED + localparam RF1_ATR_DISABLED = 1; //RF_ATR_DISABLED:RF1_ATR_DISABLED + localparam RF2_ATR_DISABLED_SIZE = 1; //RF_ATR_DISABLED:RF2_ATR_DISABLED + localparam RF2_ATR_DISABLED_MSB = 2; //RF_ATR_DISABLED:RF2_ATR_DISABLED + localparam RF2_ATR_DISABLED = 2; //RF_ATR_DISABLED:RF2_ATR_DISABLED + localparam RF3_ATR_DISABLED_SIZE = 1; //RF_ATR_DISABLED:RF3_ATR_DISABLED + localparam RF3_ATR_DISABLED_MSB = 3; //RF_ATR_DISABLED:RF3_ATR_DISABLED + localparam RF3_ATR_DISABLED = 3; //RF_ATR_DISABLED:RF3_ATR_DISABLED + + // Return the offset of an element of register array RF0_ATR_STATE + function integer RF0_ATR_STATE (input integer i); + RF0_ATR_STATE = (i * 'h4) + 'h0; + endfunction + + // Return the offset of an element of register array RF1_ATR_STATE + function integer RF1_ATR_STATE (input integer i); + RF1_ATR_STATE = (i * 'h4) + 'h400; + endfunction + + // Return the offset of an element of register array RF2_ATR_STATE + function integer RF2_ATR_STATE (input integer i); + RF2_ATR_STATE = (i * 'h4) + 'h800; + endfunction + + // Return the offset of an element of register array RF3_ATR_STATE + function integer RF3_ATR_STATE (input integer i); + RF3_ATR_STATE = (i * 'h4) + 'hC00; + endfunction diff --git a/top/x400/dboards/fbx/regmap/rf_sync_regmap_utils.vh b/top/x400/dboards/fbx/regmap/rf_sync_regmap_utils.vh new file mode 100644 index 0000000..e0f6698 --- /dev/null +++ b/top/x400/dboards/fbx/regmap/rf_sync_regmap_utils.vh @@ -0,0 +1,113 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rf_sync_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // SYNC_1_REG : 0x0 (ctrlport_to_i2c_sync_ctrl.v) + // SYNC_2_REG : 0x4 (ctrlport_to_i2c_sync_ctrl.v) + // SYNC_3_REG : 0x8 (ctrlport_to_i2c_sync_ctrl.v) + // SYNC_4_REG : 0xC (ctrlport_to_i2c_sync_ctrl.v) + // SYNC_5_REG : 0x10 (ctrlport_to_i2c_sync_ctrl.v) + // RFS_EN_REG : 0x14 (ctrlport_to_i2c_sync_ctrl.v) + // SETUP_REG/SETUP_STATUS_REG : 0x18 (ctrlport_to_i2c_sync_ctrl.v, ctrlport_to_i2c_sync_ctrl.v) + // CONFIG_IO_REG/CONFIG_IO_STATUS_REG : 0x1C (ctrlport_to_i2c_sync_ctrl.v, ctrlport_to_i2c_sync_ctrl.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // SYNC_SWITCH Type (from ctrlport_to_i2c_sync_ctrl.v) + localparam SYNC_SWITCH_SIZE = 32; + localparam SYNC_SWITCH_MASK = 32'h7; + localparam CONTROL_PIN_V1_SIZE = 1; //SYNC_SWITCH:CONTROL_PIN_V1 + localparam CONTROL_PIN_V1_MSB = 0; //SYNC_SWITCH:CONTROL_PIN_V1 + localparam CONTROL_PIN_V1 = 0; //SYNC_SWITCH:CONTROL_PIN_V1 + localparam CONTROL_PIN_V2_SIZE = 1; //SYNC_SWITCH:CONTROL_PIN_V2 + localparam CONTROL_PIN_V2_MSB = 1; //SYNC_SWITCH:CONTROL_PIN_V2 + localparam CONTROL_PIN_V2 = 1; //SYNC_SWITCH:CONTROL_PIN_V2 + localparam CONTROL_PIN_V3_SIZE = 1; //SYNC_SWITCH:CONTROL_PIN_V3 + localparam CONTROL_PIN_V3_MSB = 2; //SYNC_SWITCH:CONTROL_PIN_V3 + localparam CONTROL_PIN_V3 = 2; //SYNC_SWITCH:CONTROL_PIN_V3 + +//=============================================================================== +// Register Group RF_SYNC_REGISTERS +//=============================================================================== + + // Enumerated type IO_EXPANDER_REGISTER_ADRS + localparam IO_EXPANDER_REGISTER_ADRS_SIZE = 8; + localparam IO_EXP_INPUT_PORT0_REG = 'h0; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_INPUT_PORT0_REG + localparam IO_EXP_INPUT_PORT1_REG = 'h1; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_INPUT_PORT1_REG + localparam IO_EXP_OUTPUT_PORT0_REG = 'h2; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_OUTPUT_PORT0_REG + localparam IO_EXP_OUTPUT_PORT1_REG = 'h3; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_OUTPUT_PORT1_REG + localparam IO_EXP_POLARITY_INV0_REG = 'h4; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_POLARITY_INV0_REG + localparam IO_EXP_POLARITY_INV1_REG = 'h5; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_POLARITY_INV1_REG + localparam IO_EXP_CONFIG0_REG = 'h6; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_CONFIG0_REG + localparam IO_EXP_CONFIG1_REG = 'h7; // IO_EXPANDER_REGISTER_ADRS:IO_EXP_CONFIG1_REG + + // SYNC_1_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam SYNC_1_REG = 'h0; // Register Offset + localparam SYNC_1_REG_SIZE = 32; // register width in bits + + // SYNC_2_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam SYNC_2_REG = 'h4; // Register Offset + localparam SYNC_2_REG_SIZE = 32; // register width in bits + + // SYNC_3_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam SYNC_3_REG = 'h8; // Register Offset + localparam SYNC_3_REG_SIZE = 32; // register width in bits + + // SYNC_4_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam SYNC_4_REG = 'hC; // Register Offset + localparam SYNC_4_REG_SIZE = 32; // register width in bits + + // SYNC_5_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam SYNC_5_REG = 'h10; // Register Offset + localparam SYNC_5_REG_SIZE = 32; // register width in bits + + // RFS_EN_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam RFS_EN_REG = 'h14; // Register Offset + localparam RFS_EN_REG_SIZE = 32; // register width in bits + localparam RFS_EN_REG_MASK = 32'h1; + localparam RFS_EN_PIN_SIZE = 1; //RFS_EN_REG:RFS_EN_PIN + localparam RFS_EN_PIN_MSB = 0; //RFS_EN_REG:RFS_EN_PIN + localparam RFS_EN_PIN = 0; //RFS_EN_REG:RFS_EN_PIN + + // SETUP_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam SETUP_REG = 'h18; // Register Offset + localparam SETUP_REG_SIZE = 32; // register width in bits + localparam SETUP_REG_MASK = 32'h1; + localparam SETUP_TRIG_SIZE = 1; //SETUP_REG:SETUP_TRIG + localparam SETUP_TRIG_MSB = 0; //SETUP_REG:SETUP_TRIG + localparam SETUP_TRIG = 0; //SETUP_REG:SETUP_TRIG + + // SETUP_STATUS_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam SETUP_STATUS_REG = 'h18; // Register Offset + localparam SETUP_STATUS_REG_SIZE = 32; // register width in bits + localparam SETUP_STATUS_REG_MASK = 32'h1; + localparam SETUP_STATUS_SIZE = 1; //SETUP_STATUS_REG:SETUP_STATUS + localparam SETUP_STATUS_MSB = 0; //SETUP_STATUS_REG:SETUP_STATUS + localparam SETUP_STATUS = 0; //SETUP_STATUS_REG:SETUP_STATUS + + // CONFIG_IO_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam CONFIG_IO_REG = 'h1C; // Register Offset + localparam CONFIG_IO_REG_SIZE = 32; // register width in bits + localparam CONFIG_IO_REG_MASK = 32'h1; + localparam CONFIG_IO_TRIG_SIZE = 1; //CONFIG_IO_REG:CONFIG_IO_TRIG + localparam CONFIG_IO_TRIG_MSB = 0; //CONFIG_IO_REG:CONFIG_IO_TRIG + localparam CONFIG_IO_TRIG = 0; //CONFIG_IO_REG:CONFIG_IO_TRIG + + // CONFIG_IO_STATUS_REG Register (from ctrlport_to_i2c_sync_ctrl.v) + localparam CONFIG_IO_STATUS_REG = 'h1C; // Register Offset + localparam CONFIG_IO_STATUS_REG_SIZE = 32; // register width in bits + localparam CONFIG_IO_STATUS_REG_MASK = 32'h1; + localparam CONFIG_IO_STATUS_SIZE = 1; //CONFIG_IO_STATUS_REG:CONFIG_IO_STATUS + localparam CONFIG_IO_STATUS_MSB = 0; //CONFIG_IO_STATUS_REG:CONFIG_IO_STATUS + localparam CONFIG_IO_STATUS = 0; //CONFIG_IO_STATUS_REG:CONFIG_IO_STATUS diff --git a/top/x400/dboards/fbx/rf_atr_control.v b/top/x400/dboards/fbx/rf_atr_control.v new file mode 100644 index 0000000..8358a9a --- /dev/null +++ b/top/x400/dboards/fbx/rf_atr_control.v @@ -0,0 +1,519 @@ +// +// Copyright 2022 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rf_atr_control +// +// Description: +// +// Implements control over RF switches via CtrlPort. Uses RAM to store multiple +// ATR configurations. +// There are three supported control schemes for these switches: +// - ATR Disabled - Single persistent state. +// - Classic ATR - Each channel's switches depend on the transmission state +// of the respective channel. +// - DB State - Each channel's switches depend on the transmission state +// of all channels in this radio. +// +// Parameters: +// +// REG_BASE : Base address to use for registers. +// REG_SIZE : Register space size. +// + +module rf_atr_control #( + parameter REG_BASE = 0, + parameter REG_SIZE = 'h2000 +) ( + // Slave ctrlport interface + input wire ctrlport_clk, + input wire ctrlport_rst, + input wire s_ctrlport_req_wr, + input wire s_ctrlport_req_rd, + input wire [19:0] s_ctrlport_req_addr, + input wire [31:0] s_ctrlport_req_data, + output reg s_ctrlport_resp_ack = 1'b0, + output reg [ 1:0] s_ctrlport_resp_status = 2'b00, + output reg [31:0] s_ctrlport_resp_data = {32 {1'b0}}, + // Run state signals that indicate tx and rx operation + input wire [7:0] db_state, + // Switch control outputs + output reg rf0_tx_rx_rfs, + output reg rf0_rx_rfs, + output reg rf0_tdds, + output reg rf1_tx_rx_rfs, + output reg rf1_rx_rfs, + output reg rf1_tdds, + output reg rf2_tx_rx_rfs, + output reg rf2_rx_rfs, + output reg rf2_tdds, + output reg rf3_tx_rx_rfs, + output reg rf3_rx_rfs, + output reg rf3_tdds +); + + `include "../../../../lib/rfnoc/core/ctrlport.vh" + `include "regmap/rf_atr_regmap_utils.vh" + + //--------------------------------------------------------------- + // ATR memory signals + //--------------------------------------------------------------- + reg ram_rf0_wea; + wire [RFS_SIZE-1:0] ram_rf0_doa; + wire [RFS_SIZE-1:0] ram_rf0_dob; + + reg ram_rf1_wea; + wire [RFS_SIZE-1:0] ram_rf1_doa; + wire [RFS_SIZE-1:0] ram_rf1_dob; + + reg ram_rf2_wea; + wire [RFS_SIZE-1:0] ram_rf2_doa; + wire [RFS_SIZE-1:0] ram_rf2_dob; + + reg ram_rf3_wea; + wire [RFS_SIZE-1:0] ram_rf3_doa; + wire [RFS_SIZE-1:0] ram_rf3_dob; + + + //--------------------------------------------------------------- + // ATR Scheme signals + //--------------------------------------------------------------- + reg [3:0] atr_disable = 4'b0; + + // DB state/Classic ATR selector + reg [3:0] atr_mode = 4'b0; + + //--------------------------------------------------------------------------- + // Control interface handling + //--------------------------------------------------------------------------- + + // Check that address is within this module's range. + wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE); + + // Check that address is targeting an ATR state. + wire address_is_atr = (s_ctrlport_req_addr >= REG_BASE + RF0_ATR_STATE(0)) && (s_ctrlport_req_addr <= REG_BASE + RF3_ATR_STATE(RF3_ATR_STATE_COUNT-1)); + + // Read request shift register to align memory read and response generation. + reg [ 1:0] read_req_shift_reg = 2'b0; + // Mask out 8 bits for ATR configurations to be able to compare all ATR + // configurations against the same base register address. + wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]}; + // Decode the ATR state being addressed. + wire [ 7:0] atr_address = s_ctrlport_req_addr[9:2]; + + always @ (posedge ctrlport_clk) begin + if (ctrlport_rst) begin + s_ctrlport_resp_ack <= 1'b0; + s_ctrlport_resp_data <= 32'b0; + s_ctrlport_resp_status <= 2'b00; + + atr_disable <= 4'b0; + atr_mode <= 4'b0; + + ram_rf0_wea <= 1'b0; + ram_rf1_wea <= 1'b0; + ram_rf2_wea <= 1'b0; + ram_rf3_wea <= 1'b0; + + end else begin + // default assignments + read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd}; + + ram_rf0_wea <= 1'b0; + ram_rf1_wea <= 1'b0; + ram_rf2_wea <= 1'b0; + ram_rf3_wea <= 1'b0; + + // Write registers + if (s_ctrlport_req_wr) begin + // Acknowledge by default + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + // Address ATR state writes + if(address_is_atr) begin + + case (register_base_address) + REG_BASE + RF0_ATR_STATE(0): begin + ram_rf0_wea <= 1'b1; + end + + REG_BASE + RF1_ATR_STATE(0): begin + ram_rf1_wea <= 1'b1; + end + + REG_BASE + RF2_ATR_STATE(0): begin + ram_rf2_wea <= 1'b1; + end + + REG_BASE + RF3_ATR_STATE(0): begin + ram_rf3_wea <= 1'b1; + end + + // error on undefined address + default: begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + end + endcase + end else begin + + // Address writes to the rest of the register space + case (s_ctrlport_req_addr) + + REG_BASE + ATR_OPTION_REGISTER: begin + atr_mode[0] <= s_ctrlport_req_data[RF0_ATR_OPTION]; + atr_mode[1] <= s_ctrlport_req_data[RF1_ATR_OPTION]; + atr_mode[2] <= s_ctrlport_req_data[RF2_ATR_OPTION]; + atr_mode[3] <= s_ctrlport_req_data[RF3_ATR_OPTION]; + end + + REG_BASE + RF_ATR_DISABLED: begin + atr_disable[0] <= s_ctrlport_req_data[RF0_ATR_DISABLED]; + atr_disable[1] <= s_ctrlport_req_data[RF1_ATR_DISABLED]; + atr_disable[2] <= s_ctrlport_req_data[RF2_ATR_DISABLED]; + atr_disable[3] <= s_ctrlport_req_data[RF3_ATR_DISABLED]; + end + + // No register implementation for provided address + default: begin + // Acknowledge and provide error status if address is in range + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // No response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + end + + // Read registers + end else if (read_req_shift_reg[1]) begin + // Acknowledge by default + s_ctrlport_resp_ack <= 1'b1; + s_ctrlport_resp_status <= CTRL_STS_OKAY; + + // Address ATR state reads + if(address_is_atr) begin + + case (register_base_address) + REG_BASE + RF0_ATR_STATE(0): begin + s_ctrlport_resp_data <= ram_rf0_doa & RF_ATR_STATE_MASK; + end + REG_BASE + RF1_ATR_STATE(0): begin + s_ctrlport_resp_data <= ram_rf1_doa & RF_ATR_STATE_MASK; + end + REG_BASE + RF2_ATR_STATE(0): begin + s_ctrlport_resp_data <= ram_rf2_doa & RF_ATR_STATE_MASK; + end + REG_BASE + RF3_ATR_STATE(0): begin + s_ctrlport_resp_data <= ram_rf3_doa & RF_ATR_STATE_MASK; + end + + default: begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + end + endcase + + end else begin + + // Address reads to the rest of the register space + case (s_ctrlport_req_addr) + + REG_BASE + ATR_OPTION_REGISTER: begin + s_ctrlport_resp_data[RF0_ATR_OPTION] <= atr_mode[0]; + s_ctrlport_resp_data[RF1_ATR_OPTION] <= atr_mode[1]; + s_ctrlport_resp_data[RF2_ATR_OPTION] <= atr_mode[2]; + s_ctrlport_resp_data[RF3_ATR_OPTION] <= atr_mode[3]; + end + + REG_BASE + RF_ATR_DISABLED: begin + s_ctrlport_resp_data[RF0_ATR_DISABLED] <= atr_disable[0]; + s_ctrlport_resp_data[RF1_ATR_DISABLED] <= atr_disable[1]; + s_ctrlport_resp_data[RF2_ATR_DISABLED] <= atr_disable[2]; + s_ctrlport_resp_data[RF3_ATR_DISABLED] <= atr_disable[3]; + end + + // No register implementation for provided address + default: begin + // Acknowledge and provide error status if address is in range + if (address_in_range) begin + s_ctrlport_resp_status <= CTRL_STS_CMDERR; + + // No response if out of range + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + endcase + end + + end else begin + s_ctrlport_resp_ack <= 1'b0; + end + end + end + + // register without reset + reg [ 7:0] ram_addr = 8'b0; + reg [RFS_SIZE-1:0] ram_datain = {RFS_SIZE{1'b0}}; + always @(posedge ctrlport_clk) begin + // memories + ram_addr <= atr_address; + ram_datain <= s_ctrlport_req_data[RFS_SIZE-1:0]; + end + + // ATR Scheme selection + reg [7:0] atr_config_rf [3:0]; + + generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin: read_address_gen + + always @(posedge ctrlport_clk) begin + if (atr_disable[i]) begin + atr_config_rf[i] <= 8'b0; + end else begin + if (atr_mode[i]) begin + atr_config_rf[i] <= {6'b0, db_state[2*i+:2]}; + end else begin + atr_config_rf[i] <= db_state; + end + end + end + + end + endgenerate + + + // Output decoding + always @(posedge ctrlport_clk) begin + rf0_tx_rx_rfs <= ram_rf0_dob[TX_RX_RFS]; + rf0_rx_rfs <= ram_rf0_dob[RX_RFS]; + rf0_tdds <= ram_rf0_dob[TDDS]; + + rf1_tx_rx_rfs <= ram_rf1_dob[TX_RX_RFS]; + rf1_rx_rfs <= ram_rf1_dob[RX_RFS]; + rf1_tdds <= ram_rf1_dob[TDDS]; + + rf2_tx_rx_rfs <= ram_rf2_dob[TX_RX_RFS]; + rf2_rx_rfs <= ram_rf2_dob[RX_RFS]; + rf2_tdds <= ram_rf2_dob[TDDS]; + + rf3_tx_rx_rfs <= ram_rf3_dob[TX_RX_RFS]; + rf3_rx_rfs <= ram_rf3_dob[RX_RFS]; + rf3_tdds <= ram_rf3_dob[TDDS]; + end + + + //--------------------------------------------------------------- + // ATR memory + //--------------------------------------------------------------- + ram_2port #( + .DWIDTH (RFS_SIZE), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0) + ) ram_rf0_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_rf0_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_rf0_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf[0]), + .dib ({RFS_SIZE{1'b0}}), + .dob (ram_rf0_dob)); + + ram_2port #( + .DWIDTH (RFS_SIZE), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0) + ) ram_rf1_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_rf1_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_rf1_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf[1]), + .dib ({RFS_SIZE{1'b0}}), + .dob (ram_rf1_dob)); + + ram_2port #( + .DWIDTH (RFS_SIZE), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0) + ) ram_rf2_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_rf2_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_rf2_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf[2]), + .dib ({RFS_SIZE{1'b0}}), + .dob (ram_rf2_dob)); + + ram_2port #( + .DWIDTH (RFS_SIZE), + .AWIDTH (8), + .RW_MODE ("READ-FIRST"), + .RAM_TYPE ("AUTOMATIC"), + .OUT_REG (0) + ) ram_rf3_i ( + .clka (ctrlport_clk), + .ena (1'b1), + .wea (ram_rf3_wea), + .addra (ram_addr), + .dia (ram_datain), + .doa (ram_rf3_doa), + .clkb (ctrlport_clk), + .enb (1'b1), + .web (1'b0), + .addrb (atr_config_rf[3]), + .dib ({RFS_SIZE{1'b0}}), + .dob (ram_rf3_dob)); + +endmodule + +//XmlParse xml_on +// +// +// +// Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1 +// switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for +// all four switches are not considered time critical controls, and are hence driven by an I/O +// expander controlled via I2C. +// This register map describes how to control the behavior of the 3 HMC849A switches' control lines. +// There are three supported control schemes for these switches:
    +//
      +//
    • ATR Disabled - Single persistent state.
      • +//
    • Classic ATR - Each channel's switches depend on the transmission state +// of the respective channel.
      • +//
    • DB State - Each channel's switches depend on the transmission state +// of all channels in this radio.
      • +//
    +//     +// +// +// +// +// +// +// Holds the value for the control lines of each channel's switches +// for a particular ATR sate +// +// +// +// +// +// +// +// Describes switch control behavior for the different ATR states. When @.RF0_ATR_OPTION +// is set to use the DB states, TX and RX states for RF0-RF3 are +// combined to create a single vector. This creates 256 different +// combinations, each with its own register. When @.RF0_ATR_OPTION is set to +// classic ATR, the first 4 offsets in this register group will be driven +// in accordance with the state of RF0. +// CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1, +// TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1] +// +// +// +// +// +// Describes switch control behavior for the different ATR states. When @.RF1_ATR_OPTION +// is set to use the DB states, TX and RX states for RF0-RF3 are +// combined to create a single vector. This creates 256 different +// combinations, each with its own register. When @.RF1_ATR_OPTION is set to +// classic ATR, the first 4 offsets in this register group will be driven +// in accordance with the state of RF1. +// CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1, +// TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1] +// +// +// +// +// +// Describes switch control behavior for the different ATR states. When @.RF2_ATR_OPTION +// is set to use the DB states, TX and RX states for RF0-RF3 are +// combined to create a single vector. This creates 256 different +// combinations, each with its own register. When @.RF2_ATR_OPTION is set to +// classic ATR, the first 4 offsets in this register group will be driven +// in accordance with the state of RF2. +// CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1, +// TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1] +// +// +// +// +// +// Describes switch control behavior for the different ATR states. When @.RF3_ATR_OPTION +// is set to use the DB states, TX and RX states for RF0-RF3 are +// combined to create a single vector. This creates 256 different +// combinations, each with its own register. When @.RF3_ATR_OPTION is set to +// classic ATR, the first 4 offsets in this register group will be driven +// in accordance with the state of RF3. +// CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1, +// TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1] +// +// +// +// +// Controls whether switch control lines use the TX and RX state of +// their respective channel (Classic ATR) or the daughterboard state +// to select which state to use from values set in RF_ATR_STATE registers. +// For each particular bit:
    +// 0: Use DB state for ATR
    +// 1: Classic ATR mode. +//     +// +// +// Control ATR scheme for RF0. +// +// +// +// +// Control ATR scheme for RF1. +// +// +// +// +// Control ATR scheme for RF2. +// +// +// +// +// Control ATR scheme for RF3. +// +// +//     +// +// +// Disable ATR Control. DB state 0 will be reflected regardless of the ATR state. +// +// +// +// +// +// +//     +//     +//XmlParse xml_off diff --git a/top/x400/dboards/fbx/sim/clock_en_control/Makefile b/top/x400/dboards/fbx/sim/clock_en_control/Makefile new file mode 100644 index 0000000..4d1533c --- /dev/null +++ b/top/x400/dboards/fbx/sim/clock_en_control/Makefile @@ -0,0 +1,74 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir. +BASE_DIR = ../../../../.. +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynquplusRFSOC +PART_ID = xczu28dr/ffvg1517/-1/e + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/control/Makefile.srcs + + +DESIGN_SRCS += $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +$(WISHBONE_SRCS) \ +) + + +DESIGN_SRCS += $(abspath \ +../../regmap/fbx_ctrl_regmap_utils.vh \ +../../regmap/clock_en_regmap_utils.vh \ +../../clock_en_control.v \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = $(BASE_DIR)/x400/ip +LIB_IP_DIR = $(BASE_DIR)/../lib/ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +# +# These TBs don't use any IP yet :) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +include $(BASE_DIR)/../sim/general/Makefile.srcs + +# Define only one top-level module +SIM_TOP = clock_en_control_tb glbl + +# Simulation runtime in microseconds +SIM_RUNTIME_US = 100000 + +SIM_SRCS = \ +$(abspath clock_en_control_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/top/x400/dboards/fbx/sim/clock_en_control/clock_en_control_tb.sv b/top/x400/dboards/fbx/sim/clock_en_control/clock_en_control_tb.sv new file mode 100644 index 0000000..a46d0b4 --- /dev/null +++ b/top/x400/dboards/fbx/sim/clock_en_control/clock_en_control_tb.sv @@ -0,0 +1,172 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: clock_en_control_tb +// +// Description: +// Testbench for clock_en_control and clock_div modules. Tasks defined for ctrlport write and +// read transactions. Tests clock enable control with ctrlport reads and writes. +// +`timescale 1ns / 1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 4 +`include "sim_exec_report.vh" +`include "sim_clks_rsts.vh" + + +module clock_en_control_tb(); + import PkgRandom::*; + PkgRandom::Rand #(5) rand_clk_count; + `TEST_BENCH_INIT("clock_en_control_tb", `NUM_TEST_CASES, `NS_PER_TICK); + //sets up clock + localparam CLK_PERIOD = $ceil(1e9/50.0e6); + localparam CLK_PERIOD_10 = $ceil(1e9/10.0e6); + `DEFINE_CLK(clk50, CLK_PERIOD, 50); + `DEFINE_CLK(clk10, CLK_PERIOD_10, 50); + localparam N = 2; + localparam N_DIV2 = N/2; + + reg reset_clk50; + reg clk10_rst; + reg s_ctrlport_req_wr; + reg s_ctrlport_req_rd; + reg [19:0] s_ctrlport_req_addr; + reg [31:0] s_ctrlport_req_data; + + // Response + wire s_ctrlport_resp_ack; + wire [ 1:0] s_ctrlport_resp_status; + wire [31:0] s_ctrlport_resp_data; + + + wire clk5, clk5_buf; + `include "../../regmap/clock_en_regmap_utils.vh" + + task cp_write; + input [19:0] a; + input [31:0] d; + begin + s_ctrlport_req_addr = a; + s_ctrlport_req_data = d; + @(posedge clk50); + s_ctrlport_req_wr = 1; + @(posedge clk50); + while(~s_ctrlport_resp_ack) @(posedge clk50); + s_ctrlport_req_wr = 0; + @(posedge clk50); + end + endtask + + task cp_read; + input [19:0] a; + input [31:0] d; + input debug; + begin + s_ctrlport_req_addr = a; + @(posedge clk50); + s_ctrlport_req_rd = 1; + @(posedge clk50); + while(~s_ctrlport_resp_ack) @(posedge clk50); + s_ctrlport_req_rd = 0; + @(posedge clk50); + if(debug) begin + $display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data); + end + `ASSERT_ERROR( s_ctrlport_resp_data == d, "CtrlPort read returned unexpected value."); + end + endtask + + clock_div #( + .N(N) + ) clock_div_5mhz ( + .clk_in (clk10), + .clk_in_rst (clk10_rst), + .clk_out (clk5) + ); + + clock_en_control #( + .BASE_ADDRESS(0) + ) clock_en_control_inst ( + .ctrlport_clk (clk50), + .ctrlport_rst (reset_clk50), + .s_ctrlport_req_wr (s_ctrlport_req_wr), + .s_ctrlport_req_rd (s_ctrlport_req_rd), + .s_ctrlport_req_addr (s_ctrlport_req_addr), + .s_ctrlport_req_data (s_ctrlport_req_data), + .s_ctrlport_resp_ack (s_ctrlport_resp_ack), + .s_ctrlport_resp_status (s_ctrlport_resp_status), + .s_ctrlport_resp_data (s_ctrlport_resp_data), + .clk_in (clk5), + .clk_out (clk5_buf) + ); + + // clock counters to verify clock division + reg counter_reset; + reg [8:0] clock_counter; + reg [10:0] div_clock_counter; + reg [10:0] expected_clock_count; + reg [8:0] expected_div_clock_count; + + always @(posedge clk10) begin + if(counter_reset) begin + clock_counter <= 0; + end else begin + clock_counter <= clock_counter + 1; + end + end + + always @(posedge clk5_buf) begin + if(counter_reset) begin + div_clock_counter <= 0; + end else begin + div_clock_counter <= div_clock_counter + 1; + end + end + + // main test cases + initial begin : tb_main + `TEST_CASE_START("initialize UUT"); + reset_clk50 = 1; + clk10_rst = 1; + s_ctrlport_req_wr = 0; + s_ctrlport_req_rd = 0; + s_ctrlport_req_addr = 0; + s_ctrlport_req_data = 0; + #200 //wait a cycle for the 10mhz clk rst + reset_clk50 = 0; + clk10_rst = 0; + $display("status: %t done reset here", $time); + `TEST_CASE_DONE(~reset_clk50); + // trigger setup + `TEST_CASE_START("Check that clock_out is not running"); + @(posedge clk5); + @(posedge clk10); + `ASSERT_ERROR( clk5_buf == 0, "clk5_buf should be zero now."); + repeat (N) @(posedge clk10); + `TEST_CASE_DONE(clk5_buf == 0 && clk5 == 1); + `TEST_CASE_START("Enable clock with clock_en_control enable register"); + cp_read(CLK_EN_CONTROL, 0, 1); //initial value should be zero + cp_write(CLK_EN_CONTROL, CLK_EN_CONTROL_MASK); + cp_read(CLK_EN_CONTROL, CLK_EN_CONTROL_MASK, 1); + @(posedge clk5_buf); + repeat (N_DIV2+1) @(posedge clk10); + `ASSERT_ERROR( clk5_buf == 0, "clk5_buf should be zero now."); + repeat (N_DIV2) @(posedge clk10); + `TEST_CASE_DONE(clk5_buf == 1 && s_ctrlport_resp_data == CLK_EN_CONTROL_MASK); + `TEST_CASE_START("Verify expected clock division."); + expected_div_clock_count = 5 + rand_clk_count.rand_bit(); + expected_clock_count = N*expected_div_clock_count; + $display("Reset clock counters @ time %t and then count main clock &d times and divided clock %d times", $time, expected_clock_count, expected_div_clock_count); + @(posedge clk5_buf); + counter_reset = 1; + @(posedge clk5_buf); + counter_reset = 0; + repeat (expected_div_clock_count) @(posedge clk5_buf); + @(posedge clk10); + `TEST_CASE_DONE(div_clock_counter == expected_div_clock_count && clock_counter == expected_clock_count); + `TEST_BENCH_DONE; +end +endmodule + diff --git a/top/x400/dboards/fbx/sim/i2c_sync_ctrl/Makefile b/top/x400/dboards/fbx/sim/i2c_sync_ctrl/Makefile new file mode 100644 index 0000000..b963cb2 --- /dev/null +++ b/top/x400/dboards/fbx/sim/i2c_sync_ctrl/Makefile @@ -0,0 +1,75 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir. +BASE_DIR = ../../../../.. +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Define part using PART_ID (//) +ARCH = zynquplusRFSOC +PART_ID = xczu28dr/ffvg1517/-1/e + +# Include makefiles and sources for the DUT and its dependencies +include $(BASE_DIR)/../lib/control/Makefile.srcs +include $(BASE_DIR)/../lib/wishbone/Makefile.srcs + + +DESIGN_SRCS += $(abspath \ +$(FIFO_SRCS) \ +$(AXI_SRCS) \ +$(CONTROL_LIB_SRCS) \ +$(WISHBONE_SRCS) \ +) + + +DESIGN_SRCS += $(abspath \ +../../regmap/fbx_ctrl_regmap_utils.vh \ +../../regmap/rf_sync_regmap_utils.vh \ +../../ctrlport_to_i2c_sync_ctrl.v \ +) + +#------------------------------------------------- +# IP Specific +#------------------------------------------------- +# If simulation contains IP, define the IP_DIR and point +# it to the base level IP directory +IP_DIR = $(BASE_DIR)/x400/ip +LIB_IP_DIR = $(BASE_DIR)/../lib/ip + +# Include makefiles and sources for all IP components +# *after* defining the IP_DIR +# +# These TBs don't use any IP yet :) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +include $(BASE_DIR)/../sim/general/Makefile.srcs + +# Define only one top-level module +SIM_TOP = ctrlport_to_i2c_sync_ctrl_tb + +# Simulation runtime in microseconds +SIM_RUNTIME_US = 200000 + +SIM_SRCS = \ +$(abspath ctrlport_to_i2c_sync_ctrl_tb.sv) \ +$(abspath $(BASE_DIR)/../lib/sim/wishbone/i2c/i2c_slave_model.v) \ + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/top/x400/dboards/fbx/sim/i2c_sync_ctrl/ctrlport_to_i2c_sync_ctrl_tb.sv b/top/x400/dboards/fbx/sim/i2c_sync_ctrl/ctrlport_to_i2c_sync_ctrl_tb.sv new file mode 100644 index 0000000..2de138b --- /dev/null +++ b/top/x400/dboards/fbx/sim/i2c_sync_ctrl/ctrlport_to_i2c_sync_ctrl_tb.sv @@ -0,0 +1,204 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: ctrlport_to_i2c_sync_ctrl_tb +// +// Description: +// testbench for ctrlport_to_i2c_sync_ctrl module. Tasks defined for ctrlport write and +// read transactions. Tests ability to write to SYNC/RFS_EN regs and then +// initialize i2c_master and i2c peripheral and then configure io through the +// i2c interface to the io expander. +// +`timescale 1ns / 1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 5 +`include "sim_exec_report.vh" +`include "sim_clks_rsts.vh" +`define SIM_TIMEOUT_US 200000 //overwrite this def from sim_exec_report.vh + + +module ctrlport_to_i2c_sync_ctrl_tb(); + import PkgRandom::*; + + `TEST_BENCH_INIT("ctrlport_to_i2c_sync_ctrl_tb", `NUM_TEST_CASES, `NS_PER_TICK); + //sets up clock + localparam CLK_PERIOD = $ceil(1e9/50.0e6); + `DEFINE_CLK(clk50, CLK_PERIOD, 50); + + reg reset_clk50; + reg s_ctrlport_req_wr; + reg s_ctrlport_req_rd; + reg [19:0] s_ctrlport_req_addr; + reg [31:0] s_ctrlport_req_data; + + // Response + wire s_ctrlport_resp_ack; + wire [ 1:0] s_ctrlport_resp_status; + wire [31:0] s_ctrlport_resp_data; + + + wire i2c_scl_i, i2c_scl_o, i2c_scl_en_o; + wire i2c_sda_i, i2c_sda_o, i2c_sda_en_o; + PkgRandom::Rand #(3) rand_sync; + PkgRandom::Rand #(1) rand_rfs_en; + reg [2:0] sync1, sync2, sync3, sync4, sync5; + reg rfs_en; + `include "../../regmap/rf_sync_regmap_utils.vh" + + task cp_write; + input [19:0] a; + input [31:0] d; + begin + s_ctrlport_req_addr = a; + s_ctrlport_req_data = d; + @(posedge clk50); + s_ctrlport_req_wr = 1; + @(posedge clk50); + while(~s_ctrlport_resp_ack) @(posedge clk50); + s_ctrlport_req_wr = 0; + @(posedge clk50); + end + endtask + + task cp_read; + input [19:0] a; + input [31:0] d; + input debug; + begin + s_ctrlport_req_addr = a; + s_ctrlport_req_rd = 1; + @(posedge clk50); + while(~s_ctrlport_resp_ack) @(posedge clk50); + s_ctrlport_req_rd = 0; + @(posedge clk50); + if(debug) begin + $display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data); + end + `ASSERT_ERROR( s_ctrlport_resp_data == d, "CtrlPort read returned unexpected value."); + end + endtask + + task cp_poll; + input [19:0] a; + input [31:0] d; + input debug; + begin + s_ctrlport_req_addr = a; + s_ctrlport_req_rd = 1; + @(posedge clk50); + while(~s_ctrlport_resp_ack) @(posedge clk50); + s_ctrlport_req_rd = 0; + @(posedge clk50); + while(s_ctrlport_resp_data != d && s_ctrlport_req_addr == a) begin + s_ctrlport_req_addr = a; + s_ctrlport_req_rd = 1; + @(posedge clk50); + while(~s_ctrlport_resp_ack) @(posedge clk50); + s_ctrlport_req_rd = 0; + @(posedge clk50); + end + if(debug) begin + $display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data); + end + end + endtask + + + ctrlport_to_i2c_sync_ctrl #( + .BASE_ADDRESS(0) + ) ctrlport_to_i2c_inst ( + .ctrlport_clk (clk50), + .ctrlport_rst (reset_clk50), + .s_ctrlport_req_wr (s_ctrlport_req_wr), + .s_ctrlport_req_rd (s_ctrlport_req_rd), + .s_ctrlport_req_addr (s_ctrlport_req_addr), + .s_ctrlport_req_data (s_ctrlport_req_data), + .s_ctrlport_resp_ack (s_ctrlport_resp_ack), + .s_ctrlport_resp_status (s_ctrlport_resp_status), + .s_ctrlport_resp_data (s_ctrlport_resp_data), + .scl_pad_i (i2c_scl_i), + .scl_pad_o (i2c_scl_o), + .scl_pad_en_o (i2c_scl_en_o), + .sda_pad_i (i2c_sda_i), + .sda_pad_o (i2c_sda_o), + .sda_pad_en_o (i2c_sda_en_o) + ); + + // hookup i2c slave model + i2c_slave_model #( + ctrlport_to_i2c_inst.SYNC_IO_SLV_ADR + ) i2c_slave ( + .scl(i2c_scl_i), + .sda(i2c_sda_i) + ); + + // create i2c lines + delay m0_scl (i2c_scl_en_o ? 1'bz : i2c_scl_o, i2c_scl_i), + m0_sda (i2c_sda_en_o ? 1'bz : i2c_sda_o, i2c_sda_i); + + pullup p1(i2c_scl_i); // pullup scl line + pullup p2(i2c_sda_i); // pullup sda line + + initial begin : tb_main + `TEST_CASE_START("initialize UUT"); + clk50 = 0; + reset_clk50 = 1; + s_ctrlport_req_wr = 0; + s_ctrlport_req_rd = 0; + s_ctrlport_req_addr = 0; + s_ctrlport_req_data = 0; + #100 + reset_clk50 = 0; + $display("status: %t done reset here", $time); + `TEST_CASE_DONE(~reset_clk50); + // trigger setup + `TEST_CASE_START("Initialize core and I2C peripheral"); + cp_write(SETUP_REG, 1); + cp_poll(SETUP_STATUS_REG,1,1); + `TEST_CASE_DONE(i2c_slave.mem[7] == 0 & i2c_slave.mem[6] == 0); + $display("status: %t SETUP DONE", $time); + // configure SYNC and RFS_EN Regs + for (int i=0; i<3; i=i+1) begin + `TEST_CASE_START("configure SYNC and RFS_EN Regs loop"); + $display("loop # %d", i); + sync1 = rand_sync.rand_bit(); + sync2 = rand_sync.rand_bit(); + sync3 = rand_sync.rand_bit(); + sync4 = rand_sync.rand_bit(); + sync5 = rand_sync.rand_bit(); + rfs_en = rand_rfs_en.rand_bit(); + cp_write(SYNC_1_REG, sync1); + cp_write(SYNC_2_REG, sync2); + cp_write(SYNC_3_REG, sync3); + cp_write(SYNC_4_REG, sync4); + cp_write(SYNC_5_REG, sync5); + cp_write(RFS_EN_REG, rfs_en); + cp_read(SYNC_1_REG, {28'b0, sync1}, 1); + cp_read(SYNC_2_REG, {28'b0, sync2}, 1); + cp_read(SYNC_3_REG, {28'b0, sync3}, 1); + cp_read(SYNC_4_REG, {28'b0, sync4}, 1); + cp_read(SYNC_5_REG, {28'b0, sync5}, 1); + cp_read(RFS_EN_REG, {31'b0, rfs_en}, 1); + $display("status: %t Configured ControlPort regs, now configure I2C peripheral.", $time); + cp_write(CONFIG_IO_REG, 1); + cp_poll(CONFIG_IO_STATUS_REG,32'h1,1); + `TEST_CASE_DONE(i2c_slave.mem[2] == {sync3[1:0], sync2, sync1} & + i2c_slave.mem[3] == {rfs_en, sync5, sync4, sync3[2]}); + end + `TEST_BENCH_DONE; +end +endmodule + +module delay (in, out); + input in; + output out; + + assign out = in; + + specify + (in => out) = (600,600); + endspecify +endmodule + diff --git a/top/x400/doc/X4XX_FPGA.htm b/top/x400/doc/X440/X440_FPGA.htm similarity index 51% rename from top/x400/doc/X4XX_FPGA.htm rename to top/x400/doc/X440/X440_FPGA.htm index 70f709b..bdefa98 100644 --- a/top/x400/doc/X4XX_FPGA.htm +++ b/top/x400/doc/X440/X440_FPGA.htm @@ -1,10 +1,10 @@ - X4XX_FPGA + X440_FPGA - - + + \ No newline at end of file diff --git a/top/x400/doc/X4XX_FPGA_left.htm b/top/x400/doc/X440/X440_FPGA_left.htm similarity index 81% rename from top/x400/doc/X4XX_FPGA_left.htm rename to top/x400/doc/X440/X440_FPGA_left.htm index 528c529..9ac613b 100644 --- a/top/x400/doc/X4XX_FPGA_left.htm +++ b/top/x400/doc/X440/X440_FPGA_left.htm @@ -127,10 +127,10 @@

    - + - X4XX_FPGA + + + X440_FPGA

    -
    +

    + P5 Content @@ -142,10 +142,10 @@ ports

    -

    ARM_M_AXI_HPM0

    -

    ARM_S_AXI_HPC0

    -

    ARM_S_AXI_HPC1

    -

    ARM_SPI1_CS3

    +

    ARM_M_AXI_HPM0

    +

    ARM_S_AXI_HPC0

    +

    ARM_S_AXI_HPC1

    +

    ARM_SPI1_CS3

    @@ -203,6 +203,18 @@

    enum SPI_ENDPOINT

    +

    + + + CLK_EN_REGMAP +

    +

    + + + CLK_EN_REGISTERS +

    +
    +

    CLK_EN_CONTROL

    +
    +

    + CMAC_REGMAP @@ -237,7 +249,8 @@

    GLOBAL_REGS

    VERSIONING_REGS

    -

    TIMEKEEPER

    +

    TIMEKEEPER_A

    +

    TIMEKEEPER_B

    DIO

    @@ -329,6 +342,21 @@

    ETH_IO_CTRL

    +

    + + + FBX_CTRL_REGMAP +

    +

    + + + FBX_CONTROLS +

    +
    +

    RF_ATR_REGS

    +

    RF_SYNC_REGS

    +

    LED_ATR_REGS

    +

    SYNC_CLK_EN_REGS

    +
    +

    + GLOBAL_REGS_REGMAP @@ -386,18 +414,33 @@

    - + - JTAG_REGMAP -

    + + + LED_ATR_REGMAP +

    - + - JTAG_REGS + + + LED_ATR_REGISTERS

    -
    -

    TX_DATA

    -

    STB_DATA

    -

    CONTROL

    -

    RX_DATA

    +
    +

    enum LED_SIZE_TYPE

    +

    LED0_ATR_STATE

    +

    LED1_ATR_STATE

    +

    LED2_ATR_STATE

    +

    LED3_ATR_STATE

    +

    LED_ATR_OPTION_REGISTER

    +

    LED_ATR_DISABLED

    +
    +
    +

    + + + LED_SETUP_REGMAP +

    +

    + + + LED_SETUP_REGISTERS +

    +
    +

    LED_CONTROL

    @@ -410,8 +453,8 @@

    PL_REGISTERS

    -

    JTAG_DB0

    -

    JTAG_DB1

    +

    PL_DB0_LED_REGISTERS

    +

    PL_DB1_LED_REGISTERS

    @@ -619,6 +662,59 @@

    FLASH_CFM0_END_ADDR_REG

    +

    + + + RF_ATR_REGMAP +

    +

    + + + RF_ATR_REGISTERS +

    +
    +

    enum RF_SWITCHES_SIZE_TYPE

    +

    RF0_ATR_STATE

    +

    RF1_ATR_STATE

    +

    RF2_ATR_STATE

    +

    RF3_ATR_STATE

    +

    ATR_OPTION_REGISTER

    +

    RF_ATR_DISABLED

    +
    +
    +

    + + + RF_SYNC_REGMAP +

    +

    + + + RF_SYNC_REGISTERS +

    +
    +

    enum IO_EXPANDER_REGISTER_ADRS

    +

    SYNC_1_REG

    +

    SYNC_2_REG

    +

    SYNC_3_REG

    +

    SYNC_4_REG

    +

    SYNC_5_REG

    +

    RFS_EN_REG

    +

    SETUP_REG

    +

    SETUP_STATUS_REG

    +

    CONFIG_IO_REG

    +

    CONFIG_IO_STATUS_REG

    +
    +
    +

    + + + RFDC_MAPPING_REGMAP +

    +

    + + + CHANNEL_SWAPPING +

    +
    +

    enum RFDC_ADC_MAPPING

    +

    enum RFDC_DAC_MAPPING

    +
    +

    + RFDC_REGS_REGMAP @@ -630,17 +726,23 @@

    enum FABRIC_DSP_BW_ENUM

    MMCM

    -

    INVERT_IQ_REG

    +

    INVERT_DB0_IQ_REG

    +

    INVERT_DB1_IQ_REG

    MMCM_RESET_REG

    -

    RF_RESET_CONTROL_REG

    -

    RF_RESET_STATUS_REG

    +

    RF0_RESET_CONTROL_REG

    +

    RF0_RESET_STATUS_REG

    +

    RF1_RESET_CONTROL_REG

    +

    RF1_RESET_STATUS_REG

    RF_AXI_STATUS_REG

    FABRIC_DSP_REG

    CALIBRATION_DATA

    CALIBRATION_ENABLE

    THRESHOLD_STATUS

    RF_PLL_CONTROL_REG

    -

    RF_PLL_STATUS_REG

    +

    RF_PLL_STATUS_REG

    +

    ADC_TILEMAP_REG

    +

    DAC_TILEMAP_REG

    +

    RFDC_INFO_REG

    @@ -707,8 +809,7 @@

    enum CPLD_IFC_VERSION

    enum DB_GPIO_IFC_VERSION

    enum FPGA_VERSION

    -

    enum RF_CORE_100M_VERSION

    -

    enum RF_CORE_400M_VERSION

    +

    enum RF_CORE_FULL_VERSION

    + diff --git a/top/x400/doc/X4XX_FPGA_right.htm b/top/x400/doc/X440/X440_FPGA_right.htm similarity index 77% rename from top/x400/doc/X4XX_FPGA_right.htm rename to top/x400/doc/X440/X440_FPGA_right.htm index c3e149b..0089b13 100644 --- a/top/x400/doc/X4XX_FPGA_right.htm +++ b/top/x400/doc/X440/X440_FPGA_right.htm @@ -693,661 +693,26 @@ pre[data-line] {

    - -

    X4XX_FPGA

    - This documentation provides a description of the different register spaces available - for the USRP X4xx Open-Source FPGA target implementation, accessible through the - embedded ARM A53 processor in the RFSoC chip, and other UHD hosts. -

    The top is defined in HDL source file common_regs.v, x4xx.v.

    + +

    X440_FPGA

    + This map contains register windows for controlling the different sources + that drive the state of FBX control lines. +

    The top is defined in HDL source file x440_rfdc_regs.v, x4xx.v.

    P5 Content

    Register map supplied for open-source projects



    "All content provided is Copyright 2023 National Instruments Corporation. @@ -1360,7 +725,7 @@ For information on NI trademark guidelines, please see - +

    Port ARM_M_AXI_HPM0 (input)

    @@ -1379,13 +744,13 @@ This is the main AXI4-Lite master interface that the PS

    - This port is defined in HDL source file common_regs.v. + This port is defined in HDL source file x440_rfdc_regs.v.

    - +

    Port ARM_S_AXI_HPC0 (output)

    @@ -1403,13 +768,13 @@ This is one of the two cache-coherent AXI slave ports available to

    - This port is defined in HDL source file common_regs.v. + This port is defined in HDL source file x440_rfdc_regs.v.

    - +

    Port ARM_S_AXI_HPC1 (output)

    @@ -1427,13 +792,13 @@ This is one of the two cache-coherent AXI slave ports available to

    - This port is defined in HDL source file common_regs.v. + This port is defined in HDL source file x440_rfdc_regs.v.

    - +

    Port ARM_SPI1_CS3 (input)

    @@ -1474,7 +839,7 @@ This is the SPI1 interface

    - This port is defined in HDL source file common_regs.v. + This port is defined in HDL source file x440_rfdc_regs.v.

    @@ -1508,7 +873,7 @@ This port has a 40-bit address bus.

    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -1570,7 +935,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -1632,7 +997,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -1694,7 +1059,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -1756,7 +1121,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -1818,7 +1183,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -1880,7 +1245,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -1942,7 +1307,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2004,7 +1369,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2080,7 +1445,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2142,7 +1507,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2204,7 +1569,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2266,7 +1631,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2328,7 +1693,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2390,7 +1755,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2452,7 +1817,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2514,7 +1879,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -2588,7 +1953,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -2650,7 +2015,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -2712,7 +2077,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -2900,6 +2265,130 @@ Total Offset = + + +
    + +

    CLK_EN_REGMAP

    + +

    CLK_EN_REGISTERS

    + Clock Enable Register +
    + + +

    Offset 0x0000: CLK_EN_CONTROL Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|SYNC_CLK_EN_REGS
      0x006000
    + +    		 + + + + +
    CLK_EN_CONTROL
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x006000 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file clock_en_control.v.

    + +
    + +
    + +This register configures Clock Enable. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    CLK_EN   (initialvalue=0)

    +

    Enables the Clock.

    + +
    + +
    + +
    +
    @@ -2946,9 +2435,9 @@ This enumeration is used to create the constants held in the basic registers. - 173157671 + 173157672 - 0x0A522D27 + 0x0A522D28

    PS_CPLD_SIGNATURE

    @@ -2959,12 +2448,12 @@ This enumeration is used to create the constants held in the basic registers. - 538059028 + 570950676 - 0x20122114 + 0x22080414 -

    OLDEST_CPLD_REVISION

    +

    CPLD_REVISION

    @@ -2972,12 +2461,12 @@ This enumeration is used to create the constants held in the basic registers. - 554767893 + 570950676 - 0x21111615 + 0x22080414 -

    CPLD_REVISION

    +

    OLDEST_CPLD_REVISION

    @@ -3020,7 +2509,7 @@ This enumeration is used to create the constants held in the basic registers. The following diagram shows how the communication bus interacts with the modules in CORE_REGS. -

    CORE_REGS

    @@ -3038,7 +2527,7 @@ This enumeration is used to create the constants held in the basic registers. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -3108,7 +2597,7 @@ Window to access global registers in the FPGA. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -3164,12 +2653,12 @@ Window to access versioning registers in the FPGA.
    - + -

    Offset 0x1000: TIMEKEEPER Window (R|W)

    +

    Offset 0x1000: TIMEKEEPER_A Window (R|W)

    - (show extended info) -
    + (show extended info) +
    @@ -3178,7 +2667,7 @@ Window to access versioning registers in the FPGA. @@ -3195,7 +2684,7 @@ Window to access versioning registers in the FPGA. @@ -3328,7 +2887,7 @@ Window to access the DIO register map. @@ -3423,7 +2982,7 @@ Contains the product's signature. @@ -3511,7 +3070,7 @@ Read/write register for general software use. @@ -3625,7 +3184,7 @@ Clock divider used for SPI transactions targeting the MB CPLD.
    @@ -3743,7 +3302,7 @@ Clock divider used for SPI transactions targeting any of the DB CPLDs.
    @@ -4484,7 +4043,7 @@ Contains information pertaining this SPI controller block. read the GPIO lines as master. The following diagram shows how source selection multiplexers are arranged, as well as an indicator for the register that control them.
    - Front-Panel Programmable GPIOs
    Make sure the GPIO lines between FPGA and GPIO board are not driven by two drivers. Set the DIO registers in PS_CPLD_BASE_REGMAP appropriately. @@ -4503,7 +4062,7 @@ Contains information pertaining this SPI controller block. @@ -4668,7 +4227,7 @@ Sets whether the DIO signal line is driven by this register interface @@ -4833,7 +4392,7 @@ Set the direction of FPGA buffer connected to DIO ports on the DIO board.
    @@ -4996,7 +4555,7 @@ Status of each bit at the FPGA input. @@ -5160,7 +4719,7 @@ Controls the values on each DIO signal line in case the line master is @@ -5325,7 +4884,7 @@ Controls whether the DIO lines reflect the state of
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    TIMEKEEPER
    TIMEKEEPER_A
      offset=0x1000
      size=0x20 (32 bytes)
    @@ -3231,6 +2720,76 @@ Window to access the timekeeper register map. + + +
    + + +

    Offset 0x1100: TIMEKEEPER_B Window (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|CORE_REGS
      0x10000A0000
    + +    		 + + + + + +
    TIMEKEEPER_B
      offset=0x1100
      size=0x20 (32 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x10000A1100 + +
    + +

    + +

    This window is defined in HDL source file x4xx_core_common.v.

    + +
    + +
    + +Window to access the timekeeper register map. + +
    +
    @@ -3248,7 +2807,7 @@ Window to access the timekeeper register map.
    		- +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -5491,7 +5050,7 @@ Controls which radio block to use the ATR state from to determine the - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -5656,7 +5215,7 @@ Controls which of the two available digital interfaces controls the DIO lines. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -5823,7 +5382,7 @@ Controls whether the radio input to the     - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6016,7 +5575,7 @@ Controls which source is forwarded to the     - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6088,7 +5647,7 @@ Refer to Xilinx' AXI DMA v7.1 IP product guide for further - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6145,6 +5704,169 @@ MAC/PHY control for the Ethernet interface.
    +
    + +
    + +

    FBX_CTRL_REGMAP

    + This map contains register windows for controlling the different sources + that drive the state of FBX control lines. +

    FBX_CONTROLS

    + +
    + + +

    Offset 0x0000: RF_ATR_REGS Window (R|W)

    +

      Target regmap = RF_ATR_REGMAP

    + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    RF_ATR_REGS
      offset=0x0000
      size=0x2000 (8 Kbytes)
    + +

    + +

    This window is defined in HDL source file db_gpio_interface.v.

    + +
    + +
    + +Control RF switches in FBX daughterboard based on the ATR state of the accessed radio + +
    + +
    + +
    + + +

    Offset 0x2000: RF_SYNC_REGS Window (R|W)

    +

      Target regmap = RF_SYNC_REGMAP

    + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    RF_SYNC_REGS
      offset=0x2000
      size=0x2000 (8 Kbytes)
    + +

    + +

    This window is defined in HDL source file db_gpio_interface.v.

    + +
    + +
    + +I2C interface to FBX daughterboard IO Expander that controls SYNC switches and rfs en + +
    + +
    + +
    + + +

    Offset 0x4000: LED_ATR_REGS Window (R|W)

    +

      Target regmap = LED_ATR_REGMAP

    + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    LED_ATR_REGS
      offset=0x4000
      size=0x2000 (8 Kbytes)
    + +

    + +

    This window is defined in HDL source file db_gpio_interface.v.

    + +
    + +
    + +Control TX/RX LEDs based on the ATR state of the accessed radio + +
    + +
    + +
    + + +

    Offset 0x6000: SYNC_CLK_EN_REGS Window (R|W)

    +

      Target regmap = CLK_EN_REGMAP

    + (show extended info) +
    + + + + + + + + + +
    + + + + + +
    SYNC_CLK_EN_REGS
      offset=0x6000
      size=0x2000 (8 Kbytes)
    + +

    + +

    This window is defined in HDL source file db_gpio_interface.v.

    + +
    + +
    + +Clock enable register for SYNC INJECT 5 MHz clock + +
    + +
    + +
    +
    @@ -6168,7 +5890,7 @@ MAC/PHY control for the Ethernet interface. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6272,7 +5994,7 @@ Revision number - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6412,7 +6134,7 @@ Build datestamp (32-bit) - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6493,7 +6215,7 @@ Git hash of source commit. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6574,7 +6296,7 @@ Scratch register for testing. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6696,7 +6418,7 @@ Register that contains the motherboard's device ID. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -6809,7 +6531,7 @@ Register that provides information on the RFNoC protocol. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7113,7 +6835,7 @@ Control register for clocking resources. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7185,7 +6907,7 @@ Control registers for PPS generation.

    PPS_RC_ENABLED

    Enables the PPS signal in radio clock domain. Please make sure that - the values of PPS_BRC_DELAY, PPS_PRC_DELAY and PRC_RC_DIVIDER are + the values of PPS_BRC_DELAY, PPS_PRC_DELAY and @.PRC_RC_DIVIDER are set before enabling this bit. It is recommended to disable the PPS for changes on the other values. Use a wait time of at least 1 second before changing this value to ensure the values are stable for the @@ -7206,8 +6928,8 @@ Control registers for PPS generation. 29..28 -

    PRC_RC_DIVIDER

    -

    Clock multiplier used to generate radio clock from PLL reference clock. +

    PRC_RC0_DIVIDER

    +

    Clock multiplier used to generate radio clock 0 from PLL reference clock. The value written to the register has to be reduced by 2 due to HDL implementation.

    @@ -7217,8 +6939,10 @@ Control registers for PPS generation. 27..26 -

    Reserved

    -

    +

    PRC_RC1_DIVIDER

    +

    Clock multiplier used to generate radio clock 1 from PLL reference clock. + The value written to the register has to be reduced by 2 due to + HDL implementation.

    @@ -7256,7 +6980,7 @@ Control registers for PPS generation. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7307,7 +7031,7 @@ Total Offset =

    -

    Initial Value = 0x0BEBC200 +

    Initial Value not specified

    This register is defined in HDL source file x4xx_global_regs.v.

    @@ -7326,57 +7050,9 @@ Returns the RFNoC bus clock rate (CHDR). 31..0 -

    CHDR_CLK   (initialvalue=CHDR_CLK_VALUE)

    +

    CHDR_CLK

    -

    - The values for this bitfield are in the CHDR_CLK_ENUM table. - (show here) -

    -
    - -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Value Name
    Dec Hex
    2000000000xBEBC200 -

    CHDR_CLK_VALUE

    - -
    - -

    - This enumerated type is defined in HDL source file x4xx_global_regs.v. -

    - -
    - -
    - @@ -7399,7 +7075,7 @@ Returns the RFNoC bus clock rate (CHDR). - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7481,7 +7157,7 @@ Returns the count value of a free-running counter driven by the RFNoC - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7564,7 +7240,7 @@ Build seed used for this compilation. Making this value readable - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7646,7 +7322,7 @@ RESERVED. This register is not implemented on X4xx. GPS is connected - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7728,7 +7404,7 @@ RESERVED. This register is not implemented on X4xx. GPS is connected - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7809,7 +7485,7 @@ RESERVED. This register is not implemented on X4xx. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7890,7 +7566,7 @@ RESERVED. This register is not implemented on X4xx. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -7971,7 +7647,7 @@ Register that specifies the number of timekeepers in the core. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8052,7 +7728,7 @@ Least significant bytes of 8 byte serial number - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8133,7 +7809,7 @@ Most significant bytes of 8 byte serial number - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8275,7 +7951,7 @@ Control register for mfg_test functions. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8382,7 +8058,7 @@ Status register for mfg_test functions. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8463,7 +8139,7 @@ Returns information from the QSFP0 Lane0. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8544,7 +8220,7 @@ Returns information from the QSFP0 Lane1. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8625,7 +8301,7 @@ Returns information from the QSFP0 Lane2. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8706,7 +8382,7 @@ Returns information from the QSFP0 Lane3. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8787,7 +8463,7 @@ Returns information from the QSFP1 Lane0. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8868,7 +8544,7 @@ Returns information from the QSFP1 Lane1. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -8949,7 +8625,7 @@ Returns information from the QSFP1 Lane2. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -9755,29 +9431,944 @@ Reflects the logic state of each GPIO input.
    - -

    JTAG_REGMAP

    -
    -
    -

    JTAG_REGS

    -
    -

    This register map is present for each JTAG module.

    -

    Basic operation would be:

    -
      -
    • poll ready until asserted
      • -
    • write / read data
      • -
    • write CONTROL register along with reset deasserted to start a transaction
      • -
    -

    For resetting the BITQ FSM, simply assert reset.

    -

    This operation seems a little strange, but it is what the axi_bitq driver -expects. This behavior has been implemented in previous products.

    -
    - + +

    LED_ATR_REGMAP

    -

    Offset 0x0000: TX_DATA Register (W)

    +

    LED_ATR_REGISTERS

    + Each channel in the FBX daughterboard has 3 LEDs. TXRX Red/Green LEDs and RX2 Green LED. + This register map describes how to control the behavior of the 3 LEDs. + There are three supported control schemes for these LEDs:
    +
      +
    • ATR Disabled - Single persistent state.
      • +
    • Classic ATR - Each channel's LEDs depend on the transmission state + of the respective channel.
      • +
    • DB State - Each channel's LEDs depend on the transmission state + of all channels in this radio.
      • +
    +
    + + +

    LED_SIZE_TYPE Enumeration

    - (show extended info) -
    + + + + + + + + + + + + + + + + +
    Value Name
    3 +

    LED_SIZE

    + +
    + +

    + This enumerated type is defined in HDL source file led_atr_control.v. +

    + +
    + +
    + + +

    Offset 0x0000: LED0_ATR_STATE(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|LED_ATR_REGS
      0x004000
    + +    		 + + + + +
    LED0_ATR_STATE
      offset=0x0000 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x004000 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file led_atr_control.v.
    +It uses RegType LED_ATR_STATE which is defined in HDL source file led_atr_control.v.

    + +
    + +
    + +Holds the value for the control lines of each channel's LEDs + for a particular ATR sate
    +Describes led behavior for the different ATR states. When LED0_ATR_OPTION + is set to use the DB states, TX and RX states for LED0-LED3 are + combined to create a single vector. This creates 256 different + combinations, each with its own register. When LED0_ATR_OPTION is set to + classic ATR, the first 4 offsets in this register group will be driven + in accordance with the state of RF0. + CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1, + TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1] + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    TXRX_GR_LED   (initialvalue=0)

    +

    + +
    1 +

    TXRX_RED_LED   (initialvalue=0)

    +

    + +
    0 +

    RX2_LED   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0400: LED1_ATR_STATE(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|LED_ATR_REGS
      0x004000
    + +    		 + + + + +
    LED1_ATR_STATE
      offset=0x0400 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x004400 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file led_atr_control.v.
    +It uses RegType LED_ATR_STATE which is defined in HDL source file led_atr_control.v.

    + +
    + +
    + +Holds the value for the control lines of each channel's LEDs + for a particular ATR sate
    +Describes led behavior for the different ATR states. When LED1_ATR_OPTION + is set to use the DB states, TX and RX states for LED0-LED3 are + combined to create a single vector. This creates 256 different + combinations, each with its own register. When LED1_ATR_OPTION is set to + classic ATR, the first 4 offsets in this register group will be driven + in accordance with the state of RF1. + CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1, + TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1] + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    TXRX_GR_LED   (initialvalue=0)

    +

    + +
    1 +

    TXRX_RED_LED   (initialvalue=0)

    +

    + +
    0 +

    RX2_LED   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0800: LED2_ATR_STATE(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|LED_ATR_REGS
      0x004000
    + +    		 + + + + +
    LED2_ATR_STATE
      offset=0x0800 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x004800 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file led_atr_control.v.
    +It uses RegType LED_ATR_STATE which is defined in HDL source file led_atr_control.v.

    + +
    + +
    + +Holds the value for the control lines of each channel's LEDs + for a particular ATR sate
    +Describes led behavior for the different ATR states. When LED2_ATR_OPTION + is set to use the DB states, TX and RX states for LED0-LED3 are + combined to create a single vector. This creates 256 different + combinations, each with its own register. When LED2_ATR_OPTION is set to + classic ATR, the first 4 offsets in this register group will be driven + in accordance with the state of RF2. + CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1, + TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1] + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    TXRX_GR_LED   (initialvalue=0)

    +

    + +
    1 +

    TXRX_RED_LED   (initialvalue=0)

    +

    + +
    0 +

    RX2_LED   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0C00: LED3_ATR_STATE(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|LED_ATR_REGS
      0x004000
    + +    		 + + + + +
    LED3_ATR_STATE
      offset=0x0C00 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x004C00 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file led_atr_control.v.
    +It uses RegType LED_ATR_STATE which is defined in HDL source file led_atr_control.v.

    + +
    + +
    + +Holds the value for the control lines of each channel's LEDs + for a particular ATR sate
    +Describes led behavior for the different ATR states. When LED3_ATR_OPTION + is set to use the DB states, TX and RX states for LED0-LED3 are + combined to create a single vector. This creates 256 different + combinations, each with its own register. When LED3_ATR_OPTION is set to + classic ATR, the first 4 offsets in this register group will be driven + in accordance with the state of RF3. + CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1, + TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1] + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    TXRX_GR_LED   (initialvalue=0)

    +

    + +
    1 +

    TXRX_RED_LED   (initialvalue=0)

    +

    + +
    0 +

    RX2_LED   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x1000: LED_ATR_OPTION_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|LED_ATR_REGS
      0x004000
    + +    		 + + + + +
    LED_ATR_OPTION_REGISTER
      offset=0x1000
    + +    		 + + + + + +
    + + +Total Offset =
      0x005000 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file led_atr_control.v.

    + +
    + +
    + +Controls whether switch control lines use the TX and RX state of + their respective channel (Classic ATR) or the daughterboard state + to select which state to use from values set in LED_ATR_STATE registers. + For each particular bit:
    + 0: Use DB state for ATR
    + 1: Classic ATR mode. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3 +

    LED3_ATR_OPTION   (initialvalue=0)

    +

    Control ATR scheme for RF3.

    + +
    2 +

    LED2_ATR_OPTION   (initialvalue=0)

    +

    Control ATR scheme for RF2.

    + +
    1 +

    LED1_ATR_OPTION   (initialvalue=0)

    +

    Control ATR scheme for RF1.

    + +
    0 +

    LED0_ATR_OPTION   (initialvalue=0)

    +

    Control ATR scheme for RF0.

    + +
    + +
    + +
    + + +

    Offset 0x1004: LED_ATR_DISABLED Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|LED_ATR_REGS
      0x004000
    + +    		 + + + + +
    LED_ATR_DISABLED
      offset=0x1004
    + +    		 + + + + + +
    + + +Total Offset =
      0x005004 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file led_atr_control.v.

    + +
    + +
    + +Disable ATR Control. DB state 0 will be reflected regardless of the ATR state. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3 +

    LED3_ATR_DISABLED   (initialvalue=0)

    +

    + +
    2 +

    LED2_ATR_DISABLED   (initialvalue=0)

    +

    + +
    1 +

    LED1_ATR_DISABLED   (initialvalue=0)

    +

    + +
    0 +

    LED0_ATR_DISABLED   (initialvalue=0)

    +

    + +
    + +
    + +
    + +
    + +
    + +

    LED_SETUP_REGMAP

    + +

    LED_SETUP_REGISTERS

    + Contains registers that control the LEDs. +
    + + +

    Offset 0x0000: LED_CONTROL Register (R|W)

    + + (show extended info) +
    @@ -9786,7 +10377,7 @@ expects. This behavior has been implemented in previous products.

    @@ -9812,8 +10403,8 @@ expects. This behavior has been implemented in previous products.

    @@ -9821,7 +10412,7 @@ expects. This behavior has been implemented in previous products.

    + +
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - - + +
    MB_CPLD_PL_REGMAP|JTAG_DB0
      0x000060
    MB_CPLD_PL_REGMAP|PL_DB0_LED_REGISTERS
      0x000050
    		 - +
    TX_DATA
    LED_CONTROL
      offset=0x0000
    @@ -9834,6 +10425,34 @@ expects. This behavior has been implemented in previous products.

    +Total Offset =
      0x1000088050 + +
    + + + + + + + + + + + + +
    MB_CPLD_PL_REGMAP|PL_DB1_LED_REGISTERS
      0x000060
    + + + + + + + + - - - - - - - -
    + + Total Offset =
      0x1000088060 @@ -9844,285 +10463,18 @@ Total Offset =
    - - - - -
    MB_CPLD_PL_REGMAP|JTAG_DB1
      0x000080
    - -    		 - - - - - -
    - - -Total Offset =
      0x1000088080 - -
    - -

    -

    Initial Value not specified +

    Initial Value = 0x00000000

    -

    This register is defined in HDL source file ctrlport_to_jtag.v.

    +

    This register is defined in HDL source file led_control.v.

    -
    -

    Data to be transmitted (TDI)

    - -
    - -
    - -
    - - -

    Offset 0x0004: STB_DATA Register (W)

    - - (show extended info) -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    - - - -
    Port ARM_M_AXI_HPM0
    - -    		 - - - - -
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    - -    		 - - - - -
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    - -    		 - - - - -
    MB_CPLD_PL_REGMAP|JTAG_DB0
      0x000060
    - -    		 - - - - -
    STB_DATA
      offset=0x0004
    - -    		 - - - - - -
    - - -Total Offset =
      0x1000088064 - -
    - -
    - - - - -
    MB_CPLD_PL_REGMAP|JTAG_DB1
      0x000080
    - -    		 - - - - - -
    - - -Total Offset =
      0x1000088084 - -
    - -

    - -

    Initial Value not specified -

    - -

    This register is defined in HDL source file ctrlport_to_jtag.v.

    - -
    - -
    - -
    -

    Data to be transmitted (TMS)

    - -
    - -
    - -
    - - -

    Offset 0x0008: CONTROL Register (R|W)

    - - (show extended info) -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    - - - -
    Port ARM_M_AXI_HPM0
    - -    		 - - - - -
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    - -    		 - - - - -
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    - -    		 - - - - -
    MB_CPLD_PL_REGMAP|JTAG_DB0
      0x000060
    - -    		 - - - - -
    CONTROL
      offset=0x0008
    - -    		 - - - - - -
    - - -Total Offset =
      0x1000088068 - -
    - -
    - - - - -
    MB_CPLD_PL_REGMAP|JTAG_DB1
      0x000080
    - -    		 - - - - - -
    - - -Total Offset =
      0x1000088088 - -
    - -

    - -

    Initial Value = 0x00000001 -

    - -

    This register is defined in HDL source file ctrlport_to_jtag.v.

    - -
    - -
    - -
    -

    JTAG module status and control

    +This register configures RF Frontend LEDs.
    @@ -10130,48 +10482,7 @@ Total Offset = BitsName - 31r - -

    ready

    -

    -

    Bitq FSM is ready for input (no data transmission in progress).

    - - - - - - 31w - -

    reset

    -

    -

    When asserted ('1') a soft-reset for the bitq FSM is triggered, -preventing any transactions to take place.

    -

    Deassert this bit, along with values for prescalar and length -to trigger a new transaction (start strobe).

    - - - - - - 30..24 - -

    Reserved

    -

    - - - - - - 23..16 - -

    Reserved

    -

    - - - - - - 15..13 + 31..27

    Reserved

    @@ -10180,146 +10491,142 @@ to trigger a new transaction (start strobe).

    - 12..8 + 26 -

    length

    -

    -

    (Number of bits - 1) to be transferred

    +

    CH3_TRX1_LED_GR_EN   (initialvalue=0)

    +

    Enables the Ch3 TRX (RX) Green LED

    + + + + + + 25 + +

    CH3_TRX1_LED_RED_EN   (initialvalue=0)

    +

    Enables the Ch3 TRX (TX) Red LED

    + + + + + + 24 + +

    CH3_RX2_LED_EN   (initialvalue=0)

    +

    Enables the Ch3 Rx2 Green LED

    - 7..0 + 23..19 -

    prescalar   (initialvalue=true)

    -

    -

    Clock divider. Resulting JTAG frequency will be f_ctrlport / (2*(prescalar + 1)). See window description for details on the initial/minimum value.

    +

    Reserved

    +

    + + + + + + 18 + +

    CH2_TRX1_LED_GR_EN   (initialvalue=0)

    +

    Enables the Ch2 TRX (RX) Green LED

    + + + + + + 17 + +

    CH2_TRX1_LED_RED_EN   (initialvalue=0)

    +

    Enables the Ch2 TRX (TX) Red LED

    + + + + + + 16 + +

    CH2_RX2_LED_EN   (initialvalue=0)

    +

    Enables the Ch2 Rx2 Green LED

    + + + + + + 15..11 + +

    Reserved

    +

    + + + + + + 10 + +

    CH1_TRX1_LED_GR_EN   (initialvalue=0)

    +

    Enables the Ch1 TRX (RX) Green LED

    + + + + + + 9 + +

    CH1_TRX1_LED_RED_EN   (initialvalue=0)

    +

    Enables the Ch1 TRX (TX) Red LED

    + + + + + + 8 + +

    CH1_RX2_LED_EN   (initialvalue=0)

    +

    Enables the Ch1 Rx2 Green LED

    + + + + + + 7..3 + +

    Reserved

    +

    + + + + + + 2 + +

    CH0_TRX1_LED_GR_EN   (initialvalue=0)

    +

    Enables the Ch0 TRX (RX) Green LED

    + + + + + + 1 + +

    CH0_TRX1_LED_RED_EN   (initialvalue=0)

    +

    Enables the Ch0 TRX (TX) Red LED

    + + + + + + 0 + +

    CH0_RX2_LED_EN   (initialvalue=0)

    +

    Enables the Ch0 Rx2 Green LED

    -
    - -
    - - -

    Offset 0x000C: RX_DATA Register (R)

    - - (show extended info) -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    - - - -
    Port ARM_M_AXI_HPM0
    - -    		 - - - - -
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    - -    		 - - - - -
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    - -    		 - - - - -
    MB_CPLD_PL_REGMAP|JTAG_DB0
      0x000060
    - -    		 - - - - -
    RX_DATA
      offset=0x000C
    - -    		 - - - - - -
    - - -Total Offset =
      0x100008806C - -
    - -
    - - - - -
    MB_CPLD_PL_REGMAP|JTAG_DB1
      0x000080
    - -    		 - - - - - -
    - - -Total Offset =
      0x100008808C - -
    - -

    - -

    Initial Value not specified -

    - -

    This register is defined in HDL source file ctrlport_to_jtag.v.

    - -
    - -
    - -
    -

    Received data (TDO)

    - -
    -
    @@ -10350,7 +10657,7 @@ All protocol masters controller by this register map are running with a clock fr - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -10416,12 +10723,12 @@ Total Offset =
    - + -

    Offset 0x0060: JTAG_DB0 Window (R|W)

    -

      Target regmap = JTAG_REGMAP

    - (show extended info) -
    +

    Offset 0x0050: PL_DB0_LED_REGISTERS Window (R|W)

    +

      Target regmap = LED_SETUP_REGMAP

    + (show extended info) +
    @@ -10430,7 +10737,7 @@ Total Offset = @@ -10456,9 +10763,89 @@ Total Offset = + + + + + +
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    - + + + +
    JTAG_DB0
    PL_DB0_LED_REGISTERS
      offset=0x0050
      size=0x10 (16 bytes)
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000088050 + +
    + +

    + +

    This window is defined in HDL source file mb_cpld.v.

    + +
    + +
    + +
    +
    + +
    + +
    + +
    + + +

    Offset 0x0060: PL_DB1_LED_REGISTERS Window (R|W)

    +

      Target regmap = LED_SETUP_REGMAP

    + (show extended info) +
    + + + + + + + + + + + + @@ -10489,90 +10876,8 @@ Total Offset =
    -

    JTAG Master connected to first daugherboard's CPLD JTAG interface.

    -

    Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.

    -
    - - -
    - - -

    Offset 0x0080: JTAG_DB1 Window (R|W)

    -

      Target regmap = JTAG_REGMAP

    - (show extended info) -
    - -
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    + +    		 + + + + +
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    + +    		 + + + - +
    PL_DB1_LED_REGISTERS
      offset=0x0060
      size=0x20 (32 bytes)
      size=0x10 (16 bytes)
    - - - - - - - - - - - - - - - -
    - - - -
    Port ARM_M_AXI_HPM0
    - -    		 - - - - -
    AXI_HPM0_REGMAP|MPM_ENDPOINT
      0x1000080000
    - -    		 - - - - -
    PL_CPLD_REGMAP|MB_CPLD
      0x008000
    - -    		 - - - - - -
    JTAG_DB1
      offset=0x0080
      size=0x20 (32 bytes)
    - -    		 - - - - - -
    - - -Total Offset =
      0x1000088080 - -
    - -

    - -

    This window is defined in HDL source file mb_cpld.v.

    - -
    - -
    - -
    -

    JTAG Master connected to second daugherboard's CPLD JTAG interface.

    -

    Use minimum value of 1 for JTAG_REGMAP.prescalar because the DB CPLD JTAG interface maximum clock frequency is 20 MHz.

    -
    @@ -10604,7 +10909,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -10960,7 +11265,7 @@ meaning varies based on the MGT_PROTOCOL.

    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -11286,7 +11591,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -11582,7 +11887,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -11922,7 +12227,7 @@ When clear the activity LED set on any TX or RX traffic to the mgt

    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -12200,7 +12505,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -12478,7 +12783,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -12756,7 +13061,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -13034,7 +13339,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -13317,7 +13622,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -13603,7 +13908,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -13740,7 +14045,7 @@ Provides to the LEDs of the QSFP ports. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -13857,7 +14162,7 @@ Information from FPGA about the cable present status. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -13961,7 +14266,7 @@ Contains the product's signature. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -14092,7 +14397,7 @@ Contains the CPLD revision (see CPLD_REVISION of CON - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -14226,7 +14531,7 @@ This register returns (in YYMMDDHH format) the oldest revision - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -14316,7 +14621,7 @@ Read/write register for general software use. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -14442,7 +14747,7 @@ Git hash of commit used to build this image.
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -14512,7 +14817,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -14582,7 +14887,7 @@ All registers of the MB CPLD (PL part). - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -14652,7 +14957,7 @@ All registers of the first DB CPLD. Register map will be added later on. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -14723,7 +15028,7 @@ All registers of the second DB CPLD. Register map will be added later on.

    Offset 0x0000: AXI_HPC0_WINDOW Window (R|W)

    -

      Target port = X4XX_FPGA|ARM_S_AXI_HPC0

    +

      Target port = X440_FPGA|ARM_S_AXI_HPC0

    (show extended info)
    @@ -14774,7 +15079,7 @@ The HPC0 port of the PS is used for general purpose cache-coherent accesses

    Offset 0x0000: AXI_HPC1_WINDOW Window (R|W)

    -

      Target port = X4XX_FPGA|ARM_S_AXI_HPC1

    +

      Target port = X440_FPGA|ARM_S_AXI_HPC1

    (show extended info)
    @@ -14843,7 +15148,7 @@ The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -14961,7 +15266,7 @@ Set the direction of FPGA buffer connected to DIO ports on the DIO board.
    - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -15033,7 +15338,7 @@ Least significant bytes of 5 byte serial number. - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -15105,7 +15410,7 @@ Most significant byte of 5 byte serial number. - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -15240,7 +15545,7 @@ Control CMI communication and delivers information on the CMI link status. - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -15526,7 +15831,7 @@ Register to control the PL part DB SPI connection and reset generation. - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -15612,7 +15917,7 @@ Contains the product's signature. - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -15725,7 +16030,7 @@ Contains the CPLD revision (see CPLD_REVISION of CON - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -15841,7 +16146,7 @@ This register returns (in YYMMDDHH format) the oldest revision - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -15913,7 +16218,7 @@ Read/write register for general software use. - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -16020,7 +16325,7 @@ Git hash of commit used to build this image.
    - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -16182,7 +16487,7 @@ Controls the power supplies for the iPass connectors. - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -16331,7 +16636,7 @@ Controls the power supplies for the oscillators. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -16598,7 +16903,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -16865,7 +17170,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -17132,7 +17437,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -17398,7 +17703,7 @@ Total Offset = starts at offset 0x80000 in the RFNoC Radio block's register space. The following diagram displays the distribution of the CtrlPort interface to the different modules it interacts with. -     @@ -17984,7 +18289,7 @@ These values are the start and end address of the CFM image flash - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -18226,7 +18531,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -18493,7 +18798,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -18601,7 +18906,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -18689,7 +18994,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -18776,7 +19081,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -18862,7 +19167,7 @@ Total Offset = - +
    Port ARM_SPI1_CS3
    Port ARM_SPI1_CS3
    @@ -18935,6 +19240,2584 @@ Total Offset =
    +
    + +
    + +

    RF_ATR_REGMAP

    + +

    RF_ATR_REGISTERS

    + Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1 + switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for + all four switches are not considered time critical controls, and are hence driven by an I/O + expander controlled via I2C. + This register map describes how to control the behavior of the 3 HMC849A switches' control lines. + There are three supported control schemes for these switches:
    +
      +
    • ATR Disabled - Single persistent state.
      • +
    • Classic ATR - Each channel's switches depend on the transmission state + of the respective channel.
      • +
    • DB State - Each channel's switches depend on the transmission state + of all channels in this radio.
      • +
    +
    + + +

    RF_SWITCHES_SIZE_TYPE Enumeration

    + + + + + + + + + + + + + + + + + +
    Value Name
    3 +

    RFS_SIZE

    + +
    + +

    + This enumerated type is defined in HDL source file rf_atr_control.v. +

    + +
    + +
    + + +

    Offset 0x0000: RF0_ATR_STATE(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_ATR_REGS
      0x000000
    + +    		 + + + + +
    RF0_ATR_STATE
      offset=0x0000 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x000000 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file rf_atr_control.v.
    +It uses RegType RF_ATR_STATE which is defined in HDL source file rf_atr_control.v.

    + +
    + +
    + +Holds the value for the control lines of each channel's switches + for a particular ATR sate
    +Describes switch control behavior for the different ATR states. When RF0_ATR_OPTION + is set to use the DB states, TX and RX states for RF0-RF3 are + combined to create a single vector. This creates 256 different + combinations, each with its own register. When RF0_ATR_OPTION is set to + classic ATR, the first 4 offsets in this register group will be driven + in accordance with the state of RF0. + CLASSIC ATR MAPPING: Idle[RF0: TX=0, RX=0], RX[RF0: TX=0, RX=1, + TX[RF0: TX=1, RX=0], FDX[RF0: TX=1, RX=1] + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    TDDS   (initialvalue=0)

    +

    + +
    1 +

    RX_RFS   (initialvalue=0)

    +

    + +
    0 +

    TX_RX_RFS   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0400: RF1_ATR_STATE(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_ATR_REGS
      0x000000
    + +    		 + + + + +
    RF1_ATR_STATE
      offset=0x0400 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x000400 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file rf_atr_control.v.
    +It uses RegType RF_ATR_STATE which is defined in HDL source file rf_atr_control.v.

    + +
    + +
    + +Holds the value for the control lines of each channel's switches + for a particular ATR sate
    +Describes switch control behavior for the different ATR states. When RF1_ATR_OPTION + is set to use the DB states, TX and RX states for RF0-RF3 are + combined to create a single vector. This creates 256 different + combinations, each with its own register. When RF1_ATR_OPTION is set to + classic ATR, the first 4 offsets in this register group will be driven + in accordance with the state of RF1. + CLASSIC ATR MAPPING: Idle[RF1: TX=0, RX=0], RX[RF1: TX=0, RX=1, + TX[RF1: TX=1, RX=0], FDX[RF1: TX=1, RX=1] + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    TDDS   (initialvalue=0)

    +

    + +
    1 +

    RX_RFS   (initialvalue=0)

    +

    + +
    0 +

    TX_RX_RFS   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0800: RF2_ATR_STATE(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_ATR_REGS
      0x000000
    + +    		 + + + + +
    RF2_ATR_STATE
      offset=0x0800 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x000800 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file rf_atr_control.v.
    +It uses RegType RF_ATR_STATE which is defined in HDL source file rf_atr_control.v.

    + +
    + +
    + +Holds the value for the control lines of each channel's switches + for a particular ATR sate
    +Describes switch control behavior for the different ATR states. When RF2_ATR_OPTION + is set to use the DB states, TX and RX states for RF0-RF3 are + combined to create a single vector. This creates 256 different + combinations, each with its own register. When RF2_ATR_OPTION is set to + classic ATR, the first 4 offsets in this register group will be driven + in accordance with the state of RF2. + CLASSIC ATR MAPPING: Idle[RF2: TX=0, RX=0], RX[RF2: TX=0, RX=1, + TX[RF2: TX=1, RX=0], FDX[RF2: TX=1, RX=1] + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    TDDS   (initialvalue=0)

    +

    + +
    1 +

    RX_RFS   (initialvalue=0)

    +

    + +
    0 +

    TX_RX_RFS   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0C00: RF3_ATR_STATE(255:0) Register Array (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_ATR_REGS
      0x000000
    + +    		 + + + + +
    RF3_ATR_STATE
      offset=0x0C00 + i*4
    + +    		 + + + + + + +
    + + +Cannot determine accessibility through this path
    +Total Offset =
      0x000C00 + i*4 + +
    + +

    + +

    Initial Values
    + + +
    default=>0x00000000
    +

    + +

    This register is defined in HDL source file rf_atr_control.v.
    +It uses RegType RF_ATR_STATE which is defined in HDL source file rf_atr_control.v.

    + +
    + +
    + +Holds the value for the control lines of each channel's switches + for a particular ATR sate
    +Describes switch control behavior for the different ATR states. When RF3_ATR_OPTION + is set to use the DB states, TX and RX states for RF0-RF3 are + combined to create a single vector. This creates 256 different + combinations, each with its own register. When RF3_ATR_OPTION is set to + classic ATR, the first 4 offsets in this register group will be driven + in accordance with the state of RF3. + CLASSIC ATR MAPPING: Idle[RF3: TX=0, RX=0], RX[RF3: TX=0, RX=1, + TX[RF3: TX=1, RX=0], FDX[RF3: TX=1, RX=1] + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    TDDS   (initialvalue=0)

    +

    + +
    1 +

    RX_RFS   (initialvalue=0)

    +

    + +
    0 +

    TX_RX_RFS   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x1000: ATR_OPTION_REGISTER Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_ATR_REGS
      0x000000
    + +    		 + + + + +
    ATR_OPTION_REGISTER
      offset=0x1000
    + +    		 + + + + + +
    + + +Total Offset =
      0x001000 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file rf_atr_control.v.

    + +
    + +
    + +Controls whether switch control lines use the TX and RX state of + their respective channel (Classic ATR) or the daughterboard state + to select which state to use from values set in RF_ATR_STATE registers. + For each particular bit:
    + 0: Use DB state for ATR
    + 1: Classic ATR mode. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3 +

    RF3_ATR_OPTION   (initialvalue=0)

    +

    Control ATR scheme for RF3.

    + +
    2 +

    RF2_ATR_OPTION   (initialvalue=0)

    +

    Control ATR scheme for RF2.

    + +
    1 +

    RF1_ATR_OPTION   (initialvalue=0)

    +

    Control ATR scheme for RF1.

    + +
    0 +

    RF0_ATR_OPTION   (initialvalue=0)

    +

    Control ATR scheme for RF0.

    + +
    + +
    + +
    + + +

    Offset 0x1004: RF_ATR_DISABLED Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_ATR_REGS
      0x000000
    + +    		 + + + + +
    RF_ATR_DISABLED
      offset=0x1004
    + +    		 + + + + + +
    + + +Total Offset =
      0x001004 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file rf_atr_control.v.

    + +
    + +
    + +Disable ATR Control. DB state 0 will be reflected regardless of the ATR state. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3 +

    RF3_ATR_DISABLED   (initialvalue=0)

    +

    + +
    2 +

    RF2_ATR_DISABLED   (initialvalue=0)

    +

    + +
    1 +

    RF1_ATR_DISABLED   (initialvalue=0)

    +

    + +
    0 +

    RF0_ATR_DISABLED   (initialvalue=0)

    +

    + +
    + +
    + +
    + +
    + +
    + +

    RF_SYNC_REGMAP

    + +

    RF_SYNC_REGISTERS

    + Each channel in the FBX daughterboard has 4 switches in its path. 3 of these are HMC849A 2:1 + switches and the last one is a PE42442 4:1 switch. The latter, as well as the enable lines for + all four switches are not considered time critical controls, and are hence driven by a + TCA6416A I/O expander controlled via I2C. + This register map controls that I/O expander. The first 6 registers in + this space set the values of the 5 3-pin sync switches and then an + RFS enable bit. The 2 additional registers trigger a init sequence for + the expander peripheral and configuring the I/O with the contents of + the value registers both with a series of I2C commands. +
    + + +

    IO_EXPANDER_REGISTER_ADRS Enumeration

    +This is not a register spaces for this ctrlport interface but + instead register addresses on the TCA6416A. Therefore, we will just + define an enum with these addresses so there is no clash with the + above ctrlport regmap. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    0 +

    IO_EXP_INPUT_PORT0_REG

    + +
    1 +

    IO_EXP_INPUT_PORT1_REG

    + +
    2 +

    IO_EXP_OUTPUT_PORT0_REG

    + +
    3 +

    IO_EXP_OUTPUT_PORT1_REG

    + +
    4 +

    IO_EXP_POLARITY_INV0_REG

    + +
    5 +

    IO_EXP_POLARITY_INV1_REG

    + +
    6 +

    IO_EXP_CONFIG0_REG

    + +
    7 +

    IO_EXP_CONFIG1_REG

    + +
    + +

    + This enumerated type is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v. +

    + +
    + +
    + + +

    Offset 0x0000: SYNC_1_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    SYNC_1_REG
      offset=0x0000
    + +    		 + + + + + +
    + + +Total Offset =
      0x002000 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
    +It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Sets I/O to control Sync Switch.
    +Sets I/O state to control Sync Switch 1. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    CONTROL_PIN_V3   (initialvalue=0)

    +

    + +
    1 +

    CONTROL_PIN_V2   (initialvalue=0)

    +

    + +
    0 +

    CONTROL_PIN_V1   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0004: SYNC_2_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    SYNC_2_REG
      offset=0x0004
    + +    		 + + + + + +
    + + +Total Offset =
      0x002004 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
    +It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Sets I/O to control Sync Switch.
    +Sets I/O state to control Sync Switch 2. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    CONTROL_PIN_V3   (initialvalue=0)

    +

    + +
    1 +

    CONTROL_PIN_V2   (initialvalue=0)

    +

    + +
    0 +

    CONTROL_PIN_V1   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0008: SYNC_3_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    SYNC_3_REG
      offset=0x0008
    + +    		 + + + + + +
    + + +Total Offset =
      0x002008 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
    +It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Sets I/O to control Sync Switch.
    +Sets I/O state to control Sync Switch 3. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    CONTROL_PIN_V3   (initialvalue=0)

    +

    + +
    1 +

    CONTROL_PIN_V2   (initialvalue=0)

    +

    + +
    0 +

    CONTROL_PIN_V1   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x000C: SYNC_4_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    SYNC_4_REG
      offset=0x000C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00200C + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
    +It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Sets I/O to control Sync Switch.
    +Sets I/O state to control Sync Switch 4. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    CONTROL_PIN_V3   (initialvalue=0)

    +

    + +
    1 +

    CONTROL_PIN_V2   (initialvalue=0)

    +

    + +
    0 +

    CONTROL_PIN_V1   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0010: SYNC_5_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    SYNC_5_REG
      offset=0x0010
    + +    		 + + + + + +
    + + +Total Offset =
      0x002010 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.
    +It uses RegType SYNC_SWITCH which is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Sets I/O to control Sync Switch.
    +Sets I/O state to control Sync Switch 5. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..3 +

    Reserved

    +

    + +
    2 +

    CONTROL_PIN_V3   (initialvalue=0)

    +

    + +
    1 +

    CONTROL_PIN_V2   (initialvalue=0)

    +

    + +
    0 +

    CONTROL_PIN_V1   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0014: RFS_EN_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    RFS_EN_REG
      offset=0x0014
    + +    		 + + + + + +
    + + +Total Offset =
      0x002014 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Sets I/O state to control RFS Enable. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    RFS_EN_PIN   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0018: SETUP_REG Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    SETUP_REG
      offset=0x0018
    + +    		 + + + + + +
    + + +Total Offset =
      0x002018 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Write to this register to trigger initialization sequence of + I2C Master core and TCA6416A I/O expander peripheral. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0w +

    SETUP_TRIG   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x0018: SETUP_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    SETUP_STATUS_REG
      offset=0x0018
    + +    		 + + + + + +
    + + +Total Offset =
      0x002018 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Read from this register to check the status of setup. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    SETUP_STATUS   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x001C: CONFIG_IO_REG Register (W)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    CONFIG_IO_REG
      offset=0x001C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00201C + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Write to this register to trigger I/O configuration I2C sequence of + TCA6416A I/O expander peripheral. + Read from this register to check the status of reconfiguring the setup. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0w +

    CONFIG_IO_TRIG   (initialvalue=0)

    +

    + +
    + +
    + +
    + + +

    Offset 0x001C: CONFIG_IO_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + +
    + + + + +
    FBX_CTRL_REGMAP|RF_SYNC_REGS
      0x002000
    + +    		 + + + + +
    CONFIG_IO_STATUS_REG
      offset=0x001C
    + +    		 + + + + + +
    + + +Total Offset =
      0x00201C + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file ctrlport_to_i2c_sync_ctrl.v.

    + +
    + +
    + +Read from this register to check the status of reconfiguring the setup. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..8 +

    Reserved

    +

    + +
    7..1 +

    Reserved

    +

    + +
    0 +

    CONFIG_IO_STATUS   (initialvalue=0)

    +

    + +
    + +
    + +
    + +
    + +
    + +

    RFDC_MAPPING_REGMAP

    + +

    CHANNEL_SWAPPING

    + +
    + + +

    RFDC_ADC_MAPPING Enumeration

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x0 +

    CH2_RX_MAPPING

    + +
    10x1 +

    CH1_RX_MAPPING

    + +
    20x2 +

    CH3_RX_MAPPING

    + +
    30x3 +

    CH0_RX_MAPPING

    + +
    40x4 +

    CH6_RX_MAPPING

    + +
    50x5 +

    CH5_RX_MAPPING

    + +
    60x6 +

    CH7_RX_MAPPING

    + +
    70x7 +

    CH4_RX_MAPPING

    + +
    + +

    + This enumerated type is defined in HDL source file x440_rfdc_mapping.v. +

    + +
    + +
    + + +

    RFDC_DAC_MAPPING Enumeration

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Value Name
    Dec Hex
    00x0 +

    CH0_TX_MAPPING

    + +
    10x1 +

    CH3_TX_MAPPING

    + +
    20x2 +

    CH1_TX_MAPPING

    + +
    30x3 +

    CH2_TX_MAPPING

    + +
    40x4 +

    CH4_TX_MAPPING

    + +
    50x5 +

    CH7_TX_MAPPING

    + +
    60x6 +

    CH5_TX_MAPPING

    + +
    70x7 +

    CH6_TX_MAPPING

    + +
    + +

    + This enumerated type is defined in HDL source file x440_rfdc_mapping.v. +

    + +
    + +
    +
    @@ -19017,6 +21900,19 @@ Total Offset = + + + 1000 + + 0x3E8 + + +

    FABRIC_DSP_BW_FULL

    + + + + +

    @@ -19040,7 +21936,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -19083,7 +21979,7 @@ Total Offset =

    -

    This window is defined in HDL source file common_regs.v.

    +

    This window is defined in HDL source file x440_rfdc_regs.v.

    @@ -19100,12 +21996,12 @@ Register space for controlling the data clock MMCM instance
    - + -

    Offset 0x10000: INVERT_IQ_REG Register (R|W)

    +

    Offset 0x10000: INVERT_DB0_IQ_REG Register (R|W)

    - (show extended info) -
    + (show extended info) +
    @@ -19114,7 +22010,7 @@ Register space for controlling the data clock MMCM instance @@ -19131,7 +22027,7 @@ Register space for controlling the data clock MMCM instance

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.

    @@ -19191,36 +22087,9 @@ Control register for inverting I/Q data. - + - - - - - - - - - - - - - - - @@ -19229,7 +22098,7 @@ Control register for inverting I/Q data. @@ -19238,7 +22107,7 @@ Control register for inverting I/Q data. @@ -19247,7 +22116,7 @@ Control register for inverting I/Q data. @@ -19256,43 +22125,16 @@ Control register for inverting I/Q data. - + - - - - - - - - - - - - - - - @@ -19301,7 +22143,7 @@ Control register for inverting I/Q data. @@ -19310,7 +22152,7 @@ Control register for inverting I/Q data. @@ -19319,7 +22161,7 @@ Control register for inverting I/Q data. @@ -19328,7 +22170,192 @@ Control register for inverting I/Q data. + + +
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    INVERT_IQ_REG
    INVERT_DB0_IQ_REG
      offset=0x10000
    @@ -19159,7 +22055,7 @@ Total Offset =
    1515..12 -

    INVERT_DB1_DAC3_IQ

    -

    - -
    14 -

    INVERT_DB1_DAC2_IQ

    -

    - -
    13 -

    INVERT_DB1_DAC1_IQ

    -

    - -
    12 -

    INVERT_DB1_DAC0_IQ

    +

    Reserved

    11 -

    INVERT_DB0_DAC3_IQ

    +

    INVERT_DB0_DAC3_IQ

    10 -

    INVERT_DB0_DAC2_IQ

    +

    INVERT_DB0_DAC2_IQ

    9 -

    INVERT_DB0_DAC1_IQ

    +

    INVERT_DB0_DAC1_IQ

    8 -

    INVERT_DB0_DAC0_IQ

    +

    INVERT_DB0_DAC0_IQ

    77..4 -

    INVERT_DB1_ADC3_IQ

    -

    - -
    6 -

    INVERT_DB1_ADC2_IQ

    -

    - -
    5 -

    INVERT_DB1_ADC1_IQ

    -

    - -
    4 -

    INVERT_DB1_ADC0_IQ

    +

    Reserved

    3 -

    INVERT_DB0_ADC3_IQ

    +

    INVERT_DB0_ADC3_IQ

    2 -

    INVERT_DB0_ADC2_IQ

    +

    INVERT_DB0_ADC2_IQ

    1 -

    INVERT_DB0_ADC1_IQ

    +

    INVERT_DB0_ADC1_IQ

    0 -

    INVERT_DB0_ADC0_IQ

    +

    INVERT_DB0_ADC0_IQ

    +

    + +
    + +
    + +
    + + +

    Offset 0x10800: INVERT_DB1_IQ_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    INVERT_DB1_IQ_REG
      offset=0x10800
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000150800 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x440_rfdc_regs.v.

    + +
    + +
    + +Control register for inverting I/Q data. + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -19353,7 +22380,7 @@ Control register for inverting I/Q data. @@ -19398,7 +22425,7 @@ Total Offset =

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.

    @@ -19462,12 +22489,12 @@ Control register for resetting the data clock MMCM.
    - + -

    Offset 0x12000: RF_RESET_CONTROL_REG Register (R|W)

    +

    Offset 0x12000: RF0_RESET_CONTROL_REG Register (R|W)

    - (show extended info) -
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11 +

    INVERT_DB1_DAC3_IQ

    +

    + +
    10 +

    INVERT_DB1_DAC2_IQ

    +

    + +
    9 +

    INVERT_DB1_DAC1_IQ

    +

    + +
    8 +

    INVERT_DB1_DAC0_IQ

    +

    + +
    7..4 +

    Reserved

    +

    + +
    3 +

    INVERT_DB1_ADC3_IQ

    +

    + +
    2 +

    INVERT_DB1_ADC2_IQ

    +

    + +
    1 +

    INVERT_DB1_ADC1_IQ

    +

    + +
    0 +

    INVERT_DB1_ADC0_IQ

    		- +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -19476,7 +22503,7 @@ Control register for resetting the data clock MMCM. @@ -19493,7 +22520,7 @@ Control register for resetting the data clock MMCM.

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType RF_RESET_CONTROL_REGTYPE which is defined in HDL source file common_regs.v.

    @@ -19534,7 +22562,8 @@ Control register for the RF reset controller. Wait until DB*_DONE is asserted to release the trigger. The DB*_DONE signal should then de-assert.
    Note: The *_DB1 constants are not used in the HDL, their purpose is - merely for documentation. + merely for documentation.
    + @@ -19571,7 +22600,7 @@ Control register for the RF reset controller. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    RF_RESET_CONTROL_REG
    RF0_RESET_CONTROL_REG
      offset=0x12000
    @@ -19521,7 +22548,8 @@ Total Offset =
    9 -

    DAC_ENABLE

    +

    DAC_ENABLE

    Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted.

    @@ -19582,7 +22611,7 @@ Control register for the RF reset controller.
    8 -

    DAC_RESET

    +

    DAC_RESET

    Write a '1' to this bit to trigger a reset for the daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done is asserted.

    @@ -19602,7 +22631,7 @@ Control register for the RF reset controller.
    5 -

    ADC_ENABLE

    +

    ADC_ENABLE

    Write a '1' to this bit to trigger the enable sequence for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted.

    @@ -19613,7 +22642,7 @@ Control register for the RF reset controller.
    4 -

    ADC_RESET

    +

    ADC_RESET

    Write a '1' to this bit to trigger a reset for the daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done is asserted.

    @@ -19633,7 +22662,7 @@ Control register for the RF reset controller.
    0 -

    FSM_RESET

    +

    FSM_RESET

    Write a '1' to this bit to reset the RF reset controller. Write a '0' once db0_fsm_reset_done asserts.

    @@ -19645,12 +22674,12 @@ Control register for the RF reset controller.
    - + -

    Offset 0x12008: RF_RESET_STATUS_REG Register (R)

    +

    Offset 0x12008: RF0_RESET_STATUS_REG Register (R)

    - (show extended info) -
    + (show extended info) +
    @@ -19659,7 +22688,7 @@ Control register for the RF reset controller. @@ -19676,7 +22705,7 @@ Control register for the RF reset controller.

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType RF_RESET_STATUS_REGTYPE which is defined in HDL source file common_regs.v.

    @@ -19712,10 +22742,11 @@ Total Offset = Status register for the RF reset controller. Verify the FSM ID before polling starting any reset sequence. - Refer to RF_RESET_CONTROL_REG for instructions on how to use + Refer to RF*_RESET_CONTROL_REG for instructions on how to use the status bits in this register.
    Note: The *_DB1 constants are not used in the HDL, their purpose is - merely for documentation. + merely for documentation.
    + @@ -19752,7 +22783,7 @@ Status register for the RF reset controller. + + + + + + + +
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    		 - +
    RF_RESET_STATUS_REG
    RF0_RESET_STATUS_REG
      offset=0x12008
    @@ -19704,7 +22733,8 @@ Total Offset =
    11 -

    DAC_SEQ_DONE

    +

    DAC_SEQ_DONE

    This bit asserts ('1') when the DB0 DAC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset).

    @@ -19772,7 +22803,7 @@ Status register for the RF reset controller.
    7 -

    ADC_SEQ_DONE

    +

    ADC_SEQ_DONE

    This bit asserts ('1') when the DB0 ADC chain reset sequence is completed. The bitfield deasserts ('0') after deasserting the issued triggered (enable or reset).

    @@ -19792,7 +22823,363 @@ Status register for the RF reset controller.
    3 -

    FSM_RESET_DONE

    +

    FSM_RESET_DONE

    +

    This bit asserts ('1') when the DB0 RF reset controller FSM + reset sequence is completed. The bitfield deasserts ('0') + after deasserting db0_fsm_reset.

    + +
    2..0 +

    Reserved

    +

    + +
    + +
    + +
    + + +

    Offset 0x12800: RF1_RESET_CONTROL_REG Register (R|W)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RF1_RESET_CONTROL_REG
      offset=0x12800
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000152800 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType RF_RESET_CONTROL_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +Control register for the RF reset controller. + Verify the FSM ID before polling starting any reset sequence. + To use the SW reset triggers: Wait until DB*_DONE is de-asserted. + Assert either the *_RESET or *_ENABLE bitfields. + Wait until DB*_DONE is asserted to release the trigger. + The DB*_DONE signal should then de-assert.
    + Note: The *_DB1 constants are not used in the HDL, their purpose is + merely for documentation.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..10 +

    Reserved

    +

    + +
    9 +

    DAC_ENABLE

    +

    Write a '1' to this bit to trigger the enable sequence for + the daughterboard 0 DAC chain. Write a '0' once + db0_dac_seq_done is asserted.

    + +
    8 +

    DAC_RESET

    +

    Write a '1' to this bit to trigger a reset for the + daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done + is asserted.

    + +
    7..6 +

    Reserved

    +

    + +
    5 +

    ADC_ENABLE

    +

    Write a '1' to this bit to trigger the enable sequence for + the daughterboard 0 ADC chain. Write a '0' once + db0_adc_seq_done is asserted.

    + +
    4 +

    ADC_RESET

    +

    Write a '1' to this bit to trigger a reset for the + daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done + is asserted.

    + +
    3..1 +

    Reserved

    +

    + +
    0 +

    FSM_RESET

    +

    Write a '1' to this bit to reset the RF reset controller. + Write a '0' once db0_fsm_reset_done asserts.

    + +
    + +
    + +
    + + +

    Offset 0x12808: RF1_RESET_STATUS_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RF1_RESET_STATUS_REG
      offset=0x12808
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000152808 + +
    + +

    + +

    Initial Value not specified +

    + +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType RF_RESET_STATUS_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +Status register for the RF reset controller. + Verify the FSM ID before polling starting any reset sequence. + Refer to RF*_RESET_CONTROL_REG for instructions on how to use + the status bits in this register.
    + Note: The *_DB1 constants are not used in the HDL, their purpose is + merely for documentation.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -19873,7 +23260,8 @@ Total Offset =

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType RF_AXI_STATUS_REGTYPE which is defined in HDL source file common_regs.v.

    @@ -19881,7 +23269,8 @@ Total Offset = Status register for the RF AXI-Stream interfaces.
    Note: The *_DB1 constants are not used in the HDL, their purpose is - merely for documentation. + merely for documentation.
    + @@ -20083,7 +23472,7 @@ Status register for the RF AXI-Stream interfaces.
    @@ -20128,7 +23517,8 @@ Total Offset =

    Initial Value = 0x00000000

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType FABRIC_DSP_REGTYPE which is defined in HDL source file common_regs.v.

    @@ -20143,7 +23533,8 @@ This register provides information to the driver on the type configure the RFDC with the proper settings. Also, channel count for the DSP module is included.
    Note: The *_DB1 constants are not used in the HDL, their purpose is - merely for documentation. + merely for documentation.
    + @@ -20151,142 +23542,10 @@ This register provides information to the driver on the type - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + +
    BitsName
    31..24 +

    Reserved

    +

    + +
    23..16 +

    Reserved

    +

    + +
    15..12 +

    Reserved

    +

    + +
    11 +

    DAC_SEQ_DONE

    +

    This bit asserts ('1') when the DB0 DAC chain reset sequence + is completed. The bitfield deasserts ('0') after + deasserting the issued triggered (enable or reset).

    + +
    10..8 +

    Reserved

    +

    + +
    7 +

    ADC_SEQ_DONE

    +

    This bit asserts ('1') when the DB0 ADC chain reset sequence + is completed. The bitfield deasserts ('0') after + deasserting the issued triggered (enable or reset).

    + +
    6..4 +

    Reserved

    +

    + +
    3 +

    FSM_RESET_DONE

    This bit asserts ('1') when the DB0 RF reset controller FSM reset sequence is completed. The bitfield deasserts ('0') after deasserting db0_fsm_reset.

    @@ -19828,7 +23215,7 @@ Status register for the RF reset controller.     		- +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    BitsName
    31..30 -

    FABRIC_DSP_TX_CNT_DB1   (initialvalue=0)

    -

    Fabric DSP TX channel count for daughterboard 0.

    - -
    29..28 -

    FABRIC_DSP_RX_CNT_DB1   (initialvalue=0)

    -

    Fabric DSP RX channel count for daughterboard 0.

    - -
    27..16 -

    FABRIC_DSP_BW_DB1   (initialvalue=FABRIC_DSP_BW_NONE)

    -

    Fabric DSP BW in MHz for daughterboard 1.

    - -

    - The values for this bitfield are in the FABRIC_DSP_BW_ENUM table. - (show here) -

    -
    - -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Value Name
    Dec Hex
    00x000 -

    FABRIC_DSP_BW_NONE

    - -
    1000x064 -

    FABRIC_DSP_BW_100M

    - -
    2000x0C8 -

    FABRIC_DSP_BW_200M

    - -
    4000x190 -

    FABRIC_DSP_BW_400M

    - -
    - -

    - This enumerated type is defined in HDL source file common_regs.v. -

    - -
    - -
    - -
    15..14 -

    FABRIC_DSP_TX_CNT   (initialvalue=0)

    -

    Fabric DSP TX channel count for daughterboard 0.

    - -
    13..12 -

    FABRIC_DSP_RX_CNT   (initialvalue=0)

    -

    Fabric DSP RX channel count for daughterboard 0.

    - -
    11..031..20

    FABRIC_DSP_BW   (initialvalue=FABRIC_DSP_BW_NONE)

    -

    Fabric DSP BW in MHz for daughterboard 0.

    +

    Fabric DSP BW in MHz for both daughterboards.

    The values for this bitfield are in the FABRIC_DSP_BW_ENUM table. @@ -20365,6 +23624,19 @@ This register provides information to the driver on the type

    10000x3E8 +

    FABRIC_DSP_BW_FULL

    + +

    @@ -20378,6 +23650,60 @@ This register provides information to the driver on the type

    19..18 +

    FABRIC_DSP_RESERVED_DB1   (initialvalue=0)

    +

    Reserved for future use.

    + +
    17..14 +

    FABRIC_DSP_TX_CNT_DB1   (initialvalue=0)

    +

    Fabric DSP TX channel count for daughterboard 0.

    + +
    13..10 +

    FABRIC_DSP_RX_CNT_DB1   (initialvalue=0)

    +

    Fabric DSP RX channel count for daughterboard 0.

    + +
    9..8 +

    FABRIC_DSP_RESERVED   (initialvalue=0)

    +

    Reserved for future use.

    + +
    7..4 +

    FABRIC_DSP_TX_CNT   (initialvalue=0)

    +

    Fabric DSP TX channel count for daughterboard 0.

    + +
    3..0 +

    FABRIC_DSP_RX_CNT   (initialvalue=0)

    +

    Fabric DSP RX channel count for daughterboard 0.

    + +
    @@ -20397,7 +23723,7 @@ This register provides information to the driver on the type - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -20442,7 +23768,7 @@ Total Offset =

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.

    @@ -20493,7 +23819,7 @@ The fields of this register provide data to all the DAC channels when enabled - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -20538,7 +23864,7 @@ Total Offset =

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.

    @@ -20582,10 +23908,19 @@ This register enables calibration data in the DAC data path for each of the - 7..6 + 7 -

    Reserved

    -

    +

    ENABLE_CALIBRATION_DATA_7

    +

    Enables calibration data for channel #1/3.

    + + + + + + 6 + +

    ENABLE_CALIBRATION_DATA_6

    +

    Enables calibration data for channel #1/2.

    @@ -20593,8 +23928,8 @@ This register enables calibration data in the DAC data path for each of the 5 -

    ENABLE_CALIBRATION_DATA_3

    -

    Enables calibration data for channel 3.

    +

    ENABLE_CALIBRATION_DATA_5

    +

    Enables calibration data for channel #1/1.

    @@ -20602,17 +23937,26 @@ This register enables calibration data in the DAC data path for each of the 4 -

    ENABLE_CALIBRATION_DATA_2

    -

    Enables calibration data for channel 2.

    +

    ENABLE_CALIBRATION_DATA_4

    +

    Enables calibration data for channel #1/0.

    - 3..2 + 3 -

    Reserved

    -

    +

    ENABLE_CALIBRATION_DATA_3

    +

    Enables calibration data for channel #0/3.

    + + + + + + 2 + +

    ENABLE_CALIBRATION_DATA_2

    +

    Enables calibration data for channel #0/2.

    @@ -20621,7 +23965,7 @@ This register enables calibration data in the DAC data path for each of the 1

    ENABLE_CALIBRATION_DATA_1

    -

    Enables calibration data for channel 1.

    +

    Enables calibration data for channel #0/1.

    @@ -20630,7 +23974,7 @@ This register enables calibration data in the DAC data path for each of the 0

    ENABLE_CALIBRATION_DATA_0

    -

    Enables calibration data for channel 0.

    +

    Enables calibration data for channel #0/0.

    @@ -20654,7 +23998,7 @@ This register enables calibration data in the DAC data path for each of the - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -20699,7 +24043,7 @@ Total Offset =

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.

    @@ -20738,9 +24082,36 @@ This register shows threshold status for the ADCs. Each bit reflects the - 15..12 + 15 -

    Reserved

    +

    ADC3_23_THRESHOLD2

    +

    + + + + + + 14 + +

    ADC3_23_THRESHOLD1

    +

    + + + + + + 13 + +

    ADC3_01_THRESHOLD2

    +

    + + + + + + 12 + +

    ADC3_01_THRESHOLD1

    @@ -20783,9 +24154,36 @@ This register shows threshold status for the ADCs. Each bit reflects the - 7..4 + 7 -

    Reserved

    +

    ADC1_23_THRESHOLD2

    +

    + + + + + + 6 + +

    ADC1_23_THRESHOLD1

    +

    + + + + + + 5 + +

    ADC1_01_THRESHOLD2

    +

    + + + + + + 4 + +

    ADC1_01_THRESHOLD1

    @@ -20846,7 +24244,7 @@ This register shows threshold status for the ADCs. Each bit reflects the - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -20891,7 +24289,7 @@ Total Offset =

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.

    @@ -20905,7 +24303,7 @@ Enable RF MMCM outputs. BitsName - 31..24 + 31..25

    Reserved

    @@ -20913,8 +24311,35 @@ Enable RF MMCM outputs. + + 24 + +

    ENABLE_RF1_CLK_2X

    +

    + + + + - 23..17 + 23..21 + +

    Reserved

    +

    + + + + + + 20 + +

    ENABLE_RF1_CLK

    +

    + + + + + + 19..17

    Reserved

    @@ -20943,7 +24368,7 @@ Enable RF MMCM outputs. 12 -

    ENABLE_RF_CLK_2X

    +

    ENABLE_RF0_CLK_2X

    @@ -20961,14 +24386,14 @@ Enable RF MMCM outputs. 8 -

    ENABLE_RF_CLK

    +

    ENABLE_RF0_CLK

    - 7..5 + 7..0

    Reserved

    @@ -20976,33 +24401,6 @@ Enable RF MMCM outputs. - - 4 - -

    ENABLE_DATA_CLK_2X

    -

    - - - - - - 3..1 - -

    Reserved

    -

    - - - - - - 0 - -

    ENABLE_DATA_CLK

    -

    - - - - @@ -21022,7 +24420,7 @@ Enable RF MMCM outputs. - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -21067,7 +24465,7 @@ Total Offset =

    Initial Value not specified

    -

    This register is defined in HDL source file common_regs.v.

    +

    This register is defined in HDL source file x440_rfdc_regs.v.

    @@ -21145,6 +24543,622 @@ Data Clk Pll Status Register + + +
    + + +

    Offset 0x17000: ADC_TILEMAP_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    ADC_TILEMAP_REG
      offset=0x17000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000157000 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType ADC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +This register describes how the ADCs map to the respective tiles. It + lets us designate an ADC as channel 0, channel 1, etc. depending on + how those channels are externally connected to the RFSoC.
    + + For every channel, this register stores the tile number and the block + number of the converter. This can be used to then address the correct + converter in the various Xilinx interfaces/APIs.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..30 +

    ADC_TILEMAP_DB1_CHAN3_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 3, daughterboard 1.

    + +
    29..28 +

    ADC_TILEMAP_DB1_CHAN3_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 3, daughterboard 1.

    + +
    27..26 +

    ADC_TILEMAP_DB1_CHAN2_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 2, daughterboard 1.

    + +
    25..24 +

    ADC_TILEMAP_DB1_CHAN2_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 2, daughterboard 1.

    + +
    23..22 +

    ADC_TILEMAP_DB1_CHAN1_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 1, daughterboard 1.

    + +
    21..20 +

    ADC_TILEMAP_DB1_CHAN1_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 1, daughterboard 1.

    + +
    19..18 +

    ADC_TILEMAP_DB1_CHAN0_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 0, daughterboard 1.

    + +
    17..16 +

    ADC_TILEMAP_DB1_CHAN0_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 0, daughterboard 1.

    + +
    15..14 +

    ADC_TILEMAP_DB0_CHAN3_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 3, daughterboard 0.

    + +
    13..12 +

    ADC_TILEMAP_DB0_CHAN3_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 3, daughterboard 0.

    + +
    11..10 +

    ADC_TILEMAP_DB0_CHAN2_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 2, daughterboard 0.

    + +
    9..8 +

    ADC_TILEMAP_DB0_CHAN2_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 2, daughterboard 0.

    + +
    7..6 +

    ADC_TILEMAP_DB0_CHAN1_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 1, daughterboard 0.

    + +
    5..4 +

    ADC_TILEMAP_DB0_CHAN1_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 1, daughterboard 0.

    + +
    3..2 +

    ADC_TILEMAP_DB0_CHAN0_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the ADC for channel 0, daughterboard 0.

    + +
    1..0 +

    ADC_TILEMAP_DB0_CHAN0_TILE   (initialvalue=0)

    +

    Tile number of the ADC for channel 0, daughterboard 0.

    + +
    + +
    + +
    + + +

    Offset 0x17008: DAC_TILEMAP_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    DAC_TILEMAP_REG
      offset=0x17008
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000157008 + +
    + +

    + +

    Initial Value = 0x00000000 +

    + +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType DAC_TILEMAP_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +This register describes how the DACs map to the respective tiles. It + lets us designate an DAC as channel 0, channel 1, etc. depending on + how those channels are externally connected to the RFSoC.
    + + For every channel, this register stores the tile number and the block + number of the converter. This can be used to then address the correct + converter in the various Xilinx interfaces/APIs.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..30 +

    DAC_TILEMAP_DB1_CHAN3_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 3, daughterboard 1.

    + +
    29..28 +

    DAC_TILEMAP_DB1_CHAN3_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 3, daughterboard 1.

    + +
    27..26 +

    DAC_TILEMAP_DB1_CHAN2_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 2, daughterboard 1.

    + +
    25..24 +

    DAC_TILEMAP_DB1_CHAN2_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 2, daughterboard 1.

    + +
    23..22 +

    DAC_TILEMAP_DB1_CHAN1_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 1, daughterboard 1.

    + +
    21..20 +

    DAC_TILEMAP_DB1_CHAN1_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 1, daughterboard 1.

    + +
    19..18 +

    DAC_TILEMAP_DB1_CHAN0_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 0, daughterboard 1.

    + +
    17..16 +

    DAC_TILEMAP_DB1_CHAN0_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 0, daughterboard 1.

    + +
    15..14 +

    DAC_TILEMAP_DB0_CHAN3_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 3, daughterboard 0.

    + +
    13..12 +

    DAC_TILEMAP_DB0_CHAN3_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 3, daughterboard 0.

    + +
    11..10 +

    DAC_TILEMAP_DB0_CHAN2_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 2, daughterboard 0.

    + +
    9..8 +

    DAC_TILEMAP_DB0_CHAN2_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 2, daughterboard 0.

    + +
    7..6 +

    DAC_TILEMAP_DB0_CHAN1_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 1, daughterboard 0.

    + +
    5..4 +

    DAC_TILEMAP_DB0_CHAN1_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 1, daughterboard 0.

    + +
    3..2 +

    DAC_TILEMAP_DB0_CHAN0_BLOCK   (initialvalue=0)

    +

    Block number (within the tile) of the DAC for channel 0, daughterboard 0.

    + +
    1..0 +

    DAC_TILEMAP_DB0_CHAN0_TILE   (initialvalue=0)

    +

    Tile number of the DAC for channel 0, daughterboard 0.

    + +
    + +
    + +
    + + +

    Offset 0x18000: RFDC_INFO_REG Register (R)

    + + (show extended info) +
    + + + + + + + + + + + + + + + +
    + + + +
    Port ARM_M_AXI_HPM0
    + +    		 + + + + +
    AXI_HPM0_REGMAP|RFDC_REGS
      0x1000140000
    + +    		 + + + + +
    RFDC_INFO_REG
      offset=0x18000
    + +    		 + + + + + +
    + + +Total Offset =
      0x1000158000 + +
    + +

    + +

    Initial Value = 0x00910091 +

    + +

    This register is defined in HDL source file x440_rfdc_regs.v.
    +It uses RegType RFDC_INFO_REGTYPE which is defined in HDL source file common_regs.v.

    + +
    + +
    + +This register provides information about how the RFDC is connected to + the rest of the fabric.
    + Specifically, between the actual RFDC and the RFNoC infrastructure, + there may be additional resampling (if the RFDC resampler cannot handle + all the resampling itself) and it is important to know how wide the + connection from the RFDC gearbox FIFO to the rest of the design is. + Note: The *_DB1 constants are not used in the HDL, their purpose is + merely for documentation.
    + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BitsName
    31..26 +

    Reserved

    +

    + +
    25..23 +

    RFDC_INFO_SPC_TX_DB1   (initialvalue=1)

    +

    Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 1.

    + +
    22..20 +

    RFDC_INFO_SPC_RX_DB1   (initialvalue=1)

    +

    Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 1.

    + +
    19..16 +

    RFDC_INFO_XTRA_RESAMP_DB1   (initialvalue=1)

    +

    Additional resampling happening outside the RFDC for daughterboard 0.

    + +
    15..10 +

    Reserved

    +

    + +
    9..7 +

    RFDC_INFO_SPC_TX   (initialvalue=1)

    +

    Log2 of SPC value for TX connection (fabric into RFDC) for daughterboard 0.

    + +
    6..4 +

    RFDC_INFO_SPC_RX   (initialvalue=1)

    +

    Log2 of SPC value for RX connection (RFDC into fabric) for daughterboard 0.

    + +
    3..0 +

    RFDC_INFO_XTRA_RESAMP   (initialvalue=1)

    +

    Additional resampling happening outside the RFDC for daughterboard 0.

    + +
    +
    @@ -21805,7 +25819,7 @@ Only 64 bits of data are available via this register interface.

    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -22083,7 +26097,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -22361,7 +26375,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -22639,7 +26653,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -22917,7 +26931,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -23195,7 +27209,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -23473,7 +27487,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -23757,7 +27771,7 @@ end - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -24035,7 +28049,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -24313,7 +28327,7 @@ Total Offset = - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -24846,9 +28860,9 @@ Daughterboard GPIO interface.
    - 537986582 + 570884374 - 0x20110616 + 0x22070116

    DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME

    @@ -24891,6 +28905,19 @@ FPGA version.
    + + + 0 + + 0x00000000 + + +

    FPGA_CURRENT_VERSION_MINOR

    + + + + + 0 @@ -24932,9 +28959,9 @@ FPGA version.
    - 7 + 8 - 0x00000007 + 0x00000008

    FPGA_CURRENT_VERSION_MAJOR

    @@ -24945,9 +28972,9 @@ FPGA version.
    - 7 + 8 - 0x00000007 + 0x00000008

    FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR

    @@ -24958,22 +28985,9 @@ FPGA version.
    - 10 + 587472913 - 0x0000000A - - -

    FPGA_CURRENT_VERSION_MINOR

    - - - - - - - - 571610633 - - 0x22121609 + 0x23042011

    FPGA_VERSION_LAST_MODIFIED_TIME

    @@ -24991,10 +29005,10 @@ FPGA version.
    - + -

    RF_CORE_100M_VERSION Enumeration

    -100 MHz RF core.
    +

    RF_CORE_FULL_VERSION Enumeration

    +Full BW RF core.
    For guidance on when to update these revision numbers, please refer to the register map documentation accordingly:
  • Current version: CURRENT_VERSION @@ -25023,7 +29037,7 @@ FPGA version.
    0x00000000 -

    RF_CORE_100M_CURRENT_VERSION_MINOR

    +

    RF_CORE_FULL_CURRENT_VERSION_MINOR

    @@ -25036,7 +29050,7 @@ FPGA version.
    0x00000000 -

    RF_CORE_100M_CURRENT_VERSION_BUILD

    +

    RF_CORE_FULL_CURRENT_VERSION_BUILD

    @@ -25049,7 +29063,7 @@ FPGA version.
    0x00000000 -

    RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR

    +

    RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR

    @@ -25062,7 +29076,7 @@ FPGA version.
    0x00000000 -

    RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD

    +

    RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD

    @@ -25075,7 +29089,7 @@ FPGA version.
    0x00000001 -

    RF_CORE_100M_CURRENT_VERSION_MAJOR

    +

    RF_CORE_FULL_CURRENT_VERSION_MAJOR

    @@ -25088,7 +29102,7 @@ FPGA version.
    0x00000001 -

    RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR

    +

    RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR

    @@ -25096,12 +29110,12 @@ FPGA version.
    - 537929239 + 570829056 - 0x20102617 + 0x22062900 -

    RF_CORE_100M_VERSION_LAST_MODIFIED_TIME

    +

    RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME

    @@ -25110,132 +29124,7 @@ FPGA version.

    - This enumerated type is defined in HDL source file rf_core_100m.v. -

    - - - -
    - - -

    RF_CORE_400M_VERSION Enumeration

    -400 MHz RF core.
    - For guidance on when to update these revision numbers, - please refer to the register map documentation accordingly: -
  • Current version: CURRENT_VERSION -
  • Oldest compatible version: OLDEST_COMPATIBLE_VERSION -
  • Version last modified: VERSION_LAST_MODIFIED - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Value Name
    Dec Hex
    00x00000000 -

    RF_CORE_400M_CURRENT_VERSION_MINOR

    - -
    00x00000000 -

    RF_CORE_400M_CURRENT_VERSION_BUILD

    - -
    00x00000000 -

    RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR

    - -
    00x00000000 -

    RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD

    - -
    10x00000001 -

    RF_CORE_400M_CURRENT_VERSION_MAJOR

    - -
    10x00000001 -

    RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR

    - -
    5379292390x20102617 -

    RF_CORE_400M_VERSION_LAST_MODIFIED_TIME

    - -
    - -

    - This enumerated type is defined in HDL source file rf_core_400m.v. + This enumerated type is defined in HDL source file rf_core_full.v.

    @@ -25354,7 +29243,7 @@ This enum contains indexes for all the components in the X410 - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -25496,7 +29385,7 @@ Component's current version.
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -25639,7 +29528,7 @@ Component's oldest compatible version.
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    @@ -25768,7 +29657,7 @@ Component's versions update time.
    - +
    Port ARM_M_AXI_HPM0
    Port ARM_M_AXI_HPM0
    diff --git a/top/x400/dts/usrp_x440_fpga_C1.dts b/top/x400/dts/usrp_x440_fpga_C1.dts new file mode 100644 index 0000000..9490f36 --- /dev/null +++ b/top/x400/dts/usrp_x440_fpga_C1.dts @@ -0,0 +1,20 @@ +/* + * Copyright 2021 Ettus Research, a National Instruments Brand + * + * SPDX-License-Identifier: LGPL-3.0-or-later + */ + +/dts-v1/; +/plugin/; + +#include "x440-version-info.dtsi" + +#include "x440-fpga.dtsi" + +#include "x4xx-common.dtsi" + +#include "x440-rfdc.dtsi" + +#include "x4xx-dma.dtsi" + +#include "x4xx-100gbe-port0.dtsi" diff --git a/top/x400/dts/usrp_x440_fpga_CG.dts b/top/x400/dts/usrp_x440_fpga_CG.dts new file mode 100644 index 0000000..2cbe6a9 --- /dev/null +++ b/top/x400/dts/usrp_x440_fpga_CG.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2022 Ettus Research, a National Instruments Brand + * + * SPDX-License-Identifier: LGPL-3.0-or-later + */ + +/dts-v1/; +/plugin/; + +#include "x440-version-info.dtsi" + +#include "x440-fpga.dtsi" + +#include "x4xx-common.dtsi" + +#include "x440-rfdc.dtsi" + +#include "x4xx-dma.dtsi" + +#include "x4xx-100gbe-port0.dtsi" + +#include "x4xx-100gbe-port1.dtsi" diff --git a/top/x400/dts/usrp_x440_fpga_X1.dts b/top/x400/dts/usrp_x440_fpga_X1.dts new file mode 100644 index 0000000..1124e98 --- /dev/null +++ b/top/x400/dts/usrp_x440_fpga_X1.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2021 Ettus Research, a National Instruments Brand + * + * SPDX-License-Identifier: LGPL-3.0-or-later + */ + +/dts-v1/; +/plugin/; + +#include "x440-version-info.dtsi" + +#include "x440-fpga.dtsi" + +#include "x4xx-common.dtsi" + +#include "x440-rfdc.dtsi" + +#include "x4xx-dma.dtsi" + +#include "x4xx-10gbe-port0.dtsi" + diff --git a/top/x400/dts/usrp_x440_fpga_X4.dts b/top/x400/dts/usrp_x440_fpga_X4.dts new file mode 100644 index 0000000..2185d0c --- /dev/null +++ b/top/x400/dts/usrp_x440_fpga_X4.dts @@ -0,0 +1,20 @@ +/* + * Copyright 2022 Ettus Research, a National Instruments Brand + * + * SPDX-License-Identifier: LGPL-3.0-or-later + */ + +/dts-v1/; +/plugin/; + +#include "x440-version-info.dtsi" + +#include "x440-fpga.dtsi" + +#include "x4xx-common.dtsi" + +#include "x440-rfdc.dtsi" + +#include "x4xx-dma.dtsi" + +#include "x4xx-10gbe-port0-x4.dtsi" diff --git a/top/x400/dts/x440-fpga.dtsi b/top/x400/dts/x440-fpga.dtsi new file mode 100644 index 0000000..570fc95 --- /dev/null +++ b/top/x400/dts/x440-fpga.dtsi @@ -0,0 +1,9 @@ +/* + * Copyright 2022 Ettus Research, a National Instruments Brand + * + * SPDX-License-Identifier: LGPL-3.0-or-later + */ + +&fpga_full { + firmware-name = "x440.bin"; +}; diff --git a/top/x400/dts/x440-rfdc.dtsi b/top/x400/dts/x440-rfdc.dtsi new file mode 100644 index 0000000..c786c8e --- /dev/null +++ b/top/x400/dts/x440-rfdc.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright 2021 Ettus Research, a National Instruments Brand + * + * SPDX-License-Identifier: LGPL-3.0-or-later + */ + +&fpga_full { + #address-cells = <2>; + #size-cells = <2>; + + misc_clk_1: misc_clk_1 { + #clock-cells = <0>; + clock-frequency = <40000000>; + compatible = "fixed-clock"; + }; + + misc_clk_2: misc_clk_2 { + #clock-cells = <0>; + clock-frequency = <184320000>; + compatible = "fixed-clock"; + }; + + rf_data_converter: usp_rf_data_converter@1000100000 { + clock-names = "s_axi_aclk", "m0_axis_aclk", "m1_axis_aclk", "m2_axis_aclk", "m3_axis_aclk", "s0_axis_aclk", "s1_axis_aclk"; + clocks = <&misc_clk_1>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>; + compatible = "xlnx,usp-rf-data-converter-2.1"; + num-insts = <0x1>; + param-list = [ 00 00 00 00 00 10 00 10 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 67 40 0a d7 a3 70 3d 0a 67 40 30 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 67 40 0a d7 a3 70 3d 0a 67 40 30 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 04 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 10 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 9a 99 99 99 99 99 19 40 00 00 00 00 00 00 b9 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 9a 99 99 99 99 99 19 40 00 00 00 00 00 00 b9 40 00 00 00 00 00 00 00 00 0a 00 00 00 02 00 00 00 01 00 00 00 00 00 00 00 9e ef a7 c6 4b 37 1a 40 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 77 40 0a d7 a3 70 3d 0a 67 40 18 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 77 40 0a d7 a3 70 3d 0a 67 40 18 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 77 40 0a d7 a3 70 3d 0a 67 40 18 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 01 00 00 00 0f d6 ff 39 cc 97 07 40 0a d7 a3 70 3d 0a 77 40 0a d7 a3 70 3d 0a 67 40 18 00 00 00 03 00 00 00 01 00 00 00 00 00 00 00 fc a9 f1 d2 4d 62 10 40 02 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00 01 00 00 00 08 00 00 00 02 00 00 00 00 00 00 00 02 00 00 00]; + reg = <0x00000010 0x00100000 0x0 0x40000>; + }; + + rfdc_regs: uio@1000140000 { + status = "okay"; + compatible = "usrp-uio"; + reg = <0x10 0x00140000 0x0 0x20000>; + reg-names = "rfdc-regs"; + }; +}; diff --git a/top/x400/ip/Makefile.inc b/top/x400/ip/Makefile.inc index eff9121..eefc18a 100644 --- a/top/x400/ip/Makefile.inc +++ b/top/x400/ip/Makefile.inc @@ -33,6 +33,14 @@ include $(IP_DIR)/dac_400m_bd/Makefile.inc include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc endif +ifdef X440 +include $(IP_DIR)/adc_full_bd/Makefile.inc +include $(IP_DIR)/adc_100m_bd/Makefile.inc +include $(IP_DIR)/dac_100m_bd/Makefile.inc +include $(IP_DIR)/ddr4_64bits_x440/Makefile.inc +include $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc +endif + BD_SRCS = \ $(IP_X4XX_PS_RFDC_BD_SRCS) \ $(IP_X4XX_PS_RFDC_HDL_SRCS) \ @@ -66,6 +74,16 @@ $(IP_DAC_400M_BD_SRCS) \ $(IP_DAC_400M_HDL_SRCS) endif +ifdef X440 +BD_SRCS += \ +$(IP_ADC_FULL_BD_SRCS) \ +$(IP_ADC_FULL_HDL_SRCS) \ +$(IP_ADC_100M_BD_SRCS) \ +$(IP_ADC_100M_HDL_SRCS) \ +$(IP_DAC_100M_BD_SRCS) \ +$(IP_DAC_100M_HDL_SRCS) +endif + IP_XCI_SRCS = \ $(IP_XGE_PCS_PMA_SRCS) \ $(IP_AXI64_4K_2CLK_FIFO_SRCS) \ @@ -79,6 +97,11 @@ IP_XCI_SRCS += \ $(IP_DDR4_64BITS_SRCS) endif +ifdef X440 +IP_XCI_SRCS += \ +$(IP_DDR4_64BITS_X440_SRCS) +endif + BD_OUTPUTS = \ $(BD_X4XX_PS_RFDC_BD_OUTS) \ $(BD_AXI_INTERCONNECT_APP_BD_OUTS) \ @@ -103,6 +126,13 @@ $(BD_DAC_100M_BD_OUTS) \ $(BD_DAC_400M_BD_OUTS) endif +ifdef X440 +BD_OUTPUTS += \ +$(BD_ADC_FULL_BD_OUTS) \ +$(BD_ADC_100M_BD_OUTS) \ +$(BD_DAC_100M_BD_OUTS) +endif + IP_SYNTH_OUTPUTS = \ $(IP_XGE_PCS_PMA_OUTS) \ $(IP_AXI64_4K_2CLK_FIFO_OUTS) \ @@ -116,6 +146,11 @@ IP_SYNTH_OUTPUTS += \ $(IP_DDR4_64BITS_OUTS) endif +ifdef X440 +IP_SYNTH_OUTPUTS += \ +$(IP_DDR4_64BITS_X440_OUTS) +endif + IP_HDL_SIM_SRCS = \ $(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \ $(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \ diff --git a/top/x400/ip/adc_full_bd/Makefile.inc b/top/x400/ip/adc_full_bd/Makefile.inc new file mode 100644 index 0000000..49adb24 --- /dev/null +++ b/top/x400/ip/adc_full_bd/Makefile.inc @@ -0,0 +1,38 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_ADC_FULL_ORIG_SRCS = $(addprefix $(IP_DIR)/adc_full_bd/, \ +adc_full_bd.tcl \ +) + +IP_ADC_FULL_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/, \ +common/adc_iq_repacker.v \ +) + +IP_ADC_FULL_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \ +adc_full_bd.tcl \ +) + +IP_ADC_FULL_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \ +adc_full_bd/adc_full_bd.bd \ +) + +BD_ADC_FULL_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \ +adc_full_bd.bd.out \ +adc_full_bd/adc_full_bd_ooc.xdc \ +adc_full_bd/synth/adc_full_bd.v \ +) + +EMPTY_IP_SRCS = + +.INTERMEDIATE: IP_ADC_FULL_BD_TRGT +$(IP_ADC_FULL_BD_SRCS) $(BD_ADC_FULL_BD_OUTS) $(IP_ADC_FULL_BDTCL_SRCS): IP_ADC_FULL_BD_TRGT + @: + +IP_ADC_FULL_BD_TRGT: $(IP_ADC_FULL_ORIG_SRCS) $(IP_ADC_FULL_HDL_SRCS) + $(call BUILD_VIVADO_BDTCL,adc_full_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_FULL_HDL_SRCS),) diff --git a/top/x400/ip/adc_full_bd/adc_full_bd.tcl b/top/x400/ip/adc_full_bd/adc_full_bd.tcl new file mode 100644 index 0000000..bcd8c25 --- /dev/null +++ b/top/x400/ip/adc_full_bd/adc_full_bd.tcl @@ -0,0 +1,338 @@ + +################################################################ +# This is a generated script based on design: adc_full_bd +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2021.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source adc_full_bd_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# adc_iq_repacker + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu28dr-ffvg1517-2-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name adc_full_bd + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + + # Add USER_COMMENTS on $design_name + set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name] + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axis_register_slice:1.1\ +xilinx.com:ip:xlconstant:1.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +################################################################## +# CHECK Modules +################################################################## +set bCheckModules 1 +if { $bCheckModules == 1 } { + set list_check_mods "\ +adc_iq_repacker\ +" + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {512000000} \ + ] $adc_data_out + + set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {512000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {16} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $adc_i_data_in + + set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {512000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {16} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $adc_q_data_in + + + # Create ports + set enable_data_to_repacker_rclk [ create_bd_port -dir I enable_data_to_repacker_rclk ] + set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ] + set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 512000000 rfdc_clk ] + set swap_iq_rclk [ create_bd_port -dir I swap_iq_rclk ] + + # Create instance: adc_data_to_axi, and set properties + set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ] + set_property -dict [ list \ + CONFIG.REG_CONFIG {1} \ + CONFIG.TDATA_NUM_BYTES {32} \ + ] $adc_data_to_axi + + # Create instance: adc_i_data_from_axi, and set properties + set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ] + set_property -dict [ list \ + CONFIG.REG_CONFIG {0} \ + CONFIG.TDATA_NUM_BYTES {16} \ + ] $adc_i_data_from_axi + + # Create instance: adc_iq_repacker, and set properties + set block_name adc_iq_repacker + set block_cell_name adc_iq_repacker + if { [catch {set adc_iq_repacker [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $adc_iq_repacker eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + set_property -dict [ list \ + CONFIG.SPC {8} \ + ] $adc_iq_repacker + + # Create instance: adc_q_data_from_axi, and set properties + set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ] + set_property -dict [ list \ + CONFIG.REG_CONFIG {0} \ + CONFIG.TDATA_NUM_BYTES {16} \ + ] $adc_q_data_from_axi + + # Create instance: const_1, and set properties + set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ] + + # Create interface connections + connect_bd_intf_net -intf_net adc_i_data_in_1 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS] + connect_bd_intf_net -intf_net adc_iq_repacker_0_data_out [get_bd_intf_pins adc_data_to_axi/S_AXIS] [get_bd_intf_pins adc_iq_repacker/data_out] + connect_bd_intf_net -intf_net adc_q_data_from_axi1_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS] + connect_bd_intf_net -intf_net adc_q_data_in_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS] + + # Create port connections + connect_bd_net -net adc_i_data_from_axi_m_axis_tdata [get_bd_pins adc_i_data_from_axi/m_axis_tdata] [get_bd_pins adc_iq_repacker/adc_i_in] + connect_bd_net -net adc_i_data_from_axi_m_axis_tvalid [get_bd_pins adc_i_data_from_axi/m_axis_tvalid] [get_bd_pins adc_iq_repacker/valid_in] + connect_bd_net -net adc_q_data_from_axi_m_axis_tdata [get_bd_pins adc_iq_repacker/adc_q_in] [get_bd_pins adc_q_data_from_axi/m_axis_tdata] + connect_bd_net -net const_1_dout [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout] + connect_bd_net -net enable_data_to_repacker_rclk_1 [get_bd_ports enable_data_to_repacker_rclk] [get_bd_pins adc_iq_repacker/enable] + connect_bd_net -net rfdc_adc_axi_resetn_rclk_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_data_to_axi/aresetn] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn] + connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_iq_repacker/clk] [get_bd_pins adc_q_data_from_axi/aclk] + connect_bd_net -net swap_iq_rclk_1 [get_bd_ports swap_iq_rclk] [get_bd_pins adc_iq_repacker/swap_iq] + + # Create address segments + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/top/x400/ip/adc_full_bd/hdl_sources.tcl b/top/x400/ip/adc_full_bd/hdl_sources.tcl new file mode 100644 index 0000000..f8a9765 --- /dev/null +++ b/top/x400/ip/adc_full_bd/hdl_sources.tcl @@ -0,0 +1,6 @@ +set script_loc [file normalize [info script]] +set script_dir [file dirname $script_loc] + +# Vivado's block diagram default library for files not belonging to any special +# library is called xil_defaultlib +read_verilog -library xil_defaultlib $script_dir/../../rf/common/adc_iq_repacker.v diff --git a/top/x400/ip/ddr4_64bits_x440/Makefile.inc b/top/x400/ip/ddr4_64bits_x440/Makefile.inc new file mode 100644 index 0000000..9ebc6bf --- /dev/null +++ b/top/x400/ip/ddr4_64bits_x440/Makefile.inc @@ -0,0 +1,21 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_DDR4_64BITS_X440_SRCS = \ +$(IP_BUILD_DIR)/ddr4_64bits_x440/ddr4_64bits_x440.xci + +IP_DDR4_64BITS_X440_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr4_64bits_x440/, \ +ddr4_64bits_x440.xci.out \ +) + +.INTERMEDIATE: IP_DDR4_64BITS_X440_TRGT +$(IP_DDR4_64BITS_X440_SRCS) $(IP_DDR4_64BITS_X440_OUTS): IP_DDR4_64BITS_X440_TRGT + @: + +IP_DDR4_64BITS_X440_TRGT: $(IP_DIR)/ddr4_64bits_x440/ddr4_64bits_x440.xci + $(call BUILD_VIVADO_IP,ddr4_64bits_x440,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0) diff --git a/top/x400/ip/ddr4_64bits_x440/ddr4_64bits_x440.xci b/top/x400/ip/ddr4_64bits_x440/ddr4_64bits_x440.xci new file mode 100644 index 0000000..6407de3 --- /dev/null +++ b/top/x400/ip/ddr4_64bits_x440/ddr4_64bits_x440.xci @@ -0,0 +1,493 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr4_64bits_x440 + + + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + + + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + + 0 + 0 + 0 + 32 + 0 + 0 + 0 + + 512 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 4 + 0 + 256 + 2 + 1 + 2 + 1 + 0.0 + AXI4 + READ_WRITE + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 29 + 512 + 64 + X0Y11 + X0Y10 + X0Y70 + X0Y11 + 0 + 0 + DDR4_SDRAM + 17 + 0 + false + 32 + 512 + 4 + 1 + 2 + 0 + 0 + 0 + 1 + 1 + 0 + 15 + 9996 + 5 + 0 + VCO_2X + 10 + 8Gb + 29 + 1 + 0 + 0 + 8 + 8 + 0 + 938 + 1 + 8 + 8 + 64 + false + 0 + 1.2V + false + No + 1600 + 0 + 0 + MT40A512M16HA-075E + Components + 16 + 8Gb + 8 + 8192 + 16 + 4294967296 + 750 + DDR4_750_Timing + 0 + 0 + ROW_COLUMN_BANK + 1 + 0 + 1 + 16 + 0 + 0 + 075E + 1 + 1 + 300000000 + 1 + 1 + 0.84 + 0 + 4 + 1 + 5 + 833 + 0 + 37 + 16 + 2 + 39 + 17 + 9363 + 421 + 145 + 17 + + 8 + 7 + 4 + 10 + 19 + + 10 + 4 + 109 + 128 + 0 + 256 + DDR4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + FALSE + 9996 + 0 + 0 + 0 + 0 + 0 + 0 + NONE + Disable + 1 + 0.0 + 0 + 0.0 + 0 + 0.0 + 0 + 0.0 + 0 + 1 + BFM + Differential + None + None + None + None + 0 + 17 + 1 + 1 + 1 + 1 + DDR4_SDRAM + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + false + false + 32 + RD_PRI_REG + 512 + 4 + false + true + 0 + 0 + 0 + 0 + 8 + Sequential + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 15 + 5 + 0 + 0 + 0 + 0 + 512 + 17 + 12 + true + false + no_file_loaded + 1 + DM_NO_DBI + 64 + false + false + false + 9996 + 0 + 0 + false + ROW_COLUMN_BANK + MainMemory + MT40A512M16HA-075E + Components + 1.2V + 0 + 0 + 0 + 0 + RZQ/6 + Normal + RZQ/7 + 0 + 4:1 + false + false + false + Single + false + 0 + 0 + 0 + 0 + 833 + false + false + false + 0 + 0 + 0 + 5 + 1 + false + 1 + 1 + Custom + Custom + false + ddr4_64bits_x440 + false + false + Disable + false + false + true + SIMPLE_TG + OFF + false + 1 + false + false + 1 + false + 1 + Complete_Memory_Controller + false + Custom + Differential + false + BFM + Differential + false + false + false + zynquplusRFSOC + + + xczu28dr + ffvg1517 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 12 + TRUE + . + + . + 2021.1_AR76780 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc b/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc deleted file mode 100644 index ebb0fd9..0000000 --- a/top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc +++ /dev/null @@ -1,50 +0,0 @@ -# -# Copyright 2021 Ettus Research, a National Instruments Brand -# -# SPDX-License-Identifier: LGPL-3.0-or-later -# - -include $(TOOLS_DIR)/make/viv_ip_builder.mak - -IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/, \ -x4xx_ps_rfdc_bd.tcl \ -) - -IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \ -capture_sysref.v \ -rf_nco_reset.vhd \ -rf_reset_controller.vhd \ -rf_reset.vhd \ -clock_gates.vhd \ -sync_wrapper.v \ -axis_mux.vhd \ -gpio_to_axis_mux.vhd \ -) \ -$(addprefix $(BASE_DIR)/../lib/control/, \ -synchronizer.v \ -synchronizer_impl.v \ -) \ -$(addprefix $(BASE_DIR)/x400/regmap/, PkgRFDC_REGS_REGMAP.vhd ) - -IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \ -x4xx_ps_rfdc_bd.tcl \ -) - -IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \ -x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.bd \ -) - -BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \ -x4xx_ps_rfdc_bd.bd.out \ -x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd_ooc.xdc \ -x4xx_ps_rfdc_bd/synth/x4xx_ps_rfdc_bd.v \ -) - -EMPTY_IP_SRCS = - -.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT -$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT - @: - -IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS) - $(call BUILD_VIVADO_BDTCL,x4xx_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS)) diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl b/top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl deleted file mode 100644 index 65c3aa6..0000000 --- a/top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl +++ /dev/null @@ -1,14 +0,0 @@ -set script_loc [file normalize [info script]] -set script_dir [file dirname $script_loc] - -read_verilog -library work $script_dir/../../rf/common/capture_sysref.v -read_verilog -library work $script_dir/../../../../lib/control/synchronizer.v -read_verilog -library work $script_dir/../../../../lib/control/synchronizer_impl.v -read_verilog -library work $script_dir/../../rf/common/sync_wrapper.v -read_vhdl -library work $script_dir/../../rf/common/rf_nco_reset.vhd -read_vhdl -library work $script_dir/../../regmap/PkgRFDC_REGS_REGMAP.vhd -read_vhdl -library work $script_dir/../../rf/common/rf_reset_controller.vhd -read_vhdl -library work $script_dir/../../rf/common/rf_reset.vhd -read_vhdl -library work $script_dir/../../rf/common/clock_gates.vhd -read_vhdl -library work $script_dir/../../rf/common/axis_mux.vhd -read_vhdl -library work $script_dir/../../rf/common/gpio_to_axis_mux.vhd diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/regmap/common_regs.v b/top/x400/ip/x4xx_ps_rfdc_bd/regmap/common_regs.v deleted file mode 100644 index 00c7187..0000000 --- a/top/x400/ip/x4xx_ps_rfdc_bd/regmap/common_regs.v +++ /dev/null @@ -1,550 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Company -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: common_regs -// Description: -// Registers definition within the x4xx_ps_rfdc_bd IP. - -//XmlParse xml_on -// -// -// -// This section lists all common Processing System ports through -// which the register maps in this project are accessed. Each input -// port to the fabric will point to a regmap. -// -// -// -// This is the main AXI4-Lite master interface that the PS -// exposes to the kernel to interact with the FPGA fabric. -// There are multiple endpoints connected to this interface. -// -// -// -// -// This is one of the two cache-coherent AXI slave ports available to -// communicate from the fabric (master) to the PS (slave). -// -// -// -// -// This is one of the two cache-coherent AXI slave ports available to -// communicate from the fabric (master) to the PS (slave). -// -// -// -// -// This is the SPI1 interface -// (see Zynq UltraScale+ Devices Register Reference) -// of the PS. -// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br} -// The request format on SPI is defined as.{br} -// {b}Write request:{/b} -// {ul} -// {li}1'b1 = write -// {li}15 bit address -// {li}32 bit data (MOSI) -// {li}8 bit processing gap -// {li}5 bit padding -// {li}1 bit ack -// {li}2 bit status -// {/ul} -// {b}Read request:{/b} -// {ul} -// {li}1'b0 = read -// {li}15 bit address -// {li}8 bit processing gap -// {li}32 bit data (MISO) -// {li}5 bit padding -// {li}1 bit ack -// {li}2 bit status -// {/ul} -// -// -// -// -// -// -// -// -// -// -// -// This is the map for the register space that the Processing System's -// M_AXI_HPM0_FPD port (AXI4 master interface) has access to. -// This port has a 40-bit address bus. -// -// -// -// Space reserved for RPU access -// -// -// Register space for the JTAG engine for MB CPLD programming. -// -// -// Register space reserved for future use. -// -// -// MPM endpoint fro MB/DB communication. -// -// -// Register space reserved for mboard-regs (Core). -// -// -// AXI DMA engine for internal Ethernet interface. -// -// -// Misc. registers for internal Ethernet. -// -// -// Register space occupied by the Xilinx RFDC IP block. -// -// -// Register space for RFDC control/status registers. -// -// -// -// -// -// -// This is the map that the nixge driver uses in Ethernet DMA to -// move data between the Processing System's architecture and the fabric. -// This map is a combination of two main components: a Xilix AXI DMA engine -// and some registers for MAC/PHY control. -// -// -// -// -// Refer to Xilinx' AXI DMA v7.1 IP product guide for further -// information on this register map: -// https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf -// -// -// -// MAC/PHY control for the Ethernet interface. -// -// -// -// -// -// This is a regmap to document the different ports that have access to the PS system memory. -// Each port may have different restrictions on system memory. See the corresponding window -// for details -// -// -// -// -// The HPC0 port of the PS is used for general purpose cache-coherent accesses -// to the PS system memory. Different applications may use it for different -// purposes. Its access is configured as follows: {br} -// {table border="1"} -// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr} -// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr} -// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr} -// {tr}{td}0xFF000000{/td} {td}0x01000000{/td} {td}LPS_OCM{/td}{tr} -// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr} -// {/table} -// -// -// -// -// -// -// The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave -// interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx. -// Its access is configured as follows: {br} -// {table border="1"} -// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr} -// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr} -// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr} -// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr} -// {/table} -// -// -// -// -// -// -// -// -// These are the registers located within the RFDC block design -// that provide control and status support for the RF chain. -// -// -// -// -// Register space for controlling the data clock MMCM instance -// within the RFDC block design. -// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the -// regiter space description in chapter 2. -// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf) -// -// -// -// -// Control register for inverting I/Q data. -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// Control register for resetting the data clock MMCM. -// -// -// Write a '1' to this bit to reset the MMCM. Then write a -// '0' to place the MMCM out of reset. -// -// -// -// -// -// -// Control register for the RF reset controller. -// Verify the FSM ID before polling starting any reset sequence. -// To use the SW reset triggers: Wait until DB*_DONE is de-asserted. -// Assert either the *_RESET or *_ENABLE bitfields. -// Wait until DB*_DONE is asserted to release the trigger. -// The DB*_DONE signal should then de-assert.{BR/} -// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is -// merely for documentation.{/b} -// -// -// -// Write a '1' to this bit to reset the RF reset controller. -// Write a '0' once db0_fsm_reset_done asserts. -// -// -// -// -// Write a '1' to this bit to trigger a reset for the -// daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done -// is asserted. -// -// -// -// -// Write a '1' to this bit to trigger the enable sequence for -// the daughterboard 0 ADC chain. Write a '0' once -// db0_adc_seq_done is asserted. -// -// -// -// -// Write a '1' to this bit to trigger a reset for the -// daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done -// is asserted. -// -// -// -// -// Write a '1' to this bit to trigger the enable sequence for -// the daughterboard 0 DAC chain. Write a '0' once -// db0_dac_seq_done is asserted. -// -// -// -// -// -// -// Status register for the RF reset controller. -// Verify the FSM ID before polling starting any reset sequence. -// Refer to RF_RESET_CONTROL_REG for instructions on how to use -// the status bits in this register.{BR/} -// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is -// merely for documentation.{/b} -// -// -// -// This bit asserts ('1') when the DB0 RF reset controller FSM -// reset sequence is completed. The bitfield deasserts ('0') -// after deasserting db0_fsm_reset. -// -// -// -// -// This bit asserts ('1') when the DB0 ADC chain reset sequence -// is completed. The bitfield deasserts ('0') after -// deasserting the issued triggered (enable or reset). -// -// -// -// -// This bit asserts ('1') when the DB0 DAC chain reset sequence -// is completed. The bitfield deasserts ('0') after -// deasserting the issued triggered (enable or reset). -// -// -// -// -// -// -// Status register for the RF AXI-Stream interfaces.{BR/} -// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is -// merely for documentation.{/b} -// -// -// -// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream -// TReady handshake signals. The LSB is channel 0 and the MSB -// is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream -// TValid handshake signals. The LSB is channel 0 and the MSB -// is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream -// TReady handshake signals (Q portion). The LSB is channel 0 -// and the MSB is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream -// TReady handshake signals (I portion). The LSB is channel 0 -// and the MSB is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream -// TValid handshake signals (Q portion). The LSB is channel 0 -// and the MSB is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream -// TValid handshake signals (I portion). The LSB is channel 0 -// and the MSB is channel 1. -// -// -// -// -// This bitfield is wired to the user's ADC (DB0) AXI-Stream -// TValid handshake signals. The LSB is channel 0 and the MSB -// is channel 1. -// -// -// -// -// This bitfield is wired to the user's ADC (DB0) AXI-Stream -// TReady handshake signals. The LSB is channel 0 and the MSB -// is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream -// TReady handshake signals. The LSB is channel 0 and the MSB -// is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream -// TValid handshake signals. The LSB is channel 0 and the MSB -// is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream -// TReady handshake signals (Q portion). The LSB is channel 0 -// and the MSB is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream -// TReady handshake signals (I portion). The LSB is channel 0 -// and the MSB is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream -// TValid handshake signals (Q portion). The LSB is channel 0 -// and the MSB is channel 1. -// -// -// -// -// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream -// TValid handshake signals (I portion). The LSB is channel 0 -// and the MSB is channel 1. -// -// -// -// -// This bitfield is wired to the user's ADC (DB1) AXI-Stream -// TValid handshake signals. The LSB is channel 0 and the MSB -// is channel 1. -// -// -// -// -// This bitfield is wired to the user's ADC (DB1) AXI-Stream -// TReady handshake signals. The LSB is channel 0 and the MSB -// is channel 1. -// -// -// -// -// -// -// The fields of this register provide data to all the DAC channels when enabled -// by the CALIBRATION_ENABLE register. -// -// -// -// -// -// -// -// -// -// This register enables calibration data in the DAC data path for each of the -// four channels. Each of these bits is normally '0'. When written '1', DAC data -// for the corresponding channel will be constantly driven with the contents of -// the CALIBRATION_DATA register. -// -// -// -// Enables calibration data for channel 0. -// -// -// -// -// Enables calibration data for channel 1. -// -// -// -// -// Enables calibration data for channel 2. -// -// -// -// -// Enables calibration data for channel 3. -// -// -// -// -// -// -// Enable RF MMCM outputs. -// -// -// -// -// -// -// -// -// -// -// Data Clk Pll Status Register -// -// -// -// -// -// -// -// This register shows threshold status for the ADCs. Each bit reflects the -// RFDC's real-time ADC status signals, which will assert when the ADC input -// signal exceeds the programmed threshold value. The status will remain -// asserted until cleared by software. -// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is -// the location of the tile in the converter column and ZZ is either 01 (the -// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile). -// See also the Xilinx document PG269. -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// -// This register provides information to the driver on the type -// of DSP that is instantiated in the fabric.{BR/} -// The X410 platform supports multiple RF daughterboards, each requiring -// a different fabric RF DSP chain that works with specific RFDC settings. -// Each bandwidth DSP chain has a unique identifier (BW in MHz), this -// information is conveyed in this register to let the driver -// configure the RFDC with the proper settings. -// Also, channel count for the DSP module is included.{BR/} -// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is -// merely for documentation.{/b} -// -// -// Fabric DSP BW in MHz for daughterboard 0. -// -// -// Fabric DSP RX channel count for daughterboard 0. -// -// -// Fabric DSP TX channel count for daughterboard 0. -// -// -// Fabric DSP BW in MHz for daughterboard 1. -// -// -// Fabric DSP RX channel count for daughterboard 0. -// -// -// Fabric DSP TX channel count for daughterboard 0. -// -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/regmap/uhd_regs.v b/top/x400/ip/x4xx_ps_rfdc_bd/regmap/uhd_regs.v deleted file mode 100644 index 329393b..0000000 --- a/top/x400/ip/x4xx_ps_rfdc_bd/regmap/uhd_regs.v +++ /dev/null @@ -1,336 +0,0 @@ -// -// Copyright 2021 Ettus Research, A National Instruments Company -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: uhd_regs -// Description: -// Registers definition within the x4xx_ps_rfdc_bd IP. - -//XmlParse xml_on -// -// -// -// 100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187. -// -// - http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf -// -// -// -// - -//XmlParse xml_on -// -// -// -// -// 10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf -// -// -// -// - - -// -// -// -// Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11 -// -// - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf -// -// -// -// - -// -// -// -// -// -// -// nixge (maps to 10g mac if present) -// -// -// -// -// Constant indicating version for this space. -// Not used by the NIXGE driver (12/4/2020) -// -// -// -// -// Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL. -// -// -// -// -// Generically means that a connection with a peer has been established. Specific -// meaning varies based on the MGT_PROTOCOL. -// -// -// -// -// Constant indicating what flavor of communication this port is using -// -// - 0 = NONE -// - 1 = 1GbE -// - 2 = 10GbE -// - 3 = Aurora -// - 4 = WhiteRabbit -// - 5 = 100GbE -// -// -// -// -// -// Constant indicating which port this register is hooked to -// -// - 0 = QSFP0 -// - 1 = QSFP1 -// -// -// -// -// -// -// Definition of this register depends on Protocol -// -// **10GBE** -// -// *READ - Status* -// -// - 0 = status_crc_error -// - 1 = status_fragment_error -// - 2 = status_txdfifo_ovflow -// - 3 = status_txdfifo_udflow -// - 4 = status_rxdfifo_ovflow -// - 5 = status_rxdfifo_udflow -// - 6 = status_pause_frame_rx -// - 7 = status_local_fault -// - 8 = status_remote_fault -// -// *WRITE - Ctl* -// -// - 0 = ctrl_tx_enable -// -// **100 GBE** -// -// *READ - Status* -// -// - 0 = tx_ovfout - Sets if TX overflow reported by CMAC -// (Stays set till MAC is reset). This is a fatal error -// - 1 = tx_unfout - Sets if TX underflow reported by CMAC -// (Stays set till MAC is reset). This is a fatal error -// - 2 = stat_rx_aligned - goes high when CMAC has finished -// alignment, and is ready to start reception of traffic. -// - 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID) -// but upstream is trying to hold(TREADY)off we drop a packet. -// Upstream circuitry should detect this when traffic is forked -// between CHDR and CPU, so this bit will only set if there is a -// HW design error. -// - 4 = auto_config_done - This bit goes high when the auto_config -// state machine finishes operation. It is very similiar to -// stat_rx_alligned, but waits for extra writes which occur -// after allignement to complete. -// - 24:16 = pause_mask - readable version of pause_mask bellow. -// -// *WRITE - Ctl* -// -// - 0 = auto_enable - Defaults to ON after reset - Enables a -// state machine that performs CMAC register writes to -// bring up the MAC without SW intervention. -// - 24:16 = pause_mask - A second layer of enables(the first being -// register in the CMAC) on the pause_request mechanic. Bits -// 7:0 of enable pause on PFC7:0. Bit 8 enables global pause -// request (not priority controlled). The mask is used for TX -// and RX. -// -// -// -// -// -// Definition of this register depends on Protocol -// -// **10GBE** -// -// *READ - Status * -// -// - 0 = core_status 0 - link_up -// - 1 = core_status 1 -// - 2 = core_status 2 -// - 3 = core_status 3 -// - 4 = core_status 4 -// - 5 = core_status 5 -// - 6 = core_status 6 -// - 7 = core_status 7 -// -// **100 GBE** -// -// *READ - Status* -// -// - 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets. -// - 1 = usr_rx_reset - RX PLL's have locked -// -// -// -// -// -// -// When set identify_value is used to control the activity LED. -// When clear the activity LED set on any TX or RX traffic to the mgt -// -// -// -// -// When identify_enable is set, this value controls the activity LED. -// -// -// -// -// -// The x4xx family of products does not use MDIO. -// -// -// -// -// Only valid if the protocol is Aurora. -// -// -// -// -// Only valid if the protocol is Aurora. -// -// -// -// -// Only valid if the protocol is Aurora. -// -// -// -// -// Only valid if the protocol is Aurora. -// -// -// -// -// -// -// -// -// UIO -// -// -// -// Set this port's IP address -// -// -// -// -// Set the UDP port for CHDR_traffic -// -// -// -// -// If BRIDGE_ENABLE is set use this MAC_ID -// -// -// -// -// If BRIDGE_ENABLE is set use this MAC_ID -// -// -// -// -// If BRIDGE_ENABLE is set use this IP Address -// -// -// -// -// If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic -// -// -// -// -// Bit 0 Controls the following logic -// -//```verilog -// always_comb begin : bridge_mux -// my_mac = bridge_en ? bridge_mac_reg : mac_reg; -// my_ip = bridge_en ? bridge_ip_reg : ip_reg; -// my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port; -// end -//``` -// -// -// -// -// -// Count the number of Packets dropped that were addressed to the CHDR section. -// -// -// -// -// Count the number of Packets dropped that were addressed to us, but not to the CHDR section. -// -// -// -// -// -// If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only -// used with 100Gb ethernet -// -// -// -// -// If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause. -// *Pause clear must be less than pause set or terrible things will happen.* -// The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only -// used with 100Gb ethernet -// -// -// -// -// - -// -// -// -// Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations -// -// - 1X10GB Ethernet - Using OpenCore XGE MAC -// - 1x100GB Ethernet - Using Xilinx CMAC -// - (future possible) - Xilinx Aurora (various rates and lane widths) -// - (future possible) - 4X10GB Ethernet -// -// -// -// -// -// -// -// - - -// -// -// -// - 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0 -// - 0_1 indicates QSFP0 - Lane1 -// - 0_2 indicates QSFP0 - Lane2 -// - 0_3 indicates QSFP0 - Lane3 -// - 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1 -// - 1_1 indicates QSFP1 - Lane1 -// - 1_2 indicates QSFP1 - Lane2 -// - 1_3 indicates QSFP1 - Lane3 -// -// -// -// -// -// -// -// -// -// -// -//XmlParse xml_off diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc new file mode 100644 index 0000000..9da4907 --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc @@ -0,0 +1,56 @@ +# +# Copyright 2022 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/, \ +x440_ps_rfdc_bd.tcl \ +) + +IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \ +capture_sysref.v \ +rf_nco_reset.vhd \ +rf_reset.vhd \ +sync_wrapper.v \ +axis_mux.vhd \ +gpio_to_axis_mux.vhd \ +) \ +$(addprefix $(BASE_DIR)/x400/rf/x440/, \ +x440_clock_gates.vhd \ +x440_rf_reset_controller.vhd \ +x440_rfdc_tx_control_remap.v \ +) \ +$(addprefix $(BASE_DIR)/../lib/control/, \ +synchronizer.v \ +synchronizer_impl.v \ +) \ +$(addprefix $(BASE_DIR)/x400/regmap/x440/, \ +PkgRFDC_REGS_REGMAP.vhd \ +rfdc_mapping_regmap_utils.vh \ +) + +IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \ +x440_ps_rfdc_bd.tcl \ +) + +IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \ +x440_ps_rfdc_bd/x440_ps_rfdc_bd.bd \ +) + +BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \ +x440_ps_rfdc_bd.bd.out \ +x440_ps_rfdc_bd/x440_ps_rfdc_bd_ooc.xdc \ +x440_ps_rfdc_bd/synth/x440_ps_rfdc_bd.v \ +) + +EMPTY_IP_SRCS = + +.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT +$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT + @: + +IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS) + $(call BUILD_VIVADO_BDTCL,x440_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR)/x4xx_ps_rfdc_bd,$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS)) diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/hdl_sources.tcl b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/hdl_sources.tcl new file mode 100644 index 0000000..cf00c76 --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/hdl_sources.tcl @@ -0,0 +1,16 @@ +set script_loc [file normalize [info script]] +set script_dir [file dirname $script_loc] + +read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v +read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v +read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v +read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v +read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh +read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v +read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd +read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd +read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd +read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd +read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd +read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd +read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/regmap/x440_rfdc_regs.v b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/regmap/x440_rfdc_regs.v new file mode 100644 index 0000000..8a11d71 --- /dev/null +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/regmap/x440_rfdc_regs.v @@ -0,0 +1,262 @@ +// +// Copyright 2022 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: x440_rfdc_regs +// Description: +// Registers definition within the x4xx_ps_rfdc_bd IP. + +//XmlParse xml_on +// +// +// +// This section lists all common Processing System ports through +// which the register maps in this project are accessed. Each input +// port to the fabric will point to a regmap. +// +// +// +// This is the main AXI4-Lite master interface that the PS +// exposes to the kernel to interact with the FPGA fabric. +// There are multiple endpoints connected to this interface. +// +// +// +// +// This is one of the two cache-coherent AXI slave ports available to +// communicate from the fabric (master) to the PS (slave). +// +// +// +// +// This is one of the two cache-coherent AXI slave ports available to +// communicate from the fabric (master) to the PS (slave). +// +// +// +// +// This is the SPI1 interface +// (see Zynq UltraScale+ Devices Register Reference) +// of the PS. +// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br} +// The request format on SPI is defined as.{br} +// {b}Write request:{/b} +// {ul} +// {li}1'b1 = write +// {li}15 bit address +// {li}32 bit data (MOSI) +// {li}8 bit processing gap +// {li}5 bit padding +// {li}1 bit ack +// {li}2 bit status +// {/ul} +// {b}Read request:{/b} +// {ul} +// {li}1'b0 = read +// {li}15 bit address +// {li}8 bit processing gap +// {li}32 bit data (MISO) +// {li}5 bit padding +// {li}1 bit ack +// {li}2 bit status +// {/ul} +// +// +// +// +// +// +// +// +// +// +// +// +// These are the registers located within the RFDC block design +// that provide control and status support for the RF chain. +// +// +// +// +// Register space for controlling the data clock MMCM instance +// within the RFDC block design. +// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the +// regiter space description in chapter 2. +// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf) +// +// +// +// +// Control register for inverting I/Q data. +// +// +// +// +// +// +// +// +// +// +// +// Control register for inverting I/Q data. +// +// +// +// +// +// +// +// +// +// +// +// Control register for resetting the data clock MMCM. +// +// +// Write a '1' to this bit to reset the MMCM. Then write a +// '0' to place the MMCM out of reset. +// +// +// +// +// +// +// +// +// +// +// +// +// +// The fields of this register provide data to all the DAC channels when enabled +// by the CALIBRATION_ENABLE register. +// +// +// +// +// +// +// +// +// +// This register enables calibration data in the DAC data path for each of the +// four channels. Each of these bits is normally '0'. When written '1', DAC data +// for the corresponding channel will be constantly driven with the contents of +// the CALIBRATION_DATA register. +// +// +// +// Enables calibration data for channel #0/0. +// +// +// +// +// Enables calibration data for channel #0/1. +// +// +// +// +// Enables calibration data for channel #0/2. +// +// +// +// +// Enables calibration data for channel #0/3. +// +// +// +// +// Enables calibration data for channel #1/0. +// +// +// +// +// Enables calibration data for channel #1/1. +// +// +// +// +// Enables calibration data for channel #1/2. +// +// +// +// +// Enables calibration data for channel #1/3. +// +// +// +// +// +// +// Enable RF MMCM outputs. +// +// +// +// +// +// +// +// +// +// +// Data Clk Pll Status Register +// +// +// +// +// +// +// +// This register shows threshold status for the ADCs. Each bit reflects the +// RFDC's real-time ADC status signals, which will assert when the ADC input +// signal exceeds the programmed threshold value. The status will remain +// asserted until cleared by software. +// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is +// the location of the tile in the converter column and ZZ is either 01 (the +// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile). +// See also the Xilinx document PG269. +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/synthstub/x440_ps_rfdc_bd.vhd similarity index 81% rename from top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd rename to top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/synthstub/x440_ps_rfdc_bd.vhd index fd853cd..2e1feaa 100644 --- a/top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/synthstub/x440_ps_rfdc_bd.vhd @@ -1,9 +1,9 @@ ------------------------------------------------------------------------------------------ -- --- File: x4xx_ps_rfdc_bd.vhd +-- File: x440_ps_rfdc_bd.vhd -- Author: niBlockDesign::niBdExportStub -- Original Project: HwBuildTools --- Date: 27 September 2021 +-- Date: 06 September 2022 -- ------------------------------------------------------------------------------------------ -- (c) Copyright National Instruments Corporation @@ -12,7 +12,7 @@ ------------------------------------------------------------------------------------------ -- -- Purpose: This is an automatically generated stub file to match the entity --- declaration for 'x4xx_ps_rfdc_bd'. This file was created using niBdExportStub +-- declaration for 'x440_ps_rfdc_bd'. This file was created using niBdExportStub -- Do not modify this file directly! -- ------------------------------------------------------------------------------------------ @@ -22,37 +22,44 @@ use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; -entity x4xx_ps_rfdc_bd is +entity x440_ps_rfdc_bd is port ( adc_data_out_resetn_dclk : out STD_LOGIC; - adc_enable_data_rclk : out STD_LOGIC; - adc_reset_pulse_dclk : in STD_LOGIC; - adc_rfdc_axi_resetn_rclk : out STD_LOGIC; + adc_enable_data_r0clk : out STD_LOGIC; + adc_enable_data_r1clk : out STD_LOGIC; + adc_reset_pulse_r0clk : in STD_LOGIC; + adc_reset_pulse_r1clk : in STD_LOGIC; + adc_resetn_r0clk2x : out STD_LOGIC; + adc_resetn_r1clk2x : out STD_LOGIC; + adc_rfdc_axi_resetn_r0clk : out STD_LOGIC; + adc_rfdc_axi_resetn_r1clk : out STD_LOGIC; bus_clk : in STD_LOGIC; bus_rstn : in STD_LOGIC; clk40 : in STD_LOGIC; clk40_rstn : in STD_LOGIC; - dac_data_in_resetn_dclk : out STD_LOGIC; - dac_data_in_resetn_dclk2x : out STD_LOGIC; - dac_data_in_resetn_rclk : out STD_LOGIC; - dac_data_in_resetn_rclk2x : out STD_LOGIC; - dac_reset_pulse_dclk : in STD_LOGIC; - data_clk : out STD_LOGIC; - data_clk_2x : out STD_LOGIC; + dac_data_in_resetn_r0clk : out STD_LOGIC; + dac_data_in_resetn_r0clk2x : out STD_LOGIC; + dac_data_in_resetn_r1clk : out STD_LOGIC; + dac_data_in_resetn_r1clk2x : out STD_LOGIC; + dac_reset_pulse_r0clk : in STD_LOGIC; + dac_reset_pulse_r1clk : in STD_LOGIC; data_clock_locked : out STD_LOGIC; enable_gated_clocks_clk40 : in STD_LOGIC; - enable_sysref_rclk : in STD_LOGIC; - fir_resetn_rclk2x : out STD_LOGIC; + enable_sysref_r0clk : in STD_LOGIC; + enable_sysref_r1clk : in STD_LOGIC; gated_base_clks_valid_clk40 : out STD_LOGIC; - invert_adc_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); - invert_dac_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + invert_adc_iq_r0clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + invert_adc_iq_r1clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + invert_dac_iq_r0clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + invert_dac_iq_r1clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); irq0_lpd_rpu_n : in STD_LOGIC; irq1_lpd_rpu_n : in STD_LOGIC; jtag0_tck : inout STD_LOGIC; jtag0_tdi : inout STD_LOGIC; jtag0_tdo : in STD_LOGIC; jtag0_tms : inout STD_LOGIC; - nco_reset_done_dclk : out STD_LOGIC; + nco_reset_done_r0clk : out STD_LOGIC; + nco_reset_done_r1clk : out STD_LOGIC; pl_clk40 : out STD_LOGIC; pl_clk100 : out STD_LOGIC; pl_clk166 : out STD_LOGIC; @@ -65,15 +72,18 @@ port ( pl_resetn3 : out STD_LOGIC; pll_ref_clk_in : in STD_LOGIC; pll_ref_clk_out : out STD_LOGIC; + radio0_rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 ); + radio0_rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 ); + radio1_rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 ); + radio1_rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 ); rf_axi_status_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 ); rf_dsp_info_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 ); - rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 ); rfdc_irq : out STD_LOGIC; s_axi_hp0_aclk : in STD_LOGIC; s_axi_hp1_aclk : in STD_LOGIC; s_axi_hpc0_aclk : in STD_LOGIC; - start_nco_reset_dclk : in STD_LOGIC; + start_nco_reset_r0clk : in STD_LOGIC; + start_nco_reset_r1clk : in STD_LOGIC; sysref_out_pclk : out STD_LOGIC; sysref_out_rclk : out STD_LOGIC; sysref_pl_in : in STD_LOGIC; @@ -201,8 +211,20 @@ port ( s_axi_hpc0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); adc0_clk_clk_n : in STD_LOGIC; adc0_clk_clk_p : in STD_LOGIC; + adc1_clk_clk_n : in STD_LOGIC; + adc1_clk_clk_p : in STD_LOGIC; adc2_clk_clk_n : in STD_LOGIC; adc2_clk_clk_p : in STD_LOGIC; + adc3_clk_clk_n : in STD_LOGIC; + adc3_clk_clk_p : in STD_LOGIC; + adc_tile225_ch0_vin_v_n : in STD_LOGIC; + adc_tile225_ch0_vin_v_p : in STD_LOGIC; + adc_tile225_ch1_vin_v_n : in STD_LOGIC; + adc_tile225_ch1_vin_v_p : in STD_LOGIC; + adc_tile227_ch0_vin_v_n : in STD_LOGIC; + adc_tile227_ch0_vin_v_p : in STD_LOGIC; + adc_tile227_ch1_vin_v_n : in STD_LOGIC; + adc_tile227_ch1_vin_v_p : in STD_LOGIC; m_axi_app_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 ); m_axi_app_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_app_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); @@ -226,6 +248,18 @@ port ( dac0_clk_clk_p : in STD_LOGIC; dac1_clk_clk_n : in STD_LOGIC; dac1_clk_clk_p : in STD_LOGIC; + dac_tile228_ch2_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile228_ch2_din_tvalid : in STD_LOGIC; + dac_tile228_ch2_din_tready : out STD_LOGIC; + dac_tile228_ch3_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile228_ch3_din_tvalid : in STD_LOGIC; + dac_tile228_ch3_din_tready : out STD_LOGIC; + dac_tile229_ch2_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile229_ch2_din_tvalid : in STD_LOGIC; + dac_tile229_ch2_din_tready : out STD_LOGIC; + dac_tile229_ch3_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); + dac_tile229_ch3_din_tvalid : in STD_LOGIC; + dac_tile229_ch3_din_tready : out STD_LOGIC; gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 ); gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 ); @@ -310,6 +344,14 @@ port ( m_axi_mpm_ep_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_mpm_ep_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_mpm_ep_rready : out STD_LOGIC_VECTOR ( 0 to 0 ); + dac_tile228_ch0_vout_v_n : out STD_LOGIC; + dac_tile228_ch0_vout_v_p : out STD_LOGIC; + dac_tile228_ch1_vout_v_n : out STD_LOGIC; + dac_tile228_ch1_vout_v_p : out STD_LOGIC; + dac_tile229_ch0_vout_v_n : out STD_LOGIC; + dac_tile229_ch0_vout_v_p : out STD_LOGIC; + dac_tile229_ch1_vout_v_n : out STD_LOGIC; + dac_tile229_ch1_vout_v_p : out STD_LOGIC; adc_tile224_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); adc_tile224_ch0_dout_i_tready : in STD_LOGIC; adc_tile224_ch0_dout_i_tvalid : out STD_LOGIC; @@ -322,6 +364,18 @@ port ( adc_tile224_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); adc_tile224_ch1_dout_q_tready : in STD_LOGIC; adc_tile224_ch1_dout_q_tvalid : out STD_LOGIC; + adc_tile225_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile225_ch0_dout_i_tready : in STD_LOGIC; + adc_tile225_ch0_dout_i_tvalid : out STD_LOGIC; + adc_tile225_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile225_ch0_dout_q_tready : in STD_LOGIC; + adc_tile225_ch0_dout_q_tvalid : out STD_LOGIC; + adc_tile225_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile225_ch1_dout_i_tready : in STD_LOGIC; + adc_tile225_ch1_dout_i_tvalid : out STD_LOGIC; + adc_tile225_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile225_ch1_dout_q_tready : in STD_LOGIC; + adc_tile225_ch1_dout_q_tvalid : out STD_LOGIC; adc_tile226_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); adc_tile226_ch0_dout_i_tready : in STD_LOGIC; adc_tile226_ch0_dout_i_tvalid : out STD_LOGIC; @@ -334,14 +388,26 @@ port ( adc_tile226_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); adc_tile226_ch1_dout_q_tready : in STD_LOGIC; adc_tile226_ch1_dout_q_tvalid : out STD_LOGIC; - dac_tile228_ch0_vout_v_n : out STD_LOGIC; - dac_tile228_ch0_vout_v_p : out STD_LOGIC; - dac_tile228_ch1_vout_v_n : out STD_LOGIC; - dac_tile228_ch1_vout_v_p : out STD_LOGIC; - dac_tile229_ch0_vout_v_n : out STD_LOGIC; - dac_tile229_ch0_vout_v_p : out STD_LOGIC; - dac_tile229_ch1_vout_v_n : out STD_LOGIC; - dac_tile229_ch1_vout_v_p : out STD_LOGIC; + adc_tile227_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile227_ch0_dout_i_tready : in STD_LOGIC; + adc_tile227_ch0_dout_i_tvalid : out STD_LOGIC; + adc_tile227_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile227_ch0_dout_q_tready : in STD_LOGIC; + adc_tile227_ch0_dout_q_tvalid : out STD_LOGIC; + adc_tile227_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile227_ch1_dout_i_tready : in STD_LOGIC; + adc_tile227_ch1_dout_i_tvalid : out STD_LOGIC; + adc_tile227_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 ); + adc_tile227_ch1_dout_q_tready : in STD_LOGIC; + adc_tile227_ch1_dout_q_tvalid : out STD_LOGIC; + dac_tile228_ch2_vout_v_n : out STD_LOGIC; + dac_tile228_ch2_vout_v_p : out STD_LOGIC; + dac_tile228_ch3_vout_v_n : out STD_LOGIC; + dac_tile228_ch3_vout_v_p : out STD_LOGIC; + dac_tile229_ch2_vout_v_n : out STD_LOGIC; + dac_tile229_ch2_vout_v_p : out STD_LOGIC; + dac_tile229_ch3_vout_v_n : out STD_LOGIC; + dac_tile229_ch3_vout_v_p : out STD_LOGIC; dac_tile228_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 ); dac_tile228_ch0_din_tvalid : in STD_LOGIC; dac_tile228_ch0_din_tready : out STD_LOGIC; @@ -404,8 +470,8 @@ port ( s_axi_hpc1_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_hpc1_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ) ); - end entity x4xx_ps_rfdc_bd; + end entity x440_ps_rfdc_bd; -architecture stub of x4xx_ps_rfdc_bd is +architecture stub of x440_ps_rfdc_bd is begin end architecture stub; diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl similarity index 78% rename from top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl rename to top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl index 9ffe461..e6a04ee 100644 --- a/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl @@ -1,6 +1,6 @@ ################################################################ -# This is a generated script based on design: x4xx_ps_rfdc_bd +# This is a generated script based on design: x440_ps_rfdc_bd # # Though there are limitations about the generated script, # the main purpose of this utility is to make learning @@ -35,12 +35,12 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ################################################################ # To test this script, run the following commands from Vivado Tcl console: -# source x4xx_ps_rfdc_bd_script.tcl +# source x440_ps_rfdc_bd_script.tcl # The design that will be created by this Tcl script contains the following # module references: -# capture_sysref, clock_gates, rf_nco_reset, rf_reset_controller, gpio_to_axis_mux +# capture_sysref, x440_clock_gates, rf_nco_reset, x440_rf_reset_controller, x440_rf_reset_controller, gpio_to_axis_mux, x440_rfdc_tx_control_remap # Please add the sources of those modules before sourcing this Tcl script. @@ -50,13 +50,13 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { set list_projs [get_projects -quiet] if { $list_projs eq "" } { - create_project project_1 myproj -part xczu28dr-ffvg1517-1-e + create_project project_1 myproj -part xczu28dr-ffvg1517-2-e } # CHANGE DESIGN NAME HERE variable design_name -set design_name x4xx_ps_rfdc_bd +set design_name x440_ps_rfdc_bd # If you do not already have an existing IP Integrator design open, # you can create a design using the following command: @@ -122,6 +122,12 @@ if { ${design_name} eq "" } { set_property USER_COMMENTS.comment_3 "reg_invert_iq: [15:8] = invert DAC channels [7:0] = invert ADC channels" [get_bd_designs $design_name] + set_property USER_COMMENTS.comment_4 "The ADC/DAC mappings need to match the RFDC settings, +but there's no clear way to pull them out of the RFDC configuration +above. This means that the values in these constants need to be +manually matched to the RFDC configuration object. + +The format of the ADC/DAC maps is documented in gen_x4xx_rfdc_regmap.py." [get_bd_designs $design_name] common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." @@ -175,10 +181,12 @@ set bCheckModules 1 if { $bCheckModules == 1 } { set list_check_mods "\ capture_sysref\ -clock_gates\ +x440_clock_gates\ rf_nco_reset\ -rf_reset_controller\ +x440_rf_reset_controller\ +x440_rf_reset_controller\ gpio_to_axis_mux\ +x440_rfdc_tx_control_remap\ " set list_mods_missing "" @@ -244,32 +252,56 @@ proc create_hier_cell_rf_clock_buffers { parentCell nameHier } { # Create interface pins # Create pins - create_bd_pin -dir O -from 0 -to 0 rfdc_clk - create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x - create_bd_pin -dir I -from 0 -to 0 rfdc_clk_2x_ce - create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_2x_pll - create_bd_pin -dir I -from 0 -to 0 rfdc_clk_ce - create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_pll + create_bd_pin -dir I -from 0 -to 0 radio0_rfdc_clk_2x_ce + create_bd_pin -dir I -from 0 -to 0 -type clk radio0_rfdc_clk_2x_pll + create_bd_pin -dir I -from 0 -to 0 radio0_rfdc_clk_ce + create_bd_pin -dir I -from 0 -to 0 -type clk radio0_rfdc_clk_pll + create_bd_pin -dir I -from 0 -to 0 radio1_rfdc_clk_2x_ce + create_bd_pin -dir I -from 0 -to 0 -type clk radio1_rfdc_clk_2x_pll + create_bd_pin -dir I -from 0 -to 0 radio1_rfdc_clk_ce + create_bd_pin -dir I -from 0 -to 0 -type clk radio1_rfdc_clk_pll + create_bd_pin -dir O -from 0 -to 0 rf0_clk_1x + create_bd_pin -dir O -from 0 -to 0 rf0_clk_2x + create_bd_pin -dir O -from 0 -to 0 rf1_clk_1x + create_bd_pin -dir O -from 0 -to 0 rf1_clk_2x - # Create instance: rfdc_clk_1x_buf, and set properties - set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_1x_buf ] + # Create instance: rf0_clk_1x_buf, and set properties + set rf0_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf0_clk_1x_buf ] set_property -dict [ list \ CONFIG.C_BUF_TYPE {BUFGCE} \ - ] $rfdc_clk_1x_buf + ] $rf0_clk_1x_buf - # Create instance: rfdc_clk_2x_buf, and set properties - set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_2x_buf ] + # Create instance: rf0_clk_2x_buf, and set properties + set rf0_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf0_clk_2x_buf ] set_property -dict [ list \ CONFIG.C_BUF_TYPE {BUFGCE} \ - ] $rfdc_clk_2x_buf + ] $rf0_clk_2x_buf + + # Create instance: rf1_clk_1x_buf, and set properties + set rf1_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf1_clk_1x_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {BUFGCE} \ + ] $rf1_clk_1x_buf + + # Create instance: rf1_clk_2x_buf, and set properties + set rf1_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf1_clk_2x_buf ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {BUFGCE} \ + ] $rf1_clk_2x_buf # Create port connections - connect_bd_net -net BUFGCE_I2_1 [get_bd_pins rfdc_clk_2x_pll] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_I] - connect_bd_net -net rfdc_clk_1 [get_bd_pins rfdc_clk_pll] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_I] - connect_bd_net -net rfdc_clk_1x_buf_BUFGCE_O [get_bd_pins rfdc_clk] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_O] - connect_bd_net -net rfdc_clk_2x_buf_BUFGCE_O [get_bd_pins rfdc_clk_2x] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_O] - connect_bd_net -net rfdc_clk_2x_ce_1 [get_bd_pins rfdc_clk_2x_ce] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_CE] - connect_bd_net -net rfdc_clk_ce_1 [get_bd_pins rfdc_clk_ce] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_CE] + connect_bd_net -net BUFGCE_I2_1 [get_bd_pins radio0_rfdc_clk_2x_pll] [get_bd_pins rf0_clk_2x_buf/BUFGCE_I] + connect_bd_net -net radio0_rfdc_clk_2x_ce1_1 [get_bd_pins radio1_rfdc_clk_2x_ce] [get_bd_pins rf1_clk_2x_buf/BUFGCE_CE] + connect_bd_net -net radio0_rfdc_clk_pll1_1 [get_bd_pins radio1_rfdc_clk_pll] [get_bd_pins rf1_clk_1x_buf/BUFGCE_I] + connect_bd_net -net radio0_rfdc_clk_pll2_1 [get_bd_pins radio1_rfdc_clk_2x_pll] [get_bd_pins rf1_clk_2x_buf/BUFGCE_I] + connect_bd_net -net radio1_rfdc_clk_ce [get_bd_pins radio1_rfdc_clk_ce] [get_bd_pins rf1_clk_1x_buf/BUFGCE_CE] + connect_bd_net -net rf1_clk_1x_buf_BUFGCE_O [get_bd_pins rf1_clk_1x] [get_bd_pins rf1_clk_1x_buf/BUFGCE_O] + connect_bd_net -net rf1_clk_2x_buf_BUFGCE_O [get_bd_pins rf1_clk_2x] [get_bd_pins rf1_clk_2x_buf/BUFGCE_O] + connect_bd_net -net rfdc_clk_1 [get_bd_pins radio0_rfdc_clk_pll] [get_bd_pins rf0_clk_1x_buf/BUFGCE_I] + connect_bd_net -net rfdc_clk_1x_buf_BUFGCE_O [get_bd_pins rf0_clk_1x] [get_bd_pins rf0_clk_1x_buf/BUFGCE_O] + connect_bd_net -net rfdc_clk_2x_buf_BUFGCE_O [get_bd_pins rf0_clk_2x] [get_bd_pins rf0_clk_2x_buf/BUFGCE_O] + connect_bd_net -net rfdc_clk_2x_ce_1 [get_bd_pins radio0_rfdc_clk_2x_ce] [get_bd_pins rf0_clk_2x_buf/BUFGCE_CE] + connect_bd_net -net rfdc_clk_ce_1 [get_bd_pins radio0_rfdc_clk_ce] [get_bd_pins rf0_clk_1x_buf/BUFGCE_CE] # Restore current instance current_bd_instance $oldCurInst @@ -316,21 +348,38 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } { create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch2_din + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch3_din + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch2_din + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch3_din + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_0_0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_0_1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_1_0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_1_1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_2_0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_2_1 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_3_0 + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_3_1 + # Create pins create_bd_pin -dir I -type clk s_axi_aclk_0 + create_bd_pin -dir I -type clk s_axi_aclk_1 create_bd_pin -dir I -type rst s_axi_config_aresetn create_bd_pin -dir I -type clk s_axi_config_clk @@ -357,6 +406,17 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } { CONFIG.kGpioWidth {32} \ ] $gpio_to_axis_mux_0 + # Create instance: x440_rfdc_tx_control_0, and set properties + set block_name x440_rfdc_tx_control_remap + set block_cell_name x440_rfdc_tx_control_0 + if { [catch {set x440_rfdc_tx_control_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $x440_rfdc_tx_control_0 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + # Create interface connections connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axis_0_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_0] connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins m_axis_1_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_1] @@ -364,16 +424,26 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } { connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins m_axis_3_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_3] connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins dac_tile228_ch0_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_0] connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins dac_tile228_ch1_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_1] - connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins dac_tile229_ch0_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_2] - connect_bd_intf_net -intf_net Conn8 [get_bd_intf_pins dac_tile229_ch1_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_3] connect_bd_intf_net -intf_net Conn10 [get_bd_intf_pins S_AXI_1] [get_bd_intf_pins axi_gpio_data/S_AXI] + connect_bd_intf_net -intf_net dac_tile228_ch2_din_1 [get_bd_intf_pins dac_tile228_ch2_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_2] + connect_bd_intf_net -intf_net dac_tile228_ch3_din_1 [get_bd_intf_pins dac_tile228_ch3_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_3] + connect_bd_intf_net -intf_net dac_tile229_ch0_din_1 [get_bd_intf_pins dac_tile229_ch0_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_4] + connect_bd_intf_net -intf_net dac_tile229_ch1_din_1 [get_bd_intf_pins dac_tile229_ch1_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_5] + connect_bd_intf_net -intf_net dac_tile229_ch2_din_1 [get_bd_intf_pins dac_tile229_ch2_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_6] + connect_bd_intf_net -intf_net dac_tile229_ch3_din_1 [get_bd_intf_pins dac_tile229_ch3_din] [get_bd_intf_pins gpio_to_axis_mux_0/s_axis_7] + connect_bd_intf_net -intf_net gpio_to_axis_mux_0_m_axis_4 [get_bd_intf_pins m_axis_0_1] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_4] + connect_bd_intf_net -intf_net gpio_to_axis_mux_0_m_axis_5 [get_bd_intf_pins m_axis_1_1] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_5] + connect_bd_intf_net -intf_net gpio_to_axis_mux_0_m_axis_6 [get_bd_intf_pins m_axis_2_1] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_6] + connect_bd_intf_net -intf_net gpio_to_axis_mux_0_m_axis_7 [get_bd_intf_pins m_axis_3_1] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_7] # Create port connections connect_bd_net -net Net [get_bd_pins s_axi_config_clk] [get_bd_pins axi_gpio_data/s_axi_aclk] connect_bd_net -net Net1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins axi_gpio_data/s_axi_aresetn] connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_data/gpio_io_o] [get_bd_pins gpio_to_axis_mux_0/gpio] - connect_bd_net -net axi_gpio_data_gpio2_io_o [get_bd_pins axi_gpio_data/gpio2_io_o] [get_bd_pins gpio_to_axis_mux_0/mux_select] + connect_bd_net -net axi_gpio_data_gpio2_io_o [get_bd_pins axi_gpio_data/gpio2_io_o] [get_bd_pins x440_rfdc_tx_control_0/input_controls] connect_bd_net -net s_axi_aclk_0_1 [get_bd_pins s_axi_aclk_0] [get_bd_pins gpio_to_axis_mux_0/m_axis_0_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_1_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_2_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_3_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_0_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_1_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_2_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_3_aclk] + connect_bd_net -net s_axi_aclk_1_1 [get_bd_pins s_axi_aclk_1] [get_bd_pins gpio_to_axis_mux_0/m_axis_4_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_5_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_6_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_7_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_4_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_5_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_6_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_7_aclk] + connect_bd_net -net x440_rfdc_tx_control_0_output_controls [get_bd_pins gpio_to_axis_mux_0/mux_select] [get_bd_pins x440_rfdc_tx_control_0/output_controls] # Restore current instance current_bd_instance $oldCurInst @@ -422,10 +492,18 @@ proc create_hier_cell_ThresholdRegister { parentCell nameHier } { create_bd_pin -dir I -from 0 -to 0 In1 create_bd_pin -dir I -from 0 -to 0 In2 create_bd_pin -dir I -from 0 -to 0 In3 + create_bd_pin -dir I -from 0 -to 0 In4 create_bd_pin -dir I -from 0 -to 0 In5 create_bd_pin -dir I -from 0 -to 0 In6 create_bd_pin -dir I -from 0 -to 0 In7 create_bd_pin -dir I -from 0 -to 0 In8 + create_bd_pin -dir I -from 0 -to 0 In9 + create_bd_pin -dir I -from 0 -to 0 In10 + create_bd_pin -dir I -from 0 -to 0 In11 + create_bd_pin -dir I -from 0 -to 0 In12 + create_bd_pin -dir I -from 0 -to 0 In13 + create_bd_pin -dir I -from 0 -to 0 In14 + create_bd_pin -dir I -from 0 -to 0 In15 create_bd_pin -dir I -type rst s_axi_config_aresetn create_bd_pin -dir I -type clk s_axi_config_clk @@ -433,37 +511,38 @@ proc create_hier_cell_ThresholdRegister { parentCell nameHier } { set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] set_property -dict [ list \ CONFIG.C_ALL_INPUTS {1} \ - CONFIG.C_GPIO_WIDTH {12} \ + CONFIG.C_GPIO_WIDTH {16} \ ] $axi_gpio_0 # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] set_property -dict [ list \ - CONFIG.NUM_PORTS {9} \ + CONFIG.NUM_PORTS {16} \ ] $xlconcat_0 - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_WIDTH {4} \ - ] $xlconstant_0 - # Create interface connections connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] # Create port connections connect_bd_net -net In0_1 [get_bd_pins In0] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net In10_1 [get_bd_pins In10] [get_bd_pins xlconcat_0/In10] + connect_bd_net -net In11_1 [get_bd_pins In11] [get_bd_pins xlconcat_0/In11] + connect_bd_net -net In12_1 [get_bd_pins In12] [get_bd_pins xlconcat_0/In12] + connect_bd_net -net In13_1 [get_bd_pins In13] [get_bd_pins xlconcat_0/In13] + connect_bd_net -net In14_1 [get_bd_pins In14] [get_bd_pins xlconcat_0/In14] + connect_bd_net -net In15_1 [get_bd_pins In15] [get_bd_pins xlconcat_0/In15] connect_bd_net -net In1_1 [get_bd_pins In1] [get_bd_pins xlconcat_0/In1] connect_bd_net -net In2_1 [get_bd_pins In2] [get_bd_pins xlconcat_0/In2] connect_bd_net -net In3_1 [get_bd_pins In3] [get_bd_pins xlconcat_0/In3] + connect_bd_net -net In4_1 [get_bd_pins In4] [get_bd_pins xlconcat_0/In4] connect_bd_net -net In5_1 [get_bd_pins In5] [get_bd_pins xlconcat_0/In5] connect_bd_net -net In6_1 [get_bd_pins In6] [get_bd_pins xlconcat_0/In6] connect_bd_net -net In7_1 [get_bd_pins In7] [get_bd_pins xlconcat_0/In7] connect_bd_net -net In8_1 [get_bd_pins In8] [get_bd_pins xlconcat_0/In8] + connect_bd_net -net In9_1 [get_bd_pins In9] [get_bd_pins xlconcat_0/In9] connect_bd_net -net s_axi_config_aresetn_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins axi_gpio_0/s_axi_aclk] connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_gpio_0/gpio_io_i] [get_bd_pins xlconcat_0/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In4] [get_bd_pins xlconstant_0/dout] # Restore current instance current_bd_instance $oldCurInst @@ -697,8 +776,12 @@ proc create_hier_cell_rfdc { parentCell nameHier } { # Create interface pins create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc1_clk + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc2_clk + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc3_clk + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_i create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_q @@ -711,6 +794,18 @@ proc create_hier_cell_rfdc { parentCell nameHier } { create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch1_vin + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch0_vin + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch1_vin + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_i create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_q @@ -723,6 +818,18 @@ proc create_hier_cell_rfdc { parentCell nameHier } { create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch1_vin + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile227_ch0_vin + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_i + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_q + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile227_ch1_vin + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk @@ -735,6 +842,14 @@ proc create_hier_cell_rfdc { parentCell nameHier } { create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch1_vout + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch2_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch2_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch3_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch3_vout + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch0_vout @@ -743,18 +858,27 @@ proc create_hier_cell_rfdc { parentCell nameHier } { create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch1_vout + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch2_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch2_vout + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch3_din + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch3_vout + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_config create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_usp_rf_data_converter:diff_pins_rtl:1.0 sysref_rf_in # Create pins - create_bd_pin -dir O adc_data_out_resetn_dclk + create_bd_pin -dir O -from 0 -to 0 adc_data_out_resetn_dclk create_bd_pin -dir O adc_enable_data_rclk create_bd_pin -dir I adc_reset_pulse_dclk create_bd_pin -dir O adc_rfdc_axi_resetn_rclk - create_bd_pin -dir O dac_data_in_resetn_dclk - create_bd_pin -dir O dac_data_in_resetn_dclk2x + create_bd_pin -dir O clk_adc0 + create_bd_pin -dir O -from 0 -to 0 dac_data_in_resetn_dclk + create_bd_pin -dir O -from 0 -to 0 dac_data_in_resetn_dclk2x create_bd_pin -dir O dac_data_in_resetn_rclk create_bd_pin -dir O dac_data_in_resetn_rclk2x create_bd_pin -dir I dac_reset_pulse_dclk @@ -765,15 +889,20 @@ proc create_hier_cell_rfdc { parentCell nameHier } { create_bd_pin -dir I enable_sysref_rclk create_bd_pin -dir O fir_resetn_rclk2x create_bd_pin -dir O gated_base_clks_valid_clk40 - create_bd_pin -dir O -from 7 -to 0 invert_adc_iq_rclk2 - create_bd_pin -dir O -from 7 -to 0 invert_dac_iq_rclk2 create_bd_pin -dir O nco_reset_done_dclk create_bd_pin -dir I -type clk pll_ref_clk_in create_bd_pin -dir O -type clk pll_ref_clk_out + create_bd_pin -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk + create_bd_pin -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk + create_bd_pin -dir O -from 0 -to 0 radio0_rfdc_clk + create_bd_pin -dir O -from 0 -to 0 radio0_rfdc_clk_2x + create_bd_pin -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk + create_bd_pin -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk + create_bd_pin -dir O -from 0 -to 0 radio1_rfdc_clk_1x + create_bd_pin -dir O -from 0 -to 0 radio1_rfdc_clk_2x create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk - create_bd_pin -dir O -from 0 -to 0 rfdc_clk - create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x + create_bd_pin -dir I -from 31 -to 0 rf_rfdc_info_sclk create_bd_pin -dir O -type intr rfdc_irq create_bd_pin -dir I -type rst s_axi_config_aresetn create_bd_pin -dir I -type clk s_axi_config_clk @@ -789,7 +918,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } { set axi_interconnect_rf [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_rf ] set_property -dict [ list \ CONFIG.ENABLE_ADVANCED_OPTIONS {0} \ - CONFIG.NUM_MI {9} \ + CONFIG.NUM_MI {13} \ CONFIG.STRATEGY {1} \ ] $axi_interconnect_rf @@ -808,19 +937,19 @@ proc create_hier_cell_rfdc { parentCell nameHier } { } set_property -dict [ list \ - CONFIG.FREQ_HZ {61440000} \ + CONFIG.FREQ_HZ {64000000} \ CONFIG.PHASE {0} \ - CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_pll_ref_clk_in} \ + CONFIG.CLK_DOMAIN {x440_ps_rfdc_bd_pll_ref_clk_in} \ ] [get_bd_pins /rfdc/capture_sysref/pll_ref_clk] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ CONFIG.PHASE {0} \ - CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_pll_ref_clk_in} \ + CONFIG.CLK_DOMAIN {x440_ps_rfdc_bd_pll_ref_clk_in} \ ] [get_bd_pins /rfdc/capture_sysref/rfdc_clk] # Create instance: clock_gates_0, and set properties - set block_name clock_gates + set block_name x440_clock_gates set block_cell_name clock_gates_0 if { [catch {set clock_gates_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} @@ -837,53 +966,65 @@ proc create_hier_cell_rfdc { parentCell nameHier } { set data_clock_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 data_clock_mmcm ] set_property -dict [ list \ CONFIG.AXI_DRP {true} \ - CONFIG.CLKIN1_JITTER_PS {162.76} \ + CONFIG.CLKIN1_JITTER_PS {156.25} \ CONFIG.CLKOUT1_DRIVES {Buffer} \ - CONFIG.CLKOUT1_JITTER {116.960} \ - CONFIG.CLKOUT1_PHASE_ERROR {124.626} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {61.44} \ + CONFIG.CLKOUT1_JITTER {130.541} \ + CONFIG.CLKOUT1_PHASE_ERROR {128.385} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {64.00} \ CONFIG.CLKOUT2_DRIVES {Buffer} \ - CONFIG.CLKOUT2_JITTER {104.559} \ - CONFIG.CLKOUT2_PHASE_ERROR {124.626} \ - CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {122.88} \ + CONFIG.CLKOUT2_JITTER {116.118} \ + CONFIG.CLKOUT2_PHASE_ERROR {128.385} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {128.00} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_DRIVES {Buffer} \ - CONFIG.CLKOUT3_JITTER {98.017} \ - CONFIG.CLKOUT3_PHASE_ERROR {124.626} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {184.32} \ + CONFIG.CLKOUT3_JITTER {130.541} \ + CONFIG.CLKOUT3_PHASE_ERROR {128.385} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {64.00} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_DRIVES {Buffer} \ - CONFIG.CLKOUT4_JITTER {93.671} \ - CONFIG.CLKOUT4_PHASE_ERROR {124.626} \ - CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {245.76} \ + CONFIG.CLKOUT4_JITTER {103.479} \ + CONFIG.CLKOUT4_PHASE_ERROR {128.385} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {256.00} \ CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT5_DRIVES {Buffer} \ - CONFIG.CLKOUT5_JITTER {87.938} \ - CONFIG.CLKOUT5_PHASE_ERROR {124.626} \ - CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {368.64} \ + CONFIG.CLKOUT5_JITTER {116.118} \ + CONFIG.CLKOUT5_PHASE_ERROR {128.385} \ + CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {128.00} \ CONFIG.CLKOUT5_USED {true} \ CONFIG.CLKOUT6_DRIVES {Buffer} \ + CONFIG.CLKOUT6_JITTER {130.541} \ + CONFIG.CLKOUT6_PHASE_ERROR {128.385} \ + CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {64.00} \ + CONFIG.CLKOUT6_USED {true} \ CONFIG.CLKOUT7_DRIVES {Buffer} \ + CONFIG.CLKOUT7_JITTER {116.118} \ + CONFIG.CLKOUT7_PHASE_ERROR {128.385} \ + CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {128.00} \ + CONFIG.CLKOUT7_USED {true} \ CONFIG.CLK_OUT1_PORT {pll_ref_clk_out} \ CONFIG.CLK_OUT2_PORT {data_clk} \ - CONFIG.CLK_OUT3_PORT {rfdc_clk} \ + CONFIG.CLK_OUT3_PORT {r0_rfdc_clk} \ CONFIG.CLK_OUT4_PORT {data_clk_2x} \ - CONFIG.CLK_OUT5_PORT {rfdc_clk_2x} \ + CONFIG.CLK_OUT5_PORT {r0_rfdc_clk_2x} \ + CONFIG.CLK_OUT6_PORT {r1_rfdc_clk} \ + CONFIG.CLK_OUT7_PORT {r1_rfdc_clk_2x} \ CONFIG.ENABLE_CLOCK_MONITOR {false} \ CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \ - CONFIG.MMCM_CLKIN1_PERIOD {16.276} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {20.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {15.625} \ CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \ - CONFIG.MMCM_CLKOUT1_DIVIDE {12} \ - CONFIG.MMCM_CLKOUT2_DIVIDE {8} \ - CONFIG.MMCM_CLKOUT3_DIVIDE {6} \ - CONFIG.MMCM_CLKOUT4_DIVIDE {4} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {10} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {20} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {5} \ + CONFIG.MMCM_CLKOUT4_DIVIDE {10} \ + CONFIG.MMCM_CLKOUT5_DIVIDE {20} \ + CONFIG.MMCM_CLKOUT6_DIVIDE {10} \ CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - CONFIG.NUM_OUT_CLKS {5} \ + CONFIG.NUM_OUT_CLKS {7} \ CONFIG.PHASE_DUTY_CONFIG {false} \ CONFIG.PRIMITIVE {MMCM} \ - CONFIG.PRIM_IN_FREQ {61.44} \ + CONFIG.PRIM_IN_FREQ {64.00} \ CONFIG.PRIM_SOURCE {No_buffer} \ CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \ CONFIG.USE_CLKFB_STOPPED {false} \ @@ -905,11 +1046,17 @@ proc create_hier_cell_rfdc { parentCell nameHier } { CONFIG.C_IS_DUAL {1} \ ] $reg_clock_gate_control - # Create instance: reg_invert_iq, and set properties - set reg_invert_iq [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_invert_iq ] + # Create instance: reg_invert_iq_radio0, and set properties + set reg_invert_iq_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_invert_iq_radio0 ] set_property -dict [ list \ CONFIG.C_ALL_OUTPUTS {1} \ - ] $reg_invert_iq + ] $reg_invert_iq_radio0 + + # Create instance: reg_invert_iq_radio1, and set properties + set reg_invert_iq_radio1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_invert_iq_radio1 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + ] $reg_invert_iq_radio1 # Create instance: reg_reset_mmcm, and set properties set reg_reset_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_reset_mmcm ] @@ -928,14 +1075,37 @@ proc create_hier_cell_rfdc { parentCell nameHier } { CONFIG.C_IS_DUAL {1} \ ] $reg_rf_axi_status - # Create instance: reg_rf_reset_control, and set properties - set reg_rf_reset_control [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rf_reset_control ] + # Create instance: reg_rf_reset_control_radio0, and set properties + set reg_rf_reset_control_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rf_reset_control_radio0 ] set_property -dict [ list \ CONFIG.C_ALL_INPUTS_2 {1} \ CONFIG.C_ALL_OUTPUTS {1} \ CONFIG.C_GPIO_WIDTH {32} \ CONFIG.C_IS_DUAL {1} \ - ] $reg_rf_reset_control + ] $reg_rf_reset_control_radio0 + + # Create instance: reg_rf_reset_control_radio1, and set properties + set reg_rf_reset_control_radio1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rf_reset_control_radio1 ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {32} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_rf_reset_control_radio1 + + # Create instance: reg_rfdc_info, and set properties + set reg_rfdc_info [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rfdc_info ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS {1} \ + ] $reg_rfdc_info + + # Create instance: reg_rfdc_tile_mapping, and set properties + set reg_rfdc_tile_mapping [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rfdc_tile_mapping ] + set_property -dict [ list \ + CONFIG.C_ALL_INPUTS {1} \ + CONFIG.C_ALL_INPUTS_2 {1} \ + CONFIG.C_IS_DUAL {1} \ + ] $reg_rfdc_tile_mapping # Create instance: rf_clock_buffers create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers @@ -944,37 +1114,51 @@ proc create_hier_cell_rfdc { parentCell nameHier } { set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ] set_property -dict [ list \ CONFIG.ADC0_Enable {1} \ - CONFIG.ADC0_Fabric_Freq {184.320} \ + CONFIG.ADC0_Fabric_Freq {64.000} \ CONFIG.ADC0_Multi_Tile_Sync {true} \ - CONFIG.ADC0_Outclk_Freq {184.320} \ - CONFIG.ADC0_Refclk_Freq {2949.120} \ - CONFIG.ADC0_Sampling_Rate {2.94912} \ - CONFIG.ADC1_Enable {0} \ - CONFIG.ADC1_Fabric_Freq {0.0} \ - CONFIG.ADC1_Multi_Tile_Sync {false} \ - CONFIG.ADC1_Outclk_Freq {15.625} \ - CONFIG.ADC1_Refclk_Freq {2000.000} \ - CONFIG.ADC1_Sampling_Rate {2.0} \ + CONFIG.ADC0_Outclk_Freq {64.000} \ + CONFIG.ADC0_PLL_Enable {true} \ + CONFIG.ADC0_Refclk_Freq {512.000} \ + CONFIG.ADC0_Sampling_Rate {4.096} \ + CONFIG.ADC1_Enable {1} \ + CONFIG.ADC1_Fabric_Freq {64.000} \ + CONFIG.ADC1_Multi_Tile_Sync {true} \ + CONFIG.ADC1_Outclk_Freq {64.000} \ + CONFIG.ADC1_PLL_Enable {true} \ + CONFIG.ADC1_Refclk_Freq {512.000} \ + CONFIG.ADC1_Sampling_Rate {4.096} \ CONFIG.ADC224_En {true} \ CONFIG.ADC225_En {false} \ CONFIG.ADC2_Enable {1} \ - CONFIG.ADC2_Fabric_Freq {184.320} \ + CONFIG.ADC2_Fabric_Freq {64.000} \ CONFIG.ADC2_Multi_Tile_Sync {true} \ - CONFIG.ADC2_Outclk_Freq {184.320} \ - CONFIG.ADC2_Refclk_Freq {2949.120} \ - CONFIG.ADC2_Sampling_Rate {2.94912} \ + CONFIG.ADC2_Outclk_Freq {64.000} \ + CONFIG.ADC2_PLL_Enable {true} \ + CONFIG.ADC2_Refclk_Freq {512.000} \ + CONFIG.ADC2_Sampling_Rate {4.096} \ + CONFIG.ADC3_Enable {1} \ + CONFIG.ADC3_Fabric_Freq {64.000} \ + CONFIG.ADC3_Multi_Tile_Sync {true} \ + CONFIG.ADC3_Outclk_Freq {64.000} \ + CONFIG.ADC3_PLL_Enable {true} \ + CONFIG.ADC3_Refclk_Freq {512.000} \ + CONFIG.ADC3_Sampling_Rate {4.096} \ CONFIG.ADC_Data_Type00 {1} \ CONFIG.ADC_Data_Type01 {1} \ CONFIG.ADC_Data_Type02 {1} \ CONFIG.ADC_Data_Type03 {1} \ - CONFIG.ADC_Data_Type10 {0} \ - CONFIG.ADC_Data_Type11 {0} \ - CONFIG.ADC_Data_Type12 {0} \ - CONFIG.ADC_Data_Type13 {0} \ + CONFIG.ADC_Data_Type10 {1} \ + CONFIG.ADC_Data_Type11 {1} \ + CONFIG.ADC_Data_Type12 {1} \ + CONFIG.ADC_Data_Type13 {1} \ CONFIG.ADC_Data_Type20 {1} \ CONFIG.ADC_Data_Type21 {1} \ CONFIG.ADC_Data_Type22 {1} \ CONFIG.ADC_Data_Type23 {1} \ + CONFIG.ADC_Data_Type30 {1} \ + CONFIG.ADC_Data_Type31 {1} \ + CONFIG.ADC_Data_Type32 {1} \ + CONFIG.ADC_Data_Type33 {1} \ CONFIG.ADC_Data_Width00 {8} \ CONFIG.ADC_Data_Width01 {8} \ CONFIG.ADC_Data_Width02 {8} \ @@ -988,98 +1172,130 @@ proc create_hier_cell_rfdc { parentCell nameHier } { CONFIG.ADC_Data_Width22 {8} \ CONFIG.ADC_Data_Width23 {8} \ CONFIG.ADC_Debug {false} \ - CONFIG.ADC_Decimation_Mode00 {2} \ - CONFIG.ADC_Decimation_Mode01 {2} \ - CONFIG.ADC_Decimation_Mode02 {2} \ - CONFIG.ADC_Decimation_Mode03 {2} \ - CONFIG.ADC_Decimation_Mode10 {0} \ - CONFIG.ADC_Decimation_Mode11 {0} \ - CONFIG.ADC_Decimation_Mode12 {0} \ - CONFIG.ADC_Decimation_Mode13 {0} \ - CONFIG.ADC_Decimation_Mode20 {2} \ - CONFIG.ADC_Decimation_Mode21 {2} \ - CONFIG.ADC_Decimation_Mode22 {2} \ - CONFIG.ADC_Decimation_Mode23 {2} \ + CONFIG.ADC_Decimation_Mode00 {8} \ + CONFIG.ADC_Decimation_Mode01 {8} \ + CONFIG.ADC_Decimation_Mode02 {8} \ + CONFIG.ADC_Decimation_Mode03 {8} \ + CONFIG.ADC_Decimation_Mode10 {8} \ + CONFIG.ADC_Decimation_Mode11 {8} \ + CONFIG.ADC_Decimation_Mode12 {8} \ + CONFIG.ADC_Decimation_Mode13 {8} \ + CONFIG.ADC_Decimation_Mode20 {8} \ + CONFIG.ADC_Decimation_Mode21 {8} \ + CONFIG.ADC_Decimation_Mode22 {8} \ + CONFIG.ADC_Decimation_Mode23 {8} \ + CONFIG.ADC_Decimation_Mode30 {8} \ + CONFIG.ADC_Decimation_Mode31 {8} \ + CONFIG.ADC_Decimation_Mode32 {8} \ + CONFIG.ADC_Decimation_Mode33 {8} \ CONFIG.ADC_Dither00 {false} \ CONFIG.ADC_Dither01 {false} \ CONFIG.ADC_Dither02 {false} \ CONFIG.ADC_Dither03 {false} \ - CONFIG.ADC_Dither10 {true} \ - CONFIG.ADC_Dither11 {true} \ - CONFIG.ADC_Dither12 {true} \ - CONFIG.ADC_Dither13 {true} \ + CONFIG.ADC_Dither10 {false} \ + CONFIG.ADC_Dither11 {false} \ + CONFIG.ADC_Dither12 {false} \ + CONFIG.ADC_Dither13 {false} \ CONFIG.ADC_Dither20 {false} \ CONFIG.ADC_Dither21 {false} \ CONFIG.ADC_Dither22 {false} \ CONFIG.ADC_Dither23 {false} \ + CONFIG.ADC_Dither30 {false} \ + CONFIG.ADC_Dither31 {false} \ + CONFIG.ADC_Dither32 {false} \ + CONFIG.ADC_Dither33 {false} \ CONFIG.ADC_Mixer_Mode00 {0} \ CONFIG.ADC_Mixer_Mode01 {0} \ CONFIG.ADC_Mixer_Mode02 {0} \ CONFIG.ADC_Mixer_Mode03 {0} \ - CONFIG.ADC_Mixer_Mode10 {2} \ - CONFIG.ADC_Mixer_Mode11 {2} \ - CONFIG.ADC_Mixer_Mode12 {2} \ - CONFIG.ADC_Mixer_Mode13 {2} \ + CONFIG.ADC_Mixer_Mode10 {0} \ + CONFIG.ADC_Mixer_Mode11 {0} \ + CONFIG.ADC_Mixer_Mode12 {0} \ + CONFIG.ADC_Mixer_Mode13 {0} \ CONFIG.ADC_Mixer_Mode20 {0} \ CONFIG.ADC_Mixer_Mode21 {0} \ CONFIG.ADC_Mixer_Mode22 {0} \ CONFIG.ADC_Mixer_Mode23 {0} \ + CONFIG.ADC_Mixer_Mode30 {0} \ + CONFIG.ADC_Mixer_Mode31 {0} \ + CONFIG.ADC_Mixer_Mode32 {0} \ + CONFIG.ADC_Mixer_Mode33 {0} \ CONFIG.ADC_Mixer_Type00 {2} \ CONFIG.ADC_Mixer_Type01 {2} \ CONFIG.ADC_Mixer_Type02 {2} \ CONFIG.ADC_Mixer_Type03 {2} \ - CONFIG.ADC_Mixer_Type10 {3} \ - CONFIG.ADC_Mixer_Type11 {3} \ - CONFIG.ADC_Mixer_Type12 {3} \ - CONFIG.ADC_Mixer_Type13 {3} \ + CONFIG.ADC_Mixer_Type10 {2} \ + CONFIG.ADC_Mixer_Type11 {2} \ + CONFIG.ADC_Mixer_Type12 {2} \ + CONFIG.ADC_Mixer_Type13 {2} \ CONFIG.ADC_Mixer_Type20 {2} \ CONFIG.ADC_Mixer_Type21 {2} \ CONFIG.ADC_Mixer_Type22 {2} \ CONFIG.ADC_Mixer_Type23 {2} \ + CONFIG.ADC_Mixer_Type30 {2} \ + CONFIG.ADC_Mixer_Type31 {2} \ + CONFIG.ADC_Mixer_Type32 {2} \ + CONFIG.ADC_Mixer_Type33 {2} \ CONFIG.ADC_NCO_Freq00 {0.200} \ CONFIG.ADC_NCO_Freq01 {0.200} \ CONFIG.ADC_NCO_Freq02 {0.200} \ CONFIG.ADC_NCO_Freq03 {0.200} \ - CONFIG.ADC_NCO_Freq10 {0.0} \ - CONFIG.ADC_NCO_Freq11 {0.0} \ - CONFIG.ADC_NCO_Freq12 {0.0} \ - CONFIG.ADC_NCO_Freq13 {0.0} \ + CONFIG.ADC_NCO_Freq10 {0.200} \ + CONFIG.ADC_NCO_Freq11 {0.200} \ + CONFIG.ADC_NCO_Freq12 {0.200} \ + CONFIG.ADC_NCO_Freq13 {0.200} \ CONFIG.ADC_NCO_Freq20 {0.200} \ CONFIG.ADC_NCO_Freq21 {0.200} \ CONFIG.ADC_NCO_Freq22 {0.200} \ CONFIG.ADC_NCO_Freq23 {0.200} \ - CONFIG.ADC_NCO_Freq30 {0.0} \ - CONFIG.ADC_NCO_Freq31 {0.0} \ + CONFIG.ADC_NCO_Freq30 {0.200} \ + CONFIG.ADC_NCO_Freq31 {0.200} \ + CONFIG.ADC_NCO_Freq32 {0.200} \ CONFIG.ADC_NCO_RTS {true} \ + CONFIG.ADC_RESERVED_1_00 {false} \ + CONFIG.ADC_RESERVED_1_02 {false} \ + CONFIG.ADC_RESERVED_1_10 {false} \ + CONFIG.ADC_RESERVED_1_12 {false} \ + CONFIG.ADC_RESERVED_1_20 {false} \ + CONFIG.ADC_RESERVED_1_22 {false} \ + CONFIG.ADC_RESERVED_1_30 {false} \ + CONFIG.ADC_RESERVED_1_32 {false} \ CONFIG.ADC_RTS {true} \ CONFIG.ADC_Slice00_Enable {true} \ CONFIG.ADC_Slice01_Enable {true} \ CONFIG.ADC_Slice02_Enable {true} \ CONFIG.ADC_Slice03_Enable {true} \ - CONFIG.ADC_Slice10_Enable {false} \ - CONFIG.ADC_Slice11_Enable {false} \ - CONFIG.ADC_Slice12_Enable {false} \ - CONFIG.ADC_Slice13_Enable {false} \ + CONFIG.ADC_Slice10_Enable {true} \ + CONFIG.ADC_Slice11_Enable {true} \ + CONFIG.ADC_Slice12_Enable {true} \ + CONFIG.ADC_Slice13_Enable {true} \ CONFIG.ADC_Slice20_Enable {true} \ CONFIG.ADC_Slice21_Enable {true} \ CONFIG.ADC_Slice22_Enable {true} \ CONFIG.ADC_Slice23_Enable {true} \ + CONFIG.ADC_Slice30_Enable {true} \ + CONFIG.ADC_Slice31_Enable {true} \ + CONFIG.ADC_Slice32_Enable {true} \ + CONFIG.ADC_Slice33_Enable {true} \ + CONFIG.Auto_Calibration_Freeze {true} \ CONFIG.Axiclk_Freq {40} \ CONFIG.Calibration_Freeze {true} \ CONFIG.Converter_Setup {1} \ CONFIG.DAC0_Band {0} \ CONFIG.DAC0_Enable {1} \ - CONFIG.DAC0_Fabric_Freq {184.320} \ + CONFIG.DAC0_Fabric_Freq {64.000} \ CONFIG.DAC0_Multi_Tile_Sync {true} \ - CONFIG.DAC0_Outclk_Freq {184.320} \ - CONFIG.DAC0_Refclk_Freq {2949.120} \ - CONFIG.DAC0_Sampling_Rate {2.94912} \ + CONFIG.DAC0_Outclk_Freq {64.000} \ + CONFIG.DAC0_PLL_Enable {true} \ + CONFIG.DAC0_Refclk_Freq {256.000} \ + CONFIG.DAC0_Sampling_Rate {4.096} \ CONFIG.DAC1_Enable {1} \ - CONFIG.DAC1_Fabric_Freq {184.320} \ + CONFIG.DAC1_Fabric_Freq {64.000} \ CONFIG.DAC1_Multi_Tile_Sync {true} \ - CONFIG.DAC1_Outclk_Freq {184.320} \ - CONFIG.DAC1_Refclk_Freq {2949.120} \ - CONFIG.DAC1_Sampling_Rate {2.94912} \ + CONFIG.DAC1_Outclk_Freq {64.000} \ + CONFIG.DAC1_PLL_Enable {true} \ + CONFIG.DAC1_Refclk_Freq {256.000} \ + CONFIG.DAC1_Sampling_Rate {4.096} \ CONFIG.DAC228_En {true} \ CONFIG.DAC_Data_Type00 {0} \ CONFIG.DAC_Data_Type01 {0} \ @@ -1090,43 +1306,62 @@ proc create_hier_cell_rfdc { parentCell nameHier } { CONFIG.DAC_Data_Width10 {16} \ CONFIG.DAC_Data_Width11 {16} \ CONFIG.DAC_Debug {false} \ - CONFIG.DAC_Interpolation_Mode00 {2} \ - CONFIG.DAC_Interpolation_Mode01 {2} \ - CONFIG.DAC_Interpolation_Mode02 {0} \ - CONFIG.DAC_Interpolation_Mode03 {0} \ - CONFIG.DAC_Interpolation_Mode10 {2} \ - CONFIG.DAC_Interpolation_Mode11 {2} \ + CONFIG.DAC_Interpolation_Mode00 {8} \ + CONFIG.DAC_Interpolation_Mode01 {8} \ + CONFIG.DAC_Interpolation_Mode02 {8} \ + CONFIG.DAC_Interpolation_Mode03 {8} \ + CONFIG.DAC_Interpolation_Mode10 {8} \ + CONFIG.DAC_Interpolation_Mode11 {8} \ + CONFIG.DAC_Interpolation_Mode12 {8} \ + CONFIG.DAC_Interpolation_Mode13 {8} \ CONFIG.DAC_Invsinc_Ctrl00 {false} \ CONFIG.DAC_Mixer_Mode00 {0} \ CONFIG.DAC_Mixer_Mode01 {0} \ - CONFIG.DAC_Mixer_Mode02 {2} \ - CONFIG.DAC_Mixer_Mode03 {2} \ + CONFIG.DAC_Mixer_Mode02 {0} \ + CONFIG.DAC_Mixer_Mode03 {0} \ CONFIG.DAC_Mixer_Mode10 {0} \ CONFIG.DAC_Mixer_Mode11 {0} \ - CONFIG.DAC_Mixer_Mode13 {2} \ + CONFIG.DAC_Mixer_Mode12 {0} \ + CONFIG.DAC_Mixer_Mode13 {0} \ CONFIG.DAC_Mixer_Mode20 {2} \ CONFIG.DAC_Mixer_Mode21 {2} \ CONFIG.DAC_Mixer_Mode30 {2} \ CONFIG.DAC_Mixer_Mode31 {2} \ CONFIG.DAC_Mixer_Type00 {2} \ CONFIG.DAC_Mixer_Type01 {2} \ - CONFIG.DAC_Mixer_Type02 {3} \ - CONFIG.DAC_Mixer_Type03 {3} \ + CONFIG.DAC_Mixer_Type02 {2} \ + CONFIG.DAC_Mixer_Type03 {2} \ CONFIG.DAC_Mixer_Type10 {2} \ CONFIG.DAC_Mixer_Type11 {2} \ + CONFIG.DAC_Mixer_Type12 {2} \ + CONFIG.DAC_Mixer_Type13 {2} \ CONFIG.DAC_NCO_Freq00 {0.200} \ CONFIG.DAC_NCO_Freq01 {0.200} \ + CONFIG.DAC_NCO_Freq02 {0.200} \ + CONFIG.DAC_NCO_Freq03 {0.200} \ CONFIG.DAC_NCO_Freq10 {0.200} \ CONFIG.DAC_NCO_Freq11 {0.200} \ + CONFIG.DAC_NCO_Freq12 {0.200} \ + CONFIG.DAC_NCO_Freq13 {0.200} \ CONFIG.DAC_NCO_RTS {true} \ CONFIG.DAC_Output_Current {1} \ + CONFIG.DAC_RESERVED_1_00 {false} \ + CONFIG.DAC_RESERVED_1_01 {false} \ + CONFIG.DAC_RESERVED_1_02 {false} \ + CONFIG.DAC_RESERVED_1_03 {false} \ + CONFIG.DAC_RESERVED_1_10 {false} \ + CONFIG.DAC_RESERVED_1_11 {false} \ + CONFIG.DAC_RESERVED_1_12 {false} \ + CONFIG.DAC_RESERVED_1_13 {false} \ CONFIG.DAC_RTS {false} \ CONFIG.DAC_Slice00_Enable {true} \ CONFIG.DAC_Slice01_Enable {true} \ - CONFIG.DAC_Slice02_Enable {false} \ - CONFIG.DAC_Slice03_Enable {false} \ + CONFIG.DAC_Slice02_Enable {true} \ + CONFIG.DAC_Slice03_Enable {true} \ CONFIG.DAC_Slice10_Enable {true} \ CONFIG.DAC_Slice11_Enable {true} \ + CONFIG.DAC_Slice12_Enable {true} \ + CONFIG.DAC_Slice13_Enable {true} \ CONFIG.mADC_Data_Type00 {0} \ CONFIG.mADC_Data_Type01 {0} \ CONFIG.mADC_Data_Type02 {0} \ @@ -1208,7 +1443,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } { } # Create instance: rf_reset_controller_0, and set properties - set block_name rf_reset_controller + set block_name x440_rf_reset_controller set block_cell_name rf_reset_controller_0 if { [catch {set rf_reset_controller_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} @@ -1218,131 +1453,227 @@ proc create_hier_cell_rfdc { parentCell nameHier } { return 1 } - # Create instance: slice_15_8, and set properties - set slice_15_8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_15_8 ] + # Create instance: rf_reset_controller_1, and set properties + set block_name x440_rf_reset_controller + set block_cell_name rf_reset_controller_1 + if { [catch {set rf_reset_controller_1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $rf_reset_controller_1 eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: rfdc_adc_map, and set properties + set rfdc_adc_map [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rfdc_adc_map ] set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DIN_TO {8} \ - CONFIG.DOUT_WIDTH {8} \ - ] $slice_15_8 + CONFIG.CONST_VAL {0b00110010011001110001000001000101} \ + CONFIG.CONST_WIDTH {32} \ + ] $rfdc_adc_map - # Create instance: slice_7_0, and set properties - set slice_7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_7_0 ] + # Create instance: rfdc_dac_map, and set properties + set rfdc_dac_map [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rfdc_dac_map ] set_property -dict [ list \ - CONFIG.DIN_FROM {7} \ - CONFIG.DOUT_WIDTH {8} \ - ] $slice_7_0 + CONFIG.CONST_VAL {0b01011101100100010100110010000000} \ + CONFIG.CONST_WIDTH {32} \ + ] $rfdc_dac_map + + # Create instance: slice_iqswap_11_8_radio0, and set properties + set slice_iqswap_11_8_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_11_8_radio0 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {11} \ + CONFIG.DIN_TO {8} \ + CONFIG.DOUT_WIDTH {4} \ + ] $slice_iqswap_11_8_radio0 + + # Create instance: slice_iqswap_11_8_radio1, and set properties + set slice_iqswap_11_8_radio1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_11_8_radio1 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {11} \ + CONFIG.DIN_TO {8} \ + CONFIG.DOUT_WIDTH {4} \ + ] $slice_iqswap_11_8_radio1 + + # Create instance: slice_iqswap_3_0_radio0, and set properties + set slice_iqswap_3_0_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_3_0_radio0 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DOUT_WIDTH {4} \ + ] $slice_iqswap_3_0_radio0 + + # Create instance: slice_iqswap_3_0_radio1, and set properties + set slice_iqswap_3_0_radio1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_3_0_radio1 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {3} \ + CONFIG.DOUT_WIDTH {4} \ + ] $slice_iqswap_3_0_radio1 + + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] # Create interface connections connect_bd_intf_net -intf_net S_AXI_1_1 [get_bd_intf_pins axi_interconnect_rf/M06_AXI] [get_bd_intf_pins calibration_muxes/S_AXI_1] connect_bd_intf_net -intf_net adc0_clk_0_1 [get_bd_intf_pins adc0_clk] [get_bd_intf_pins rf_data_converter/adc0_clk] + connect_bd_intf_net -intf_net adc1_clk_1 [get_bd_intf_pins adc1_clk] [get_bd_intf_pins rf_data_converter/adc1_clk] connect_bd_intf_net -intf_net adc2_clk_0_1 [get_bd_intf_pins adc2_clk] [get_bd_intf_pins rf_data_converter/adc2_clk] + connect_bd_intf_net -intf_net adc3_clk_1 [get_bd_intf_pins adc3_clk] [get_bd_intf_pins rf_data_converter/adc3_clk] connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_rf/M00_AXI] [get_bd_intf_pins rf_data_converter/s_axi] connect_bd_intf_net -intf_net axi_interconnect_rf_M01_AXI [get_bd_intf_pins axi_interconnect_rf/M01_AXI] [get_bd_intf_pins data_clock_mmcm/s_axi_lite] - connect_bd_intf_net -intf_net axi_interconnect_rf_M02_AXI [get_bd_intf_pins axi_interconnect_rf/M02_AXI] [get_bd_intf_pins reg_invert_iq/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M02_AXI [get_bd_intf_pins axi_interconnect_rf/M02_AXI] [get_bd_intf_pins reg_invert_iq_radio0/S_AXI] connect_bd_intf_net -intf_net axi_interconnect_rf_M03_AXI [get_bd_intf_pins axi_interconnect_rf/M03_AXI] [get_bd_intf_pins reg_reset_mmcm/S_AXI] - connect_bd_intf_net -intf_net axi_interconnect_rf_M04_AXI [get_bd_intf_pins axi_interconnect_rf/M04_AXI] [get_bd_intf_pins reg_rf_reset_control/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M04_AXI [get_bd_intf_pins axi_interconnect_rf/M04_AXI] [get_bd_intf_pins reg_rf_reset_control_radio0/S_AXI] connect_bd_intf_net -intf_net axi_interconnect_rf_M05_AXI [get_bd_intf_pins axi_interconnect_rf/M05_AXI] [get_bd_intf_pins reg_rf_axi_status/S_AXI] connect_bd_intf_net -intf_net axi_interconnect_rf_M07_AXI [get_bd_intf_pins axi_interconnect_rf/M07_AXI] [get_bd_intf_pins reg_clock_gate_control/S_AXI] connect_bd_intf_net -intf_net axi_interconnect_rf_M08_AXI [get_bd_intf_pins ThresholdRegister/S_AXI] [get_bd_intf_pins axi_interconnect_rf/M08_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M09_AXI [get_bd_intf_pins axi_interconnect_rf/M09_AXI] [get_bd_intf_pins reg_rfdc_tile_mapping/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M10_AXI [get_bd_intf_pins axi_interconnect_rf/M10_AXI] [get_bd_intf_pins reg_rfdc_info/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M11_AXI [get_bd_intf_pins axi_interconnect_rf/M11_AXI] [get_bd_intf_pins reg_invert_iq_radio1/S_AXI] + connect_bd_intf_net -intf_net axi_interconnect_rf_M12_AXI [get_bd_intf_pins axi_interconnect_rf/M12_AXI] [get_bd_intf_pins reg_rf_reset_control_radio1/S_AXI] connect_bd_intf_net -intf_net calibration_muxes_m_axis_0_0 [get_bd_intf_pins calibration_muxes/m_axis_0_0] [get_bd_intf_pins rf_data_converter/s00_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_0_1 [get_bd_intf_pins calibration_muxes/m_axis_0_1] [get_bd_intf_pins rf_data_converter/s10_axis] connect_bd_intf_net -intf_net calibration_muxes_m_axis_1_0 [get_bd_intf_pins calibration_muxes/m_axis_1_0] [get_bd_intf_pins rf_data_converter/s01_axis] - connect_bd_intf_net -intf_net calibration_muxes_m_axis_2_0 [get_bd_intf_pins calibration_muxes/m_axis_2_0] [get_bd_intf_pins rf_data_converter/s10_axis] - connect_bd_intf_net -intf_net calibration_muxes_m_axis_3_0 [get_bd_intf_pins calibration_muxes/m_axis_3_0] [get_bd_intf_pins rf_data_converter/s11_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_1_1 [get_bd_intf_pins calibration_muxes/m_axis_1_1] [get_bd_intf_pins rf_data_converter/s11_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_2_0 [get_bd_intf_pins calibration_muxes/m_axis_2_0] [get_bd_intf_pins rf_data_converter/s02_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_2_1 [get_bd_intf_pins calibration_muxes/m_axis_2_1] [get_bd_intf_pins rf_data_converter/s12_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_3_0 [get_bd_intf_pins calibration_muxes/m_axis_3_0] [get_bd_intf_pins rf_data_converter/s03_axis] + connect_bd_intf_net -intf_net calibration_muxes_m_axis_3_1 [get_bd_intf_pins calibration_muxes/m_axis_3_1] [get_bd_intf_pins rf_data_converter/s13_axis] connect_bd_intf_net -intf_net dac0_clk_0_1 [get_bd_intf_pins dac0_clk] [get_bd_intf_pins rf_data_converter/dac0_clk] connect_bd_intf_net -intf_net dac1_clk_0_1 [get_bd_intf_pins dac1_clk] [get_bd_intf_pins rf_data_converter/dac1_clk] connect_bd_intf_net -intf_net dac_tile228_ch0_din_1 [get_bd_intf_pins dac_tile228_ch0_din] [get_bd_intf_pins calibration_muxes/dac_tile228_ch0_din] connect_bd_intf_net -intf_net dac_tile228_ch1_din_1 [get_bd_intf_pins dac_tile228_ch1_din] [get_bd_intf_pins calibration_muxes/dac_tile228_ch1_din] + connect_bd_intf_net -intf_net dac_tile228_ch2_din_1 [get_bd_intf_pins dac_tile228_ch2_din] [get_bd_intf_pins calibration_muxes/dac_tile228_ch2_din] + connect_bd_intf_net -intf_net dac_tile228_ch3_din_1 [get_bd_intf_pins dac_tile228_ch3_din] [get_bd_intf_pins calibration_muxes/dac_tile228_ch3_din] connect_bd_intf_net -intf_net dac_tile229_ch0_din_1 [get_bd_intf_pins dac_tile229_ch0_din] [get_bd_intf_pins calibration_muxes/dac_tile229_ch0_din] connect_bd_intf_net -intf_net dac_tile229_ch1_din_1 [get_bd_intf_pins dac_tile229_ch1_din] [get_bd_intf_pins calibration_muxes/dac_tile229_ch1_din] + connect_bd_intf_net -intf_net dac_tile229_ch2_din_1 [get_bd_intf_pins dac_tile229_ch2_din] [get_bd_intf_pins calibration_muxes/dac_tile229_ch2_din] + connect_bd_intf_net -intf_net dac_tile229_ch3_din_1 [get_bd_intf_pins dac_tile229_ch3_din] [get_bd_intf_pins calibration_muxes/dac_tile229_ch3_din] connect_bd_intf_net -intf_net rf_data_converter_m00_axis [get_bd_intf_pins adc_tile224_ch0_dout_i] [get_bd_intf_pins rf_data_converter/m00_axis] connect_bd_intf_net -intf_net rf_data_converter_m01_axis [get_bd_intf_pins adc_tile224_ch0_dout_q] [get_bd_intf_pins rf_data_converter/m01_axis] connect_bd_intf_net -intf_net rf_data_converter_m02_axis [get_bd_intf_pins adc_tile224_ch1_dout_i] [get_bd_intf_pins rf_data_converter/m02_axis] connect_bd_intf_net -intf_net rf_data_converter_m03_axis [get_bd_intf_pins adc_tile224_ch1_dout_q] [get_bd_intf_pins rf_data_converter/m03_axis] + connect_bd_intf_net -intf_net rf_data_converter_m10_axis [get_bd_intf_pins adc_tile225_ch0_dout_i] [get_bd_intf_pins rf_data_converter/m10_axis] + connect_bd_intf_net -intf_net rf_data_converter_m11_axis [get_bd_intf_pins adc_tile225_ch0_dout_q] [get_bd_intf_pins rf_data_converter/m11_axis] + connect_bd_intf_net -intf_net rf_data_converter_m12_axis [get_bd_intf_pins adc_tile225_ch1_dout_i] [get_bd_intf_pins rf_data_converter/m12_axis] + connect_bd_intf_net -intf_net rf_data_converter_m13_axis [get_bd_intf_pins adc_tile225_ch1_dout_q] [get_bd_intf_pins rf_data_converter/m13_axis] connect_bd_intf_net -intf_net rf_data_converter_m20_axis [get_bd_intf_pins adc_tile226_ch0_dout_i] [get_bd_intf_pins rf_data_converter/m20_axis] connect_bd_intf_net -intf_net rf_data_converter_m21_axis [get_bd_intf_pins adc_tile226_ch0_dout_q] [get_bd_intf_pins rf_data_converter/m21_axis] connect_bd_intf_net -intf_net rf_data_converter_m22_axis [get_bd_intf_pins adc_tile226_ch1_dout_i] [get_bd_intf_pins rf_data_converter/m22_axis] connect_bd_intf_net -intf_net rf_data_converter_m23_axis [get_bd_intf_pins adc_tile226_ch1_dout_q] [get_bd_intf_pins rf_data_converter/m23_axis] + connect_bd_intf_net -intf_net rf_data_converter_m30_axis [get_bd_intf_pins adc_tile227_ch0_dout_i] [get_bd_intf_pins rf_data_converter/m30_axis] + connect_bd_intf_net -intf_net rf_data_converter_m31_axis [get_bd_intf_pins adc_tile227_ch0_dout_q] [get_bd_intf_pins rf_data_converter/m31_axis] + connect_bd_intf_net -intf_net rf_data_converter_m32_axis [get_bd_intf_pins adc_tile227_ch1_dout_i] [get_bd_intf_pins rf_data_converter/m32_axis] + connect_bd_intf_net -intf_net rf_data_converter_m33_axis [get_bd_intf_pins adc_tile227_ch1_dout_q] [get_bd_intf_pins rf_data_converter/m33_axis] connect_bd_intf_net -intf_net rf_data_converter_vout00 [get_bd_intf_pins dac_tile228_ch0_vout] [get_bd_intf_pins rf_data_converter/vout00] connect_bd_intf_net -intf_net rf_data_converter_vout01 [get_bd_intf_pins dac_tile228_ch1_vout] [get_bd_intf_pins rf_data_converter/vout01] + connect_bd_intf_net -intf_net rf_data_converter_vout02 [get_bd_intf_pins dac_tile228_ch2_vout] [get_bd_intf_pins rf_data_converter/vout02] + connect_bd_intf_net -intf_net rf_data_converter_vout03 [get_bd_intf_pins dac_tile228_ch3_vout] [get_bd_intf_pins rf_data_converter/vout03] connect_bd_intf_net -intf_net rf_data_converter_vout10 [get_bd_intf_pins dac_tile229_ch0_vout] [get_bd_intf_pins rf_data_converter/vout10] connect_bd_intf_net -intf_net rf_data_converter_vout11 [get_bd_intf_pins dac_tile229_ch1_vout] [get_bd_intf_pins rf_data_converter/vout11] + connect_bd_intf_net -intf_net rf_data_converter_vout12 [get_bd_intf_pins dac_tile229_ch2_vout] [get_bd_intf_pins rf_data_converter/vout12] + connect_bd_intf_net -intf_net rf_data_converter_vout13 [get_bd_intf_pins dac_tile229_ch3_vout] [get_bd_intf_pins rf_data_converter/vout13] connect_bd_intf_net -intf_net s_axi_config_1 [get_bd_intf_pins s_axi_config] [get_bd_intf_pins axi_interconnect_rf/S00_AXI] connect_bd_intf_net -intf_net sysref_in_0_1 [get_bd_intf_pins sysref_rf_in] [get_bd_intf_pins rf_data_converter/sysref_in] connect_bd_intf_net -intf_net vin0_01_0_1 [get_bd_intf_pins adc_tile224_ch0_vin] [get_bd_intf_pins rf_data_converter/vin0_01] connect_bd_intf_net -intf_net vin0_23_0_1 [get_bd_intf_pins adc_tile224_ch1_vin] [get_bd_intf_pins rf_data_converter/vin0_23] + connect_bd_intf_net -intf_net vin1_01_1 [get_bd_intf_pins adc_tile225_ch0_vin] [get_bd_intf_pins rf_data_converter/vin1_01] + connect_bd_intf_net -intf_net vin1_23_1 [get_bd_intf_pins adc_tile225_ch1_vin] [get_bd_intf_pins rf_data_converter/vin1_23] connect_bd_intf_net -intf_net vin2_01_0_1 [get_bd_intf_pins adc_tile226_ch0_vin] [get_bd_intf_pins rf_data_converter/vin2_01] connect_bd_intf_net -intf_net vin2_23_0_1 [get_bd_intf_pins adc_tile226_ch1_vin] [get_bd_intf_pins rf_data_converter/vin2_23] + connect_bd_intf_net -intf_net vin3_01_1 [get_bd_intf_pins adc_tile227_ch0_vin] [get_bd_intf_pins rf_data_converter/vin3_01] + connect_bd_intf_net -intf_net vin3_23_1 [get_bd_intf_pins adc_tile227_ch1_vin] [get_bd_intf_pins rf_data_converter/vin3_23] # Create port connections - connect_bd_net -net M02_ARESETN_1 [get_bd_pins axi_interconnect_rf/M02_ARESETN] [get_bd_pins const_1/dout] [get_bd_pins reg_invert_iq/s_axi_aresetn] - connect_bd_net -net adc_reset_pulse_dclk_1 [get_bd_pins adc_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dAdcResetPulse] - connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_rclk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] - connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_pins sysref_out_pclk] [get_bd_pins capture_sysref/sysref_out_pclk] [get_bd_pins rf_nco_reset_0/dSysref] + connect_bd_net -net M02_ARESETN_1 [get_bd_pins axi_interconnect_rf/M02_ARESETN] [get_bd_pins axi_interconnect_rf/M11_ARESETN] [get_bd_pins const_1/dout] [get_bd_pins reg_invert_iq_radio0/s_axi_aresetn] [get_bd_pins reg_invert_iq_radio1/s_axi_aresetn] + connect_bd_net -net adc_reset_pulse_dclk_1 [get_bd_pins adc_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/rAdcResetPulse] [get_bd_pins rf_reset_controller_1/rAdcResetPulse] + connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_rclk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] [get_bd_pins rf_nco_reset_0/dSysref] + connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_pins sysref_out_pclk] [get_bd_pins capture_sysref/sysref_out_pclk] connect_bd_net -net clk_in1_0_1 [get_bd_pins pll_ref_clk_in] [get_bd_pins data_clock_mmcm/clk_in1] + connect_bd_net -net clock_gates_0_aEnableRf1Bufg2x [get_bd_pins clock_gates_0/aEnableRf1Bufg2x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_2x_ce] connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i] connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid] connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked] - connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_ce] - connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg1x] [get_bd_pins rf_clock_buffers/rfdc_clk_ce] - connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_pins dac_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dDacResetPulse] - connect_bd_net -net data_clk_2x_pll [get_bd_pins clock_gates_0/DataClk2xPll] [get_bd_pins data_clock_mmcm/data_clk_2x] - connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins clock_gates_0/DataClk1x] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/DataClk] - connect_bd_net -net data_clock_mmcm_data_clk1 [get_bd_pins clock_gates_0/DataClk1xPll] [get_bd_pins data_clock_mmcm/data_clk] - connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins clock_gates_0/DataClk2x] [get_bd_pins rf_reset_controller_0/DataClk2x] + connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg2x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_2x_ce] + connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg1x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_ce] + connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_pins dac_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/rDacResetPulse] [get_bd_pins rf_reset_controller_1/rDacResetPulse] + connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins data_clock_mmcm/data_clk] + connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins data_clock_mmcm/data_clk_2x] connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked] - connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins rfdc_clk] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_0/RfClk] - connect_bd_net -net data_clock_mmcm_rfdc_clk1 [get_bd_pins data_clock_mmcm/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk_pll] - connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins rfdc_clk_2x] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins reg_invert_iq/s_axi_aclk] [get_bd_pins rf_clock_buffers/rfdc_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x] - connect_bd_net -net data_clock_mmcm_rfdc_clk_2x1 [get_bd_pins data_clock_mmcm/rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_pll] - connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] + connect_bd_net -net data_clock_mmcm_r0_rfdc_clk [get_bd_pins data_clock_mmcm/r0_rfdc_clk] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_pll] + connect_bd_net -net data_clock_mmcm_r0_rfdc_clk_2x [get_bd_pins data_clock_mmcm/r0_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_2x_pll] + connect_bd_net -net data_clock_mmcm_r1_rfdc_clk [get_bd_pins data_clock_mmcm/r1_rfdc_clk] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_pll] + connect_bd_net -net data_clock_mmcm_r1_rfdc_clk_2x [get_bd_pins data_clock_mmcm/r1_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_2x_pll] + connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins radio0_rfdc_clk] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins calibration_muxes/s_axi_aclk_1] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins rf_clock_buffers/rf0_clk_1x] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m1_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/RfClk] + connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins radio0_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rf0_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x] + connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk] connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks] connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_rclk] [get_bd_pins capture_sysref/enable_rclk] connect_bd_net -net gpio2_io_i_0_2 [get_bd_pins rf_dsp_info_sclk] [get_bd_pins reg_rf_axi_status/gpio2_io_i] connect_bd_net -net gpio_io_i_0_1 [get_bd_pins rf_axi_status_sclk] [get_bd_pins reg_rf_axi_status/gpio_io_i] + connect_bd_net -net radio1_rfdc_clk_ce_1 [get_bd_pins clock_gates_0/aEnableRf1Bufg1x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_ce] + connect_bd_net -net reg_invert_iq_radio1_gpio_io_o [get_bd_pins reg_invert_iq_radio1/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio1/Din] [get_bd_pins slice_iqswap_3_0_radio1/Din] connect_bd_net -net reg_reset_mmcm_gpio_io_o [get_bd_pins axi_interconnect_rf/M01_ARESETN] [get_bd_pins clock_gates_0/rPllReset_n] [get_bd_pins data_clock_mmcm/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/gpio_io_o] connect_bd_net -net reg_rf_reset_control1_gpio_io_o [get_bd_pins clock_gates_0/rSoftwareControl] [get_bd_pins reg_clock_gate_control/gpio_io_o] - connect_bd_net -net reg_rf_resets_gpio_io_o [get_bd_pins reg_rf_reset_control/gpio_io_o] [get_bd_pins rf_reset_controller_0/cSoftwareControl] + connect_bd_net -net reg_rf_reset_control_radio1_gpio_io_o [get_bd_pins reg_rf_reset_control_radio1/gpio_io_o] [get_bd_pins rf_reset_controller_1/cSoftwareControl] + connect_bd_net -net reg_rf_resets_gpio_io_o [get_bd_pins reg_rf_reset_control_radio0/gpio_io_o] [get_bd_pins rf_reset_controller_0/cSoftwareControl] + connect_bd_net -net rf_clock_buffers_rf1_clk_1x [get_bd_pins radio1_rfdc_clk_1x] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_clock_buffers/rf1_clk_1x] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/m3_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_1/RfClk] + connect_bd_net -net rf_clock_buffers_rf1_clk_2x [get_bd_pins radio1_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rf1_clk_2x] [get_bd_pins rf_reset_controller_1/RfClk2x] connect_bd_net -net rf_data_converter_adc0_01_over_threshold1 [get_bd_pins ThresholdRegister/In0] [get_bd_pins rf_data_converter/adc0_01_over_threshold1] connect_bd_net -net rf_data_converter_adc0_01_over_threshold2 [get_bd_pins ThresholdRegister/In1] [get_bd_pins rf_data_converter/adc0_01_over_threshold2] connect_bd_net -net rf_data_converter_adc0_23_over_threshold1 [get_bd_pins ThresholdRegister/In2] [get_bd_pins rf_data_converter/adc0_23_over_threshold1] connect_bd_net -net rf_data_converter_adc0_23_over_threshold2 [get_bd_pins ThresholdRegister/In3] [get_bd_pins rf_data_converter/adc0_23_over_threshold2] connect_bd_net -net rf_data_converter_adc0_nco_update_busy [get_bd_pins rf_data_converter/adc0_nco_update_busy] [get_bd_pins rf_nco_reset_0/cAdc0xNcoUpdateBusy] - connect_bd_net -net rf_data_converter_adc2_01_over_threshold1 [get_bd_pins ThresholdRegister/In5] [get_bd_pins rf_data_converter/adc2_01_over_threshold1] - connect_bd_net -net rf_data_converter_adc2_01_over_threshold2 [get_bd_pins ThresholdRegister/In6] [get_bd_pins rf_data_converter/adc2_01_over_threshold2] - connect_bd_net -net rf_data_converter_adc2_23_over_threshold1 [get_bd_pins ThresholdRegister/In7] [get_bd_pins rf_data_converter/adc2_23_over_threshold1] - connect_bd_net -net rf_data_converter_adc2_23_over_threshold2 [get_bd_pins ThresholdRegister/In8] [get_bd_pins rf_data_converter/adc2_23_over_threshold2] + connect_bd_net -net rf_data_converter_adc1_01_over_threshold1 [get_bd_pins ThresholdRegister/In4] [get_bd_pins rf_data_converter/adc1_01_over_threshold1] + connect_bd_net -net rf_data_converter_adc1_01_over_threshold2 [get_bd_pins ThresholdRegister/In5] [get_bd_pins rf_data_converter/adc1_01_over_threshold2] + connect_bd_net -net rf_data_converter_adc1_23_over_threshold1 [get_bd_pins ThresholdRegister/In6] [get_bd_pins rf_data_converter/adc1_23_over_threshold1] + connect_bd_net -net rf_data_converter_adc1_23_over_threshold2 [get_bd_pins ThresholdRegister/In7] [get_bd_pins rf_data_converter/adc1_23_over_threshold2] + connect_bd_net -net rf_data_converter_adc1_nco_update_busy [get_bd_pins rf_data_converter/adc1_nco_update_busy] [get_bd_pins rf_nco_reset_0/cAdc1xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_adc2_01_over_threshold1 [get_bd_pins ThresholdRegister/In8] [get_bd_pins rf_data_converter/adc2_01_over_threshold1] + connect_bd_net -net rf_data_converter_adc2_01_over_threshold2 [get_bd_pins ThresholdRegister/In9] [get_bd_pins rf_data_converter/adc2_01_over_threshold2] + connect_bd_net -net rf_data_converter_adc2_23_over_threshold1 [get_bd_pins ThresholdRegister/In10] [get_bd_pins rf_data_converter/adc2_23_over_threshold1] + connect_bd_net -net rf_data_converter_adc2_23_over_threshold2 [get_bd_pins ThresholdRegister/In11] [get_bd_pins rf_data_converter/adc2_23_over_threshold2] connect_bd_net -net rf_data_converter_adc2_nco_update_busy [get_bd_pins rf_data_converter/adc2_nco_update_busy] [get_bd_pins rf_nco_reset_0/cAdc2xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_adc3_01_over_threshold1 [get_bd_pins ThresholdRegister/In12] [get_bd_pins rf_data_converter/adc3_01_over_threshold1] + connect_bd_net -net rf_data_converter_adc3_01_over_threshold2 [get_bd_pins ThresholdRegister/In13] [get_bd_pins rf_data_converter/adc3_01_over_threshold2] + connect_bd_net -net rf_data_converter_adc3_23_over_threshold1 [get_bd_pins ThresholdRegister/In14] [get_bd_pins rf_data_converter/adc3_23_over_threshold1] + connect_bd_net -net rf_data_converter_adc3_23_over_threshold2 [get_bd_pins ThresholdRegister/In15] [get_bd_pins rf_data_converter/adc3_23_over_threshold2] + connect_bd_net -net rf_data_converter_adc3_nco_update_busy [get_bd_pins rf_data_converter/adc3_nco_update_busy] [get_bd_pins rf_nco_reset_0/cAdc3xNcoUpdateBusy] + connect_bd_net -net rf_data_converter_clk_adc0 [get_bd_pins clk_adc0] [get_bd_pins rf_data_converter/clk_adc0] connect_bd_net -net rf_data_converter_dac0_nco_update_busy [get_bd_pins rf_data_converter/dac0_nco_update_busy] [get_bd_pins rf_nco_reset_0/cDac0xNcoUpdateBusy] connect_bd_net -net rf_data_converter_dac1_nco_update_busy [get_bd_pins rf_data_converter/dac1_nco_update_busy] [get_bd_pins rf_nco_reset_0/cDac1xNcoUpdateBusy] connect_bd_net -net rf_data_converter_irq [get_bd_pins rfdc_irq] [get_bd_pins rf_data_converter/irq] connect_bd_net -net rf_nco_reset_0_cAdc0xNcoUpdateReq [get_bd_pins rf_data_converter/adc0_nco_update_req] [get_bd_pins rf_nco_reset_0/cAdc0xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cAdc1xNcoUpdateReq [get_bd_pins rf_data_converter/adc1_nco_update_req] [get_bd_pins rf_nco_reset_0/cAdc1xNcoUpdateReq] connect_bd_net -net rf_nco_reset_0_cAdc2xNcoUpdateReq [get_bd_pins rf_data_converter/adc2_nco_update_req] [get_bd_pins rf_nco_reset_0/cAdc2xNcoUpdateReq] + connect_bd_net -net rf_nco_reset_0_cAdc3xNcoUpdateReq [get_bd_pins rf_data_converter/adc3_nco_update_req] [get_bd_pins rf_nco_reset_0/cAdc3xNcoUpdateReq] connect_bd_net -net rf_nco_reset_0_cDac0xNcoUpdateReq [get_bd_pins rf_data_converter/dac0_nco_update_req] [get_bd_pins rf_nco_reset_0/cDac0xNcoUpdateReq] connect_bd_net -net rf_nco_reset_0_cDac0xSysrefIntGating [get_bd_pins rf_data_converter/dac0_sysref_int_gating] [get_bd_pins rf_nco_reset_0/cDac0xSysrefIntGating] connect_bd_net -net rf_nco_reset_0_cDac0xSysrefIntReenable [get_bd_pins rf_data_converter/dac0_sysref_int_reenable] [get_bd_pins rf_nco_reset_0/cDac0xSysrefIntReenable] connect_bd_net -net rf_nco_reset_0_cDac1xNcoUpdateReq [get_bd_pins rf_data_converter/dac1_nco_update_req] [get_bd_pins rf_nco_reset_0/cDac1xNcoUpdateReq] - connect_bd_net -net rf_nco_reset_0_cNcoPhaseRst [get_bd_pins rf_data_converter/adc0_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc0_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_23_nco_phase_rst] [get_bd_pins rf_data_converter/dac00_nco_phase_rst] [get_bd_pins rf_data_converter/dac01_nco_phase_rst] [get_bd_pins rf_data_converter/dac10_nco_phase_rst] [get_bd_pins rf_data_converter/dac11_nco_phase_rst] [get_bd_pins rf_nco_reset_0/cNcoPhaseRst] - connect_bd_net -net rf_nco_reset_0_cNcoUpdateEn [get_bd_pins rf_data_converter/adc0_01_nco_update_en] [get_bd_pins rf_data_converter/adc0_23_nco_update_en] [get_bd_pins rf_data_converter/adc2_01_nco_update_en] [get_bd_pins rf_data_converter/adc2_23_nco_update_en] [get_bd_pins rf_data_converter/dac00_nco_update_en] [get_bd_pins rf_data_converter/dac01_nco_update_en] [get_bd_pins rf_data_converter/dac10_nco_update_en] [get_bd_pins rf_data_converter/dac11_nco_update_en] [get_bd_pins rf_nco_reset_0/cNcoUpdateEn] + connect_bd_net -net rf_nco_reset_0_cNcoPhaseRst [get_bd_pins rf_data_converter/adc0_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc0_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc1_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc1_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc2_23_nco_phase_rst] [get_bd_pins rf_data_converter/adc3_01_nco_phase_rst] [get_bd_pins rf_data_converter/adc3_23_nco_phase_rst] [get_bd_pins rf_data_converter/dac00_nco_phase_rst] [get_bd_pins rf_data_converter/dac01_nco_phase_rst] [get_bd_pins rf_data_converter/dac02_nco_phase_rst] [get_bd_pins rf_data_converter/dac03_nco_phase_rst] [get_bd_pins rf_data_converter/dac10_nco_phase_rst] [get_bd_pins rf_data_converter/dac11_nco_phase_rst] [get_bd_pins rf_data_converter/dac12_nco_phase_rst] [get_bd_pins rf_data_converter/dac13_nco_phase_rst] [get_bd_pins rf_nco_reset_0/cNcoPhaseRst] + connect_bd_net -net rf_nco_reset_0_cNcoUpdateEn [get_bd_pins rf_data_converter/adc0_01_nco_update_en] [get_bd_pins rf_data_converter/adc0_23_nco_update_en] [get_bd_pins rf_data_converter/adc1_01_nco_update_en] [get_bd_pins rf_data_converter/adc1_23_nco_update_en] [get_bd_pins rf_data_converter/adc2_01_nco_update_en] [get_bd_pins rf_data_converter/adc2_23_nco_update_en] [get_bd_pins rf_data_converter/adc3_01_nco_update_en] [get_bd_pins rf_data_converter/adc3_23_nco_update_en] [get_bd_pins rf_data_converter/dac00_nco_update_en] [get_bd_pins rf_data_converter/dac01_nco_update_en] [get_bd_pins rf_data_converter/dac02_nco_update_en] [get_bd_pins rf_data_converter/dac03_nco_update_en] [get_bd_pins rf_data_converter/dac10_nco_update_en] [get_bd_pins rf_data_converter/dac11_nco_update_en] [get_bd_pins rf_data_converter/dac12_nco_update_en] [get_bd_pins rf_data_converter/dac13_nco_update_en] [get_bd_pins rf_nco_reset_0/cNcoUpdateEn] connect_bd_net -net rf_nco_reset_0_dNcoResetDone [get_bd_pins nco_reset_done_dclk] [get_bd_pins rf_nco_reset_0/dNcoResetDone] - connect_bd_net -net rf_reset_controller_0_cSoftwareStatus [get_bd_pins reg_rf_reset_control/gpio2_io_i] [get_bd_pins rf_reset_controller_0/cSoftwareStatus] - connect_bd_net -net rf_reset_controller_0_d2DacFirReset_n [get_bd_pins dac_data_in_resetn_dclk2x] [get_bd_pins rf_reset_controller_0/d2DacFirReset_n] - connect_bd_net -net rf_reset_controller_0_dAdcDataOutReset_n [get_bd_pins adc_data_out_resetn_dclk] [get_bd_pins rf_reset_controller_0/dAdcDataOutReset_n] - connect_bd_net -net rf_reset_controller_0_dDacDataInReset_n [get_bd_pins dac_data_in_resetn_dclk] [get_bd_pins rf_reset_controller_0/dDacDataInReset_n] - connect_bd_net -net rf_reset_controller_0_r2AdcFirReset_n [get_bd_pins fir_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2AdcFirReset_n] - connect_bd_net -net rf_reset_controller_0_r2DacFirReset_n [get_bd_pins dac_data_in_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2DacFirReset_n] - connect_bd_net -net rf_reset_controller_0_rAdcEnableData [get_bd_pins adc_enable_data_rclk] [get_bd_pins rf_reset_controller_0/rAdcEnableData] - connect_bd_net -net rf_reset_controller_0_rAdcGearboxReset_n [get_bd_pins adc_rfdc_axi_resetn_rclk] [get_bd_pins rf_reset_controller_0/rAdcGearboxReset_n] - connect_bd_net -net rf_reset_controller_0_rAdcRfdcAxiReset_n [get_bd_pins rf_data_converter/m0_axis_aresetn] [get_bd_pins rf_data_converter/m2_axis_aresetn] [get_bd_pins rf_reset_controller_0/rAdcRfdcAxiReset_n] - connect_bd_net -net rf_reset_controller_0_rDacGearboxReset_n [get_bd_pins dac_data_in_resetn_rclk] [get_bd_pins rf_reset_controller_0/rDacGearboxReset_n] - connect_bd_net -net rf_reset_controller_0_rDacRfdcAxiReset_n [get_bd_pins rf_data_converter/s0_axis_aresetn] [get_bd_pins rf_data_converter/s1_axis_aresetn] [get_bd_pins rf_reset_controller_0/rDacRfdcAxiReset_n] - connect_bd_net -net rfdc_regs_gpio_io_o [get_bd_pins reg_invert_iq/gpio_io_o] [get_bd_pins slice_15_8/Din] [get_bd_pins slice_7_0/Din] - connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins ThresholdRegister/s_axi_config_aresetn] [get_bd_pins axi_interconnect_rf/ARESETN] [get_bd_pins axi_interconnect_rf/M00_ARESETN] [get_bd_pins axi_interconnect_rf/M03_ARESETN] [get_bd_pins axi_interconnect_rf/M04_ARESETN] [get_bd_pins axi_interconnect_rf/M05_ARESETN] [get_bd_pins axi_interconnect_rf/M06_ARESETN] [get_bd_pins axi_interconnect_rf/M07_ARESETN] [get_bd_pins axi_interconnect_rf/M08_ARESETN] [get_bd_pins axi_interconnect_rf/S00_ARESETN] [get_bd_pins calibration_muxes/s_axi_config_aresetn] [get_bd_pins reg_clock_gate_control/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/s_axi_aresetn] [get_bd_pins reg_rf_axi_status/s_axi_aresetn] [get_bd_pins reg_rf_reset_control/s_axi_aresetn] [get_bd_pins rf_data_converter/s_axi_aresetn] - connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins ThresholdRegister/s_axi_config_clk] [get_bd_pins axi_interconnect_rf/ACLK] [get_bd_pins axi_interconnect_rf/M00_ACLK] [get_bd_pins axi_interconnect_rf/M01_ACLK] [get_bd_pins axi_interconnect_rf/M03_ACLK] [get_bd_pins axi_interconnect_rf/M04_ACLK] [get_bd_pins axi_interconnect_rf/M05_ACLK] [get_bd_pins axi_interconnect_rf/M06_ACLK] [get_bd_pins axi_interconnect_rf/M07_ACLK] [get_bd_pins axi_interconnect_rf/M08_ACLK] [get_bd_pins axi_interconnect_rf/S00_ACLK] [get_bd_pins calibration_muxes/s_axi_config_clk] [get_bd_pins clock_gates_0/ReliableClk] [get_bd_pins data_clock_mmcm/s_axi_aclk] [get_bd_pins reg_clock_gate_control/s_axi_aclk] [get_bd_pins reg_reset_mmcm/s_axi_aclk] [get_bd_pins reg_rf_axi_status/s_axi_aclk] [get_bd_pins reg_rf_reset_control/s_axi_aclk] [get_bd_pins rf_data_converter/s_axi_aclk] [get_bd_pins rf_nco_reset_0/ConfigClk] [get_bd_pins rf_reset_controller_0/ConfigClk] + connect_bd_net -net rf_reset_controller_0_rAdcRfdcAxiReset_n [get_bd_pins adc_rfdc_axi_resetn_rclk] [get_bd_pins rf_data_converter/m0_axis_aresetn] [get_bd_pins rf_data_converter/m1_axis_aresetn] [get_bd_pins rf_reset_controller_0/rAdcReset_n] + connect_bd_net -net rf_reset_controller_1_cSoftwareStatus [get_bd_pins reg_rf_reset_control_radio1/gpio2_io_i] [get_bd_pins rf_reset_controller_1/cSoftwareStatus] + connect_bd_net -net rf_reset_controller_1_rAdcReset_n [get_bd_pins rf_data_converter/m2_axis_aresetn] [get_bd_pins rf_data_converter/m3_axis_aresetn] [get_bd_pins rf_reset_controller_1/rAdcReset_n] + connect_bd_net -net rf_reset_controller_1_rDacReset_n [get_bd_pins rf_data_converter/s1_axis_aresetn] [get_bd_pins rf_reset_controller_1/rDacReset_n] + connect_bd_net -net rf_rfdc_info_sclk_1 [get_bd_pins rf_rfdc_info_sclk] [get_bd_pins reg_rfdc_info/gpio_io_i] + connect_bd_net -net rfdc_adc_map_dout [get_bd_pins reg_rfdc_tile_mapping/gpio_io_i] [get_bd_pins rfdc_adc_map/dout] + connect_bd_net -net rfdc_regs_gpio_io_o [get_bd_pins reg_invert_iq_radio0/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio0/Din] [get_bd_pins slice_iqswap_3_0_radio0/Din] + connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins ThresholdRegister/s_axi_config_aresetn] [get_bd_pins axi_interconnect_rf/ARESETN] [get_bd_pins axi_interconnect_rf/M00_ARESETN] [get_bd_pins axi_interconnect_rf/M03_ARESETN] [get_bd_pins axi_interconnect_rf/M04_ARESETN] [get_bd_pins axi_interconnect_rf/M05_ARESETN] [get_bd_pins axi_interconnect_rf/M06_ARESETN] [get_bd_pins axi_interconnect_rf/M07_ARESETN] [get_bd_pins axi_interconnect_rf/M08_ARESETN] [get_bd_pins axi_interconnect_rf/M09_ARESETN] [get_bd_pins axi_interconnect_rf/M10_ARESETN] [get_bd_pins axi_interconnect_rf/M12_ARESETN] [get_bd_pins axi_interconnect_rf/S00_ARESETN] [get_bd_pins calibration_muxes/s_axi_config_aresetn] [get_bd_pins reg_clock_gate_control/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/s_axi_aresetn] [get_bd_pins reg_rf_axi_status/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aresetn] [get_bd_pins reg_rfdc_info/s_axi_aresetn] [get_bd_pins reg_rfdc_tile_mapping/s_axi_aresetn] [get_bd_pins rf_data_converter/s_axi_aresetn] + connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins ThresholdRegister/s_axi_config_clk] [get_bd_pins axi_interconnect_rf/ACLK] [get_bd_pins axi_interconnect_rf/M00_ACLK] [get_bd_pins axi_interconnect_rf/M01_ACLK] [get_bd_pins axi_interconnect_rf/M03_ACLK] [get_bd_pins axi_interconnect_rf/M04_ACLK] [get_bd_pins axi_interconnect_rf/M05_ACLK] [get_bd_pins axi_interconnect_rf/M06_ACLK] [get_bd_pins axi_interconnect_rf/M07_ACLK] [get_bd_pins axi_interconnect_rf/M08_ACLK] [get_bd_pins axi_interconnect_rf/M09_ACLK] [get_bd_pins axi_interconnect_rf/M10_ACLK] [get_bd_pins axi_interconnect_rf/M12_ACLK] [get_bd_pins axi_interconnect_rf/S00_ACLK] [get_bd_pins calibration_muxes/s_axi_config_clk] [get_bd_pins clock_gates_0/ReliableClk] [get_bd_pins data_clock_mmcm/s_axi_aclk] [get_bd_pins reg_clock_gate_control/s_axi_aclk] [get_bd_pins reg_reset_mmcm/s_axi_aclk] [get_bd_pins reg_rf_axi_status/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aclk] [get_bd_pins reg_rfdc_info/s_axi_aclk] [get_bd_pins reg_rfdc_tile_mapping/s_axi_aclk] [get_bd_pins rf_data_converter/s_axi_aclk] [get_bd_pins rf_nco_reset_0/ConfigClk] [get_bd_pins rf_reset_controller_0/ConfigClk] [get_bd_pins rf_reset_controller_1/ConfigClk] + connect_bd_net -net slice_iqswap_11_8_radio0_Dout [get_bd_pins radio0_invert_dac_iq_r0clk] [get_bd_pins slice_iqswap_11_8_radio0/Dout] + connect_bd_net -net slice_iqswap_11_8_radio1_Dout [get_bd_pins radio1_invert_dac_iq_r1clk] [get_bd_pins slice_iqswap_11_8_radio1/Dout] + connect_bd_net -net slice_iqswap_3_0_radio0_Dout [get_bd_pins radio0_invert_adc_iq_r0clk] [get_bd_pins slice_iqswap_3_0_radio0/Dout] + connect_bd_net -net slice_iqswap_3_0_radio1_Dout [get_bd_pins radio1_invert_adc_iq_r1clk] [get_bd_pins slice_iqswap_3_0_radio1/Dout] connect_bd_net -net start_nco_reset_rclk_1 [get_bd_pins start_nco_reset_dclk] [get_bd_pins rf_nco_reset_0/dStartNcoReset] connect_bd_net -net sysref_in_0_2 [get_bd_pins sysref_pl_in] [get_bd_pins capture_sysref/sysref_in] - connect_bd_net -net xlslice_0_Dout [get_bd_pins invert_adc_iq_rclk2] [get_bd_pins slice_7_0/Dout] - connect_bd_net -net xlslice_1_Dout [get_bd_pins invert_dac_iq_rclk2] [get_bd_pins slice_15_8/Dout] + connect_bd_net -net x440_rf_reset_contro_0_cSoftwareStatus [get_bd_pins reg_rf_reset_control_radio0/gpio2_io_i] [get_bd_pins rf_reset_controller_0/cSoftwareStatus] + connect_bd_net -net x440_rf_reset_contro_0_r2AdcReset_n [get_bd_pins fir_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2AdcReset_n] + connect_bd_net -net x440_rf_reset_contro_0_r2DacReset_n [get_bd_pins dac_data_in_resetn_rclk2x] [get_bd_pins rf_reset_controller_0/r2DacReset_n] + connect_bd_net -net x440_rf_reset_contro_0_rAdcEnableData [get_bd_pins adc_enable_data_rclk] [get_bd_pins rf_reset_controller_0/rAdcEnableData] + connect_bd_net -net x440_rf_reset_contro_0_rDacReset_n [get_bd_pins dac_data_in_resetn_rclk] [get_bd_pins rf_data_converter/s0_axis_aresetn] [get_bd_pins rf_reset_controller_0/rDacReset_n] + connect_bd_net -net xlconstant_0_dout [get_bd_pins adc_data_out_resetn_dclk] [get_bd_pins dac_data_in_resetn_dclk] [get_bd_pins dac_data_in_resetn_dclk2x] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconstant_1_dout [get_bd_pins reg_rfdc_tile_mapping/gpio2_io_i] [get_bd_pins rfdc_dac_map/dout] # Restore current instance current_bd_instance $oldCurInst @@ -1443,12 +1774,12 @@ proc create_hier_cell_ps { parentCell nameHier } { set_property -dict [ list \ CONFIG.FREQ_HZ {40000000} \ - CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \ + CONFIG.CLK_DOMAIN {x440_ps_rfdc_bd_clk40} \ ] [get_bd_intf_pins /ps/cpld_jtag_engine/S_AXI] set_property -dict [ list \ CONFIG.FREQ_HZ {40000000} \ - CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \ + CONFIG.CLK_DOMAIN {x440_ps_rfdc_bd_clk40} \ ] [get_bd_pins /ps/cpld_jtag_engine/S_AXI_ACLK] # Create instance: eth_dma_internal @@ -2675,7 +3006,6 @@ MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\ CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ - CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ @@ -2784,18 +3114,18 @@ MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\ CONFIG.PSU__PROTECTION__DEBUG {0} \ CONFIG.PSU__PROTECTION__ENABLE {0} \ CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure\ -;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000\ ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ -Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ -;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000\ +Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000\ ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ -Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ -;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000\ +Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000\ ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ -Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ -;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000\ +Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000\ ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ -Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ ;WrAllowed:Read/Write;subsystemId:PMU Firmware}\ CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ @@ -3102,63 +3432,116 @@ proc create_root_design { parentCell } { # Create interface ports set adc0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc0_clk ] + set adc1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc1_clk ] + set adc2_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc2_clk ] + set adc3_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 adc3_clk ] + set adc_tile224_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_i ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ ] $adc_tile224_ch0_dout_i set adc_tile224_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_q ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ ] $adc_tile224_ch0_dout_q set adc_tile224_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch0_vin ] set adc_tile224_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_i ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ ] $adc_tile224_ch1_dout_i set adc_tile224_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_q ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ ] $adc_tile224_ch1_dout_q set adc_tile224_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch1_vin ] + set adc_tile225_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_i ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + ] $adc_tile225_ch0_dout_i + + set adc_tile225_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_q ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + ] $adc_tile225_ch0_dout_q + + set adc_tile225_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch0_vin ] + + set adc_tile225_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_i ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + ] $adc_tile225_ch1_dout_i + + set adc_tile225_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_q ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + ] $adc_tile225_ch1_dout_q + + set adc_tile225_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch1_vin ] + set adc_tile226_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_i ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ ] $adc_tile226_ch0_dout_i set adc_tile226_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_q ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ ] $adc_tile226_ch0_dout_q set adc_tile226_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch0_vin ] set adc_tile226_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_i ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ ] $adc_tile226_ch1_dout_i set adc_tile226_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_q ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ ] $adc_tile226_ch1_dout_q set adc_tile226_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch1_vin ] + set adc_tile227_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_i ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + ] $adc_tile227_ch0_dout_i + + set adc_tile227_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_q ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + ] $adc_tile227_ch0_dout_q + + set adc_tile227_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile227_ch0_vin ] + + set adc_tile227_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_i ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + ] $adc_tile227_ch1_dout_i + + set adc_tile227_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_q ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + CONFIG.PHASE {0.0} \ + ] $adc_tile227_ch1_dout_q + + set adc_tile227_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile227_ch1_vin ] + set dac0_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac0_clk ] set dac1_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 dac1_clk ] set dac_tile228_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TREADY {1} \ @@ -3174,7 +3557,7 @@ proc create_root_design { parentCell } { set dac_tile228_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TREADY {1} \ @@ -3188,9 +3571,43 @@ proc create_root_design { parentCell } { set dac_tile228_ch1_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch1_vout ] + set dac_tile228_ch2_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch2_din ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.PHASE {0.0} \ + CONFIG.TDATA_NUM_BYTES {32} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_tile228_ch2_din + + set dac_tile228_ch2_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch2_vout ] + + set dac_tile228_ch3_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch3_din ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.PHASE {0.0} \ + CONFIG.TDATA_NUM_BYTES {32} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_tile228_ch3_din + + set dac_tile228_ch3_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile228_ch3_vout ] + set dac_tile229_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TREADY {1} \ @@ -3206,7 +3623,7 @@ proc create_root_design { parentCell } { set dac_tile229_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din ] set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ + CONFIG.FREQ_HZ {64000000} \ CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TREADY {1} \ @@ -3220,6 +3637,40 @@ proc create_root_design { parentCell } { set dac_tile229_ch1_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch1_vout ] + set dac_tile229_ch2_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch2_din ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.PHASE {0.0} \ + CONFIG.TDATA_NUM_BYTES {32} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_tile229_ch2_din + + set dac_tile229_ch2_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch2_vout ] + + set dac_tile229_ch3_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch3_din ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {64000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.PHASE {0.0} \ + CONFIG.TDATA_NUM_BYTES {32} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $dac_tile229_ch3_din + + set dac_tile229_ch3_vout [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 dac_tile229_ch3_vout ] + set gpio_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_0 ] set m_axi_app [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_app ] @@ -3439,7 +3890,7 @@ proc create_root_design { parentCell } { # Create ports - set adc_data_out_resetn_dclk [ create_bd_port -dir O adc_data_out_resetn_dclk ] + set adc_data_out_resetn_dclk [ create_bd_port -dir O -from 0 -to 0 adc_data_out_resetn_dclk ] set adc_enable_data_rclk [ create_bd_port -dir O adc_enable_data_rclk ] set adc_reset_pulse_dclk [ create_bd_port -dir I -type rst adc_reset_pulse_dclk ] set_property -dict [ list \ @@ -3458,8 +3909,9 @@ proc create_root_design { parentCell } { CONFIG.ASSOCIATED_RESET {clk40_rstn} \ ] $clk40 set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] - set dac_data_in_resetn_dclk [ create_bd_port -dir O dac_data_in_resetn_dclk ] - set dac_data_in_resetn_dclk2x [ create_bd_port -dir O dac_data_in_resetn_dclk2x ] + set clk_adc0 [ create_bd_port -dir O clk_adc0 ] + set dac_data_in_resetn_dclk [ create_bd_port -dir O -from 0 -to 0 dac_data_in_resetn_dclk ] + set dac_data_in_resetn_dclk2x [ create_bd_port -dir O -from 0 -to 0 dac_data_in_resetn_dclk2x ] set dac_data_in_resetn_rclk [ create_bd_port -dir O dac_data_in_resetn_rclk ] set dac_data_in_resetn_rclk2x [ create_bd_port -dir O dac_data_in_resetn_rclk2x ] set dac_reset_pulse_dclk [ create_bd_port -dir I -type rst dac_reset_pulse_dclk ] @@ -3468,19 +3920,17 @@ proc create_root_design { parentCell } { ] $dac_reset_pulse_dclk set data_clk [ create_bd_port -dir O -type clk data_clk ] set_property -dict [ list \ - CONFIG.FREQ_HZ {122880000} \ + CONFIG.FREQ_HZ {128000000} \ ] $data_clk set data_clk_2x [ create_bd_port -dir O -type clk data_clk_2x ] set_property -dict [ list \ - CONFIG.FREQ_HZ {245760000} \ + CONFIG.FREQ_HZ {256000000} \ ] $data_clk_2x set data_clock_locked [ create_bd_port -dir O data_clock_locked ] set enable_gated_clocks_clk40 [ create_bd_port -dir I enable_gated_clocks_clk40 ] set enable_sysref_rclk [ create_bd_port -dir I enable_sysref_rclk ] set fir_resetn_rclk2x [ create_bd_port -dir O fir_resetn_rclk2x ] set gated_base_clks_valid_clk40 [ create_bd_port -dir O gated_base_clks_valid_clk40 ] - set invert_adc_iq_rclk2 [ create_bd_port -dir O -from 7 -to 0 invert_adc_iq_rclk2 ] - set invert_dac_iq_rclk2 [ create_bd_port -dir O -from 7 -to 0 invert_dac_iq_rclk2 ] set irq0_lpd_rpu_n [ create_bd_port -dir I irq0_lpd_rpu_n ] set irq1_lpd_rpu_n [ create_bd_port -dir I irq1_lpd_rpu_n ] set jtag0_tck [ create_bd_port -dir IO jtag0_tck ] @@ -3506,23 +3956,30 @@ proc create_root_design { parentCell } { set pl_resetn1 [ create_bd_port -dir O -type rst pl_resetn1 ] set pl_resetn2 [ create_bd_port -dir O -type rst pl_resetn2 ] set pl_resetn3 [ create_bd_port -dir O -type rst pl_resetn3 ] - set pll_ref_clk_in [ create_bd_port -dir I -type clk -freq_hz 61440000 pll_ref_clk_in ] + set pll_ref_clk_in [ create_bd_port -dir I -type clk -freq_hz 64000000 pll_ref_clk_in ] set pll_ref_clk_out [ create_bd_port -dir O -type clk pll_ref_clk_out ] set_property -dict [ list \ - CONFIG.FREQ_HZ {61440000} \ + CONFIG.FREQ_HZ {64000000} \ ] $pll_ref_clk_out - set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ] - set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ] - set rfdc_clk [ create_bd_port -dir O -from 0 -to 0 -type clk rfdc_clk ] + set radio0_invert_adc_iq_r0clk [ create_bd_port -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk ] + set radio0_invert_dac_iq_r0clk [ create_bd_port -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk ] + set radio0_rfdc_clk_1x [ create_bd_port -dir O -from 0 -to 0 -type clk radio0_rfdc_clk_1x ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {adc_tile224_ch0_dout_i:adc_tile224_ch1_dout_i:adc_tile224_ch1_dout_q:adc_tile224_ch0_dout_q:dac_tile228_ch0_din:dac_tile228_ch1_din:dac_tile229_ch0_din:dac_tile229_ch1_din:adc_tile226_ch0_dout_i:adc_tile226_ch0_dout_q:adc_tile226_ch1_dout_i:adc_tile226_ch1_dout_q} \ CONFIG.ASSOCIATED_RESET {adc_tile224_axis_resetn_rclk:adc_tile226_axis_resetn_rclk:dac_tile228_axis_resetn_rclk:dac_tile229_axis_resetn_rclk} \ - CONFIG.FREQ_HZ {184320000} \ - ] $rfdc_clk - set rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 -type clk rfdc_clk_2x ] + CONFIG.FREQ_HZ {64000000} \ + ] $radio0_rfdc_clk_1x + set radio0_rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 -type clk radio0_rfdc_clk_2x ] set_property -dict [ list \ - CONFIG.FREQ_HZ {368640000} \ - ] $rfdc_clk_2x + CONFIG.FREQ_HZ {128000000} \ + ] $radio0_rfdc_clk_2x + set radio1_invert_adc_iq_r1clk [ create_bd_port -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk ] + set radio1_invert_dac_iq_r1clk [ create_bd_port -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk ] + set radio1_rfdc_clk_1x [ create_bd_port -dir O -from 0 -to 0 radio1_rfdc_clk_1x ] + set radio1_rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 radio1_rfdc_clk_2x ] + set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ] + set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ] + set rf_rfdc_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_rfdc_info_clk40 ] set rfdc_irq [ create_bd_port -dir O -type intr rfdc_irq ] set s_axi_hp0_aclk [ create_bd_port -dir I -type clk -freq_hz 40000000 s_axi_hp0_aclk ] set_property -dict [ list \ @@ -3554,10 +4011,20 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net S_AXI_HP1_1 [get_bd_intf_ports s_axi_hp1] [get_bd_intf_pins ps/s_axi_hp1] connect_bd_intf_net -intf_net S_AXI_HPC0_FPD_0_1 [get_bd_intf_ports s_axi_hpc0] [get_bd_intf_pins ps/s_axi_hpc0] connect_bd_intf_net -intf_net adc0_clk_0_1 [get_bd_intf_ports adc0_clk] [get_bd_intf_pins rfdc/adc0_clk] + connect_bd_intf_net -intf_net adc1_clk_1 [get_bd_intf_ports adc1_clk] [get_bd_intf_pins rfdc/adc1_clk] connect_bd_intf_net -intf_net adc2_clk_0_1 [get_bd_intf_ports adc2_clk] [get_bd_intf_pins rfdc/adc2_clk] + connect_bd_intf_net -intf_net adc3_clk_1 [get_bd_intf_ports adc3_clk] [get_bd_intf_pins rfdc/adc3_clk] + connect_bd_intf_net -intf_net adc_tile225_ch0_vin_1 [get_bd_intf_ports adc_tile225_ch0_vin] [get_bd_intf_pins rfdc/adc_tile225_ch0_vin] + connect_bd_intf_net -intf_net adc_tile225_ch1_vin_1 [get_bd_intf_ports adc_tile225_ch1_vin] [get_bd_intf_pins rfdc/adc_tile225_ch1_vin] + connect_bd_intf_net -intf_net adc_tile227_ch0_vin_1 [get_bd_intf_ports adc_tile227_ch0_vin] [get_bd_intf_pins rfdc/adc_tile227_ch0_vin] + connect_bd_intf_net -intf_net adc_tile227_ch1_vin_1 [get_bd_intf_ports adc_tile227_ch1_vin] [get_bd_intf_pins rfdc/adc_tile227_ch1_vin] connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_uhd [get_bd_intf_ports m_axi_app] [get_bd_intf_pins ps/m_axi_app] connect_bd_intf_net -intf_net dac0_clk_0_1 [get_bd_intf_ports dac0_clk] [get_bd_intf_pins rfdc/dac0_clk] connect_bd_intf_net -intf_net dac1_clk_0_1 [get_bd_intf_ports dac1_clk] [get_bd_intf_pins rfdc/dac1_clk] + connect_bd_intf_net -intf_net dac_tile228_ch2_din_1 [get_bd_intf_ports dac_tile228_ch2_din] [get_bd_intf_pins rfdc/dac_tile228_ch2_din] + connect_bd_intf_net -intf_net dac_tile228_ch3_din_1 [get_bd_intf_ports dac_tile228_ch3_din] [get_bd_intf_pins rfdc/dac_tile228_ch3_din] + connect_bd_intf_net -intf_net dac_tile229_ch2_din_1 [get_bd_intf_ports dac_tile229_ch2_din] [get_bd_intf_pins rfdc/dac_tile229_ch2_din] + connect_bd_intf_net -intf_net dac_tile229_ch3_din_1 [get_bd_intf_ports dac_tile229_ch3_din] [get_bd_intf_pins rfdc/dac_tile229_ch3_din] connect_bd_intf_net -intf_net inst_zynq_ps_GPIO_0 [get_bd_intf_ports gpio_0] [get_bd_intf_pins ps/gpio_0] connect_bd_intf_net -intf_net ps_M07_AXI_0 [get_bd_intf_ports m_axi_eth_internal] [get_bd_intf_pins ps/m_axi_eth_internal] connect_bd_intf_net -intf_net ps_M_AXIS_MM2S_1 [get_bd_intf_ports m_axis_eth_dma] [get_bd_intf_pins ps/m_axis_eth_dma] @@ -3577,6 +4044,18 @@ proc create_root_design { parentCell } { connect_bd_intf_net -intf_net rf_data_converter_vout01 [get_bd_intf_ports dac_tile228_ch1_vout] [get_bd_intf_pins rfdc/dac_tile228_ch1_vout] connect_bd_intf_net -intf_net rf_data_converter_vout10 [get_bd_intf_ports dac_tile229_ch0_vout] [get_bd_intf_pins rfdc/dac_tile229_ch0_vout] connect_bd_intf_net -intf_net rf_data_converter_vout11 [get_bd_intf_ports dac_tile229_ch1_vout] [get_bd_intf_pins rfdc/dac_tile229_ch1_vout] + connect_bd_intf_net -intf_net rfdc_adc_tile225_ch0_dout_i [get_bd_intf_ports adc_tile225_ch0_dout_i] [get_bd_intf_pins rfdc/adc_tile225_ch0_dout_i] + connect_bd_intf_net -intf_net rfdc_adc_tile225_ch0_dout_q [get_bd_intf_ports adc_tile225_ch0_dout_q] [get_bd_intf_pins rfdc/adc_tile225_ch0_dout_q] + connect_bd_intf_net -intf_net rfdc_adc_tile225_ch1_dout_i [get_bd_intf_ports adc_tile225_ch1_dout_i] [get_bd_intf_pins rfdc/adc_tile225_ch1_dout_i] + connect_bd_intf_net -intf_net rfdc_adc_tile225_ch1_dout_q [get_bd_intf_ports adc_tile225_ch1_dout_q] [get_bd_intf_pins rfdc/adc_tile225_ch1_dout_q] + connect_bd_intf_net -intf_net rfdc_adc_tile227_ch0_dout_i [get_bd_intf_ports adc_tile227_ch0_dout_i] [get_bd_intf_pins rfdc/adc_tile227_ch0_dout_i] + connect_bd_intf_net -intf_net rfdc_adc_tile227_ch0_dout_q [get_bd_intf_ports adc_tile227_ch0_dout_q] [get_bd_intf_pins rfdc/adc_tile227_ch0_dout_q] + connect_bd_intf_net -intf_net rfdc_adc_tile227_ch1_dout_i [get_bd_intf_ports adc_tile227_ch1_dout_i] [get_bd_intf_pins rfdc/adc_tile227_ch1_dout_i] + connect_bd_intf_net -intf_net rfdc_adc_tile227_ch1_dout_q [get_bd_intf_ports adc_tile227_ch1_dout_q] [get_bd_intf_pins rfdc/adc_tile227_ch1_dout_q] + connect_bd_intf_net -intf_net rfdc_dac_tile228_ch2_vout [get_bd_intf_ports dac_tile228_ch2_vout] [get_bd_intf_pins rfdc/dac_tile228_ch2_vout] + connect_bd_intf_net -intf_net rfdc_dac_tile228_ch3_vout [get_bd_intf_ports dac_tile228_ch3_vout] [get_bd_intf_pins rfdc/dac_tile228_ch3_vout] + connect_bd_intf_net -intf_net rfdc_dac_tile229_ch2_vout [get_bd_intf_ports dac_tile229_ch2_vout] [get_bd_intf_pins rfdc/dac_tile229_ch2_vout] + connect_bd_intf_net -intf_net rfdc_dac_tile229_ch3_vout [get_bd_intf_ports dac_tile229_ch3_vout] [get_bd_intf_pins rfdc/dac_tile229_ch3_vout] connect_bd_intf_net -intf_net s00_axis_0_1 [get_bd_intf_ports dac_tile228_ch0_din] [get_bd_intf_pins rfdc/dac_tile228_ch0_din] connect_bd_intf_net -intf_net s01_axis_0_1 [get_bd_intf_ports dac_tile228_ch1_din] [get_bd_intf_pins rfdc/dac_tile228_ch1_din] connect_bd_intf_net -intf_net s10_axis_0_1 [get_bd_intf_ports dac_tile229_ch0_din] [get_bd_intf_pins rfdc/dac_tile229_ch0_din] @@ -3626,18 +4105,24 @@ proc create_root_design { parentCell } { connect_bd_net -net rf_data_converter_irq [get_bd_ports rfdc_irq] [get_bd_pins rfdc/rfdc_irq] connect_bd_net -net rf_nco_reset_0_rNcoResetDone [get_bd_ports nco_reset_done_dclk] [get_bd_pins rfdc/nco_reset_done_dclk] connect_bd_net -net rf_reset_controller_0_rAdcEnableData [get_bd_ports adc_enable_data_rclk] [get_bd_pins rfdc/adc_enable_data_rclk] + connect_bd_net -net rf_rfdc_info_clk40_1 [get_bd_ports rf_rfdc_info_clk40] [get_bd_pins rfdc/rf_rfdc_info_sclk] connect_bd_net -net rfdc_adc_rfdc_axi_resetn_rclk [get_bd_ports adc_rfdc_axi_resetn_rclk] [get_bd_pins rfdc/adc_rfdc_axi_resetn_rclk] + connect_bd_net -net rfdc_clk_adc0 [get_bd_ports clk_adc0] [get_bd_pins rfdc/clk_adc0] connect_bd_net -net rfdc_d2DacFirReset_n_0 [get_bd_ports dac_data_in_resetn_dclk2x] [get_bd_pins rfdc/dac_data_in_resetn_dclk2x] connect_bd_net -net rfdc_dAdcDataOutReset_n_0 [get_bd_ports adc_data_out_resetn_dclk] [get_bd_pins rfdc/adc_data_out_resetn_dclk] connect_bd_net -net rfdc_dDacDataInReset_n_0 [get_bd_ports dac_data_in_resetn_dclk] [get_bd_pins rfdc/dac_data_in_resetn_dclk] connect_bd_net -net rfdc_dac_data_in_resetn_rclk [get_bd_ports dac_data_in_resetn_rclk] [get_bd_pins rfdc/dac_data_in_resetn_rclk] connect_bd_net -net rfdc_gated_base_clk_valid [get_bd_ports gated_base_clks_valid_clk40] [get_bd_pins rfdc/gated_base_clks_valid_clk40] - connect_bd_net -net rfdc_invert_adc_iq_rclk2 [get_bd_ports invert_adc_iq_rclk2] [get_bd_pins rfdc/invert_adc_iq_rclk2] - connect_bd_net -net rfdc_invert_dac_iq_rclk2 [get_bd_ports invert_dac_iq_rclk2] [get_bd_pins rfdc/invert_dac_iq_rclk2] connect_bd_net -net rfdc_r2AdcFirReset_n_0 [get_bd_ports fir_resetn_rclk2x] [get_bd_pins rfdc/fir_resetn_rclk2x] connect_bd_net -net rfdc_r2DacFirReset_n_0 [get_bd_ports dac_data_in_resetn_rclk2x] [get_bd_pins rfdc/dac_data_in_resetn_rclk2x] - connect_bd_net -net rfdc_rfdc_clk [get_bd_ports rfdc_clk] [get_bd_pins rfdc/rfdc_clk] - connect_bd_net -net rfdc_rfdc_clk_2x [get_bd_ports rfdc_clk_2x] [get_bd_pins rfdc/rfdc_clk_2x] + connect_bd_net -net rfdc_radio0_invert_adc_iq_r0clk [get_bd_ports radio0_invert_adc_iq_r0clk] [get_bd_pins rfdc/radio0_invert_adc_iq_r0clk] + connect_bd_net -net rfdc_radio0_invert_dac_iq_r0clk [get_bd_ports radio0_invert_dac_iq_r0clk] [get_bd_pins rfdc/radio0_invert_dac_iq_r0clk] + connect_bd_net -net rfdc_radio1_invert_adc_iq_r1clk [get_bd_ports radio1_invert_adc_iq_r1clk] [get_bd_pins rfdc/radio1_invert_adc_iq_r1clk] + connect_bd_net -net rfdc_radio1_invert_dac_iq_r1clk [get_bd_ports radio1_invert_dac_iq_r1clk] [get_bd_pins rfdc/radio1_invert_dac_iq_r1clk] + connect_bd_net -net rfdc_radio1_rfdc_clk_1x [get_bd_ports radio1_rfdc_clk_1x] [get_bd_pins rfdc/radio1_rfdc_clk_1x] + connect_bd_net -net rfdc_radio1_rfdc_clk_2x [get_bd_ports radio1_rfdc_clk_2x] [get_bd_pins rfdc/radio1_rfdc_clk_2x] + connect_bd_net -net rfdc_rfdc_clk [get_bd_ports radio0_rfdc_clk_1x] [get_bd_pins rfdc/radio0_rfdc_clk] + connect_bd_net -net rfdc_rfdc_clk_2x [get_bd_ports radio0_rfdc_clk_2x] [get_bd_pins rfdc/radio0_rfdc_clk_2x] connect_bd_net -net s_axi_hp0_aclk_1 [get_bd_ports s_axi_hp0_aclk] [get_bd_pins ps/s_axi_hp0_aclk] connect_bd_net -net s_axi_hp1_aclk_1 [get_bd_ports s_axi_hp1_aclk] [get_bd_pins ps/s_axi_hp1_aclk] connect_bd_net -net saxihpc0_fpd_aclk_0_1 [get_bd_ports s_axi_hpc0_aclk] [get_bd_pins ps/s_axi_hpc0_aclk] @@ -3655,10 +4140,14 @@ proc create_root_design { parentCell } { assign_bd_address -offset 0x001000080000 -range 0x00020000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_mpm_ep/Reg] -force assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_rpu/Reg] -force assign_bd_address -offset 0x001000156000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_clock_gate_control/S_AXI/Reg] -force - assign_bd_address -offset 0x001000150000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq/S_AXI/Reg] -force + assign_bd_address -offset 0x001000150000 -range 0x00000800 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq_radio0/S_AXI/Reg] -force + assign_bd_address -offset 0x001000150800 -range 0x00000800 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq_radio1/S_AXI/Reg] -force assign_bd_address -offset 0x001000151000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_reset_mmcm/S_AXI/Reg] -force assign_bd_address -offset 0x001000153000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_axi_status/S_AXI/Reg] -force - assign_bd_address -offset 0x001000152000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control/S_AXI/Reg] -force + assign_bd_address -offset 0x001000152000 -range 0x00000800 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control_radio0/S_AXI/Reg] -force + assign_bd_address -offset 0x001000152800 -range 0x00000800 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control_radio1/S_AXI/Reg] -force + assign_bd_address -offset 0x001000158000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rfdc_info/S_AXI/Reg] -force + assign_bd_address -offset 0x001000157000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rfdc_tile_mapping/S_AXI/Reg] -force assign_bd_address -offset 0x001000100000 -range 0x00040000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] -force assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force diff --git a/top/x400/ipass_present_controller.v b/top/x400/ipass_present_controller.v index f88362a..43d8bfa 100644 --- a/top/x400/ipass_present_controller.v +++ b/top/x400/ipass_present_controller.v @@ -40,7 +40,11 @@ module ipass_present_controller ( ); `include "regmap/pl_cpld_regmap_utils.vh" - `include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh" + `ifdef X440 + `include "cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh" + `else // Use X410 as the default variant for regmap. + `include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh" + `endif `include "cpld/regmap/pl_cpld_base_regmap_utils.vh" `include "../../lib/rfnoc/core/ctrlport.vh" diff --git a/top/x400/regmap/rfdc_regs_regmap_utils.vh b/top/x400/regmap/rfdc_regs_regmap_utils.vh deleted file mode 100644 index 4d092f4..0000000 --- a/top/x400/regmap/rfdc_regs_regmap_utils.vh +++ /dev/null @@ -1,303 +0,0 @@ -// -// Copyright 2022 Ettus Research, A National Instruments Company -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// -// Module: rfdc_regs_regmap_utils.vh -// Description: -// The constants in this file are autogenerated by XmlParse. - -//=============================================================================== -// A numerically ordered list of registers and their HDL source files -//=============================================================================== - - // MMCM : 0x0 (common_regs.v) - // INVERT_IQ_REG : 0x10000 (common_regs.v) - // MMCM_RESET_REG : 0x11000 (common_regs.v) - // RF_RESET_CONTROL_REG : 0x12000 (common_regs.v) - // RF_RESET_STATUS_REG : 0x12008 (common_regs.v) - // RF_AXI_STATUS_REG : 0x13000 (common_regs.v) - // FABRIC_DSP_REG : 0x13008 (common_regs.v) - // CALIBRATION_DATA : 0x14000 (common_regs.v) - // CALIBRATION_ENABLE : 0x14008 (common_regs.v) - // THRESHOLD_STATUS : 0x15000 (common_regs.v) - // RF_PLL_CONTROL_REG : 0x16000 (common_regs.v) - // RF_PLL_STATUS_REG : 0x16008 (common_regs.v) - -//=============================================================================== -// RegTypes -//=============================================================================== - -//=============================================================================== -// Register Group RFDC_REGS -//=============================================================================== - - // Enumerated type FABRIC_DSP_BW_ENUM - localparam FABRIC_DSP_BW_ENUM_SIZE = 4; - localparam FABRIC_DSP_BW_NONE = 'h0; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE - localparam FABRIC_DSP_BW_100M = 'h64; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M - localparam FABRIC_DSP_BW_200M = 'hC8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M - localparam FABRIC_DSP_BW_400M = 'h190; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M - - // MMCM Window (from common_regs.v) - localparam MMCM = 'h0; // Window Offset - localparam MMCM_SIZE = 'h10000; // size in bytes - - // INVERT_IQ_REG Register (from common_regs.v) - localparam INVERT_IQ_REG = 'h10000; // Register Offset - localparam INVERT_IQ_REG_SIZE = 32; // register width in bits - localparam INVERT_IQ_REG_MASK = 32'hFFFF; - localparam INVERT_DB0_ADC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ - localparam INVERT_DB0_ADC0_IQ_MSB = 0; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ - localparam INVERT_DB0_ADC0_IQ = 0; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ - localparam INVERT_DB0_ADC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ - localparam INVERT_DB0_ADC1_IQ_MSB = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ - localparam INVERT_DB0_ADC1_IQ = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ - localparam INVERT_DB0_ADC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ - localparam INVERT_DB0_ADC2_IQ_MSB = 2; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ - localparam INVERT_DB0_ADC2_IQ = 2; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ - localparam INVERT_DB0_ADC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ - localparam INVERT_DB0_ADC3_IQ_MSB = 3; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ - localparam INVERT_DB0_ADC3_IQ = 3; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ - localparam INVERT_DB1_ADC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ - localparam INVERT_DB1_ADC0_IQ_MSB = 4; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ - localparam INVERT_DB1_ADC0_IQ = 4; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ - localparam INVERT_DB1_ADC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ - localparam INVERT_DB1_ADC1_IQ_MSB = 5; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ - localparam INVERT_DB1_ADC1_IQ = 5; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ - localparam INVERT_DB1_ADC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ - localparam INVERT_DB1_ADC2_IQ_MSB = 6; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ - localparam INVERT_DB1_ADC2_IQ = 6; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ - localparam INVERT_DB1_ADC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ - localparam INVERT_DB1_ADC3_IQ_MSB = 7; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ - localparam INVERT_DB1_ADC3_IQ = 7; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ - localparam INVERT_DB0_DAC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ - localparam INVERT_DB0_DAC0_IQ_MSB = 8; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ - localparam INVERT_DB0_DAC0_IQ = 8; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ - localparam INVERT_DB0_DAC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ - localparam INVERT_DB0_DAC1_IQ_MSB = 9; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ - localparam INVERT_DB0_DAC1_IQ = 9; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ - localparam INVERT_DB0_DAC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ - localparam INVERT_DB0_DAC2_IQ_MSB = 10; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ - localparam INVERT_DB0_DAC2_IQ = 10; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ - localparam INVERT_DB0_DAC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ - localparam INVERT_DB0_DAC3_IQ_MSB = 11; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ - localparam INVERT_DB0_DAC3_IQ = 11; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ - localparam INVERT_DB1_DAC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ - localparam INVERT_DB1_DAC0_IQ_MSB = 12; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ - localparam INVERT_DB1_DAC0_IQ = 12; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ - localparam INVERT_DB1_DAC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ - localparam INVERT_DB1_DAC1_IQ_MSB = 13; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ - localparam INVERT_DB1_DAC1_IQ = 13; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ - localparam INVERT_DB1_DAC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ - localparam INVERT_DB1_DAC2_IQ_MSB = 14; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ - localparam INVERT_DB1_DAC2_IQ = 14; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ - localparam INVERT_DB1_DAC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ - localparam INVERT_DB1_DAC3_IQ_MSB = 15; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ - localparam INVERT_DB1_DAC3_IQ = 15; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ - - // MMCM_RESET_REG Register (from common_regs.v) - localparam MMCM_RESET_REG = 'h11000; // Register Offset - localparam MMCM_RESET_REG_SIZE = 32; // register width in bits - localparam MMCM_RESET_REG_MASK = 32'h1; - localparam RESET_MMCM_SIZE = 1; //MMCM_RESET_REG:RESET_MMCM - localparam RESET_MMCM_MSB = 0; //MMCM_RESET_REG:RESET_MMCM - localparam RESET_MMCM = 0; //MMCM_RESET_REG:RESET_MMCM - - // RF_RESET_CONTROL_REG Register (from common_regs.v) - localparam RF_RESET_CONTROL_REG = 'h12000; // Register Offset - localparam RF_RESET_CONTROL_REG_SIZE = 32; // register width in bits - localparam RF_RESET_CONTROL_REG_MASK = 32'h331; - localparam FSM_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:FSM_RESET - localparam FSM_RESET_MSB = 0; //RF_RESET_CONTROL_REG:FSM_RESET - localparam FSM_RESET = 0; //RF_RESET_CONTROL_REG:FSM_RESET - localparam ADC_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:ADC_RESET - localparam ADC_RESET_MSB = 4; //RF_RESET_CONTROL_REG:ADC_RESET - localparam ADC_RESET = 4; //RF_RESET_CONTROL_REG:ADC_RESET - localparam ADC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REG:ADC_ENABLE - localparam ADC_ENABLE_MSB = 5; //RF_RESET_CONTROL_REG:ADC_ENABLE - localparam ADC_ENABLE = 5; //RF_RESET_CONTROL_REG:ADC_ENABLE - localparam DAC_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:DAC_RESET - localparam DAC_RESET_MSB = 8; //RF_RESET_CONTROL_REG:DAC_RESET - localparam DAC_RESET = 8; //RF_RESET_CONTROL_REG:DAC_RESET - localparam DAC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REG:DAC_ENABLE - localparam DAC_ENABLE_MSB = 9; //RF_RESET_CONTROL_REG:DAC_ENABLE - localparam DAC_ENABLE = 9; //RF_RESET_CONTROL_REG:DAC_ENABLE - - // RF_RESET_STATUS_REG Register (from common_regs.v) - localparam RF_RESET_STATUS_REG = 'h12008; // Register Offset - localparam RF_RESET_STATUS_REG_SIZE = 32; // register width in bits - localparam RF_RESET_STATUS_REG_MASK = 32'h888; - localparam FSM_RESET_DONE_SIZE = 1; //RF_RESET_STATUS_REG:FSM_RESET_DONE - localparam FSM_RESET_DONE_MSB = 3; //RF_RESET_STATUS_REG:FSM_RESET_DONE - localparam FSM_RESET_DONE = 3; //RF_RESET_STATUS_REG:FSM_RESET_DONE - localparam ADC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REG:ADC_SEQ_DONE - localparam ADC_SEQ_DONE_MSB = 7; //RF_RESET_STATUS_REG:ADC_SEQ_DONE - localparam ADC_SEQ_DONE = 7; //RF_RESET_STATUS_REG:ADC_SEQ_DONE - localparam DAC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REG:DAC_SEQ_DONE - localparam DAC_SEQ_DONE_MSB = 11; //RF_RESET_STATUS_REG:DAC_SEQ_DONE - localparam DAC_SEQ_DONE = 11; //RF_RESET_STATUS_REG:DAC_SEQ_DONE - - // RF_AXI_STATUS_REG Register (from common_regs.v) - localparam RF_AXI_STATUS_REG = 'h13000; // Register Offset - localparam RF_AXI_STATUS_REG_SIZE = 32; // register width in bits - localparam RF_AXI_STATUS_REG_MASK = 32'hFFFFFFFF; - localparam RFDC_DAC_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY - localparam RFDC_DAC_TREADY_MSB = 1; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY - localparam RFDC_DAC_TREADY = 0; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY - localparam RFDC_DAC_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID - localparam RFDC_DAC_TVALID_MSB = 3; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID - localparam RFDC_DAC_TVALID = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID - localparam RFDC_ADC_Q_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY - localparam RFDC_ADC_Q_TREADY_MSB = 5; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY - localparam RFDC_ADC_Q_TREADY = 4; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY - localparam RFDC_ADC_I_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY - localparam RFDC_ADC_I_TREADY_MSB = 7; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY - localparam RFDC_ADC_I_TREADY = 6; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY - localparam RFDC_ADC_Q_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID - localparam RFDC_ADC_Q_TVALID_MSB = 9; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID - localparam RFDC_ADC_Q_TVALID = 8; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID - localparam RFDC_ADC_I_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID - localparam RFDC_ADC_I_TVALID_MSB = 11; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID - localparam RFDC_ADC_I_TVALID = 10; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID - localparam USER_ADC_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TVALID - localparam USER_ADC_TVALID_MSB = 13; //RF_AXI_STATUS_REG:USER_ADC_TVALID - localparam USER_ADC_TVALID = 12; //RF_AXI_STATUS_REG:USER_ADC_TVALID - localparam USER_ADC_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TREADY - localparam USER_ADC_TREADY_MSB = 15; //RF_AXI_STATUS_REG:USER_ADC_TREADY - localparam USER_ADC_TREADY = 14; //RF_AXI_STATUS_REG:USER_ADC_TREADY - localparam RFDC_DAC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 - localparam RFDC_DAC_TREADY_DB1_MSB = 17; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 - localparam RFDC_DAC_TREADY_DB1 = 16; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 - localparam RFDC_DAC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 - localparam RFDC_DAC_TVALID_DB1_MSB = 19; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 - localparam RFDC_DAC_TVALID_DB1 = 18; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 - localparam RFDC_ADC_Q_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 - localparam RFDC_ADC_Q_TREADY_DB1_MSB = 21; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 - localparam RFDC_ADC_Q_TREADY_DB1 = 20; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 - localparam RFDC_ADC_I_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 - localparam RFDC_ADC_I_TREADY_DB1_MSB = 23; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 - localparam RFDC_ADC_I_TREADY_DB1 = 22; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 - localparam RFDC_ADC_Q_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 - localparam RFDC_ADC_Q_TVALID_DB1_MSB = 25; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 - localparam RFDC_ADC_Q_TVALID_DB1 = 24; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 - localparam RFDC_ADC_I_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 - localparam RFDC_ADC_I_TVALID_DB1_MSB = 27; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 - localparam RFDC_ADC_I_TVALID_DB1 = 26; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 - localparam USER_ADC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 - localparam USER_ADC_TVALID_DB1_MSB = 29; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 - localparam USER_ADC_TVALID_DB1 = 28; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 - localparam USER_ADC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 - localparam USER_ADC_TREADY_DB1_MSB = 31; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 - localparam USER_ADC_TREADY_DB1 = 30; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 - - // FABRIC_DSP_REG Register (from common_regs.v) - localparam FABRIC_DSP_REG = 'h13008; // Register Offset - localparam FABRIC_DSP_REG_SIZE = 32; // register width in bits - localparam FABRIC_DSP_REG_MASK = 32'hFFFFFFFF; - localparam FABRIC_DSP_BW_SIZE = 12; //FABRIC_DSP_REG:FABRIC_DSP_BW - localparam FABRIC_DSP_BW_MSB = 11; //FABRIC_DSP_REG:FABRIC_DSP_BW - localparam FABRIC_DSP_BW = 0; //FABRIC_DSP_REG:FABRIC_DSP_BW - localparam FABRIC_DSP_RX_CNT_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT - localparam FABRIC_DSP_RX_CNT_MSB = 13; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT - localparam FABRIC_DSP_RX_CNT = 12; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT - localparam FABRIC_DSP_TX_CNT_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT - localparam FABRIC_DSP_TX_CNT_MSB = 15; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT - localparam FABRIC_DSP_TX_CNT = 14; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT - localparam FABRIC_DSP_BW_DB1_SIZE = 12; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 - localparam FABRIC_DSP_BW_DB1_MSB = 27; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 - localparam FABRIC_DSP_BW_DB1 = 16; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 - localparam FABRIC_DSP_RX_CNT_DB1_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 - localparam FABRIC_DSP_RX_CNT_DB1_MSB = 29; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 - localparam FABRIC_DSP_RX_CNT_DB1 = 28; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 - localparam FABRIC_DSP_TX_CNT_DB1_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 - localparam FABRIC_DSP_TX_CNT_DB1_MSB = 31; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 - localparam FABRIC_DSP_TX_CNT_DB1 = 30; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 - - // CALIBRATION_DATA Register (from common_regs.v) - localparam CALIBRATION_DATA = 'h14000; // Register Offset - localparam CALIBRATION_DATA_SIZE = 32; // register width in bits - localparam CALIBRATION_DATA_MASK = 32'hFFFFFFFF; - localparam I_DATA_SIZE = 16; //CALIBRATION_DATA:I_DATA - localparam I_DATA_MSB = 15; //CALIBRATION_DATA:I_DATA - localparam I_DATA = 0; //CALIBRATION_DATA:I_DATA - localparam Q_DATA_SIZE = 16; //CALIBRATION_DATA:Q_DATA - localparam Q_DATA_MSB = 31; //CALIBRATION_DATA:Q_DATA - localparam Q_DATA = 16; //CALIBRATION_DATA:Q_DATA - - // CALIBRATION_ENABLE Register (from common_regs.v) - localparam CALIBRATION_ENABLE = 'h14008; // Register Offset - localparam CALIBRATION_ENABLE_SIZE = 32; // register width in bits - localparam CALIBRATION_ENABLE_MASK = 32'h33; - localparam ENABLE_CALIBRATION_DATA_0_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 - localparam ENABLE_CALIBRATION_DATA_0_MSB = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 - localparam ENABLE_CALIBRATION_DATA_0 = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 - localparam ENABLE_CALIBRATION_DATA_1_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 - localparam ENABLE_CALIBRATION_DATA_1_MSB = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 - localparam ENABLE_CALIBRATION_DATA_1 = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 - localparam ENABLE_CALIBRATION_DATA_2_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 - localparam ENABLE_CALIBRATION_DATA_2_MSB = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 - localparam ENABLE_CALIBRATION_DATA_2 = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 - localparam ENABLE_CALIBRATION_DATA_3_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 - localparam ENABLE_CALIBRATION_DATA_3_MSB = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 - localparam ENABLE_CALIBRATION_DATA_3 = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 - - // THRESHOLD_STATUS Register (from common_regs.v) - localparam THRESHOLD_STATUS = 'h15000; // Register Offset - localparam THRESHOLD_STATUS_SIZE = 32; // register width in bits - localparam THRESHOLD_STATUS_MASK = 32'hF0F; - localparam ADC0_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 - localparam ADC0_01_THRESHOLD1_MSB = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 - localparam ADC0_01_THRESHOLD1 = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 - localparam ADC0_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 - localparam ADC0_01_THRESHOLD2_MSB = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 - localparam ADC0_01_THRESHOLD2 = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 - localparam ADC0_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 - localparam ADC0_23_THRESHOLD1_MSB = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 - localparam ADC0_23_THRESHOLD1 = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 - localparam ADC0_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 - localparam ADC0_23_THRESHOLD2_MSB = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 - localparam ADC0_23_THRESHOLD2 = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 - localparam ADC2_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 - localparam ADC2_01_THRESHOLD1_MSB = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 - localparam ADC2_01_THRESHOLD1 = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 - localparam ADC2_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 - localparam ADC2_01_THRESHOLD2_MSB = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 - localparam ADC2_01_THRESHOLD2 = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 - localparam ADC2_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 - localparam ADC2_23_THRESHOLD1_MSB = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 - localparam ADC2_23_THRESHOLD1 = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 - localparam ADC2_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 - localparam ADC2_23_THRESHOLD2_MSB = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 - localparam ADC2_23_THRESHOLD2 = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 - - // RF_PLL_CONTROL_REG Register (from common_regs.v) - localparam RF_PLL_CONTROL_REG = 'h16000; // Register Offset - localparam RF_PLL_CONTROL_REG_SIZE = 32; // register width in bits - localparam RF_PLL_CONTROL_REG_MASK = 32'h11111; - localparam ENABLE_DATA_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK - localparam ENABLE_DATA_CLK_MSB = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK - localparam ENABLE_DATA_CLK = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK - localparam ENABLE_DATA_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X - localparam ENABLE_DATA_CLK_2X_MSB = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X - localparam ENABLE_DATA_CLK_2X = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X - localparam ENABLE_RF_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK - localparam ENABLE_RF_CLK_MSB = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK - localparam ENABLE_RF_CLK = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK - localparam ENABLE_RF_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X - localparam ENABLE_RF_CLK_2X_MSB = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X - localparam ENABLE_RF_CLK_2X = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X - localparam CLEAR_DATA_CLK_UNLOCKED_SIZE = 1; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED - localparam CLEAR_DATA_CLK_UNLOCKED_MSB = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED - localparam CLEAR_DATA_CLK_UNLOCKED = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED - - // RF_PLL_STATUS_REG Register (from common_regs.v) - localparam RF_PLL_STATUS_REG = 'h16008; // Register Offset - localparam RF_PLL_STATUS_REG_SIZE = 32; // register width in bits - localparam RF_PLL_STATUS_REG_MASK = 32'h110000; - localparam DATA_CLK_PLL_UNLOCKED_STICKY_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY - localparam DATA_CLK_PLL_UNLOCKED_STICKY_MSB = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY - localparam DATA_CLK_PLL_UNLOCKED_STICKY = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY - localparam DATA_CLK_PLL_LOCKED_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED - localparam DATA_CLK_PLL_LOCKED_MSB = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED - localparam DATA_CLK_PLL_LOCKED = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED diff --git a/top/x400/regmap/x440/PkgRFDC_REGS_REGMAP.vhd b/top/x400/regmap/x440/PkgRFDC_REGS_REGMAP.vhd new file mode 100644 index 0000000..5ae2d96 --- /dev/null +++ b/top/x400/regmap/x440/PkgRFDC_REGS_REGMAP.vhd @@ -0,0 +1,1100 @@ +--------------------------------------------------------------------- +-- +-- Copyright 2023 Ettus Research, A National Instruments Brand +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- Module: PkgRFDC_REGS_REGMAP.vhd +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse. +-- +---------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgRFDC_REGS_REGMAP is + +--=============================================================================== +-- A numerically ordered list of registers and their HDL source files +--=============================================================================== + + -- MMCM : 0x0 (x440_rfdc_regs.v) + -- INVERT_DB0_IQ_REG : 0x10000 (x440_rfdc_regs.v) + -- INVERT_DB1_IQ_REG : 0x10800 (x440_rfdc_regs.v) + -- MMCM_RESET_REG : 0x11000 (x440_rfdc_regs.v) + -- RF0_RESET_CONTROL_REG : 0x12000 (x440_rfdc_regs.v) + -- RF0_RESET_STATUS_REG : 0x12008 (x440_rfdc_regs.v) + -- RF1_RESET_CONTROL_REG : 0x12800 (x440_rfdc_regs.v) + -- RF1_RESET_STATUS_REG : 0x12808 (x440_rfdc_regs.v) + -- RF_AXI_STATUS_REG : 0x13000 (x440_rfdc_regs.v) + -- FABRIC_DSP_REG : 0x13008 (x440_rfdc_regs.v) + -- CALIBRATION_DATA : 0x14000 (x440_rfdc_regs.v) + -- CALIBRATION_ENABLE : 0x14008 (x440_rfdc_regs.v) + -- THRESHOLD_STATUS : 0x15000 (x440_rfdc_regs.v) + -- RF_PLL_CONTROL_REG : 0x16000 (x440_rfdc_regs.v) + -- RF_PLL_STATUS_REG : 0x16008 (x440_rfdc_regs.v) + -- ADC_TILEMAP_REG : 0x17000 (x440_rfdc_regs.v) + -- DAC_TILEMAP_REG : 0x17008 (x440_rfdc_regs.v) + -- RFDC_INFO_REG : 0x18000 (x440_rfdc_regs.v) + +--=============================================================================== +-- RegTypes +--=============================================================================== + + -- ADC_TILEMAP_REGTYPE Type (from common_regs.v) + constant kADC_TILEMAP_REGTYPESize: integer := 32; + constant kADC_TILEMAP_REGTYPEMask : std_logic_vector(31 downto 0) := X"ffffffff"; + constant kADC_TILEMAP_DB0_CHAN0_TILESize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE + constant kADC_TILEMAP_DB0_CHAN0_TILEMsb : integer := 1; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE + constant kADC_TILEMAP_DB0_CHAN0_TILE : integer := 0; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE + constant kADC_TILEMAP_DB0_CHAN0_BLOCKSize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK + constant kADC_TILEMAP_DB0_CHAN0_BLOCKMsb : integer := 3; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK + constant kADC_TILEMAP_DB0_CHAN0_BLOCK : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK + constant kADC_TILEMAP_DB0_CHAN1_TILESize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE + constant kADC_TILEMAP_DB0_CHAN1_TILEMsb : integer := 5; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE + constant kADC_TILEMAP_DB0_CHAN1_TILE : integer := 4; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE + constant kADC_TILEMAP_DB0_CHAN1_BLOCKSize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK + constant kADC_TILEMAP_DB0_CHAN1_BLOCKMsb : integer := 7; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK + constant kADC_TILEMAP_DB0_CHAN1_BLOCK : integer := 6; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK + constant kADC_TILEMAP_DB0_CHAN2_TILESize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE + constant kADC_TILEMAP_DB0_CHAN2_TILEMsb : integer := 9; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE + constant kADC_TILEMAP_DB0_CHAN2_TILE : integer := 8; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE + constant kADC_TILEMAP_DB0_CHAN2_BLOCKSize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK + constant kADC_TILEMAP_DB0_CHAN2_BLOCKMsb : integer := 11; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK + constant kADC_TILEMAP_DB0_CHAN2_BLOCK : integer := 10; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK + constant kADC_TILEMAP_DB0_CHAN3_TILESize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE + constant kADC_TILEMAP_DB0_CHAN3_TILEMsb : integer := 13; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE + constant kADC_TILEMAP_DB0_CHAN3_TILE : integer := 12; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE + constant kADC_TILEMAP_DB0_CHAN3_BLOCKSize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK + constant kADC_TILEMAP_DB0_CHAN3_BLOCKMsb : integer := 15; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK + constant kADC_TILEMAP_DB0_CHAN3_BLOCK : integer := 14; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK + constant kADC_TILEMAP_DB1_CHAN0_TILESize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE + constant kADC_TILEMAP_DB1_CHAN0_TILEMsb : integer := 17; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE + constant kADC_TILEMAP_DB1_CHAN0_TILE : integer := 16; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE + constant kADC_TILEMAP_DB1_CHAN0_BLOCKSize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK + constant kADC_TILEMAP_DB1_CHAN0_BLOCKMsb : integer := 19; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK + constant kADC_TILEMAP_DB1_CHAN0_BLOCK : integer := 18; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK + constant kADC_TILEMAP_DB1_CHAN1_TILESize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE + constant kADC_TILEMAP_DB1_CHAN1_TILEMsb : integer := 21; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE + constant kADC_TILEMAP_DB1_CHAN1_TILE : integer := 20; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE + constant kADC_TILEMAP_DB1_CHAN1_BLOCKSize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK + constant kADC_TILEMAP_DB1_CHAN1_BLOCKMsb : integer := 23; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK + constant kADC_TILEMAP_DB1_CHAN1_BLOCK : integer := 22; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK + constant kADC_TILEMAP_DB1_CHAN2_TILESize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE + constant kADC_TILEMAP_DB1_CHAN2_TILEMsb : integer := 25; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE + constant kADC_TILEMAP_DB1_CHAN2_TILE : integer := 24; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE + constant kADC_TILEMAP_DB1_CHAN2_BLOCKSize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK + constant kADC_TILEMAP_DB1_CHAN2_BLOCKMsb : integer := 27; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK + constant kADC_TILEMAP_DB1_CHAN2_BLOCK : integer := 26; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK + constant kADC_TILEMAP_DB1_CHAN3_TILESize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE + constant kADC_TILEMAP_DB1_CHAN3_TILEMsb : integer := 29; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE + constant kADC_TILEMAP_DB1_CHAN3_TILE : integer := 28; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE + constant kADC_TILEMAP_DB1_CHAN3_BLOCKSize : integer := 2; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK + constant kADC_TILEMAP_DB1_CHAN3_BLOCKMsb : integer := 31; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK + constant kADC_TILEMAP_DB1_CHAN3_BLOCK : integer := 30; --ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK + + -- DAC_TILEMAP_REGTYPE Type (from common_regs.v) + constant kDAC_TILEMAP_REGTYPESize: integer := 32; + constant kDAC_TILEMAP_REGTYPEMask : std_logic_vector(31 downto 0) := X"ffffffff"; + constant kDAC_TILEMAP_DB0_CHAN0_TILESize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE + constant kDAC_TILEMAP_DB0_CHAN0_TILEMsb : integer := 1; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE + constant kDAC_TILEMAP_DB0_CHAN0_TILE : integer := 0; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE + constant kDAC_TILEMAP_DB0_CHAN0_BLOCKSize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK + constant kDAC_TILEMAP_DB0_CHAN0_BLOCKMsb : integer := 3; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK + constant kDAC_TILEMAP_DB0_CHAN0_BLOCK : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK + constant kDAC_TILEMAP_DB0_CHAN1_TILESize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE + constant kDAC_TILEMAP_DB0_CHAN1_TILEMsb : integer := 5; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE + constant kDAC_TILEMAP_DB0_CHAN1_TILE : integer := 4; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE + constant kDAC_TILEMAP_DB0_CHAN1_BLOCKSize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK + constant kDAC_TILEMAP_DB0_CHAN1_BLOCKMsb : integer := 7; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK + constant kDAC_TILEMAP_DB0_CHAN1_BLOCK : integer := 6; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK + constant kDAC_TILEMAP_DB0_CHAN2_TILESize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE + constant kDAC_TILEMAP_DB0_CHAN2_TILEMsb : integer := 9; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE + constant kDAC_TILEMAP_DB0_CHAN2_TILE : integer := 8; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE + constant kDAC_TILEMAP_DB0_CHAN2_BLOCKSize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK + constant kDAC_TILEMAP_DB0_CHAN2_BLOCKMsb : integer := 11; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK + constant kDAC_TILEMAP_DB0_CHAN2_BLOCK : integer := 10; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK + constant kDAC_TILEMAP_DB0_CHAN3_TILESize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE + constant kDAC_TILEMAP_DB0_CHAN3_TILEMsb : integer := 13; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE + constant kDAC_TILEMAP_DB0_CHAN3_TILE : integer := 12; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE + constant kDAC_TILEMAP_DB0_CHAN3_BLOCKSize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK + constant kDAC_TILEMAP_DB0_CHAN3_BLOCKMsb : integer := 15; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK + constant kDAC_TILEMAP_DB0_CHAN3_BLOCK : integer := 14; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK + constant kDAC_TILEMAP_DB1_CHAN0_TILESize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE + constant kDAC_TILEMAP_DB1_CHAN0_TILEMsb : integer := 17; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE + constant kDAC_TILEMAP_DB1_CHAN0_TILE : integer := 16; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE + constant kDAC_TILEMAP_DB1_CHAN0_BLOCKSize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK + constant kDAC_TILEMAP_DB1_CHAN0_BLOCKMsb : integer := 19; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK + constant kDAC_TILEMAP_DB1_CHAN0_BLOCK : integer := 18; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK + constant kDAC_TILEMAP_DB1_CHAN1_TILESize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE + constant kDAC_TILEMAP_DB1_CHAN1_TILEMsb : integer := 21; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE + constant kDAC_TILEMAP_DB1_CHAN1_TILE : integer := 20; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE + constant kDAC_TILEMAP_DB1_CHAN1_BLOCKSize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK + constant kDAC_TILEMAP_DB1_CHAN1_BLOCKMsb : integer := 23; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK + constant kDAC_TILEMAP_DB1_CHAN1_BLOCK : integer := 22; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK + constant kDAC_TILEMAP_DB1_CHAN2_TILESize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE + constant kDAC_TILEMAP_DB1_CHAN2_TILEMsb : integer := 25; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE + constant kDAC_TILEMAP_DB1_CHAN2_TILE : integer := 24; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE + constant kDAC_TILEMAP_DB1_CHAN2_BLOCKSize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK + constant kDAC_TILEMAP_DB1_CHAN2_BLOCKMsb : integer := 27; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK + constant kDAC_TILEMAP_DB1_CHAN2_BLOCK : integer := 26; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK + constant kDAC_TILEMAP_DB1_CHAN3_TILESize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE + constant kDAC_TILEMAP_DB1_CHAN3_TILEMsb : integer := 29; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE + constant kDAC_TILEMAP_DB1_CHAN3_TILE : integer := 28; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE + constant kDAC_TILEMAP_DB1_CHAN3_BLOCKSize : integer := 2; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK + constant kDAC_TILEMAP_DB1_CHAN3_BLOCKMsb : integer := 31; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK + constant kDAC_TILEMAP_DB1_CHAN3_BLOCK : integer := 30; --DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK + + -- FABRIC_DSP_REGTYPE Type (from common_regs.v) + constant kFABRIC_DSP_REGTYPESize: integer := 32; + constant kFABRIC_DSP_REGTYPEMask : std_logic_vector(31 downto 0) := X"ffffffff"; + constant kFABRIC_DSP_RX_CNTSize : integer := 4; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT + constant kFABRIC_DSP_RX_CNTMsb : integer := 3; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT + constant kFABRIC_DSP_RX_CNT : integer := 0; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT + constant kFABRIC_DSP_TX_CNTSize : integer := 4; --FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT + constant kFABRIC_DSP_TX_CNTMsb : integer := 7; --FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT + constant kFABRIC_DSP_TX_CNT : integer := 4; --FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT + constant kFABRIC_DSP_RESERVEDSize : integer := 2; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED + constant kFABRIC_DSP_RESERVEDMsb : integer := 9; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED + constant kFABRIC_DSP_RESERVED : integer := 8; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED + constant kFABRIC_DSP_RX_CNT_DB1Size : integer := 4; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1 + constant kFABRIC_DSP_RX_CNT_DB1Msb : integer := 13; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1 + constant kFABRIC_DSP_RX_CNT_DB1 : integer := 10; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1 + constant kFABRIC_DSP_TX_CNT_DB1Size : integer := 4; --FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1 + constant kFABRIC_DSP_TX_CNT_DB1Msb : integer := 17; --FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1 + constant kFABRIC_DSP_TX_CNT_DB1 : integer := 14; --FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1 + constant kFABRIC_DSP_RESERVED_DB1Size : integer := 2; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1 + constant kFABRIC_DSP_RESERVED_DB1Msb : integer := 19; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1 + constant kFABRIC_DSP_RESERVED_DB1 : integer := 18; --FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1 + constant kFABRIC_DSP_BWSize : integer := 12; --FABRIC_DSP_REGTYPE:FABRIC_DSP_BW + constant kFABRIC_DSP_BWMsb : integer := 31; --FABRIC_DSP_REGTYPE:FABRIC_DSP_BW + constant kFABRIC_DSP_BW : integer := 20; --FABRIC_DSP_REGTYPE:FABRIC_DSP_BW + + -- RF_AXI_STATUS_REGTYPE Type (from common_regs.v) + constant kRF_AXI_STATUS_REGTYPESize: integer := 32; + constant kRF_AXI_STATUS_REGTYPEMask : std_logic_vector(31 downto 0) := X"ffffffff"; + constant kRFDC_DAC_TREADYSize : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY + constant kRFDC_DAC_TREADYMsb : integer := 1; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY + constant kRFDC_DAC_TREADY : integer := 0; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY + constant kRFDC_DAC_TVALIDSize : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID + constant kRFDC_DAC_TVALIDMsb : integer := 3; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID + constant kRFDC_DAC_TVALID : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID + constant kRFDC_ADC_Q_TREADYSize : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY + constant kRFDC_ADC_Q_TREADYMsb : integer := 5; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY + constant kRFDC_ADC_Q_TREADY : integer := 4; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY + constant kRFDC_ADC_I_TREADYSize : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY + constant kRFDC_ADC_I_TREADYMsb : integer := 7; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY + constant kRFDC_ADC_I_TREADY : integer := 6; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY + constant kRFDC_ADC_Q_TVALIDSize : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID + constant kRFDC_ADC_Q_TVALIDMsb : integer := 9; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID + constant kRFDC_ADC_Q_TVALID : integer := 8; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID + constant kRFDC_ADC_I_TVALIDSize : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID + constant kRFDC_ADC_I_TVALIDMsb : integer := 11; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID + constant kRFDC_ADC_I_TVALID : integer := 10; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID + constant kUSER_ADC_TVALIDSize : integer := 2; --RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID + constant kUSER_ADC_TVALIDMsb : integer := 13; --RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID + constant kUSER_ADC_TVALID : integer := 12; --RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID + constant kUSER_ADC_TREADYSize : integer := 2; --RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY + constant kUSER_ADC_TREADYMsb : integer := 15; --RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY + constant kUSER_ADC_TREADY : integer := 14; --RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY + constant kRFDC_DAC_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1 + constant kRFDC_DAC_TREADY_DB1Msb : integer := 17; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1 + constant kRFDC_DAC_TREADY_DB1 : integer := 16; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1 + constant kRFDC_DAC_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1 + constant kRFDC_DAC_TVALID_DB1Msb : integer := 19; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1 + constant kRFDC_DAC_TVALID_DB1 : integer := 18; --RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1 + constant kRFDC_ADC_Q_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1 + constant kRFDC_ADC_Q_TREADY_DB1Msb : integer := 21; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1 + constant kRFDC_ADC_Q_TREADY_DB1 : integer := 20; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1 + constant kRFDC_ADC_I_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1 + constant kRFDC_ADC_I_TREADY_DB1Msb : integer := 23; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1 + constant kRFDC_ADC_I_TREADY_DB1 : integer := 22; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1 + constant kRFDC_ADC_Q_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1 + constant kRFDC_ADC_Q_TVALID_DB1Msb : integer := 25; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1 + constant kRFDC_ADC_Q_TVALID_DB1 : integer := 24; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1 + constant kRFDC_ADC_I_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1 + constant kRFDC_ADC_I_TVALID_DB1Msb : integer := 27; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1 + constant kRFDC_ADC_I_TVALID_DB1 : integer := 26; --RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1 + constant kUSER_ADC_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1 + constant kUSER_ADC_TVALID_DB1Msb : integer := 29; --RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1 + constant kUSER_ADC_TVALID_DB1 : integer := 28; --RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1 + constant kUSER_ADC_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1 + constant kUSER_ADC_TREADY_DB1Msb : integer := 31; --RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1 + constant kUSER_ADC_TREADY_DB1 : integer := 30; --RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1 + + -- RF_RESET_CONTROL_REGTYPE Type (from common_regs.v) + constant kRF_RESET_CONTROL_REGTYPESize: integer := 32; + constant kRF_RESET_CONTROL_REGTYPEMask : std_logic_vector(31 downto 0) := X"00000331"; + constant kFSM_RESETSize : integer := 1; --RF_RESET_CONTROL_REGTYPE:FSM_RESET + constant kFSM_RESETMsb : integer := 0; --RF_RESET_CONTROL_REGTYPE:FSM_RESET + constant kFSM_RESET : integer := 0; --RF_RESET_CONTROL_REGTYPE:FSM_RESET + constant kADC_RESETSize : integer := 1; --RF_RESET_CONTROL_REGTYPE:ADC_RESET + constant kADC_RESETMsb : integer := 4; --RF_RESET_CONTROL_REGTYPE:ADC_RESET + constant kADC_RESET : integer := 4; --RF_RESET_CONTROL_REGTYPE:ADC_RESET + constant kADC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REGTYPE:ADC_ENABLE + constant kADC_ENABLEMsb : integer := 5; --RF_RESET_CONTROL_REGTYPE:ADC_ENABLE + constant kADC_ENABLE : integer := 5; --RF_RESET_CONTROL_REGTYPE:ADC_ENABLE + constant kDAC_RESETSize : integer := 1; --RF_RESET_CONTROL_REGTYPE:DAC_RESET + constant kDAC_RESETMsb : integer := 8; --RF_RESET_CONTROL_REGTYPE:DAC_RESET + constant kDAC_RESET : integer := 8; --RF_RESET_CONTROL_REGTYPE:DAC_RESET + constant kDAC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REGTYPE:DAC_ENABLE + constant kDAC_ENABLEMsb : integer := 9; --RF_RESET_CONTROL_REGTYPE:DAC_ENABLE + constant kDAC_ENABLE : integer := 9; --RF_RESET_CONTROL_REGTYPE:DAC_ENABLE + + -- RF_RESET_STATUS_REGTYPE Type (from common_regs.v) + constant kRF_RESET_STATUS_REGTYPESize: integer := 32; + constant kRF_RESET_STATUS_REGTYPEMask : std_logic_vector(31 downto 0) := X"00000888"; + constant kFSM_RESET_DONESize : integer := 1; --RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE + constant kFSM_RESET_DONEMsb : integer := 3; --RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE + constant kFSM_RESET_DONE : integer := 3; --RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE + constant kADC_SEQ_DONESize : integer := 1; --RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE + constant kADC_SEQ_DONEMsb : integer := 7; --RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE + constant kADC_SEQ_DONE : integer := 7; --RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE + constant kDAC_SEQ_DONESize : integer := 1; --RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE + constant kDAC_SEQ_DONEMsb : integer := 11; --RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE + constant kDAC_SEQ_DONE : integer := 11; --RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE + + -- RFDC_INFO_REGTYPE Type (from common_regs.v) + constant kRFDC_INFO_REGTYPESize: integer := 32; + constant kRFDC_INFO_REGTYPEMask : std_logic_vector(31 downto 0) := X"03ff03ff"; + constant kRFDC_INFO_XTRA_RESAMPSize : integer := 4; --RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP + constant kRFDC_INFO_XTRA_RESAMPMsb : integer := 3; --RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP + constant kRFDC_INFO_XTRA_RESAMP : integer := 0; --RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP + constant kRFDC_INFO_SPC_RXSize : integer := 3; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX + constant kRFDC_INFO_SPC_RXMsb : integer := 6; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX + constant kRFDC_INFO_SPC_RX : integer := 4; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX + constant kRFDC_INFO_SPC_TXSize : integer := 3; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX + constant kRFDC_INFO_SPC_TXMsb : integer := 9; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX + constant kRFDC_INFO_SPC_TX : integer := 7; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX + constant kRFDC_INFO_XTRA_RESAMP_DB1Size : integer := 4; --RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1 + constant kRFDC_INFO_XTRA_RESAMP_DB1Msb : integer := 19; --RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1 + constant kRFDC_INFO_XTRA_RESAMP_DB1 : integer := 16; --RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1 + constant kRFDC_INFO_SPC_RX_DB1Size : integer := 3; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1 + constant kRFDC_INFO_SPC_RX_DB1Msb : integer := 22; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1 + constant kRFDC_INFO_SPC_RX_DB1 : integer := 20; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1 + constant kRFDC_INFO_SPC_TX_DB1Size : integer := 3; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1 + constant kRFDC_INFO_SPC_TX_DB1Msb : integer := 25; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1 + constant kRFDC_INFO_SPC_TX_DB1 : integer := 23; --RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1 + +--=============================================================================== +-- Register Group RFDC_REGS +--=============================================================================== + + -- Enumerated type FABRIC_DSP_BW_ENUM + constant kFABRIC_DSP_BW_ENUMSize : integer := 5; + constant kFABRIC_DSP_BW_NONE : integer := 0; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE + constant kFABRIC_DSP_BW_100M : integer := 100; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M + constant kFABRIC_DSP_BW_200M : integer := 200; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M + constant kFABRIC_DSP_BW_400M : integer := 400; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M + constant kFABRIC_DSP_BW_FULL : integer := 1000; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_FULL + + -- MMCM Window (from x440_rfdc_regs.v) + constant kMMCM : integer := 16#0#; -- Window Offset + constant kMMCMSize: integer := 16#10000#; -- size in bytes + --function kMMCMRec return XReg2_t; -- Window Record function commented out due to programmable attributes + + -- INVERT_DB0_IQ_REG Register (from x440_rfdc_regs.v) + constant kINVERT_DB0_IQ_REG : integer := 16#10000#; -- Register Offset + constant kINVERT_DB0_IQ_REGSize: integer := 32; -- register width in bits + constant kINVERT_DB0_IQ_REGMask : std_logic_vector(31 downto 0) := X"00000f0f"; + constant kINVERT_DB0_ADC0_IQSize : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ + constant kINVERT_DB0_ADC0_IQMsb : integer := 0; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ + constant kINVERT_DB0_ADC0_IQ : integer := 0; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ + constant kINVERT_DB0_ADC1_IQSize : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ + constant kINVERT_DB0_ADC1_IQMsb : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ + constant kINVERT_DB0_ADC1_IQ : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ + constant kINVERT_DB0_ADC2_IQSize : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ + constant kINVERT_DB0_ADC2_IQMsb : integer := 2; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ + constant kINVERT_DB0_ADC2_IQ : integer := 2; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ + constant kINVERT_DB0_ADC3_IQSize : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ + constant kINVERT_DB0_ADC3_IQMsb : integer := 3; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ + constant kINVERT_DB0_ADC3_IQ : integer := 3; --INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ + constant kINVERT_DB0_DAC0_IQSize : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ + constant kINVERT_DB0_DAC0_IQMsb : integer := 8; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ + constant kINVERT_DB0_DAC0_IQ : integer := 8; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ + constant kINVERT_DB0_DAC1_IQSize : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ + constant kINVERT_DB0_DAC1_IQMsb : integer := 9; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ + constant kINVERT_DB0_DAC1_IQ : integer := 9; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ + constant kINVERT_DB0_DAC2_IQSize : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ + constant kINVERT_DB0_DAC2_IQMsb : integer := 10; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ + constant kINVERT_DB0_DAC2_IQ : integer := 10; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ + constant kINVERT_DB0_DAC3_IQSize : integer := 1; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ + constant kINVERT_DB0_DAC3_IQMsb : integer := 11; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ + constant kINVERT_DB0_DAC3_IQ : integer := 11; --INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ + --function kINVERT_DB0_IQ_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- INVERT_DB1_IQ_REG Register (from x440_rfdc_regs.v) + constant kINVERT_DB1_IQ_REG : integer := 16#10800#; -- Register Offset + constant kINVERT_DB1_IQ_REGSize: integer := 32; -- register width in bits + constant kINVERT_DB1_IQ_REGMask : std_logic_vector(31 downto 0) := X"00000f0f"; + constant kINVERT_DB1_ADC0_IQSize : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ + constant kINVERT_DB1_ADC0_IQMsb : integer := 0; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ + constant kINVERT_DB1_ADC0_IQ : integer := 0; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ + constant kINVERT_DB1_ADC1_IQSize : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ + constant kINVERT_DB1_ADC1_IQMsb : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ + constant kINVERT_DB1_ADC1_IQ : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ + constant kINVERT_DB1_ADC2_IQSize : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ + constant kINVERT_DB1_ADC2_IQMsb : integer := 2; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ + constant kINVERT_DB1_ADC2_IQ : integer := 2; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ + constant kINVERT_DB1_ADC3_IQSize : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ + constant kINVERT_DB1_ADC3_IQMsb : integer := 3; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ + constant kINVERT_DB1_ADC3_IQ : integer := 3; --INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ + constant kINVERT_DB1_DAC0_IQSize : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ + constant kINVERT_DB1_DAC0_IQMsb : integer := 8; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ + constant kINVERT_DB1_DAC0_IQ : integer := 8; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ + constant kINVERT_DB1_DAC1_IQSize : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ + constant kINVERT_DB1_DAC1_IQMsb : integer := 9; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ + constant kINVERT_DB1_DAC1_IQ : integer := 9; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ + constant kINVERT_DB1_DAC2_IQSize : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ + constant kINVERT_DB1_DAC2_IQMsb : integer := 10; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ + constant kINVERT_DB1_DAC2_IQ : integer := 10; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ + constant kINVERT_DB1_DAC3_IQSize : integer := 1; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ + constant kINVERT_DB1_DAC3_IQMsb : integer := 11; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ + constant kINVERT_DB1_DAC3_IQ : integer := 11; --INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ + --function kINVERT_DB1_IQ_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- MMCM_RESET_REG Register (from x440_rfdc_regs.v) + constant kMMCM_RESET_REG : integer := 16#11000#; -- Register Offset + constant kMMCM_RESET_REGSize: integer := 32; -- register width in bits + constant kMMCM_RESET_REGMask : std_logic_vector(31 downto 0) := X"00000001"; + constant kRESET_MMCMSize : integer := 1; --MMCM_RESET_REG:RESET_MMCM + constant kRESET_MMCMMsb : integer := 0; --MMCM_RESET_REG:RESET_MMCM + constant kRESET_MMCM : integer := 0; --MMCM_RESET_REG:RESET_MMCM + --function kMMCM_RESET_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF0_RESET_CONTROL_REG Register (from x440_rfdc_regs.v) + constant kRF0_RESET_CONTROL_REG : integer := 16#12000#; -- Register Offset + constant kRF0_RESET_CONTROL_REGSize: integer := 32; -- register width in bits + --function kRF0_RESET_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF0_RESET_STATUS_REG Register (from x440_rfdc_regs.v) + constant kRF0_RESET_STATUS_REG : integer := 16#12008#; -- Register Offset + constant kRF0_RESET_STATUS_REGSize: integer := 32; -- register width in bits + --function kRF0_RESET_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF1_RESET_CONTROL_REG Register (from x440_rfdc_regs.v) + constant kRF1_RESET_CONTROL_REG : integer := 16#12800#; -- Register Offset + constant kRF1_RESET_CONTROL_REGSize: integer := 32; -- register width in bits + --function kRF1_RESET_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF1_RESET_STATUS_REG Register (from x440_rfdc_regs.v) + constant kRF1_RESET_STATUS_REG : integer := 16#12808#; -- Register Offset + constant kRF1_RESET_STATUS_REGSize: integer := 32; -- register width in bits + --function kRF1_RESET_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF_AXI_STATUS_REG Register (from x440_rfdc_regs.v) + constant kRF_AXI_STATUS_REG : integer := 16#13000#; -- Register Offset + constant kRF_AXI_STATUS_REGSize: integer := 32; -- register width in bits + --function kRF_AXI_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- FABRIC_DSP_REG Register (from x440_rfdc_regs.v) + constant kFABRIC_DSP_REG : integer := 16#13008#; -- Register Offset + constant kFABRIC_DSP_REGSize: integer := 32; -- register width in bits + --function kFABRIC_DSP_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- CALIBRATION_DATA Register (from x440_rfdc_regs.v) + constant kCALIBRATION_DATA : integer := 16#14000#; -- Register Offset + constant kCALIBRATION_DATASize: integer := 32; -- register width in bits + constant kCALIBRATION_DATAMask : std_logic_vector(31 downto 0) := X"ffffffff"; + constant kI_DATASize : integer := 16; --CALIBRATION_DATA:I_DATA + constant kI_DATAMsb : integer := 15; --CALIBRATION_DATA:I_DATA + constant kI_DATA : integer := 0; --CALIBRATION_DATA:I_DATA + constant kQ_DATASize : integer := 16; --CALIBRATION_DATA:Q_DATA + constant kQ_DATAMsb : integer := 31; --CALIBRATION_DATA:Q_DATA + constant kQ_DATA : integer := 16; --CALIBRATION_DATA:Q_DATA + --function kCALIBRATION_DATARec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- CALIBRATION_ENABLE Register (from x440_rfdc_regs.v) + constant kCALIBRATION_ENABLE : integer := 16#14008#; -- Register Offset + constant kCALIBRATION_ENABLESize: integer := 32; -- register width in bits + constant kCALIBRATION_ENABLEMask : std_logic_vector(31 downto 0) := X"000000ff"; + constant kENABLE_CALIBRATION_DATA_0Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + constant kENABLE_CALIBRATION_DATA_0Msb : integer := 0; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + constant kENABLE_CALIBRATION_DATA_0 : integer := 0; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + constant kENABLE_CALIBRATION_DATA_1Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + constant kENABLE_CALIBRATION_DATA_1Msb : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + constant kENABLE_CALIBRATION_DATA_1 : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + constant kENABLE_CALIBRATION_DATA_2Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + constant kENABLE_CALIBRATION_DATA_2Msb : integer := 2; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + constant kENABLE_CALIBRATION_DATA_2 : integer := 2; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + constant kENABLE_CALIBRATION_DATA_3Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + constant kENABLE_CALIBRATION_DATA_3Msb : integer := 3; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + constant kENABLE_CALIBRATION_DATA_3 : integer := 3; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + constant kENABLE_CALIBRATION_DATA_4Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4 + constant kENABLE_CALIBRATION_DATA_4Msb : integer := 4; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4 + constant kENABLE_CALIBRATION_DATA_4 : integer := 4; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4 + constant kENABLE_CALIBRATION_DATA_5Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5 + constant kENABLE_CALIBRATION_DATA_5Msb : integer := 5; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5 + constant kENABLE_CALIBRATION_DATA_5 : integer := 5; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5 + constant kENABLE_CALIBRATION_DATA_6Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6 + constant kENABLE_CALIBRATION_DATA_6Msb : integer := 6; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6 + constant kENABLE_CALIBRATION_DATA_6 : integer := 6; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6 + constant kENABLE_CALIBRATION_DATA_7Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7 + constant kENABLE_CALIBRATION_DATA_7Msb : integer := 7; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7 + constant kENABLE_CALIBRATION_DATA_7 : integer := 7; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7 + --function kCALIBRATION_ENABLERec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- THRESHOLD_STATUS Register (from x440_rfdc_regs.v) + constant kTHRESHOLD_STATUS : integer := 16#15000#; -- Register Offset + constant kTHRESHOLD_STATUSSize: integer := 32; -- register width in bits + constant kTHRESHOLD_STATUSMask : std_logic_vector(31 downto 0) := X"0000ffff"; + constant kADC0_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + constant kADC0_01_THRESHOLD1Msb : integer := 0; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + constant kADC0_01_THRESHOLD1 : integer := 0; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + constant kADC0_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + constant kADC0_01_THRESHOLD2Msb : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + constant kADC0_01_THRESHOLD2 : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + constant kADC0_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + constant kADC0_23_THRESHOLD1Msb : integer := 2; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + constant kADC0_23_THRESHOLD1 : integer := 2; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + constant kADC0_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + constant kADC0_23_THRESHOLD2Msb : integer := 3; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + constant kADC0_23_THRESHOLD2 : integer := 3; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + constant kADC1_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC1_01_THRESHOLD1 + constant kADC1_01_THRESHOLD1Msb : integer := 4; --THRESHOLD_STATUS:ADC1_01_THRESHOLD1 + constant kADC1_01_THRESHOLD1 : integer := 4; --THRESHOLD_STATUS:ADC1_01_THRESHOLD1 + constant kADC1_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC1_01_THRESHOLD2 + constant kADC1_01_THRESHOLD2Msb : integer := 5; --THRESHOLD_STATUS:ADC1_01_THRESHOLD2 + constant kADC1_01_THRESHOLD2 : integer := 5; --THRESHOLD_STATUS:ADC1_01_THRESHOLD2 + constant kADC1_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC1_23_THRESHOLD1 + constant kADC1_23_THRESHOLD1Msb : integer := 6; --THRESHOLD_STATUS:ADC1_23_THRESHOLD1 + constant kADC1_23_THRESHOLD1 : integer := 6; --THRESHOLD_STATUS:ADC1_23_THRESHOLD1 + constant kADC1_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC1_23_THRESHOLD2 + constant kADC1_23_THRESHOLD2Msb : integer := 7; --THRESHOLD_STATUS:ADC1_23_THRESHOLD2 + constant kADC1_23_THRESHOLD2 : integer := 7; --THRESHOLD_STATUS:ADC1_23_THRESHOLD2 + constant kADC2_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + constant kADC2_01_THRESHOLD1Msb : integer := 8; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + constant kADC2_01_THRESHOLD1 : integer := 8; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + constant kADC2_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + constant kADC2_01_THRESHOLD2Msb : integer := 9; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + constant kADC2_01_THRESHOLD2 : integer := 9; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + constant kADC2_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + constant kADC2_23_THRESHOLD1Msb : integer := 10; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + constant kADC2_23_THRESHOLD1 : integer := 10; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + constant kADC2_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + constant kADC2_23_THRESHOLD2Msb : integer := 11; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + constant kADC2_23_THRESHOLD2 : integer := 11; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + constant kADC3_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC3_01_THRESHOLD1 + constant kADC3_01_THRESHOLD1Msb : integer := 12; --THRESHOLD_STATUS:ADC3_01_THRESHOLD1 + constant kADC3_01_THRESHOLD1 : integer := 12; --THRESHOLD_STATUS:ADC3_01_THRESHOLD1 + constant kADC3_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC3_01_THRESHOLD2 + constant kADC3_01_THRESHOLD2Msb : integer := 13; --THRESHOLD_STATUS:ADC3_01_THRESHOLD2 + constant kADC3_01_THRESHOLD2 : integer := 13; --THRESHOLD_STATUS:ADC3_01_THRESHOLD2 + constant kADC3_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC3_23_THRESHOLD1 + constant kADC3_23_THRESHOLD1Msb : integer := 14; --THRESHOLD_STATUS:ADC3_23_THRESHOLD1 + constant kADC3_23_THRESHOLD1 : integer := 14; --THRESHOLD_STATUS:ADC3_23_THRESHOLD1 + constant kADC3_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC3_23_THRESHOLD2 + constant kADC3_23_THRESHOLD2Msb : integer := 15; --THRESHOLD_STATUS:ADC3_23_THRESHOLD2 + constant kADC3_23_THRESHOLD2 : integer := 15; --THRESHOLD_STATUS:ADC3_23_THRESHOLD2 + --function kTHRESHOLD_STATUSRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF_PLL_CONTROL_REG Register (from x440_rfdc_regs.v) + constant kRF_PLL_CONTROL_REG : integer := 16#16000#; -- Register Offset + constant kRF_PLL_CONTROL_REGSize: integer := 32; -- register width in bits + constant kRF_PLL_CONTROL_REGMask : std_logic_vector(31 downto 0) := X"01111100"; + constant kENABLE_RF0_CLKSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF0_CLK + constant kENABLE_RF0_CLKMsb : integer := 8; --RF_PLL_CONTROL_REG:ENABLE_RF0_CLK + constant kENABLE_RF0_CLK : integer := 8; --RF_PLL_CONTROL_REG:ENABLE_RF0_CLK + constant kENABLE_RF0_CLK_2XSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X + constant kENABLE_RF0_CLK_2XMsb : integer := 12; --RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X + constant kENABLE_RF0_CLK_2X : integer := 12; --RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X + constant kCLEAR_DATA_CLK_UNLOCKEDSize : integer := 1; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + constant kCLEAR_DATA_CLK_UNLOCKEDMsb : integer := 16; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + constant kCLEAR_DATA_CLK_UNLOCKED : integer := 16; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + constant kENABLE_RF1_CLKSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF1_CLK + constant kENABLE_RF1_CLKMsb : integer := 20; --RF_PLL_CONTROL_REG:ENABLE_RF1_CLK + constant kENABLE_RF1_CLK : integer := 20; --RF_PLL_CONTROL_REG:ENABLE_RF1_CLK + constant kENABLE_RF1_CLK_2XSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X + constant kENABLE_RF1_CLK_2XMsb : integer := 24; --RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X + constant kENABLE_RF1_CLK_2X : integer := 24; --RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X + --function kRF_PLL_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF_PLL_STATUS_REG Register (from x440_rfdc_regs.v) + constant kRF_PLL_STATUS_REG : integer := 16#16008#; -- Register Offset + constant kRF_PLL_STATUS_REGSize: integer := 32; -- register width in bits + constant kRF_PLL_STATUS_REGMask : std_logic_vector(31 downto 0) := X"00110000"; + constant kDATA_CLK_PLL_UNLOCKED_STICKYSize : integer := 1; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + constant kDATA_CLK_PLL_UNLOCKED_STICKYMsb : integer := 16; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + constant kDATA_CLK_PLL_UNLOCKED_STICKY : integer := 16; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + constant kDATA_CLK_PLL_LOCKEDSize : integer := 1; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + constant kDATA_CLK_PLL_LOCKEDMsb : integer := 20; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + constant kDATA_CLK_PLL_LOCKED : integer := 20; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + --function kRF_PLL_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- ADC_TILEMAP_REG Register (from x440_rfdc_regs.v) + constant kADC_TILEMAP_REG : integer := 16#17000#; -- Register Offset + constant kADC_TILEMAP_REGSize: integer := 32; -- register width in bits + --function kADC_TILEMAP_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- DAC_TILEMAP_REG Register (from x440_rfdc_regs.v) + constant kDAC_TILEMAP_REG : integer := 16#17008#; -- Register Offset + constant kDAC_TILEMAP_REGSize: integer := 32; -- register width in bits + --function kDAC_TILEMAP_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RFDC_INFO_REG Register (from x440_rfdc_regs.v) + constant kRFDC_INFO_REG : integer := 16#18000#; -- Register Offset + constant kRFDC_INFO_REGSize: integer := 32; -- register width in bits + --function kRFDC_INFO_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + +end package; + +package body PkgRFDC_REGS_REGMAP is + + -- function kMMCMRec not implemented because MMCM has programmable attributes + ---- Return the record of window kMMCM + --function kMMCMRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"0"); + -- Rec.size := kMMCMSize; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00"); + -- Rec.rmask := XRegResize(X"00"); + -- Rec.strobemask := XRegResize(X"00"); + -- Rec.clearablemask := XRegResize(X"00"); + -- Rec.iswin := true; + -- --synopsys translate_off + -- Rec.name := rs("MMCM"); + -- --synopsys translate_on + -- return Rec; + --end function kMMCMRec; + + -- function kINVERT_DB0_IQ_REGRec not implemented because INVERT_DB0_IQ_REG has programmable attributes + ---- Return the record of register kINVERT_DB0_IQ_REG + --function kINVERT_DB0_IQ_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"10000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000f0f"); + -- Rec.rmask := XRegResize(X"00000f0f"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("INVERT_DB0_IQ_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kINVERT_DB0_IQ_REGRec; + + -- function kINVERT_DB1_IQ_REGRec not implemented because INVERT_DB1_IQ_REG has programmable attributes + ---- Return the record of register kINVERT_DB1_IQ_REG + --function kINVERT_DB1_IQ_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"10800"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000f0f"); + -- Rec.rmask := XRegResize(X"00000f0f"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("INVERT_DB1_IQ_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kINVERT_DB1_IQ_REGRec; + + -- function kMMCM_RESET_REGRec not implemented because MMCM_RESET_REG has programmable attributes + ---- Return the record of register kMMCM_RESET_REG + --function kMMCM_RESET_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"11000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000001"); + -- Rec.rmask := XRegResize(X"00000001"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("MMCM_RESET_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kMMCM_RESET_REGRec; + + -- function kRF0_RESET_CONTROL_REGRec not implemented because RF0_RESET_CONTROL_REG has programmable attributes + ---- Return the record of register kRF0_RESET_CONTROL_REG + --function kRF0_RESET_CONTROL_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"12000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000331"); + -- Rec.rmask := XRegResize(X"00000331"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF0_RESET_CONTROL_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF0_RESET_CONTROL_REGRec; + + -- function kRF0_RESET_STATUS_REGRec not implemented because RF0_RESET_STATUS_REG has programmable attributes + ---- Return the record of register kRF0_RESET_STATUS_REG + --function kRF0_RESET_STATUS_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"12008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"00000888"); + -- Rec.rmask := XRegResize(X"00000888"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF0_RESET_STATUS_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF0_RESET_STATUS_REGRec; + + -- function kRF1_RESET_CONTROL_REGRec not implemented because RF1_RESET_CONTROL_REG has programmable attributes + ---- Return the record of register kRF1_RESET_CONTROL_REG + --function kRF1_RESET_CONTROL_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"12800"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000331"); + -- Rec.rmask := XRegResize(X"00000331"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF1_RESET_CONTROL_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF1_RESET_CONTROL_REGRec; + + -- function kRF1_RESET_STATUS_REGRec not implemented because RF1_RESET_STATUS_REG has programmable attributes + ---- Return the record of register kRF1_RESET_STATUS_REG + --function kRF1_RESET_STATUS_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"12808"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"00000888"); + -- Rec.rmask := XRegResize(X"00000888"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF1_RESET_STATUS_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF1_RESET_STATUS_REGRec; + + -- function kRF_AXI_STATUS_REGRec not implemented because RF_AXI_STATUS_REG has programmable attributes + ---- Return the record of register kRF_AXI_STATUS_REG + --function kRF_AXI_STATUS_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"13000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"ffffffff"); + -- Rec.rmask := XRegResize(X"ffffffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kRFDC_DAC_TREADY) := kRFDC_DAC_TREADYMsb; + -- Rec.msblookupw(kRFDC_DAC_TVALID) := kRFDC_DAC_TVALIDMsb; + -- Rec.msblookupw(kRFDC_ADC_Q_TREADY) := kRFDC_ADC_Q_TREADYMsb; + -- Rec.msblookupw(kRFDC_ADC_I_TREADY) := kRFDC_ADC_I_TREADYMsb; + -- Rec.msblookupw(kRFDC_ADC_Q_TVALID) := kRFDC_ADC_Q_TVALIDMsb; + -- Rec.msblookupw(kRFDC_ADC_I_TVALID) := kRFDC_ADC_I_TVALIDMsb; + -- Rec.msblookupw(kUSER_ADC_TVALID) := kUSER_ADC_TVALIDMsb; + -- Rec.msblookupw(kUSER_ADC_TREADY) := kUSER_ADC_TREADYMsb; + -- Rec.msblookupw(kRFDC_DAC_TREADY_DB1) := kRFDC_DAC_TREADY_DB1Msb; + -- Rec.msblookupw(kRFDC_DAC_TVALID_DB1) := kRFDC_DAC_TVALID_DB1Msb; + -- Rec.msblookupw(kRFDC_ADC_Q_TREADY_DB1) := kRFDC_ADC_Q_TREADY_DB1Msb; + -- Rec.msblookupw(kRFDC_ADC_I_TREADY_DB1) := kRFDC_ADC_I_TREADY_DB1Msb; + -- Rec.msblookupw(kRFDC_ADC_Q_TVALID_DB1) := kRFDC_ADC_Q_TVALID_DB1Msb; + -- Rec.msblookupw(kRFDC_ADC_I_TVALID_DB1) := kRFDC_ADC_I_TVALID_DB1Msb; + -- Rec.msblookupw(kUSER_ADC_TVALID_DB1) := kUSER_ADC_TVALID_DB1Msb; + -- Rec.msblookupw(kUSER_ADC_TREADY_DB1) := kUSER_ADC_TREADY_DB1Msb; + -- Rec.msblookupr(kRFDC_DAC_TREADY) := kRFDC_DAC_TREADYMsb; + -- Rec.msblookupr(kRFDC_DAC_TVALID) := kRFDC_DAC_TVALIDMsb; + -- Rec.msblookupr(kRFDC_ADC_Q_TREADY) := kRFDC_ADC_Q_TREADYMsb; + -- Rec.msblookupr(kRFDC_ADC_I_TREADY) := kRFDC_ADC_I_TREADYMsb; + -- Rec.msblookupr(kRFDC_ADC_Q_TVALID) := kRFDC_ADC_Q_TVALIDMsb; + -- Rec.msblookupr(kRFDC_ADC_I_TVALID) := kRFDC_ADC_I_TVALIDMsb; + -- Rec.msblookupr(kUSER_ADC_TVALID) := kUSER_ADC_TVALIDMsb; + -- Rec.msblookupr(kUSER_ADC_TREADY) := kUSER_ADC_TREADYMsb; + -- Rec.msblookupr(kRFDC_DAC_TREADY_DB1) := kRFDC_DAC_TREADY_DB1Msb; + -- Rec.msblookupr(kRFDC_DAC_TVALID_DB1) := kRFDC_DAC_TVALID_DB1Msb; + -- Rec.msblookupr(kRFDC_ADC_Q_TREADY_DB1) := kRFDC_ADC_Q_TREADY_DB1Msb; + -- Rec.msblookupr(kRFDC_ADC_I_TREADY_DB1) := kRFDC_ADC_I_TREADY_DB1Msb; + -- Rec.msblookupr(kRFDC_ADC_Q_TVALID_DB1) := kRFDC_ADC_Q_TVALID_DB1Msb; + -- Rec.msblookupr(kRFDC_ADC_I_TVALID_DB1) := kRFDC_ADC_I_TVALID_DB1Msb; + -- Rec.msblookupr(kUSER_ADC_TVALID_DB1) := kUSER_ADC_TVALID_DB1Msb; + -- Rec.msblookupr(kUSER_ADC_TREADY_DB1) := kUSER_ADC_TREADY_DB1Msb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF_AXI_STATUS_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF_AXI_STATUS_REGRec; + + -- function kFABRIC_DSP_REGRec not implemented because FABRIC_DSP_REG has programmable attributes + ---- Return the record of register kFABRIC_DSP_REG + --function kFABRIC_DSP_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"13008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"ffffffff"); + -- Rec.rmask := XRegResize(X"ffffffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- Rec.initialvalue := XRegResize(X"00000000"); + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kFABRIC_DSP_RX_CNT) := kFABRIC_DSP_RX_CNTMsb; + -- Rec.msblookupw(kFABRIC_DSP_TX_CNT) := kFABRIC_DSP_TX_CNTMsb; + -- Rec.msblookupw(kFABRIC_DSP_RESERVED) := kFABRIC_DSP_RESERVEDMsb; + -- Rec.msblookupw(kFABRIC_DSP_RX_CNT_DB1) := kFABRIC_DSP_RX_CNT_DB1Msb; + -- Rec.msblookupw(kFABRIC_DSP_TX_CNT_DB1) := kFABRIC_DSP_TX_CNT_DB1Msb; + -- Rec.msblookupw(kFABRIC_DSP_RESERVED_DB1) := kFABRIC_DSP_RESERVED_DB1Msb; + -- Rec.msblookupw(kFABRIC_DSP_BW) := kFABRIC_DSP_BWMsb; + -- Rec.msblookupr(kFABRIC_DSP_RX_CNT) := kFABRIC_DSP_RX_CNTMsb; + -- Rec.msblookupr(kFABRIC_DSP_TX_CNT) := kFABRIC_DSP_TX_CNTMsb; + -- Rec.msblookupr(kFABRIC_DSP_RESERVED) := kFABRIC_DSP_RESERVEDMsb; + -- Rec.msblookupr(kFABRIC_DSP_RX_CNT_DB1) := kFABRIC_DSP_RX_CNT_DB1Msb; + -- Rec.msblookupr(kFABRIC_DSP_TX_CNT_DB1) := kFABRIC_DSP_TX_CNT_DB1Msb; + -- Rec.msblookupr(kFABRIC_DSP_RESERVED_DB1) := kFABRIC_DSP_RESERVED_DB1Msb; + -- Rec.msblookupr(kFABRIC_DSP_BW) := kFABRIC_DSP_BWMsb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("FABRIC_DSP_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kFABRIC_DSP_REGRec; + + -- function kCALIBRATION_DATARec not implemented because CALIBRATION_DATA has programmable attributes + ---- Return the record of register kCALIBRATION_DATA + --function kCALIBRATION_DATARec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"14000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"ffffffff"); + -- Rec.rmask := XRegResize(X"ffffffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kI_DATA) := kI_DATAMsb; + -- Rec.msblookupw(kQ_DATA) := kQ_DATAMsb; + -- Rec.msblookupr(kI_DATA) := kI_DATAMsb; + -- Rec.msblookupr(kQ_DATA) := kQ_DATAMsb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("CALIBRATION_DATA"); + -- --synopsys translate_on + -- return Rec; + --end function kCALIBRATION_DATARec; + + -- function kCALIBRATION_ENABLERec not implemented because CALIBRATION_ENABLE has programmable attributes + ---- Return the record of register kCALIBRATION_ENABLE + --function kCALIBRATION_ENABLERec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"14008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"000000ff"); + -- Rec.rmask := XRegResize(X"000000ff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("CALIBRATION_ENABLE"); + -- --synopsys translate_on + -- return Rec; + --end function kCALIBRATION_ENABLERec; + + -- function kTHRESHOLD_STATUSRec not implemented because THRESHOLD_STATUS has programmable attributes + ---- Return the record of register kTHRESHOLD_STATUS + --function kTHRESHOLD_STATUSRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"15000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"0000ffff"); + -- Rec.rmask := XRegResize(X"0000ffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("THRESHOLD_STATUS"); + -- --synopsys translate_on + -- return Rec; + --end function kTHRESHOLD_STATUSRec; + + -- function kRF_PLL_CONTROL_REGRec not implemented because RF_PLL_CONTROL_REG has programmable attributes + ---- Return the record of register kRF_PLL_CONTROL_REG + --function kRF_PLL_CONTROL_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"16000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"01111100"); + -- Rec.rmask := XRegResize(X"01111100"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF_PLL_CONTROL_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF_PLL_CONTROL_REGRec; + + -- function kRF_PLL_STATUS_REGRec not implemented because RF_PLL_STATUS_REG has programmable attributes + ---- Return the record of register kRF_PLL_STATUS_REG + --function kRF_PLL_STATUS_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"16008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"00110000"); + -- Rec.rmask := XRegResize(X"00110000"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF_PLL_STATUS_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF_PLL_STATUS_REGRec; + + -- function kADC_TILEMAP_REGRec not implemented because ADC_TILEMAP_REG has programmable attributes + ---- Return the record of register kADC_TILEMAP_REG + --function kADC_TILEMAP_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"17000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"ffffffff"); + -- Rec.rmask := XRegResize(X"ffffffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- Rec.initialvalue := XRegResize(X"00000000"); + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kADC_TILEMAP_DB0_CHAN0_TILE) := kADC_TILEMAP_DB0_CHAN0_TILEMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB0_CHAN0_BLOCK) := kADC_TILEMAP_DB0_CHAN0_BLOCKMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB0_CHAN1_TILE) := kADC_TILEMAP_DB0_CHAN1_TILEMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB0_CHAN1_BLOCK) := kADC_TILEMAP_DB0_CHAN1_BLOCKMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB0_CHAN2_TILE) := kADC_TILEMAP_DB0_CHAN2_TILEMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB0_CHAN2_BLOCK) := kADC_TILEMAP_DB0_CHAN2_BLOCKMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB0_CHAN3_TILE) := kADC_TILEMAP_DB0_CHAN3_TILEMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB0_CHAN3_BLOCK) := kADC_TILEMAP_DB0_CHAN3_BLOCKMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB1_CHAN0_TILE) := kADC_TILEMAP_DB1_CHAN0_TILEMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB1_CHAN0_BLOCK) := kADC_TILEMAP_DB1_CHAN0_BLOCKMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB1_CHAN1_TILE) := kADC_TILEMAP_DB1_CHAN1_TILEMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB1_CHAN1_BLOCK) := kADC_TILEMAP_DB1_CHAN1_BLOCKMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB1_CHAN2_TILE) := kADC_TILEMAP_DB1_CHAN2_TILEMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB1_CHAN2_BLOCK) := kADC_TILEMAP_DB1_CHAN2_BLOCKMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB1_CHAN3_TILE) := kADC_TILEMAP_DB1_CHAN3_TILEMsb; + -- Rec.msblookupw(kADC_TILEMAP_DB1_CHAN3_BLOCK) := kADC_TILEMAP_DB1_CHAN3_BLOCKMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB0_CHAN0_TILE) := kADC_TILEMAP_DB0_CHAN0_TILEMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB0_CHAN0_BLOCK) := kADC_TILEMAP_DB0_CHAN0_BLOCKMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB0_CHAN1_TILE) := kADC_TILEMAP_DB0_CHAN1_TILEMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB0_CHAN1_BLOCK) := kADC_TILEMAP_DB0_CHAN1_BLOCKMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB0_CHAN2_TILE) := kADC_TILEMAP_DB0_CHAN2_TILEMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB0_CHAN2_BLOCK) := kADC_TILEMAP_DB0_CHAN2_BLOCKMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB0_CHAN3_TILE) := kADC_TILEMAP_DB0_CHAN3_TILEMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB0_CHAN3_BLOCK) := kADC_TILEMAP_DB0_CHAN3_BLOCKMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB1_CHAN0_TILE) := kADC_TILEMAP_DB1_CHAN0_TILEMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB1_CHAN0_BLOCK) := kADC_TILEMAP_DB1_CHAN0_BLOCKMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB1_CHAN1_TILE) := kADC_TILEMAP_DB1_CHAN1_TILEMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB1_CHAN1_BLOCK) := kADC_TILEMAP_DB1_CHAN1_BLOCKMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB1_CHAN2_TILE) := kADC_TILEMAP_DB1_CHAN2_TILEMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB1_CHAN2_BLOCK) := kADC_TILEMAP_DB1_CHAN2_BLOCKMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB1_CHAN3_TILE) := kADC_TILEMAP_DB1_CHAN3_TILEMsb; + -- Rec.msblookupr(kADC_TILEMAP_DB1_CHAN3_BLOCK) := kADC_TILEMAP_DB1_CHAN3_BLOCKMsb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("ADC_TILEMAP_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kADC_TILEMAP_REGRec; + + -- function kDAC_TILEMAP_REGRec not implemented because DAC_TILEMAP_REG has programmable attributes + ---- Return the record of register kDAC_TILEMAP_REG + --function kDAC_TILEMAP_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"17008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"ffffffff"); + -- Rec.rmask := XRegResize(X"ffffffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- Rec.initialvalue := XRegResize(X"00000000"); + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kDAC_TILEMAP_DB0_CHAN0_TILE) := kDAC_TILEMAP_DB0_CHAN0_TILEMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB0_CHAN0_BLOCK) := kDAC_TILEMAP_DB0_CHAN0_BLOCKMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB0_CHAN1_TILE) := kDAC_TILEMAP_DB0_CHAN1_TILEMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB0_CHAN1_BLOCK) := kDAC_TILEMAP_DB0_CHAN1_BLOCKMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB0_CHAN2_TILE) := kDAC_TILEMAP_DB0_CHAN2_TILEMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB0_CHAN2_BLOCK) := kDAC_TILEMAP_DB0_CHAN2_BLOCKMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB0_CHAN3_TILE) := kDAC_TILEMAP_DB0_CHAN3_TILEMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB0_CHAN3_BLOCK) := kDAC_TILEMAP_DB0_CHAN3_BLOCKMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB1_CHAN0_TILE) := kDAC_TILEMAP_DB1_CHAN0_TILEMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB1_CHAN0_BLOCK) := kDAC_TILEMAP_DB1_CHAN0_BLOCKMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB1_CHAN1_TILE) := kDAC_TILEMAP_DB1_CHAN1_TILEMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB1_CHAN1_BLOCK) := kDAC_TILEMAP_DB1_CHAN1_BLOCKMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB1_CHAN2_TILE) := kDAC_TILEMAP_DB1_CHAN2_TILEMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB1_CHAN2_BLOCK) := kDAC_TILEMAP_DB1_CHAN2_BLOCKMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB1_CHAN3_TILE) := kDAC_TILEMAP_DB1_CHAN3_TILEMsb; + -- Rec.msblookupw(kDAC_TILEMAP_DB1_CHAN3_BLOCK) := kDAC_TILEMAP_DB1_CHAN3_BLOCKMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB0_CHAN0_TILE) := kDAC_TILEMAP_DB0_CHAN0_TILEMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB0_CHAN0_BLOCK) := kDAC_TILEMAP_DB0_CHAN0_BLOCKMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB0_CHAN1_TILE) := kDAC_TILEMAP_DB0_CHAN1_TILEMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB0_CHAN1_BLOCK) := kDAC_TILEMAP_DB0_CHAN1_BLOCKMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB0_CHAN2_TILE) := kDAC_TILEMAP_DB0_CHAN2_TILEMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB0_CHAN2_BLOCK) := kDAC_TILEMAP_DB0_CHAN2_BLOCKMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB0_CHAN3_TILE) := kDAC_TILEMAP_DB0_CHAN3_TILEMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB0_CHAN3_BLOCK) := kDAC_TILEMAP_DB0_CHAN3_BLOCKMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB1_CHAN0_TILE) := kDAC_TILEMAP_DB1_CHAN0_TILEMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB1_CHAN0_BLOCK) := kDAC_TILEMAP_DB1_CHAN0_BLOCKMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB1_CHAN1_TILE) := kDAC_TILEMAP_DB1_CHAN1_TILEMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB1_CHAN1_BLOCK) := kDAC_TILEMAP_DB1_CHAN1_BLOCKMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB1_CHAN2_TILE) := kDAC_TILEMAP_DB1_CHAN2_TILEMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB1_CHAN2_BLOCK) := kDAC_TILEMAP_DB1_CHAN2_BLOCKMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB1_CHAN3_TILE) := kDAC_TILEMAP_DB1_CHAN3_TILEMsb; + -- Rec.msblookupr(kDAC_TILEMAP_DB1_CHAN3_BLOCK) := kDAC_TILEMAP_DB1_CHAN3_BLOCKMsb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("DAC_TILEMAP_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kDAC_TILEMAP_REGRec; + + -- function kRFDC_INFO_REGRec not implemented because RFDC_INFO_REG has programmable attributes + ---- Return the record of register kRFDC_INFO_REG + --function kRFDC_INFO_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"18000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"03ff03ff"); + -- Rec.rmask := XRegResize(X"03ff03ff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- Rec.initialvalue := XRegResize(X"00910091"); + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kRFDC_INFO_XTRA_RESAMP) := kRFDC_INFO_XTRA_RESAMPMsb; + -- Rec.msblookupw(kRFDC_INFO_SPC_RX) := kRFDC_INFO_SPC_RXMsb; + -- Rec.msblookupw(kRFDC_INFO_SPC_TX) := kRFDC_INFO_SPC_TXMsb; + -- Rec.msblookupw(kRFDC_INFO_XTRA_RESAMP_DB1) := kRFDC_INFO_XTRA_RESAMP_DB1Msb; + -- Rec.msblookupw(kRFDC_INFO_SPC_RX_DB1) := kRFDC_INFO_SPC_RX_DB1Msb; + -- Rec.msblookupw(kRFDC_INFO_SPC_TX_DB1) := kRFDC_INFO_SPC_TX_DB1Msb; + -- Rec.msblookupr(kRFDC_INFO_XTRA_RESAMP) := kRFDC_INFO_XTRA_RESAMPMsb; + -- Rec.msblookupr(kRFDC_INFO_SPC_RX) := kRFDC_INFO_SPC_RXMsb; + -- Rec.msblookupr(kRFDC_INFO_SPC_TX) := kRFDC_INFO_SPC_TXMsb; + -- Rec.msblookupr(kRFDC_INFO_XTRA_RESAMP_DB1) := kRFDC_INFO_XTRA_RESAMP_DB1Msb; + -- Rec.msblookupr(kRFDC_INFO_SPC_RX_DB1) := kRFDC_INFO_SPC_RX_DB1Msb; + -- Rec.msblookupr(kRFDC_INFO_SPC_TX_DB1) := kRFDC_INFO_SPC_TX_DB1Msb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RFDC_INFO_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRFDC_INFO_REGRec; + +end package body; diff --git a/top/x400/regmap/x440/rfdc_mapping_regmap_utils.vh b/top/x400/regmap/x440/rfdc_mapping_regmap_utils.vh new file mode 100644 index 0000000..cf3e1d8 --- /dev/null +++ b/top/x400/regmap/x440/rfdc_mapping_regmap_utils.vh @@ -0,0 +1,43 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rfdc_mapping_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group CHANNEL_SWAPPING +//=============================================================================== + + // Enumerated type RFDC_ADC_MAPPING + localparam RFDC_ADC_MAPPING_SIZE = 8; + localparam CH2_RX_MAPPING = 'h0; // RFDC_ADC_MAPPING:CH2_RX_MAPPING + localparam CH1_RX_MAPPING = 'h1; // RFDC_ADC_MAPPING:CH1_RX_MAPPING + localparam CH3_RX_MAPPING = 'h2; // RFDC_ADC_MAPPING:CH3_RX_MAPPING + localparam CH0_RX_MAPPING = 'h3; // RFDC_ADC_MAPPING:CH0_RX_MAPPING + localparam CH6_RX_MAPPING = 'h4; // RFDC_ADC_MAPPING:CH6_RX_MAPPING + localparam CH5_RX_MAPPING = 'h5; // RFDC_ADC_MAPPING:CH5_RX_MAPPING + localparam CH7_RX_MAPPING = 'h6; // RFDC_ADC_MAPPING:CH7_RX_MAPPING + localparam CH4_RX_MAPPING = 'h7; // RFDC_ADC_MAPPING:CH4_RX_MAPPING + + // Enumerated type RFDC_DAC_MAPPING + localparam RFDC_DAC_MAPPING_SIZE = 8; + localparam CH0_TX_MAPPING = 'h0; // RFDC_DAC_MAPPING:CH0_TX_MAPPING + localparam CH3_TX_MAPPING = 'h1; // RFDC_DAC_MAPPING:CH3_TX_MAPPING + localparam CH1_TX_MAPPING = 'h2; // RFDC_DAC_MAPPING:CH1_TX_MAPPING + localparam CH2_TX_MAPPING = 'h3; // RFDC_DAC_MAPPING:CH2_TX_MAPPING + localparam CH4_TX_MAPPING = 'h4; // RFDC_DAC_MAPPING:CH4_TX_MAPPING + localparam CH7_TX_MAPPING = 'h5; // RFDC_DAC_MAPPING:CH7_TX_MAPPING + localparam CH5_TX_MAPPING = 'h6; // RFDC_DAC_MAPPING:CH5_TX_MAPPING + localparam CH6_TX_MAPPING = 'h7; // RFDC_DAC_MAPPING:CH6_TX_MAPPING diff --git a/top/x400/regmap/x440/rfdc_regs_regmap_utils.vh b/top/x400/regmap/x440/rfdc_regs_regmap_utils.vh new file mode 100644 index 0000000..b9084e8 --- /dev/null +++ b/top/x400/regmap/x440/rfdc_regs_regmap_utils.vh @@ -0,0 +1,512 @@ +// +// Copyright 2023 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rfdc_regs_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // MMCM : 0x0 (x440_rfdc_regs.v) + // INVERT_DB0_IQ_REG : 0x10000 (x440_rfdc_regs.v) + // INVERT_DB1_IQ_REG : 0x10800 (x440_rfdc_regs.v) + // MMCM_RESET_REG : 0x11000 (x440_rfdc_regs.v) + // RF0_RESET_CONTROL_REG : 0x12000 (x440_rfdc_regs.v) + // RF0_RESET_STATUS_REG : 0x12008 (x440_rfdc_regs.v) + // RF1_RESET_CONTROL_REG : 0x12800 (x440_rfdc_regs.v) + // RF1_RESET_STATUS_REG : 0x12808 (x440_rfdc_regs.v) + // RF_AXI_STATUS_REG : 0x13000 (x440_rfdc_regs.v) + // FABRIC_DSP_REG : 0x13008 (x440_rfdc_regs.v) + // CALIBRATION_DATA : 0x14000 (x440_rfdc_regs.v) + // CALIBRATION_ENABLE : 0x14008 (x440_rfdc_regs.v) + // THRESHOLD_STATUS : 0x15000 (x440_rfdc_regs.v) + // RF_PLL_CONTROL_REG : 0x16000 (x440_rfdc_regs.v) + // RF_PLL_STATUS_REG : 0x16008 (x440_rfdc_regs.v) + // ADC_TILEMAP_REG : 0x17000 (x440_rfdc_regs.v) + // DAC_TILEMAP_REG : 0x17008 (x440_rfdc_regs.v) + // RFDC_INFO_REG : 0x18000 (x440_rfdc_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // ADC_TILEMAP_REGTYPE Type (from common_regs.v) + localparam ADC_TILEMAP_REGTYPE_SIZE = 32; + localparam ADC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF; + localparam ADC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE + localparam ADC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE + localparam ADC_TILEMAP_DB0_CHAN0_TILE = 0; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE + localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK + localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK + localparam ADC_TILEMAP_DB0_CHAN0_BLOCK = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK + localparam ADC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE + localparam ADC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE + localparam ADC_TILEMAP_DB0_CHAN1_TILE = 4; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE + localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK + localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK + localparam ADC_TILEMAP_DB0_CHAN1_BLOCK = 6; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK + localparam ADC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE + localparam ADC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE + localparam ADC_TILEMAP_DB0_CHAN2_TILE = 8; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE + localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK + localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK + localparam ADC_TILEMAP_DB0_CHAN2_BLOCK = 10; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK + localparam ADC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE + localparam ADC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE + localparam ADC_TILEMAP_DB0_CHAN3_TILE = 12; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE + localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK + localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK + localparam ADC_TILEMAP_DB0_CHAN3_BLOCK = 14; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK + localparam ADC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE + localparam ADC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE + localparam ADC_TILEMAP_DB1_CHAN0_TILE = 16; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE + localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK + localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK + localparam ADC_TILEMAP_DB1_CHAN0_BLOCK = 18; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK + localparam ADC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE + localparam ADC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE + localparam ADC_TILEMAP_DB1_CHAN1_TILE = 20; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE + localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK + localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK + localparam ADC_TILEMAP_DB1_CHAN1_BLOCK = 22; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK + localparam ADC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE + localparam ADC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE + localparam ADC_TILEMAP_DB1_CHAN2_TILE = 24; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE + localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK + localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK + localparam ADC_TILEMAP_DB1_CHAN2_BLOCK = 26; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK + localparam ADC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE + localparam ADC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE + localparam ADC_TILEMAP_DB1_CHAN3_TILE = 28; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE + localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK + localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK + localparam ADC_TILEMAP_DB1_CHAN3_BLOCK = 30; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK + + // DAC_TILEMAP_REGTYPE Type (from common_regs.v) + localparam DAC_TILEMAP_REGTYPE_SIZE = 32; + localparam DAC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF; + localparam DAC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE + localparam DAC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE + localparam DAC_TILEMAP_DB0_CHAN0_TILE = 0; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE + localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK + localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK + localparam DAC_TILEMAP_DB0_CHAN0_BLOCK = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK + localparam DAC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE + localparam DAC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE + localparam DAC_TILEMAP_DB0_CHAN1_TILE = 4; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE + localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK + localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK + localparam DAC_TILEMAP_DB0_CHAN1_BLOCK = 6; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK + localparam DAC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE + localparam DAC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE + localparam DAC_TILEMAP_DB0_CHAN2_TILE = 8; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE + localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK + localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK + localparam DAC_TILEMAP_DB0_CHAN2_BLOCK = 10; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK + localparam DAC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE + localparam DAC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE + localparam DAC_TILEMAP_DB0_CHAN3_TILE = 12; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE + localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK + localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK + localparam DAC_TILEMAP_DB0_CHAN3_BLOCK = 14; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK + localparam DAC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE + localparam DAC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE + localparam DAC_TILEMAP_DB1_CHAN0_TILE = 16; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE + localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK + localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK + localparam DAC_TILEMAP_DB1_CHAN0_BLOCK = 18; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK + localparam DAC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE + localparam DAC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE + localparam DAC_TILEMAP_DB1_CHAN1_TILE = 20; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE + localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK + localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK + localparam DAC_TILEMAP_DB1_CHAN1_BLOCK = 22; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK + localparam DAC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE + localparam DAC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE + localparam DAC_TILEMAP_DB1_CHAN2_TILE = 24; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE + localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK + localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK + localparam DAC_TILEMAP_DB1_CHAN2_BLOCK = 26; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK + localparam DAC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE + localparam DAC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE + localparam DAC_TILEMAP_DB1_CHAN3_TILE = 28; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE + localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK + localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK + localparam DAC_TILEMAP_DB1_CHAN3_BLOCK = 30; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK + + // FABRIC_DSP_REGTYPE Type (from common_regs.v) + localparam FABRIC_DSP_REGTYPE_SIZE = 32; + localparam FABRIC_DSP_REGTYPE_MASK = 32'hFFFFFFFF; + localparam FABRIC_DSP_RX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT + localparam FABRIC_DSP_RX_CNT_MSB = 3; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT + localparam FABRIC_DSP_RX_CNT = 0; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT + localparam FABRIC_DSP_TX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT + localparam FABRIC_DSP_TX_CNT_MSB = 7; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT + localparam FABRIC_DSP_TX_CNT = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT + localparam FABRIC_DSP_RESERVED_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED + localparam FABRIC_DSP_RESERVED_MSB = 9; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED + localparam FABRIC_DSP_RESERVED = 8; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED + localparam FABRIC_DSP_RX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1 + localparam FABRIC_DSP_RX_CNT_DB1_MSB = 13; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1 + localparam FABRIC_DSP_RX_CNT_DB1 = 10; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1 + localparam FABRIC_DSP_TX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1 + localparam FABRIC_DSP_TX_CNT_DB1_MSB = 17; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1 + localparam FABRIC_DSP_TX_CNT_DB1 = 14; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1 + localparam FABRIC_DSP_RESERVED_DB1_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1 + localparam FABRIC_DSP_RESERVED_DB1_MSB = 19; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1 + localparam FABRIC_DSP_RESERVED_DB1 = 18; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1 + localparam FABRIC_DSP_BW_SIZE = 12; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW + localparam FABRIC_DSP_BW_MSB = 31; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW + localparam FABRIC_DSP_BW = 20; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW + + // RF_AXI_STATUS_REGTYPE Type (from common_regs.v) + localparam RF_AXI_STATUS_REGTYPE_SIZE = 32; + localparam RF_AXI_STATUS_REGTYPE_MASK = 32'hFFFFFFFF; + localparam RFDC_DAC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY + localparam RFDC_DAC_TREADY_MSB = 1; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY + localparam RFDC_DAC_TREADY = 0; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY + localparam RFDC_DAC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID + localparam RFDC_DAC_TVALID_MSB = 3; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID + localparam RFDC_DAC_TVALID = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID + localparam RFDC_ADC_Q_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY + localparam RFDC_ADC_Q_TREADY_MSB = 5; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY + localparam RFDC_ADC_Q_TREADY = 4; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY + localparam RFDC_ADC_I_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY + localparam RFDC_ADC_I_TREADY_MSB = 7; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY + localparam RFDC_ADC_I_TREADY = 6; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY + localparam RFDC_ADC_Q_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID + localparam RFDC_ADC_Q_TVALID_MSB = 9; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID + localparam RFDC_ADC_Q_TVALID = 8; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID + localparam RFDC_ADC_I_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID + localparam RFDC_ADC_I_TVALID_MSB = 11; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID + localparam RFDC_ADC_I_TVALID = 10; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID + localparam USER_ADC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID + localparam USER_ADC_TVALID_MSB = 13; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID + localparam USER_ADC_TVALID = 12; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID + localparam USER_ADC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY + localparam USER_ADC_TREADY_MSB = 15; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY + localparam USER_ADC_TREADY = 14; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY + localparam RFDC_DAC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1 + localparam RFDC_DAC_TREADY_DB1_MSB = 17; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1 + localparam RFDC_DAC_TREADY_DB1 = 16; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1 + localparam RFDC_DAC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1 + localparam RFDC_DAC_TVALID_DB1_MSB = 19; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1 + localparam RFDC_DAC_TVALID_DB1 = 18; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1 + localparam RFDC_ADC_Q_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1 + localparam RFDC_ADC_Q_TREADY_DB1_MSB = 21; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1 + localparam RFDC_ADC_Q_TREADY_DB1 = 20; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1 + localparam RFDC_ADC_I_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1 + localparam RFDC_ADC_I_TREADY_DB1_MSB = 23; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1 + localparam RFDC_ADC_I_TREADY_DB1 = 22; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1 + localparam RFDC_ADC_Q_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1 + localparam RFDC_ADC_Q_TVALID_DB1_MSB = 25; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1 + localparam RFDC_ADC_Q_TVALID_DB1 = 24; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1 + localparam RFDC_ADC_I_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1 + localparam RFDC_ADC_I_TVALID_DB1_MSB = 27; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1 + localparam RFDC_ADC_I_TVALID_DB1 = 26; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1 + localparam USER_ADC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1 + localparam USER_ADC_TVALID_DB1_MSB = 29; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1 + localparam USER_ADC_TVALID_DB1 = 28; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1 + localparam USER_ADC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1 + localparam USER_ADC_TREADY_DB1_MSB = 31; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1 + localparam USER_ADC_TREADY_DB1 = 30; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1 + + // RF_RESET_CONTROL_REGTYPE Type (from common_regs.v) + localparam RF_RESET_CONTROL_REGTYPE_SIZE = 32; + localparam RF_RESET_CONTROL_REGTYPE_MASK = 32'h331; + localparam FSM_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:FSM_RESET + localparam FSM_RESET_MSB = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET + localparam FSM_RESET = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET + localparam ADC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_RESET + localparam ADC_RESET_MSB = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET + localparam ADC_RESET = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET + localparam ADC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE + localparam ADC_ENABLE_MSB = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE + localparam ADC_ENABLE = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE + localparam DAC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_RESET + localparam DAC_RESET_MSB = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET + localparam DAC_RESET = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET + localparam DAC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE + localparam DAC_ENABLE_MSB = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE + localparam DAC_ENABLE = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE + + // RF_RESET_STATUS_REGTYPE Type (from common_regs.v) + localparam RF_RESET_STATUS_REGTYPE_SIZE = 32; + localparam RF_RESET_STATUS_REGTYPE_MASK = 32'h888; + localparam FSM_RESET_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE + localparam FSM_RESET_DONE_MSB = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE + localparam FSM_RESET_DONE = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE + localparam ADC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE + localparam ADC_SEQ_DONE_MSB = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE + localparam ADC_SEQ_DONE = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE + localparam DAC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE + localparam DAC_SEQ_DONE_MSB = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE + localparam DAC_SEQ_DONE = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE + + // RFDC_INFO_REGTYPE Type (from common_regs.v) + localparam RFDC_INFO_REGTYPE_SIZE = 32; + localparam RFDC_INFO_REGTYPE_MASK = 32'h3FF03FF; + localparam RFDC_INFO_XTRA_RESAMP_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP + localparam RFDC_INFO_XTRA_RESAMP_MSB = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP + localparam RFDC_INFO_XTRA_RESAMP = 0; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP + localparam RFDC_INFO_SPC_RX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX + localparam RFDC_INFO_SPC_RX_MSB = 6; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX + localparam RFDC_INFO_SPC_RX = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX + localparam RFDC_INFO_SPC_TX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX + localparam RFDC_INFO_SPC_TX_MSB = 9; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX + localparam RFDC_INFO_SPC_TX = 7; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX + localparam RFDC_INFO_XTRA_RESAMP_DB1_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1 + localparam RFDC_INFO_XTRA_RESAMP_DB1_MSB = 19; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1 + localparam RFDC_INFO_XTRA_RESAMP_DB1 = 16; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1 + localparam RFDC_INFO_SPC_RX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1 + localparam RFDC_INFO_SPC_RX_DB1_MSB = 22; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1 + localparam RFDC_INFO_SPC_RX_DB1 = 20; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1 + localparam RFDC_INFO_SPC_TX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1 + localparam RFDC_INFO_SPC_TX_DB1_MSB = 25; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1 + localparam RFDC_INFO_SPC_TX_DB1 = 23; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1 + +//=============================================================================== +// Register Group RFDC_REGS +//=============================================================================== + + // Enumerated type FABRIC_DSP_BW_ENUM + localparam FABRIC_DSP_BW_ENUM_SIZE = 5; + localparam FABRIC_DSP_BW_NONE = 'h0; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE + localparam FABRIC_DSP_BW_100M = 'h64; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M + localparam FABRIC_DSP_BW_200M = 'hC8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M + localparam FABRIC_DSP_BW_400M = 'h190; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M + localparam FABRIC_DSP_BW_FULL = 'h3E8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_FULL + + // MMCM Window (from x440_rfdc_regs.v) + localparam MMCM = 'h0; // Window Offset + localparam MMCM_SIZE = 'h10000; // size in bytes + + // INVERT_DB0_IQ_REG Register (from x440_rfdc_regs.v) + localparam INVERT_DB0_IQ_REG = 'h10000; // Register Offset + localparam INVERT_DB0_IQ_REG_SIZE = 32; // register width in bits + localparam INVERT_DB0_IQ_REG_MASK = 32'hF0F; + localparam INVERT_DB0_ADC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ + localparam INVERT_DB0_ADC0_IQ_MSB = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ + localparam INVERT_DB0_ADC0_IQ = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ + localparam INVERT_DB0_ADC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ + localparam INVERT_DB0_ADC1_IQ_MSB = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ + localparam INVERT_DB0_ADC1_IQ = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ + localparam INVERT_DB0_ADC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ + localparam INVERT_DB0_ADC2_IQ_MSB = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ + localparam INVERT_DB0_ADC2_IQ = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ + localparam INVERT_DB0_ADC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ + localparam INVERT_DB0_ADC3_IQ_MSB = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ + localparam INVERT_DB0_ADC3_IQ = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ + localparam INVERT_DB0_DAC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ + localparam INVERT_DB0_DAC0_IQ_MSB = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ + localparam INVERT_DB0_DAC0_IQ = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ + localparam INVERT_DB0_DAC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ + localparam INVERT_DB0_DAC1_IQ_MSB = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ + localparam INVERT_DB0_DAC1_IQ = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ + localparam INVERT_DB0_DAC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ + localparam INVERT_DB0_DAC2_IQ_MSB = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ + localparam INVERT_DB0_DAC2_IQ = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ + localparam INVERT_DB0_DAC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ + localparam INVERT_DB0_DAC3_IQ_MSB = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ + localparam INVERT_DB0_DAC3_IQ = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ + + // INVERT_DB1_IQ_REG Register (from x440_rfdc_regs.v) + localparam INVERT_DB1_IQ_REG = 'h10800; // Register Offset + localparam INVERT_DB1_IQ_REG_SIZE = 32; // register width in bits + localparam INVERT_DB1_IQ_REG_MASK = 32'hF0F; + localparam INVERT_DB1_ADC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ + localparam INVERT_DB1_ADC0_IQ_MSB = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ + localparam INVERT_DB1_ADC0_IQ = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ + localparam INVERT_DB1_ADC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ + localparam INVERT_DB1_ADC1_IQ_MSB = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ + localparam INVERT_DB1_ADC1_IQ = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ + localparam INVERT_DB1_ADC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ + localparam INVERT_DB1_ADC2_IQ_MSB = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ + localparam INVERT_DB1_ADC2_IQ = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ + localparam INVERT_DB1_ADC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ + localparam INVERT_DB1_ADC3_IQ_MSB = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ + localparam INVERT_DB1_ADC3_IQ = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ + localparam INVERT_DB1_DAC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ + localparam INVERT_DB1_DAC0_IQ_MSB = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ + localparam INVERT_DB1_DAC0_IQ = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ + localparam INVERT_DB1_DAC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ + localparam INVERT_DB1_DAC1_IQ_MSB = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ + localparam INVERT_DB1_DAC1_IQ = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ + localparam INVERT_DB1_DAC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ + localparam INVERT_DB1_DAC2_IQ_MSB = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ + localparam INVERT_DB1_DAC2_IQ = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ + localparam INVERT_DB1_DAC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ + localparam INVERT_DB1_DAC3_IQ_MSB = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ + localparam INVERT_DB1_DAC3_IQ = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ + + // MMCM_RESET_REG Register (from x440_rfdc_regs.v) + localparam MMCM_RESET_REG = 'h11000; // Register Offset + localparam MMCM_RESET_REG_SIZE = 32; // register width in bits + localparam MMCM_RESET_REG_MASK = 32'h1; + localparam RESET_MMCM_SIZE = 1; //MMCM_RESET_REG:RESET_MMCM + localparam RESET_MMCM_MSB = 0; //MMCM_RESET_REG:RESET_MMCM + localparam RESET_MMCM = 0; //MMCM_RESET_REG:RESET_MMCM + + // RF0_RESET_CONTROL_REG Register (from x440_rfdc_regs.v) + localparam RF0_RESET_CONTROL_REG = 'h12000; // Register Offset + localparam RF0_RESET_CONTROL_REG_SIZE = 32; // register width in bits + + // RF0_RESET_STATUS_REG Register (from x440_rfdc_regs.v) + localparam RF0_RESET_STATUS_REG = 'h12008; // Register Offset + localparam RF0_RESET_STATUS_REG_SIZE = 32; // register width in bits + + // RF1_RESET_CONTROL_REG Register (from x440_rfdc_regs.v) + localparam RF1_RESET_CONTROL_REG = 'h12800; // Register Offset + localparam RF1_RESET_CONTROL_REG_SIZE = 32; // register width in bits + + // RF1_RESET_STATUS_REG Register (from x440_rfdc_regs.v) + localparam RF1_RESET_STATUS_REG = 'h12808; // Register Offset + localparam RF1_RESET_STATUS_REG_SIZE = 32; // register width in bits + + // RF_AXI_STATUS_REG Register (from x440_rfdc_regs.v) + localparam RF_AXI_STATUS_REG = 'h13000; // Register Offset + localparam RF_AXI_STATUS_REG_SIZE = 32; // register width in bits + + // FABRIC_DSP_REG Register (from x440_rfdc_regs.v) + localparam FABRIC_DSP_REG = 'h13008; // Register Offset + localparam FABRIC_DSP_REG_SIZE = 32; // register width in bits + + // CALIBRATION_DATA Register (from x440_rfdc_regs.v) + localparam CALIBRATION_DATA = 'h14000; // Register Offset + localparam CALIBRATION_DATA_SIZE = 32; // register width in bits + localparam CALIBRATION_DATA_MASK = 32'hFFFFFFFF; + localparam I_DATA_SIZE = 16; //CALIBRATION_DATA:I_DATA + localparam I_DATA_MSB = 15; //CALIBRATION_DATA:I_DATA + localparam I_DATA = 0; //CALIBRATION_DATA:I_DATA + localparam Q_DATA_SIZE = 16; //CALIBRATION_DATA:Q_DATA + localparam Q_DATA_MSB = 31; //CALIBRATION_DATA:Q_DATA + localparam Q_DATA = 16; //CALIBRATION_DATA:Q_DATA + + // CALIBRATION_ENABLE Register (from x440_rfdc_regs.v) + localparam CALIBRATION_ENABLE = 'h14008; // Register Offset + localparam CALIBRATION_ENABLE_SIZE = 32; // register width in bits + localparam CALIBRATION_ENABLE_MASK = 32'hFF; + localparam ENABLE_CALIBRATION_DATA_0_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + localparam ENABLE_CALIBRATION_DATA_0_MSB = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + localparam ENABLE_CALIBRATION_DATA_0 = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + localparam ENABLE_CALIBRATION_DATA_1_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + localparam ENABLE_CALIBRATION_DATA_1_MSB = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + localparam ENABLE_CALIBRATION_DATA_1 = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + localparam ENABLE_CALIBRATION_DATA_2_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + localparam ENABLE_CALIBRATION_DATA_2_MSB = 2; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + localparam ENABLE_CALIBRATION_DATA_2 = 2; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + localparam ENABLE_CALIBRATION_DATA_3_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + localparam ENABLE_CALIBRATION_DATA_3_MSB = 3; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + localparam ENABLE_CALIBRATION_DATA_3 = 3; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + localparam ENABLE_CALIBRATION_DATA_4_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4 + localparam ENABLE_CALIBRATION_DATA_4_MSB = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4 + localparam ENABLE_CALIBRATION_DATA_4 = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4 + localparam ENABLE_CALIBRATION_DATA_5_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5 + localparam ENABLE_CALIBRATION_DATA_5_MSB = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5 + localparam ENABLE_CALIBRATION_DATA_5 = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5 + localparam ENABLE_CALIBRATION_DATA_6_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6 + localparam ENABLE_CALIBRATION_DATA_6_MSB = 6; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6 + localparam ENABLE_CALIBRATION_DATA_6 = 6; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6 + localparam ENABLE_CALIBRATION_DATA_7_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7 + localparam ENABLE_CALIBRATION_DATA_7_MSB = 7; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7 + localparam ENABLE_CALIBRATION_DATA_7 = 7; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7 + + // THRESHOLD_STATUS Register (from x440_rfdc_regs.v) + localparam THRESHOLD_STATUS = 'h15000; // Register Offset + localparam THRESHOLD_STATUS_SIZE = 32; // register width in bits + localparam THRESHOLD_STATUS_MASK = 32'hFFFF; + localparam ADC0_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + localparam ADC0_01_THRESHOLD1_MSB = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + localparam ADC0_01_THRESHOLD1 = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + localparam ADC0_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + localparam ADC0_01_THRESHOLD2_MSB = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + localparam ADC0_01_THRESHOLD2 = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + localparam ADC0_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + localparam ADC0_23_THRESHOLD1_MSB = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + localparam ADC0_23_THRESHOLD1 = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + localparam ADC0_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + localparam ADC0_23_THRESHOLD2_MSB = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + localparam ADC0_23_THRESHOLD2 = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + localparam ADC1_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1 + localparam ADC1_01_THRESHOLD1_MSB = 4; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1 + localparam ADC1_01_THRESHOLD1 = 4; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1 + localparam ADC1_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2 + localparam ADC1_01_THRESHOLD2_MSB = 5; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2 + localparam ADC1_01_THRESHOLD2 = 5; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2 + localparam ADC1_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1 + localparam ADC1_23_THRESHOLD1_MSB = 6; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1 + localparam ADC1_23_THRESHOLD1 = 6; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1 + localparam ADC1_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2 + localparam ADC1_23_THRESHOLD2_MSB = 7; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2 + localparam ADC1_23_THRESHOLD2 = 7; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2 + localparam ADC2_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + localparam ADC2_01_THRESHOLD1_MSB = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + localparam ADC2_01_THRESHOLD1 = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + localparam ADC2_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + localparam ADC2_01_THRESHOLD2_MSB = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + localparam ADC2_01_THRESHOLD2 = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + localparam ADC2_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + localparam ADC2_23_THRESHOLD1_MSB = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + localparam ADC2_23_THRESHOLD1 = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + localparam ADC2_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + localparam ADC2_23_THRESHOLD2_MSB = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + localparam ADC2_23_THRESHOLD2 = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + localparam ADC3_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1 + localparam ADC3_01_THRESHOLD1_MSB = 12; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1 + localparam ADC3_01_THRESHOLD1 = 12; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1 + localparam ADC3_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2 + localparam ADC3_01_THRESHOLD2_MSB = 13; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2 + localparam ADC3_01_THRESHOLD2 = 13; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2 + localparam ADC3_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1 + localparam ADC3_23_THRESHOLD1_MSB = 14; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1 + localparam ADC3_23_THRESHOLD1 = 14; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1 + localparam ADC3_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2 + localparam ADC3_23_THRESHOLD2_MSB = 15; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2 + localparam ADC3_23_THRESHOLD2 = 15; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2 + + // RF_PLL_CONTROL_REG Register (from x440_rfdc_regs.v) + localparam RF_PLL_CONTROL_REG = 'h16000; // Register Offset + localparam RF_PLL_CONTROL_REG_SIZE = 32; // register width in bits + localparam RF_PLL_CONTROL_REG_MASK = 32'h1111100; + localparam ENABLE_RF0_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK + localparam ENABLE_RF0_CLK_MSB = 8; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK + localparam ENABLE_RF0_CLK = 8; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK + localparam ENABLE_RF0_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X + localparam ENABLE_RF0_CLK_2X_MSB = 12; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X + localparam ENABLE_RF0_CLK_2X = 12; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X + localparam CLEAR_DATA_CLK_UNLOCKED_SIZE = 1; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + localparam CLEAR_DATA_CLK_UNLOCKED_MSB = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + localparam CLEAR_DATA_CLK_UNLOCKED = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + localparam ENABLE_RF1_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK + localparam ENABLE_RF1_CLK_MSB = 20; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK + localparam ENABLE_RF1_CLK = 20; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK + localparam ENABLE_RF1_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X + localparam ENABLE_RF1_CLK_2X_MSB = 24; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X + localparam ENABLE_RF1_CLK_2X = 24; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X + + // RF_PLL_STATUS_REG Register (from x440_rfdc_regs.v) + localparam RF_PLL_STATUS_REG = 'h16008; // Register Offset + localparam RF_PLL_STATUS_REG_SIZE = 32; // register width in bits + localparam RF_PLL_STATUS_REG_MASK = 32'h110000; + localparam DATA_CLK_PLL_UNLOCKED_STICKY_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + localparam DATA_CLK_PLL_UNLOCKED_STICKY_MSB = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + localparam DATA_CLK_PLL_UNLOCKED_STICKY = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + localparam DATA_CLK_PLL_LOCKED_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + localparam DATA_CLK_PLL_LOCKED_MSB = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + localparam DATA_CLK_PLL_LOCKED = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + + // ADC_TILEMAP_REG Register (from x440_rfdc_regs.v) + localparam ADC_TILEMAP_REG = 'h17000; // Register Offset + localparam ADC_TILEMAP_REG_SIZE = 32; // register width in bits + + // DAC_TILEMAP_REG Register (from x440_rfdc_regs.v) + localparam DAC_TILEMAP_REG = 'h17008; // Register Offset + localparam DAC_TILEMAP_REG_SIZE = 32; // register width in bits + + // RFDC_INFO_REG Register (from x440_rfdc_regs.v) + localparam RFDC_INFO_REG = 'h18000; // Register Offset + localparam RFDC_INFO_REG_SIZE = 32; // register width in bits diff --git a/top/x400/regmap/versioning_regs_regmap_utils.vh b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh similarity index 74% rename from top/x400/regmap/versioning_regs_regmap_utils.vh rename to top/x400/regmap/x440/versioning_regs_regmap_utils.vh index 3ad83e1..9d55b32 100644 --- a/top/x400/regmap/versioning_regs_regmap_utils.vh +++ b/top/x400/regmap/x440/versioning_regs_regmap_utils.vh @@ -1,5 +1,5 @@ // -// Copyright 2022 Ettus Research, A National Instruments Company +// Copyright 2023 Ettus Research, A National Instruments Company // // SPDX-License-Identifier: LGPL-3.0-or-later // @@ -75,37 +75,27 @@ localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD localparam DB_GPIO_IFC_CURRENT_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MAJOR localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME = 'h20110616; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME + localparam DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME = 'h22070116; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME // Enumerated type FPGA_VERSION localparam FPGA_VERSION_SIZE = 7; + localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD - localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR - localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_CURRENT_VERSION_MINOR = 'hA; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22121609; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR + localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME - // Enumerated type RF_CORE_100M_VERSION - localparam RF_CORE_100M_VERSION_SIZE = 7; - localparam RF_CORE_100M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MINOR - localparam RF_CORE_100M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_BUILD - localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR - localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD - localparam RF_CORE_100M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MAJOR - localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam RF_CORE_100M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_100M_VERSION:RF_CORE_100M_VERSION_LAST_MODIFIED_TIME - - // Enumerated type RF_CORE_400M_VERSION - localparam RF_CORE_400M_VERSION_SIZE = 7; - localparam RF_CORE_400M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MINOR - localparam RF_CORE_400M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_BUILD - localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR - localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD - localparam RF_CORE_400M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MAJOR - localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam RF_CORE_400M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_400M_VERSION:RF_CORE_400M_VERSION_LAST_MODIFIED_TIME + // Enumerated type RF_CORE_FULL_VERSION + localparam RF_CORE_FULL_VERSION_SIZE = 7; + localparam RF_CORE_FULL_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MINOR + localparam RF_CORE_FULL_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_BUILD + localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR + localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD + localparam RF_CORE_FULL_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MAJOR + localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR + localparam RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME = 'h22062900; // RF_CORE_FULL_VERSION:RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME //=============================================================================== // Register Group VERSIONING_REGS diff --git a/top/x400/regmap/x440/x440_rfdc_mapping.v b/top/x400/regmap/x440/x440_rfdc_mapping.v new file mode 100644 index 0000000..f5505c2 --- /dev/null +++ b/top/x400/regmap/x440/x440_rfdc_mapping.v @@ -0,0 +1,39 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: x440_rfdc_mapping +// Description: +// Auxiliary register map to provide a single source for RFDC mapping information + +//XmlParse xml_on +// +// +// +// +// +// Located in Tile 225, Channel 1 +// Located in Tile 224, Channel 1 +// Located in Tile 224, Channel 0 +// Located in Tile 225, Channel 0 +// Located in Tile 227, Channel 1 +// Located in Tile 226, Channel 1 +// Located in Tile 226, Channel 0 +// Located in Tile 227, Channel 0 +// +// +// +// Located in Tile 228, Channel 0 +// Located in Tile 228, Channel 2 +// Located in Tile 228, Channel 3 +// Located in Tile 228, Channel 1 +// Located in Tile 229, Channel 0 +// Located in Tile 229, Channel 2 +// Located in Tile 229, Channel 3 +// Located in Tile 229, Channel 1 +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/rf/common/Makefile.srcs b/top/x400/rf/common/Makefile.srcs index c3cae1c..b1ea271 100644 --- a/top/x400/rf/common/Makefile.srcs +++ b/top/x400/rf/common/Makefile.srcs @@ -6,6 +6,7 @@ RF_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/common/, \ PkgRf.vhd \ +adc_iq_repacker.v \ axis_mux.vhd \ capture_sysref.v \ gpio_to_axis_mux.vhd \ diff --git a/top/x400/rf/common/adc_iq_repacker.v b/top/x400/rf/common/adc_iq_repacker.v new file mode 100644 index 0000000..13e6802 --- /dev/null +++ b/top/x400/rf/common/adc_iq_repacker.v @@ -0,0 +1,115 @@ +// +// Copyright 2022 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: adc_iq_repacker +// +// Description: +// +// This component repacks IQ from independent vectors into a single +// output signal, and implements data swapping when requested. +// +// The parameters for this component describe the expected amount of +// data to be received as well as the data to be generated. +// +// - SPC = Samples per cycle: amount of samples to be expected +// on each I and Q input vector on each "clk" cycle. +// - SAMPLE_WIDTH = Amount of bits composing each sample +// +// This modules incurs in two clk cycles of delay on the data and valid +// signals from input to output. +// +// Example case : SPC = 2, SAMPLE_WIDTH = 16 +// +// adc_x_in size(for I and Q) = 2 x 16 = 32 +// adc_out size = 2 x 2 x 16 = 64 +// +// _______ _______ _______ ______ +// clk _| |_______| |_______| |_______| +// _ _______________ _______________ _______________ ______ +// adc_i_in _X_____I1,I0_____X_____I3,I2_____X____32{'X'}____X______ +// _ _______________ _______________ _______________ ______ +// adc_q_in _X_____Q1,Q0_____X_____Q3,Q2_____X____32{'X'}____X______ +// _______________________________ +// valid_in _| |______________________ +// _ _______________ _______________ _______________ ______ +// adc_out _X____64{'X'}____X____64{'X'}____X__Q1,I1,Q0,I0__X__Q3,.. +// ______________________ +// valid_out _________________________________| +// +// When the swap input is high, the order in which Q and I samples +// appear on the output vector is inverted +// +// _______ _______ _______ ______ +// clk _| |_______| |_______| |_______| +// _ _______________ _______________ _______________ ______ +// adc_i_in _X_____I1,I0_____X_____I3,I2_____X____32{'X'}____X______ +// _ _______________ _______________ _______________ ______ +// adc_q_in _X_____Q1,Q0_____X_____Q3,Q2_____X____32{'X'}____X______ +// _______________________________ +// valid_in _| |______________________ +// _ _______________ _______________ _______________ ______ +// adc_out _X____64{'X'}____X____64{'X'}____X__I1,Q1,I0,Q0__X__I3,.. +// ______________________ +// valid_out _________________________________| +// +// Parameters: +// SPC = Samples per cycle +// SAMPLE_WIDTH = width of i/q sample inputs. Output will be 2*SAMPLE_WIDTH +// + +module adc_iq_repacker #( + parameter SPC = 1, + parameter SAMPLE_WIDTH = 16 +) +( + input wire clk, + // Data in + input wire [SPC*SAMPLE_WIDTH-1:0] adc_q_in, + input wire [SPC*SAMPLE_WIDTH-1:0] adc_i_in, + input wire valid_in, + // This signal is currently driven in a related clock, and even though it runs at half the rate is should be fine + // to handle it in this clock domain(in nature it will also stay high one asserted until the next reset.) + input wire enable, + // Data is packed [Q,I] (I in LSBs) when swap_iq is '0', and [I,Q] otherwise + input wire swap_iq, + + // Data out + output reg [SPC*SAMPLE_WIDTH*2-1:0] data_out_tdata, + output reg data_out_tvalid + ); + + localparam IQ_WIDTH = SAMPLE_WIDTH*2; + + reg valid = 1'b0, valid_dly = 1'b0; + reg [SPC*SAMPLE_WIDTH-1:0] adc_q_data_in = {SPC*SAMPLE_WIDTH{1'b0}}; + reg [SPC*SAMPLE_WIDTH-1:0] adc_i_data_in = {SPC*SAMPLE_WIDTH{1'b0}}; + + integer sample_num; + + // It is safe to not reset this domain because all of the input signals will be cleared + // by a synchronous reset. Safe default values are assigned to all these registers. + always @(posedge clk) begin + adc_q_data_in <= adc_q_in; + adc_i_data_in <= adc_i_in; + // Place Q in the MSBs, I in the LSBs by default, unless swapped = 1. + for (sample_num=0; sample_num < (SPC); sample_num = sample_num + 1) + begin : data_out_gen + if (swap_iq) begin + data_out_tdata[sample_num*(IQ_WIDTH) +: IQ_WIDTH] <= + {adc_i_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH], + adc_q_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH]}; + end else begin + data_out_tdata[sample_num*(IQ_WIDTH) +: IQ_WIDTH] <= + {adc_q_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH], + adc_i_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH]}; + end + end + // Valid is simply a transferred version of the 1x clock's valid. Delay it one + // more cycle to align outputs. + valid <= valid_in && enable; + data_out_tvalid <= valid; + end + +endmodule diff --git a/top/x400/rf/full/Makefile.srcs b/top/x400/rf/full/Makefile.srcs new file mode 100644 index 0000000..db56ac3 --- /dev/null +++ b/top/x400/rf/full/Makefile.srcs @@ -0,0 +1,9 @@ +# +# Copyright 2023 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +RF_FULL_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/full/, \ +rf_core_full.v \ +)) diff --git a/top/x400/rf/full/rf_core_full.v b/top/x400/rf/full/rf_core_full.v new file mode 100644 index 0000000..b13afe4 --- /dev/null +++ b/top/x400/rf/full/rf_core_full.v @@ -0,0 +1,436 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rf_core_full +// +// Description: +// +// Top-level wrapper for the ADC/DAC processing logic. One of these wrappers +// exists for every supported Data Rate. An instance of this core should +// exist per dboard. +// +// Data/RF Specs: +// DBs: 1 +// RX/DB: 4 +// TX/DB: 4 +// Data Rate: rfdc_clk @ 8 SPC +// +// Input Clocks, all aligned to one another and coming from same MMCM +// rfdc_clk: 15.625 to 250 MHz +// rfdc_clk_2x: 2 * rfdc_clk +// + +`default_nettype none + +module rf_core_full # ( + parameter NUM_ADC_CHANNELS = 4, + parameter NUM_DAC_CHANNELS = 4 +) ( + + //--------------------------------------------------------------------------- + // Clocking + //--------------------------------------------------------------------------- + + // Main Clock Inputs + input wire rfdc_clk, + input wire rfdc_clk_2x, + + // AXI4-Lite Config Clock + // This clock is used to synchronize status bits for the RFDC + // registers in the AXI-S clock domain. + input wire s_axi_config_clk, + + + //--------------------------------------------------------------------------- + // RFDC Data Interfaces + //--------------------------------------------------------------------------- + // All ports here are in the rfdc_clk domain. + + // ADC + input wire [127:0] adc_data_in_i_tdata_0, + output wire adc_data_in_i_tready_0, + input wire adc_data_in_i_tvalid_0, + input wire [127:0] adc_data_in_q_tdata_0, + output wire adc_data_in_q_tready_0, + input wire adc_data_in_q_tvalid_0, + input wire [127:0] adc_data_in_i_tdata_1, + output wire adc_data_in_i_tready_1, + input wire adc_data_in_i_tvalid_1, + input wire [127:0] adc_data_in_q_tdata_1, + output wire adc_data_in_q_tready_1, + input wire adc_data_in_q_tvalid_1, + input wire [127:0] adc_data_in_i_tdata_2, + output wire adc_data_in_i_tready_2, + input wire adc_data_in_i_tvalid_2, + input wire [127:0] adc_data_in_q_tdata_2, + output wire adc_data_in_q_tready_2, + input wire adc_data_in_q_tvalid_2, + input wire [127:0] adc_data_in_i_tdata_3, + output wire adc_data_in_i_tready_3, + input wire adc_data_in_i_tvalid_3, + input wire [127:0] adc_data_in_q_tdata_3, + output wire adc_data_in_q_tready_3, + input wire adc_data_in_q_tvalid_3, + + + // DAC + output wire [255:0] dac_data_out_tdata_0, + input wire dac_data_out_tready_0, + output wire dac_data_out_tvalid_0, + output wire [255:0] dac_data_out_tdata_1, + input wire dac_data_out_tready_1, + output wire dac_data_out_tvalid_1, + output wire [255:0] dac_data_out_tdata_2, + input wire dac_data_out_tready_2, + output wire dac_data_out_tvalid_2, + output wire [255:0] dac_data_out_tdata_3, + input wire dac_data_out_tready_3, + output wire dac_data_out_tvalid_3, + + + //--------------------------------------------------------------------------- + // User Data Interfaces + //--------------------------------------------------------------------------- + // All ports here are in the rfdc_clk domain on the X440. + + // ADC + output wire [255:0] adc_data_out_tdata_0, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire adc_data_out_tvalid_0, + output wire [255:0] adc_data_out_tdata_1, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire adc_data_out_tvalid_1, + output wire [255:0] adc_data_out_tdata_2, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire adc_data_out_tvalid_2, + output wire [255:0] adc_data_out_tdata_3, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire adc_data_out_tvalid_3, + + // DAC + input wire [255:0] dac_data_in_tdata_0, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire dac_data_in_tready_0, + input wire dac_data_in_tvalid_0, + input wire [255:0] dac_data_in_tdata_1, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire dac_data_in_tready_1, + input wire dac_data_in_tvalid_1, + input wire [255:0] dac_data_in_tdata_2, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire dac_data_in_tready_2, + input wire dac_data_in_tvalid_2, + input wire [255:0] dac_data_in_tdata_3, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs + output wire dac_data_in_tready_3, + input wire dac_data_in_tvalid_3, + + //--------------------------------------------------------------------------- + // Miscellaneous + //--------------------------------------------------------------------------- + + // Invert I/Q control signals from RFDC to DSP chain. + input wire [3:0] invert_adc_iq_rclk2, + input wire [3:0] invert_dac_iq_rclk2, + + // Control/status vectors from/to RFDC. + // Notice these are all in the s_axi_config_clk domain. + output wire [9:0] dsp_info_sclk, + output wire [15:0] axi_status_sclk, + output wire [15:0] rfdc_info_sclk, + + // Resets. + input wire adc_enable_data_rclk, + input wire adc_rfdc_axi_resetn_rclk, + + // Version (Constant) + output wire [95:0] version_info +); + + `include "../../regmap/x440/rfdc_regs_regmap_utils.vh" + `include "../../regmap/x440/versioning_regs_regmap_utils.vh" + `include "../../regmap/versioning_utils.vh" + + // ADC data interface from RFDC. + wire [127:0] adc_data_in_i_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (I) + wire [127:0] adc_data_in_q_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (Q) + wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tready; + wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tready; + wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tvalid; + wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tvalid; + // DAC data interface to RFDC. + wire [255:0] dac_data_out_tdata [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q) + wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tready; + wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tvalid; + + // ADC data interface to user. + wire [255:0] adc_data_out_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (I + Q) + wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tready; + wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tvalid; + // DAC data interface from user. + wire [255:0] dac_data_in_tdata_preswap [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q) + wire [255:0] dac_data_in_tdata [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q) + wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tready; + wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tvalid; + + wire [15:0] axi_status; + + + //--------------------------------------------------------------------------- + // Resets, Debug and Misc. + //--------------------------------------------------------------------------- + + // Group all these status bits together. They don't toggle frequently so data + // coherency is not an issue here. + // Using constants for DB0 since the bits are the 16 LSBs in a 32-bit vector. + // DB1 simply uses the 16 MSBs when wiring the status vector. + assign axi_status[USER_ADC_TREADY_MSB :USER_ADC_TREADY ] = adc_data_out_tready[1:0]; + assign axi_status[USER_ADC_TVALID_MSB :USER_ADC_TVALID ] = adc_data_out_tvalid[1:0]; + assign axi_status[RFDC_ADC_I_TVALID_MSB:RFDC_ADC_I_TVALID] = adc_data_in_i_tvalid[1:0]; + assign axi_status[RFDC_ADC_Q_TVALID_MSB:RFDC_ADC_Q_TVALID] = adc_data_in_q_tvalid[1:0]; + assign axi_status[RFDC_ADC_I_TREADY_MSB:RFDC_ADC_I_TREADY] = adc_data_in_i_tready[1:0]; + assign axi_status[RFDC_ADC_Q_TREADY_MSB:RFDC_ADC_Q_TREADY] = adc_data_in_q_tready[1:0]; + assign axi_status[RFDC_DAC_TVALID_MSB :RFDC_DAC_TVALID ] = dac_data_out_tvalid[1:0]; + assign axi_status[RFDC_DAC_TREADY_MSB :RFDC_DAC_TREADY ] = dac_data_out_tready[1:0]; + + synchronizer #( + .WIDTH (16), + .STAGES (2), + .INITIAL_VAL (0), + .FALSE_PATH_TO_IN (1) + ) synchronizer_axis_status ( + .clk (s_axi_config_clk), + .rst (1'b0), + .in (axi_status), + .out (axi_status_sclk) + ); + + // Drive the DSP info vector with information on this specific DSP chain. + assign dsp_info_sclk[FABRIC_DSP_RX_CNT_MSB:FABRIC_DSP_RX_CNT] = NUM_ADC_CHANNELS; + assign dsp_info_sclk[FABRIC_DSP_TX_CNT_MSB:FABRIC_DSP_TX_CNT] = NUM_DAC_CHANNELS; + + // This RF core always consumes 8 SPC from the gearbox per I/Q signal + assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8); + assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16); + // This RF core module contains no additional resampling + assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd1; + + //--------------------------------------------------------------------------- + // ADC Post-Processing + //--------------------------------------------------------------------------- + + // Data comes from the RFDC as 8 SPC, separate streams for each channel and + // I/Q. + assign adc_data_in_i_tdata[0] = adc_data_in_i_tdata_0; + assign adc_data_in_q_tdata[0] = adc_data_in_q_tdata_0; + assign adc_data_in_i_tdata[1] = adc_data_in_i_tdata_1; + assign adc_data_in_q_tdata[1] = adc_data_in_q_tdata_1; + assign adc_data_in_i_tdata[2] = adc_data_in_i_tdata_2; + assign adc_data_in_q_tdata[2] = adc_data_in_q_tdata_2; + assign adc_data_in_i_tdata[3] = adc_data_in_i_tdata_3; + assign adc_data_in_q_tdata[3] = adc_data_in_q_tdata_3; + + assign adc_data_in_i_tready_0 = adc_data_in_i_tready[0]; + assign adc_data_in_i_tvalid[0] = adc_data_in_i_tvalid_0; + assign adc_data_in_q_tready_0 = adc_data_in_q_tready[0]; + assign adc_data_in_q_tvalid[0] = adc_data_in_q_tvalid_0; + assign adc_data_in_i_tready_1 = adc_data_in_i_tready[1]; + assign adc_data_in_i_tvalid[1] = adc_data_in_i_tvalid_1; + assign adc_data_in_q_tready_1 = adc_data_in_q_tready[1]; + assign adc_data_in_q_tvalid[1] = adc_data_in_q_tvalid_1; + assign adc_data_in_i_tready_2 = adc_data_in_i_tready[2]; + assign adc_data_in_i_tvalid[2] = adc_data_in_i_tvalid_2; + assign adc_data_in_q_tready_2 = adc_data_in_q_tready[2]; + assign adc_data_in_q_tvalid[2] = adc_data_in_q_tvalid_2; + assign adc_data_in_i_tready_3 = adc_data_in_i_tready[3]; + assign adc_data_in_i_tvalid[3] = adc_data_in_i_tvalid_3; + assign adc_data_in_q_tready_3 = adc_data_in_q_tready[3]; + assign adc_data_in_q_tvalid[3] = adc_data_in_q_tvalid_3; + + // ADC Data from the RFDC arrives here as 8 SPC with separate I and Q + // streams. It leaves the adc_full_rate_bd as 8 SPC with I and Q packed into + // a single 256 bit word. + genvar adc_num; + generate + for (adc_num=0; adc_num < (NUM_ADC_CHANNELS); adc_num = adc_num + 1) + begin : adc_gen + adc_full_bd adc_full_bd_gen ( + .enable_data_to_repacker_rclk (adc_enable_data_rclk), + .rfdc_adc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk), + .rfdc_clk (rfdc_clk), + .swap_iq_rclk (invert_adc_iq_rclk2 [adc_num]), + .adc_q_data_in_tvalid (adc_data_in_q_tvalid[adc_num]), + .adc_q_data_in_tready (adc_data_in_q_tready[adc_num]), + .adc_q_data_in_tdata (adc_data_in_q_tdata [adc_num]), + .adc_i_data_in_tvalid (adc_data_in_i_tvalid[adc_num]), + .adc_i_data_in_tready (adc_data_in_i_tready[adc_num]), + .adc_i_data_in_tdata (adc_data_in_i_tdata [adc_num]), + .adc_data_out_tvalid (adc_data_out_tvalid [adc_num]), + .adc_data_out_tdata (adc_data_out_tdata [adc_num]) + ); + end + endgenerate + + // Data is released to the user as 8 SPC, separate streams for each channel. + assign adc_data_out_tdata_0 = adc_data_out_tdata[0]; + assign adc_data_out_tdata_1 = adc_data_out_tdata[1]; + assign adc_data_out_tdata_2 = adc_data_out_tdata[2]; + assign adc_data_out_tdata_3 = adc_data_out_tdata[3]; + + // There is no tready going to the ADC (one has to be always ready for ADC + // data), but it is still a component of the axi_status vector as a generic + // AXI stream status. Report 1'b1 to the status vector consistent with being + // always ready + assign adc_data_out_tready[0] = 1'b1; + assign adc_data_out_tvalid_0 = adc_data_out_tvalid[0]; + assign adc_data_out_tready[1] = 1'b1; + assign adc_data_out_tvalid_1 = adc_data_out_tvalid[1]; + assign adc_data_out_tready[2] = 1'b1; + assign adc_data_out_tvalid_2 = adc_data_out_tvalid[2]; + assign adc_data_out_tready[3] = 1'b1; + assign adc_data_out_tvalid_3 = adc_data_out_tvalid[3]; + + //--------------------------------------------------------------------------- + // DAC Pre-Processing + //--------------------------------------------------------------------------- + + // Data comes from the user as 8 SPC, separate streams for each channel. + assign dac_data_in_tdata_preswap[0] = dac_data_in_tdata_0; + assign dac_data_in_tdata_preswap[1] = dac_data_in_tdata_1; + assign dac_data_in_tdata_preswap[2] = dac_data_in_tdata_2; + assign dac_data_in_tdata_preswap[3] = dac_data_in_tdata_3; + + assign dac_data_in_tready_0 = dac_data_in_tready[0]; + assign dac_data_in_tvalid[0] = dac_data_in_tvalid_0; + assign dac_data_in_tready_1 = dac_data_in_tready[1]; + assign dac_data_in_tvalid[1] = dac_data_in_tvalid_1; + assign dac_data_in_tready_2 = dac_data_in_tready[2]; + assign dac_data_in_tvalid[2] = dac_data_in_tvalid_2; + assign dac_data_in_tready_3 = dac_data_in_tready[3]; + assign dac_data_in_tvalid[3] = dac_data_in_tvalid_3; + + genvar dac_num; + generate + for (dac_num=0; dac_num < (NUM_DAC_CHANNELS); dac_num = dac_num + 1) + begin : dac_swap_gen + //IO and Q0 swap + assign dac_data_in_tdata[dac_num][15:00] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][31:16]) : (dac_data_in_tdata_preswap[dac_num][15:0]); + assign dac_data_in_tdata[dac_num][31:16] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][15:00]) : (dac_data_in_tdata_preswap[dac_num][31:16]); + + //I1 and Q1 swap + assign dac_data_in_tdata[dac_num][47:32] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][63:48]) : (dac_data_in_tdata_preswap[dac_num][47:32]); + assign dac_data_in_tdata[dac_num][63:48] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][47:32]) : (dac_data_in_tdata_preswap[dac_num][63:48]); + + //I2 and Q2 swap + assign dac_data_in_tdata[dac_num][79:64] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][95:80]) : (dac_data_in_tdata_preswap[dac_num][79:64]); + assign dac_data_in_tdata[dac_num][95:80] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][79:64]) : (dac_data_in_tdata_preswap[dac_num][95:80]); + + //I3 and Q3 swap + assign dac_data_in_tdata[dac_num][111:96] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][127:112]) : (dac_data_in_tdata_preswap[dac_num][111:96]); + assign dac_data_in_tdata[dac_num][127:112] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][111:96]) : (dac_data_in_tdata_preswap[dac_num][127:112]); + + //I4 and Q4 swap + assign dac_data_in_tdata[dac_num][143:128] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][159:144]) : (dac_data_in_tdata_preswap[dac_num][143:128]); + assign dac_data_in_tdata[dac_num][159:144] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][143:128]) : (dac_data_in_tdata_preswap[dac_num][159:144]); + + //I5 and Q5 swap + assign dac_data_in_tdata[dac_num][175:160] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][191:176]) : (dac_data_in_tdata_preswap[dac_num][175:160]); + assign dac_data_in_tdata[dac_num][191:176] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][175:160]) : (dac_data_in_tdata_preswap[dac_num][191:176]); + + //I6 and Q6 swap + assign dac_data_in_tdata[dac_num][207:192] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][223:208]) : (dac_data_in_tdata_preswap[dac_num][207:192]); + assign dac_data_in_tdata[dac_num][223:208] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][207:192]) : (dac_data_in_tdata_preswap[dac_num][223:208]); + + //I7 and Q7 swap + assign dac_data_in_tdata[dac_num][239:224] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][255:240]) : (dac_data_in_tdata_preswap[dac_num][239:224]); + assign dac_data_in_tdata[dac_num][255:240] = invert_dac_iq_rclk2[dac_num] ? + (dac_data_in_tdata_preswap[dac_num][239:224]) : (dac_data_in_tdata_preswap[dac_num][255:240]); + + end + endgenerate + + // These streams are then connected to data out, no need for a bd, and form a single + // stream per channel, 8 SPC, packed: MSB [Sample7Q, Sample7I, ... , + // Sample0Q, Sample0I] LSB. + generate + for (dac_num=0; dac_num < (NUM_DAC_CHANNELS); dac_num = dac_num + 1) + begin : dac_gen + assign dac_data_out_tdata[dac_num] = dac_data_in_tdata[dac_num]; + assign dac_data_out_tvalid[dac_num] = dac_data_in_tvalid[dac_num]; + assign dac_data_in_tready[dac_num] = dac_data_out_tready[dac_num]; + end + endgenerate + + // Data is released to the RFDC as 8 SPC, separate streams per channel (I/Q + // together). + assign dac_data_out_tdata_0 = dac_data_out_tdata[0]; + assign dac_data_out_tdata_1 = dac_data_out_tdata[1]; + assign dac_data_out_tdata_2 = dac_data_out_tdata[2]; + assign dac_data_out_tdata_3 = dac_data_out_tdata[3]; + + assign dac_data_out_tready[0] = dac_data_out_tready_0; + assign dac_data_out_tvalid_0 = dac_data_out_tvalid[0]; + assign dac_data_out_tready[1] = dac_data_out_tready_1; + assign dac_data_out_tvalid_1 = dac_data_out_tvalid[1]; + assign dac_data_out_tready[2] = dac_data_out_tready_2; + assign dac_data_out_tvalid_2 = dac_data_out_tvalid[2]; + assign dac_data_out_tready[3] = dac_data_out_tready_3; + assign dac_data_out_tvalid_3 = dac_data_out_tvalid[3]; + + + //--------------------------------------------------------------------------- + // Version + //--------------------------------------------------------------------------- + + // Version metadata, constants come from auto-generated + // versioning_regs_regmap_utils.vh + assign version_info = build_component_versions( + RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME, + build_version( + RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR, + RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR, + RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD + ), + build_version( + RF_CORE_FULL_CURRENT_VERSION_MAJOR, + RF_CORE_FULL_CURRENT_VERSION_MINOR, + RF_CORE_FULL_CURRENT_VERSION_BUILD + ) + ); + +endmodule + +`default_nettype wire + +//XmlParse xml_on +// +// +// +// +// Full BW RF core.{BR/} +// For guidance on when to update these revision numbers, +// please refer to the register map documentation accordingly: +//
  • Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION +//
  • Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION +//
  • Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED +// +// +// +// +// +// +// +// +// +// +// +//XmlParse xml_off diff --git a/top/x400/rf/sim/Makefile b/top/x400/rf/sim/Makefile index ce1a4d7..63c7e92 100644 --- a/top/x400/rf/sim/Makefile +++ b/top/x400/rf/sim/Makefile @@ -80,6 +80,7 @@ $(abspath tb_ddc_400m_saturate.vhd ) \ $(abspath tb_duc_400m_saturate.vhd ) \ $(abspath tb_rf_nco_reset.vhd ) \ $(abspath tb_x410_rf_reset_controller.vhd ) \ +$(abspath tb_adc_iq_repacker.sv ) \ $(abspath rf_all_tb.sv ) \ #------------------------------------------------- diff --git a/top/x400/rf/sim/rf_all_tb.sv b/top/x400/rf/sim/rf_all_tb.sv index 5ddfb71..3ae7ad4 100644 --- a/top/x400/rf/sim/rf_all_tb.sv +++ b/top/x400/rf/sim/rf_all_tb.sv @@ -26,6 +26,7 @@ module rf_all_tb; tb_duc_400m_saturate tb_duc_400m_saturate_i (); tb_rf_nco_reset tb_rf_nco_reset_i (); tb_x410_rf_reset_controller tb_x410_rf_reset_controller_i (); + tb_adc_iq_repacker tb_adc_iq_repacker_i (); initial begin test.start_tb("rf_all_tb", 1ms); @@ -44,7 +45,8 @@ module rf_all_tb; tb_ddc_400m_saturate_i.StopSim && tb_duc_400m_saturate_i.StopSim && tb_rf_nco_reset_i.StopSim && - tb_x410_rf_reset_controller_i.StopSim + tb_x410_rf_reset_controller_i.StopSim && + tb_adc_iq_repacker_i.StopSim ) break; end test.end_test(); diff --git a/top/x400/rf/sim/tb_adc_iq_repacker.sv b/top/x400/rf/sim/tb_adc_iq_repacker.sv new file mode 100644 index 0000000..17b0bc7 --- /dev/null +++ b/top/x400/rf/sim/tb_adc_iq_repacker.sv @@ -0,0 +1,109 @@ +// +// Copyright 2022 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: tb_adc_iq_repacker +// +// Description: +// +// This testbench mainly tests tb_adc_iq_repacker. It runs +// 3 different tests: +// - test data propagation when not swapping data +// - test data propagation when swapping data +// - check that data valid does not propagate when block +// is not enabled. +// + +`timescale 1ns/1ps +`define NS_PER_TICK 1 +`define NUM_TEST_CASES 3 + +`include "sim_clks_rsts.vh" +`include "sim_exec_report.vh" + +module tb_adc_iq_repacker(); + import PkgRandom::*; + + `TEST_BENCH_INIT("tb_adc_iq_repacker", `NUM_TEST_CASES, `NS_PER_TICK); + //sets up clock + localparam CLK_PERIOD = $ceil(1e9/100.0e6); + `DEFINE_CLK(clk, CLK_PERIOD, 50); + //declare parameters + localparam SPC = 1; + localparam SAMPLE_WIDTH = 16; + + //declare wires and regs + + reg enable; + reg valid_in; + reg swap_iq; + reg [SPC*SAMPLE_WIDTH-1:0] adc_q_in; + reg [SPC*SAMPLE_WIDTH-1:0] adc_i_in; + reg StopSim; + + wire [SPC*SAMPLE_WIDTH*2-1:0] data_out_tdata; + wire data_out_tvalid; + + PkgRandom::Rand #(SPC*SAMPLE_WIDTH) rand_i; + PkgRandom::Rand #(SPC*SAMPLE_WIDTH) rand_q; + + // instance adc_iq_repacker + adc_iq_repacker #( + .SPC(SPC), + .SAMPLE_WIDTH(SAMPLE_WIDTH) + ) adc_iq_repacker_inst ( + .clk(clk), + // Data in + .adc_q_in(adc_q_in), + .adc_i_in(adc_i_in), + .valid_in(valid_in), + .enable(enable), + // Data is packed [Q,I] (I in LSBs) when swap_iq is '0', and [I,Q] otherwise + .swap_iq(swap_iq), + // Data out + .data_out_tdata(data_out_tdata), + .data_out_tvalid(data_out_tvalid) + ); + + + // initial statement with test cases + initial begin : tb_main + + // test data propagation when not swapping data + `TEST_CASE_START("test data propagation, no swap, core enabled"); + repeat (10) @(posedge clk); + swap_iq = 0; + enable = 1; + StopSim = 0; + valid_in = 1; + for (int i = 0; i < 10; i++) begin + adc_q_in = rand_q.rand_bit(); + adc_i_in = rand_i.rand_bit(); + repeat (3) @(posedge clk); + `ASSERT_ERROR(data_out_tdata[SAMPLE_WIDTH*2-1:0] == {adc_q_in[SAMPLE_WIDTH-1:0], adc_i_in[SAMPLE_WIDTH-1:0]}, "Output data is wrong"); + `ASSERT_ERROR(data_out_tvalid == 1, "output valid not asserted"); + end + `TEST_CASE_DONE(1); + // test data propagation when swapping data + `TEST_CASE_START("test data propagation w/ swap_iq=1"); + swap_iq = 1; + for (int i = 0; i < 10; i++) begin + adc_q_in = rand_q.rand_bit(); + adc_i_in = rand_i.rand_bit(); + repeat (3) @(posedge clk); + `ASSERT_ERROR(data_out_tdata[SAMPLE_WIDTH*2-1:0] == {adc_i_in[SAMPLE_WIDTH-1:0], adc_q_in[SAMPLE_WIDTH-1:0]}, "Output data is wrong"); + `ASSERT_ERROR(data_out_tvalid == 1, "output valid not asserted"); + end + `TEST_CASE_DONE(1); + // check that data valid does not propagate when block + // is not enabled. + `TEST_CASE_START("test data valid when enable = 0"); + enable = 0; + repeat (10) @(posedge clk); + `ASSERT_ERROR(data_out_tvalid == 0, "block should be disabled"); + `TEST_CASE_DONE(1); + StopSim = 1; + + end +endmodule : tb_adc_iq_repacker diff --git a/top/x400/rf/sim/xvhdl.pb b/top/x400/rf/sim/xvhdl.pb new file mode 100644 index 0000000..56b5e19 Binary files /dev/null and b/top/x400/rf/sim/xvhdl.pb differ diff --git a/top/x400/rf/common/clock_gates.vhd b/top/x400/rf/x440/x440_clock_gates.vhd similarity index 69% rename from top/x400/rf/common/clock_gates.vhd rename to top/x400/rf/x440/x440_clock_gates.vhd index c4df28d..326fc2f 100644 --- a/top/x400/rf/common/clock_gates.vhd +++ b/top/x400/rf/x440/x440_clock_gates.vhd @@ -1,13 +1,13 @@ -- --- Copyright 2021 Ettus Research, a National Instruments Brand +-- Copyright 2022 Ettus Research, a National Instruments Brand -- -- SPDX-License-Identifier: LGPL-3.0-or-later -- --- Module: clock_gates +-- Module: x440_clock_gates -- -- Description: -- --- Gate propagation of DataClk and RfdcClk instances until the PLL lock +-- Gate propagation of RfdcClk instances until the PLL lock -- status signal is stable and software has acknowledged it by asserting the -- pertinent controls. -- @@ -16,9 +16,10 @@ -- explicitly instantiated in the Block Design. Therefore, we only generate -- the buffer enable signals for these clocks within this component. -- --- Since DataClk are only used in other Custom IP blocks within the Block --- design, it is possible to instantiate the clock buffers within this block --- for without running into IP generation failures. +-- This file heavily leverages the code from '../x410/x410_clock_gates.vhd'. +-- The main changes when comparing against that file are: +-- - One RFDC Clock pair per radio. +-- - No DataClk buffer instantiations (since DataClk is removed from BD). -- -- Parameters: -- @@ -36,7 +37,7 @@ library WORK; use WORK.PkgRFDC_REGS_REGMAP.all; -entity clock_gates is +entity x440_clock_gates is generic ( kReliableClkPeriodNs : integer := 25 ); @@ -51,18 +52,14 @@ entity clock_gates is -- Input Clocks (from MMCM) ReliableClk : in std_logic; - DataClk1xPll : in std_logic; - DataClk2xPll : in std_logic; - - -- Buffered Clock Outputs (to design) - DataClk1x : out std_logic; - DataClk2x : out std_logic; -- Buffers for these signals must be instantiated on Block design for clock -- rates to be identified. The Utility Buffers instantiated on the Block -- Design require signals to be of type std_logic_vector. - aEnableRfBufg1x : out std_logic_vector(0 downto 0); - aEnableRfBufg2x : out std_logic_vector(0 downto 0); + aEnableRf0Bufg1x : out std_logic_vector(0 downto 0); + aEnableRf0Bufg2x : out std_logic_vector(0 downto 0); + aEnableRf1Bufg1x : out std_logic_vector(0 downto 0); + aEnableRf1Bufg2x : out std_logic_vector(0 downto 0); -- PLL Status Signals rPllLocked : out std_logic; @@ -75,9 +72,9 @@ entity clock_gates is rSoftwareControl : in std_logic_vector(31 downto 0); rSoftwareStatus : out std_logic_vector(31 downto 0) ); -end clock_gates; +end x440_clock_gates; -architecture STRUCT of clock_gates is +architecture STRUCT of x440_clock_gates is component sync_wrapper generic ( @@ -92,15 +89,6 @@ architecture STRUCT of clock_gates is signal_out : out std_logic_vector((WIDTH-1) downto 0)); end component; - component BUFGCE - generic( - CE_TYPE : string); - port ( - O : out std_ulogic; - CE : in std_ulogic; - I : in std_ulogic); - end component; - -- UltraScale MMCM max lock time = 100 us / 25 ns = 4,000 clk cycles. If the -- division kPllLockTimeNs / kReliableClkPeriodNs does not evaluate to an -- integer, Vivado could either round up or down. In case they round down, we @@ -126,15 +114,15 @@ architecture STRUCT of clock_gates is signal rPllUnlockedSticky : std_logic := '0'; -- Safe BUFG enable signals - signal rEnableDataClk1x, - rEnableDataClk2x, - rEnableRfdcClk1x, - rEnableRfdcClk2x : std_logic; + signal rEnableRfdc0Clk1x, + rEnableRfdc0Clk2x, + rEnableRfdc1Clk1x, + rEnableRfdc1Clk2x : std_logic; - signal rEnableDataBufg1x : std_logic := '0'; - signal rEnableDataBufg2x : std_logic := '0'; - signal rEnableRfdcBufg1xLcl : std_logic := '0'; - signal rEnableRfdcBufg2xLcl : std_logic := '0'; + signal rEnableRfdc0Bufg1xLcl : std_logic := '0'; + signal rEnableRfdc0Bufg2xLcl : std_logic := '0'; + signal rEnableRfdc1Bufg1xLcl : std_logic := '0'; + signal rEnableRfdc1Bufg2xLcl : std_logic := '0'; -- Active high version of reset required for synchronizer blocks. signal rPllReset : std_logic; @@ -143,18 +131,10 @@ architecture STRUCT of clock_gates is -- a dont_touch attribute to preserve the signals through both synthesis and -- P&R. Implementation of "dont_touch" has been confirmed after P&R. attribute dont_touch : string; - attribute dont_touch of rEnableDataBufg1x : signal is "TRUE"; - attribute dont_touch of rEnableDataBufg2x : signal is "TRUE"; - attribute dont_touch of aEnableRfBufg1x : signal is "TRUE"; - attribute dont_touch of aEnableRfBufg2x : signal is "TRUE"; - - attribute X_INTERFACE_INFO : string; - attribute X_INTERFACE_PARAMETER : string; - - attribute X_INTERFACE_INFO of DataClk1xPll : signal is - "xilinx.com:signal:clock:1.0 DataClk1xPll CLK"; - attribute X_INTERFACE_INFO of DataClk2xPll : signal is - "xilinx.com:signal:clock:1.0 DataClk2xPll CLK"; + attribute dont_touch of aEnableRf0Bufg1x : signal is "TRUE"; + attribute dont_touch of aEnableRf0Bufg2x : signal is "TRUE"; + attribute dont_touch of aEnableRf1Bufg1x : signal is "TRUE"; + attribute dont_touch of aEnableRf1Bufg2x : signal is "TRUE"; begin @@ -168,57 +148,38 @@ begin begin if rising_edge(ReliableClk) then if rPllReset_n = '0' then - rEnableDataBufg1x <= '0'; - rEnableDataBufg2x <= '0'; - rEnableRfdcBufg1xLcl <= '0'; - rEnableRfdcBufg2xLcl <= '0'; + rEnableRfdc0Bufg1xLcl <= '0'; + rEnableRfdc0Bufg2xLcl <= '0'; + rEnableRfdc1Bufg1xLcl <= '0'; + rEnableRfdc1Bufg2xLcl <= '0'; else - rEnableDataBufg1x <= + rEnableRfdc0Bufg1xLcl <= rSafeToEnableGatedClks and - rEnableDataClk1x and + rEnableRfdc0Clk1x and (not rPllUnlockedSticky); - rEnableDataBufg2x <= + rEnableRfdc0Bufg2xLcl <= rSafeToEnableGatedClks and - rEnableDataClk2x and + rEnableRfdc0Clk2x and (not rPllUnlockedSticky); - rEnableRfdcBufg1xLcl <= + rEnableRfdc1Bufg1xLcl <= rSafeToEnableGatedClks and - rEnableRfdcClk1x and + rEnableRfdc1Clk1x and (not rPllUnlockedSticky); - rEnableRfdcBufg2xLcl <= + rEnableRfdc1Bufg2xLcl <= rSafeToEnableGatedClks and - rEnableRfdcClk2x and + rEnableRfdc1Clk2x and (not rPllUnlockedSticky); end if; end if; end process DataClkEnables; - aEnableRfBufg1x(0) <= rEnableRfdcBufg1xLcl; - aEnableRfBufg2x(0) <= rEnableRfdcBufg2xLcl; - - DataClk1xSafeBufg: BUFGCE - generic map( - CE_TYPE => "ASYNC" - ) - port map ( - I => DataClk1xPll, - CE => rEnableDataBufg1x, - O => DataClk1x - ); - - DataClk2xSafeBufg: BUFGCE - generic map( - CE_TYPE => "ASYNC" - ) - port map ( - I => DataClk2xPll, - CE => rEnableDataBufg2x, - O => DataClk2x - ); - + aEnableRf0Bufg1x(0) <= rEnableRfdc0Bufg1xLcl; + aEnableRf0Bufg2x(0) <= rEnableRfdc0Bufg2xLcl; + aEnableRf1Bufg1x(0) <= rEnableRfdc1Bufg1xLcl; + aEnableRf1Bufg2x(0) <= rEnableRfdc1Bufg2xLcl; ----------------------------------------------------------------------------- -- Create PLL Lock Signal @@ -288,11 +249,11 @@ begin rPllLocked <= rPllLockedLcl; -- AXI transaction decoding - rClearDataClkUnlockedSticky <= rSoftwareControl(kCLEAR_DATA_CLK_UNLOCKED); - rEnableDataClk1x <= rSoftwareControl(kENABLE_DATA_CLK); - rEnableDataClk2x <= rSoftwareControl(kENABLE_DATA_CLK_2X); - rEnableRfdcClk1x <= rSoftwareControl(kENABLE_RF_CLK); - rEnableRfdcClk2x <= rSoftwareControl(kENABLE_RF_CLK_2X); + rClearDataClkUnlockedSticky <= rSoftwareControl(kCLEAR_DATA_CLK_UNLOCKED); + rEnableRfdc0Clk1x <= rSoftwareControl(kENABLE_RF0_CLK); + rEnableRfdc0Clk2x <= rSoftwareControl(kENABLE_RF0_CLK_2X); + rEnableRfdc1Clk1x <= rSoftwareControl(kENABLE_RF1_CLK); + rEnableRfdc1Clk2x <= rSoftwareControl(kENABLE_RF1_CLK_2X); rSoftwareStatus(kDATA_CLK_PLL_LOCKED) <= rPllLockedLcl; rSoftwareStatus(kDATA_CLK_PLL_UNLOCKED_STICKY) <= rPllUnlockedSticky; diff --git a/top/x400/rf/common/rf_reset_controller.vhd b/top/x400/rf/x440/x440_rf_reset_controller.vhd similarity index 61% rename from top/x400/rf/common/rf_reset_controller.vhd rename to top/x400/rf/x440/x440_rf_reset_controller.vhd index d69228a..754d99a 100644 --- a/top/x400/rf/common/rf_reset_controller.vhd +++ b/top/x400/rf/x440/x440_rf_reset_controller.vhd @@ -1,13 +1,18 @@ -- --- Copyright 2021 Ettus Research, a National Instruments Brand +-- Copyright 2022 Ettus Research, a National Instruments Brand -- -- SPDX-License-Identifier: LGPL-3.0-or-later -- --- Module: rf_reset_controller +-- Module: x440_rf_reset_controller -- -- Description: -- -- Control RFDC, ADC, and DAC resets. +-- This file contains a similar structure to '../x410/x410_rf_reset_controller', +-- with the main difference of not having to support a complex reset chain. +-- This means that the instantiations of 'rf_reset' can be taken out in favor +-- having a simple combination of the incoming pulses and the software triggers +-- to generate the different outputs. -- library IEEE; @@ -17,45 +22,38 @@ library IEEE; library WORK; use WORK.PkgRFDC_REGS_REGMAP.all; -entity rf_reset_controller is +entity x440_rf_reset_controller is port( -- Clocks -- Config clock is async to all the others. ConfigClk : in std_logic; - DataClk : in std_logic; PllRefClk : in std_logic; RfClk : in std_logic; RfClk2x : in std_logic; - DataClk2x : in std_logic; -- Master resets from the Radio - dAdcResetPulse : in std_logic; - dDacResetPulse : in std_logic; + rAdcResetPulse : in std_logic; + rDacResetPulse : in std_logic; -- ADC Resets - dAdcDataOutReset_n : out std_logic; - r2AdcFirReset_n : out std_logic; - rAdcRfdcAxiReset_n : out std_logic; + r2AdcReset_n : out std_logic; rAdcEnableData : out std_logic; - rAdcGearboxReset_n : out std_logic; + rAdcReset_n : out std_logic; -- DAC Resets - dDacDataInReset_n : out std_logic; - r2DacFirReset_n : out std_logic; - d2DacFirReset_n : out std_logic; - rDacRfdcAxiReset_n : out std_logic; - rDacGearboxReset_n : out std_logic; + r2DacReset_n : out std_logic; + rDacReset_n : out std_logic; -- SW Control and Status - -- Control to initiate resets to RFDC and decimation block including the - -- gearboxes. The reset status is a sticky status of both ADC and DAC. + -- Control to initiate resets to RFDC. + -- The reset status is a sticky status of both ADC and DAC. cSoftwareControl : in std_logic_vector(31 downto 0); cSoftwareStatus : out std_logic_vector(31 downto 0) ); -end rf_reset_controller; +end x440_rf_reset_controller; -architecture RTL of rf_reset_controller is +architecture RTL of x440_rf_reset_controller is -- POR value for all resets are high. signal cTriggerAdcReset : std_logic := '1'; @@ -63,10 +61,10 @@ architecture RTL of rf_reset_controller is signal cTriggerDacReset : std_logic := '1'; signal cTriggerDacResetDlyd : std_logic := '1'; - signal dTriggerAdcReset_ms : std_logic := '1'; - signal dTriggerAdcReset : std_logic := '1'; - signal dTriggerDacReset_ms : std_logic := '1'; - signal dTriggerDacReset : std_logic := '1'; + signal rTriggerAdcReset_ms : std_logic := '1'; + signal rTriggerAdcReset : std_logic := '1'; + signal rTriggerDacReset_ms : std_logic := '1'; + signal rTriggerDacReset : std_logic := '1'; -- POR value of all reset done signals are set to low. signal cTriggerAdcResetDone_ms : std_logic := '0'; @@ -77,12 +75,12 @@ architecture RTL of rf_reset_controller is signal cDacResetDoneSticky : std_logic := '0'; attribute ASYNC_REG : string; - attribute ASYNC_REG of dTriggerAdcReset : signal is "TRUE"; - attribute ASYNC_REG of dTriggerDacReset : signal is "TRUE"; + attribute ASYNC_REG of rTriggerAdcReset : signal is "TRUE"; + attribute ASYNC_REG of rTriggerDacReset : signal is "TRUE"; attribute ASYNC_REG of cTriggerAdcResetDone : signal is "TRUE"; attribute ASYNC_REG of cTriggerDacResetDone : signal is "TRUE"; - attribute ASYNC_REG of dTriggerAdcReset_ms : signal is "TRUE"; - attribute ASYNC_REG of dTriggerDacReset_ms : signal is "TRUE"; + attribute ASYNC_REG of rTriggerAdcReset_ms : signal is "TRUE"; + attribute ASYNC_REG of rTriggerDacReset_ms : signal is "TRUE"; attribute ASYNC_REG of cTriggerAdcResetDone_ms : signal is "TRUE"; attribute ASYNC_REG of cTriggerDacResetDone_ms : signal is "TRUE"; @@ -108,14 +106,14 @@ begin -- prove all your clocks are toggling to some extent. ----------------------------------------------------------------------------- - SeqResetDataClk : process(DataClk) + SeqResetRfClk : process(RfClk) begin - if rising_edge(DataClk) then + if rising_edge(RfClk) then -- double-syncs have no sync reset! - dTriggerAdcReset_ms <= cTriggerAdcReset; - dTriggerAdcReset <= dTriggerAdcReset_ms; - dTriggerDacReset_ms <= cTriggerDacReset; - dTriggerDacReset <= dTriggerDacReset_ms; + rTriggerAdcReset_ms <= cTriggerAdcReset; + rTriggerAdcReset <= rTriggerAdcReset_ms; + rTriggerDacReset_ms <= cTriggerDacReset; + rTriggerDacReset <= rTriggerDacReset_ms; end if; end process; @@ -123,18 +121,18 @@ begin -- Reset Sequence Done Status ----------------------------------------------------------------------------- -- Now back to ConfigClk! We provide the status for all software controlled - -- resets. We move the signal from ConfigClk to DataClk domain and move it - -- back to ConfigClk domain. This just proves that DataClk is toggling and - -- the reset requested by software is sampled in the DataClk. + -- resets. We move the signal from ConfigClk to RfClk domain and move it + -- back to ConfigClk domain. This just proves that RfClk is toggling and + -- the reset requested by software is sampled in the RfClk. ----------------------------------------------------------------------------- SeqResetDone : process(ConfigClk) begin if rising_edge(ConfigClk) then -- double-syncs have no sync reset! - cTriggerAdcResetDone_ms <= dTriggerAdcReset; + cTriggerAdcResetDone_ms <= rTriggerAdcReset; cTriggerAdcResetDone <= cTriggerAdcResetDone_ms; - cTriggerDacResetDone_ms <= dTriggerDacReset; + cTriggerDacResetDone_ms <= rTriggerDacReset; cTriggerDacResetDone <= cTriggerDacResetDone_ms; end if; end process; @@ -172,37 +170,20 @@ begin ----------------------------------------------------------------------------- -- rf_reset Instances ----------------------------------------------------------------------------- + RfClkResets: process(RfClk) + begin + if rising_edge(RfClk) then + rAdcReset_n <= not (rAdcResetPulse or rTriggerAdcReset); + rDacReset_n <= not (rDacResetPulse or rTriggerDacReset); + end if; + end process RfClkResets; - AdcResets: entity work.rf_reset (RTL) - port map ( - DataClk => DataClk, - PllRefClk => PllRefClk, - RfClk => RfClk, - RfClk2x => RfClk2x, - DataClk2x => DataClk2x, - dTimedReset => dAdcResetPulse, - dSwReset => dTriggerAdcReset, - dReset_n => dAdcDataOutReset_n, - d2Reset_n => open, - r2Reset_n => r2AdcFirReset_n, - rAxiReset_n => rAdcRfdcAxiReset_n, - rReset_n => rAdcGearboxReset_n - ); - - DacResets: entity work.rf_reset (RTL) - port map ( - DataClk => DataClk, - PllRefClk => PllRefClk, - RfClk => RfClk, - RfClk2x => RfClk2x, - DataClk2x => DataClk2x, - dTimedReset => dDacResetPulse, - dSwReset => dTriggerDacReset, - dReset_n => dDacDataInReset_n, - d2Reset_n => d2DacFirReset_n, - r2Reset_n => r2DacFirReset_n, - rAxiReset_n => rDacRfdcAxiReset_n, - rReset_n => rDacGearboxReset_n - ); + RfClk2xResets: process(RfClk2x) + begin + if rising_edge(RfClk2x) then + r2AdcReset_n <= not (rAdcResetPulse or rTriggerAdcReset); + r2DacReset_n <= not (rDacResetPulse or rTriggerDacReset); + end if; + end process RfClk2xResets; end RTL; diff --git a/top/x400/rf/x440/x440_rfdc_tx_control_remap.v b/top/x400/rf/x440/x440_rfdc_tx_control_remap.v new file mode 100644 index 0000000..a857696 --- /dev/null +++ b/top/x400/rf/x440/x440_rfdc_tx_control_remap.v @@ -0,0 +1,35 @@ +// +// Copyright 2022 Ettus Research, A National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: x440_rfdc_tx_control_remap.v +// Description: +// Allows for remapping control signals to the correct tile on X440. +// This file targets the DAC tiles specifically +// + +`default_nettype none + +module x440_rfdc_tx_control_remap ( + // Input control (Front-Panel ordering) + input wire [7:0] input_controls, + // output_control (DAC Tile ordering) + output wire [7:0] output_controls +); + + `include "../../regmap/x440/rfdc_mapping_regmap_utils.vh" + + // Decode TX Channel mapping + assign output_controls[CH0_TX_MAPPING] = input_controls[0]; + assign output_controls[CH1_TX_MAPPING] = input_controls[1]; + assign output_controls[CH2_TX_MAPPING] = input_controls[2]; + assign output_controls[CH3_TX_MAPPING] = input_controls[3]; + assign output_controls[CH4_TX_MAPPING] = input_controls[4]; + assign output_controls[CH5_TX_MAPPING] = input_controls[5]; + assign output_controls[CH6_TX_MAPPING] = input_controls[6]; + assign output_controls[CH7_TX_MAPPING] = input_controls[7]; + +endmodule + +`default_nettype wire diff --git a/top/x400/setupenv.sh b/top/x400/setupenv.sh index 3030cee..cdcf519 100644 --- a/top/x400/setupenv.sh +++ b/top/x400/setupenv.sh @@ -12,6 +12,7 @@ REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) declare -A PRODUCT_ID_MAP PRODUCT_ID_MAP["X410"]="zynquplusRFSOC/xczu28dr/ffvg1517/-1/e" +PRODUCT_ID_MAP["X440"]="zynquplusRFSOC/xczu28dr/ffvg1517/-2/e" # Set default part for simulation export ARCH=zynquplusRFSOC diff --git a/top/x400/x410_400_128_static_router.hex b/top/x400/x410_400_128_static_router.hex deleted file mode 100644 index d9d6460..0000000 --- a/top/x400/x410_400_128_static_router.hex +++ /dev/null @@ -1,17 +0,0 @@ -00000010 -00400240 -02400040 -00800241 -02410080 -00c00280 -028000c0 -01000281 -02810100 -014002c0 -02c00140 -018002c1 -02c10180 -01c002c2 -02c201c0 -020002c3 -02c30200 diff --git a/top/x400/x440_1600_d_rfnoc_image_core.v b/top/x400/x440_1600_d_rfnoc_image_core.v new file mode 100644 index 0000000..714e257 --- /dev/null +++ b/top/x400/x440_1600_d_rfnoc_image_core.v @@ -0,0 +1,1126 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rfnoc_image_core (for x440) +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// Source: x440_1600_d_rfnoc_image_core.yml +// + +`default_nettype none + + +module rfnoc_image_core #( + parameter [31:0] CHDR_W = 512, + parameter [31:0] PORT_W = 512, + parameter [31:0] ETH0_W = 64, + parameter [31:0] ETH1_W = 64, + parameter [31:0] ETH2_W = 64, + parameter [31:0] ETH3_W = 64, + parameter [31:0] ETH4_W = 64, + parameter [31:0] DMA_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio0_clk, + input wire radio1_clk, + input wire radio0_2x_clk, + input wire radio1_2x_clk, + input wire dram_clk, + // Basic + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // ctrlport_radio1 + output wire [ 0:0] m_ctrlport_radio1_req_wr, + output wire [ 0:0] m_ctrlport_radio1_req_rd, + output wire [ 19:0] m_ctrlport_radio1_req_addr, + output wire [ 31:0] m_ctrlport_radio1_req_data, + output wire [ 3:0] m_ctrlport_radio1_req_byte_en, + output wire [ 0:0] m_ctrlport_radio1_req_has_time, + output wire [ 63:0] m_ctrlport_radio1_req_time, + input wire [ 0:0] m_ctrlport_radio1_resp_ack, + input wire [ 1:0] m_ctrlport_radio1_resp_status, + input wire [ 31:0] m_ctrlport_radio1_resp_data, + // time0 + input wire [ 63:0] radio_time0, + // time1 + input wire [ 63:0] radio_time1, + // radio0 + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, + // radio1 + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, + // dram + input wire [ 0:0] axi_rst, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [PORT_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [PORT_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [PORT_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [PORT_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (eth2) + input wire [PORT_W-1:0] s_eth2_tdata, + input wire s_eth2_tlast, + input wire s_eth2_tvalid, + output wire s_eth2_tready, + output wire [PORT_W-1:0] m_eth2_tdata, + output wire m_eth2_tlast, + output wire m_eth2_tvalid, + input wire m_eth2_tready, + // Transport 3 (eth3) + input wire [PORT_W-1:0] s_eth3_tdata, + input wire s_eth3_tlast, + input wire s_eth3_tvalid, + output wire s_eth3_tready, + output wire [PORT_W-1:0] m_eth3_tdata, + output wire m_eth3_tlast, + output wire m_eth3_tvalid, + input wire m_eth3_tready, + // Transport 4 (eth4) + input wire [PORT_W-1:0] s_eth4_tdata, + input wire s_eth4_tlast, + input wire s_eth4_tvalid, + output wire s_eth4_tready, + output wire [PORT_W-1:0] m_eth4_tdata, + output wire m_eth4_tlast, + output wire m_eth4_tvalid, + input wire m_eth4_tready, + // Transport 5 (dma) + input wire [PORT_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [PORT_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + localparam BLOCK_CHDR_W = 512; + localparam BYTE_MTU = MTU + $clog2(CHDR_W/8); + localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8); + localparam EP0_W = 512; + localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8); + localparam EP1_W = 512; + localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8); + localparam EP2_W = 512; + localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8); + localparam EP3_W = 512; + localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8); + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + + //--------------------------------------------------------------------------- + // CHDR Crossbar + //--------------------------------------------------------------------------- + + wire [PORT_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [PORT_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [PORT_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [PORT_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [PORT_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + + chdr_crossbar_nxn #( + .PORT_W (PORT_W), + .NPORTS (10), + .CHDR_WIDTHS ({EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}), + .DEFAULT_PORT (0), + .ROUTES ({ 10'b0011101111, + 10'b0011101111, + 10'b1100101111, + 10'b1100101111, + 10'b1111100000, + 10'b0000000000, + 10'b1111001000, + 10'b1111000100, + 10'b1111000010, + 10'b1111000001 }), + .BYTE_MTU (BYTE_MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (6), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_crossbar_nxn_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , {PORT_W{1'b0}}, s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , 1'b0, s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }), + .s_axis_tvalid ({ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, 1'b0, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, 1'bZ, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , {PORT_W{1'bZ}}, m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , 1'bZ, m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }), + .m_axis_tvalid ({xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, 1'bZ, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, 1'b1, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + + //--------------------------------------------------------------------------- + // Stream Endpoints + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 2048; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); + + wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP0_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), + .MTU (EP0_MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 2048; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + + wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP1_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), + .MTU (EP1_MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP2 = 2048; + localparam INGRESS_BUFF_SIZE_EP2 = + REQ_BUFF_SIZE_EP2 == 0 ? 5 : + REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP2); + + wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; + wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP2_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), + .MTU (EP2_MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep2_tdata), + .s_axis_chdr_tlast (xb_to_ep2_tlast), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid), + .s_axis_chdr_tready (xb_to_ep2_tready), + .m_axis_chdr_tdata (ep2_to_xb_tdata), + .m_axis_chdr_tlast (ep2_to_xb_tlast), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid), + .m_axis_chdr_tready (ep2_to_xb_tready), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP3 = 2048; + localparam INGRESS_BUFF_SIZE_EP3 = + REQ_BUFF_SIZE_EP3 == 0 ? 5 : + REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP3); + + wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; + wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP3_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), + .MTU (EP3_MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep3_tdata), + .s_axis_chdr_tlast (xb_to_ep3_tlast), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid), + .s_axis_chdr_tready (xb_to_ep3_tready), + .m_axis_chdr_tdata (ep3_to_xb_tdata), + .m_axis_chdr_tlast (ep3_to_xb_tlast), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid), + .m_axis_chdr_tready (ep3_to_xb_tready), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + + //--------------------------------------------------------------------------- + // Control Crossbar + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata; + wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_replay0_ctrl_tdata, s_replay0_ctrl_tdata; + wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast; + wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; + wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (5), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + + //--------------------------------------------------------------------------- + // RFNoC Core Kernel + //--------------------------------------------------------------------------- + + wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'hA400), + .DEVICE_FAMILY ("ULTRASCALE"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (3), + .NUM_STREAM_ENDPOINTS(4), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (6), + .NUM_EDGES (8), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + + //--------------------------------------------------------------------------- + // Blocks + //--------------------------------------------------------------------------- + + //----------------------------------- + // radio0 + //----------------------------------- + + wire radio0_radio_clk; + wire [BLOCK_CHDR_W-1:0] s_radio0_in_0_tdata ; + wire s_radio0_in_0_tlast ; + wire s_radio0_in_0_tvalid; + wire s_radio0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio0_out_0_tdata ; + wire m_radio0_out_0_tlast ; + wire m_radio0_out_0_tvalid; + wire m_radio0_out_0_tready; + + // ctrlport + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time + wire [ 63:0] radio0_radio_time; + // radio + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID (2), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (1), + .NIPC (RADIO_NIPC), + .ITEM_W (32), + .MTU (BLOCK_MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) + ); + + //----------------------------------- + // radio1 + //----------------------------------- + + wire radio1_radio_clk; + wire [BLOCK_CHDR_W-1:0] s_radio1_in_0_tdata ; + wire s_radio1_in_0_tlast ; + wire s_radio1_in_0_tvalid; + wire s_radio1_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio1_out_0_tdata ; + wire m_radio1_out_0_tlast ; + wire m_radio1_out_0_tvalid; + wire m_radio1_out_0_tready; + + // ctrlport + wire [ 0:0] radio1_m_ctrlport_req_wr; + wire [ 0:0] radio1_m_ctrlport_req_rd; + wire [ 19:0] radio1_m_ctrlport_req_addr; + wire [ 31:0] radio1_m_ctrlport_req_data; + wire [ 3:0] radio1_m_ctrlport_req_byte_en; + wire [ 0:0] radio1_m_ctrlport_req_has_time; + wire [ 63:0] radio1_m_ctrlport_req_time; + wire [ 0:0] radio1_m_ctrlport_resp_ack; + wire [ 1:0] radio1_m_ctrlport_resp_status; + wire [ 31:0] radio1_m_ctrlport_resp_data; + // time + wire [ 63:0] radio1_radio_time; + // radio + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID (3), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (1), + .NIPC (RADIO_NIPC), + .ITEM_W (32), + .MTU (BLOCK_MTU) + ) b_radio1_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time (radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time (radio1_radio_time), + .radio_rx_data (radio1_radio_rx_data), + .radio_rx_stb (radio1_radio_rx_stb), + .radio_rx_running (radio1_radio_rx_running), + .radio_tx_data (radio1_radio_tx_data), + .radio_tx_stb (radio1_radio_tx_stb), + .radio_tx_running (radio1_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) + ); + + //----------------------------------- + // replay0 + //----------------------------------- + + wire replay0_mem_clk; + wire [BLOCK_CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; + wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; + wire s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; + wire s_replay0_in_1_tready, s_replay0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_replay0_out_1_tdata , m_replay0_out_0_tdata ; + wire m_replay0_out_1_tlast , m_replay0_out_0_tlast ; + wire m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; + wire m_replay0_out_1_tready, m_replay0_out_0_tready; + + // axi_ram + wire [ 0:0] replay0_axi_rst; + wire [ 7:0] replay0_m_axi_awid; + wire [ 383:0] replay0_m_axi_awaddr; + wire [ 63:0] replay0_m_axi_awlen; + wire [ 23:0] replay0_m_axi_awsize; + wire [ 15:0] replay0_m_axi_awburst; + wire [ 7:0] replay0_m_axi_awlock; + wire [ 31:0] replay0_m_axi_awcache; + wire [ 23:0] replay0_m_axi_awprot; + wire [ 31:0] replay0_m_axi_awqos; + wire [ 31:0] replay0_m_axi_awregion; + wire [ 7:0] replay0_m_axi_awuser; + wire [ 7:0] replay0_m_axi_awvalid; + wire [ 7:0] replay0_m_axi_awready; + wire [4191:0] replay0_m_axi_wdata; + wire [ 511:0] replay0_m_axi_wstrb; + wire [ 7:0] replay0_m_axi_wlast; + wire [ 7:0] replay0_m_axi_wuser; + wire [ 7:0] replay0_m_axi_wvalid; + wire [ 7:0] replay0_m_axi_wready; + wire [ 7:0] replay0_m_axi_bid; + wire [ 15:0] replay0_m_axi_bresp; + wire [ 7:0] replay0_m_axi_buser; + wire [ 7:0] replay0_m_axi_bvalid; + wire [ 7:0] replay0_m_axi_bready; + wire [ 7:0] replay0_m_axi_arid; + wire [ 383:0] replay0_m_axi_araddr; + wire [ 63:0] replay0_m_axi_arlen; + wire [ 23:0] replay0_m_axi_arsize; + wire [ 15:0] replay0_m_axi_arburst; + wire [ 7:0] replay0_m_axi_arlock; + wire [ 31:0] replay0_m_axi_arcache; + wire [ 31:0] replay0_m_axi_arprot; + wire [ 31:0] replay0_m_axi_arqos; + wire [ 31:0] replay0_m_axi_arregion; + wire [ 7:0] replay0_m_axi_aruser; + wire [ 7:0] replay0_m_axi_arvalid; + wire [ 7:0] replay0_m_axi_arready; + wire [ 7:0] replay0_m_axi_rid; + wire [4191:0] replay0_m_axi_rdata; + wire [ 15:0] replay0_m_axi_rresp; + wire [ 7:0] replay0_m_axi_rlast; + wire [ 7:0] replay0_m_axi_ruser; + wire [ 7:0] replay0_m_axi_rvalid; + wire [ 7:0] replay0_m_axi_rready; + + rfnoc_block_replay #( + .THIS_PORTID (4), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (2), + .MEM_DATA_W (512), + .MEM_ADDR_W (32), + .MTU (BLOCK_MTU) + ) b_replay0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk (replay0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + .axi_rst (replay0_axi_rst), + .m_axi_awid (replay0_m_axi_awid), + .m_axi_awaddr (replay0_m_axi_awaddr), + .m_axi_awlen (replay0_m_axi_awlen), + .m_axi_awsize (replay0_m_axi_awsize), + .m_axi_awburst (replay0_m_axi_awburst), + .m_axi_awlock (replay0_m_axi_awlock), + .m_axi_awcache (replay0_m_axi_awcache), + .m_axi_awprot (replay0_m_axi_awprot), + .m_axi_awqos (replay0_m_axi_awqos), + .m_axi_awregion (replay0_m_axi_awregion), + .m_axi_awuser (replay0_m_axi_awuser), + .m_axi_awvalid (replay0_m_axi_awvalid), + .m_axi_awready (replay0_m_axi_awready), + .m_axi_wdata (replay0_m_axi_wdata), + .m_axi_wstrb (replay0_m_axi_wstrb), + .m_axi_wlast (replay0_m_axi_wlast), + .m_axi_wuser (replay0_m_axi_wuser), + .m_axi_wvalid (replay0_m_axi_wvalid), + .m_axi_wready (replay0_m_axi_wready), + .m_axi_bid (replay0_m_axi_bid), + .m_axi_bresp (replay0_m_axi_bresp), + .m_axi_buser (replay0_m_axi_buser), + .m_axi_bvalid (replay0_m_axi_bvalid), + .m_axi_bready (replay0_m_axi_bready), + .m_axi_arid (replay0_m_axi_arid), + .m_axi_araddr (replay0_m_axi_araddr), + .m_axi_arlen (replay0_m_axi_arlen), + .m_axi_arsize (replay0_m_axi_arsize), + .m_axi_arburst (replay0_m_axi_arburst), + .m_axi_arlock (replay0_m_axi_arlock), + .m_axi_arcache (replay0_m_axi_arcache), + .m_axi_arprot (replay0_m_axi_arprot), + .m_axi_arqos (replay0_m_axi_arqos), + .m_axi_arregion (replay0_m_axi_arregion), + .m_axi_aruser (replay0_m_axi_aruser), + .m_axi_arvalid (replay0_m_axi_arvalid), + .m_axi_arready (replay0_m_axi_arready), + .m_axi_rid (replay0_m_axi_rid), + .m_axi_rdata (replay0_m_axi_rdata), + .m_axi_rresp (replay0_m_axi_rresp), + .m_axi_rlast (replay0_m_axi_rlast), + .m_axi_ruser (replay0_m_axi_ruser), + .m_axi_rvalid (replay0_m_axi_rvalid), + .m_axi_rready (replay0_m_axi_rready), + .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_replay0_in_1_tready, s_replay0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_replay0_out_1_tdata , m_replay0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_replay0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) + ); + + //--------------------------------------------------------------------------- + // Static Router + //--------------------------------------------------------------------------- + + assign s_radio0_in_0_tdata = m_ep0_out0_tdata; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast; + assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_radio0_in_0_tready; + + assign s_ep0_in0_tdata = m_radio0_out_0_tdata; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast; + assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ep0_in0_tready; + + assign s_radio1_in_0_tdata = m_ep1_out0_tdata; + assign s_radio1_in_0_tlast = m_ep1_out0_tlast; + assign s_radio1_in_0_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio1_in_0_tready; + + assign s_ep1_in0_tdata = m_radio1_out_0_tdata; + assign s_ep1_in0_tlast = m_radio1_out_0_tlast; + assign s_ep1_in0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ep1_in0_tready; + + assign s_replay0_in_0_tdata = m_ep2_out0_tdata; + assign s_replay0_in_0_tlast = m_ep2_out0_tlast; + assign s_replay0_in_0_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_replay0_in_0_tready; + + assign s_ep2_in0_tdata = m_replay0_out_0_tdata; + assign s_ep2_in0_tlast = m_replay0_out_0_tlast; + assign s_ep2_in0_tvalid = m_replay0_out_0_tvalid; + assign m_replay0_out_0_tready = s_ep2_in0_tready; + + assign s_replay0_in_1_tdata = m_ep3_out0_tdata; + assign s_replay0_in_1_tlast = m_ep3_out0_tlast; + assign s_replay0_in_1_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_replay0_in_1_tready; + + assign s_ep3_in0_tdata = m_replay0_out_1_tdata; + assign s_ep3_in0_tlast = m_replay0_out_1_tlast; + assign s_ep3_in0_tvalid = m_replay0_out_1_tvalid; + assign m_replay0_out_1_tready = s_ep3_in0_tready; + + + //--------------------------------------------------------------------------- + // Unused Ports + //--------------------------------------------------------------------------- + + + + //--------------------------------------------------------------------------- + // Clock Domains + //--------------------------------------------------------------------------- + + assign radio0_radio_clk = radio0_clk; + assign radio1_radio_clk = radio1_clk; + assign replay0_mem_clk = dram_clk; + + + //--------------------------------------------------------------------------- + // IO Port Connection + //--------------------------------------------------------------------------- + + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + assign replay0_axi_rst = axi_rst; + assign m_axi_awid = replay0_m_axi_awid; + assign m_axi_awaddr = replay0_m_axi_awaddr; + assign m_axi_awlen = replay0_m_axi_awlen; + assign m_axi_awsize = replay0_m_axi_awsize; + assign m_axi_awburst = replay0_m_axi_awburst; + assign m_axi_awlock = replay0_m_axi_awlock; + assign m_axi_awcache = replay0_m_axi_awcache; + assign m_axi_awprot = replay0_m_axi_awprot; + assign m_axi_awqos = replay0_m_axi_awqos; + assign m_axi_awregion = replay0_m_axi_awregion; + assign m_axi_awuser = replay0_m_axi_awuser; + assign m_axi_awvalid = replay0_m_axi_awvalid; + assign replay0_m_axi_awready = m_axi_awready; + assign m_axi_wdata = replay0_m_axi_wdata; + assign m_axi_wstrb = replay0_m_axi_wstrb; + assign m_axi_wlast = replay0_m_axi_wlast; + assign m_axi_wuser = replay0_m_axi_wuser; + assign m_axi_wvalid = replay0_m_axi_wvalid; + assign replay0_m_axi_wready = m_axi_wready; + assign replay0_m_axi_bid = m_axi_bid; + assign replay0_m_axi_bresp = m_axi_bresp; + assign replay0_m_axi_buser = m_axi_buser; + assign replay0_m_axi_bvalid = m_axi_bvalid; + assign m_axi_bready = replay0_m_axi_bready; + assign m_axi_arid = replay0_m_axi_arid; + assign m_axi_araddr = replay0_m_axi_araddr; + assign m_axi_arlen = replay0_m_axi_arlen; + assign m_axi_arsize = replay0_m_axi_arsize; + assign m_axi_arburst = replay0_m_axi_arburst; + assign m_axi_arlock = replay0_m_axi_arlock; + assign m_axi_arcache = replay0_m_axi_arcache; + assign m_axi_arprot = replay0_m_axi_arprot; + assign m_axi_arqos = replay0_m_axi_arqos; + assign m_axi_arregion = replay0_m_axi_arregion; + assign m_axi_aruser = replay0_m_axi_aruser; + assign m_axi_arvalid = replay0_m_axi_arvalid; + assign replay0_m_axi_arready = m_axi_arready; + assign replay0_m_axi_rid = m_axi_rid; + assign replay0_m_axi_rdata = m_axi_rdata; + assign replay0_m_axi_rresp = m_axi_rresp; + assign replay0_m_axi_rlast = m_axi_rlast; + assign replay0_m_axi_ruser = m_axi_ruser; + assign replay0_m_axi_rvalid = m_axi_rvalid; + assign m_axi_rready = replay0_m_axi_rready; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time0; + + assign radio1_radio_time = radio_time1; + +endmodule + + +`default_nettype wire diff --git a/top/x400/x440_1600_d_rfnoc_image_core.vh b/top/x400/x440_1600_d_rfnoc_image_core.vh new file mode 100644 index 0000000..abd810e --- /dev/null +++ b/top/x400/x440_1600_d_rfnoc_image_core.vh @@ -0,0 +1,19 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Header: rfnoc_image_core.vh (for x440) +// +// Description: +// +// This is the header file for the RFNoC Image Core. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// Source: x440_1600_d_rfnoc_image_core.yml +// + +`define CHDR_WIDTH 512 +`define RFNOC_PROTOVER { 8'd1, 8'd0 } diff --git a/top/x400/x410_400_128_rfnoc_image_core.yml b/top/x400/x440_1600_d_rfnoc_image_core.yml similarity index 55% rename from top/x400/x410_400_128_rfnoc_image_core.yml rename to top/x400/x440_1600_d_rfnoc_image_core.yml index aa8d8c5..f15ea3e 100644 --- a/top/x400/x410_400_128_rfnoc_image_core.yml +++ b/top/x400/x440_1600_d_rfnoc_image_core.yml @@ -6,10 +6,10 @@ copyright: >- # Copyright information used in file hea license: >- # License information used in file headers SPDX-License-Identifier: LGPL-3.0-or-later version: '1.0' # File version -chdr_width: 128 # Bit width of the CHDR bus for this image -device: 'x410' # USRP type -image_core_name: 'x410_400_128' # Name to use for the RFNoC Image Core files -default_target: 'X410_X4_400' # Default make target +chdr_width: 512 # Bit width of the CHDR bus for this image +device: 'x440' # USRP type +image_core_name: 'x440_1600_d' # Name to use for the RFNoC Image Core files +default_target: 'X440_X4_1600' # Default make target # A list of all stream endpoints in design # ---------------------------------------- @@ -17,35 +17,37 @@ stream_endpoints: ep0: # Stream endpoint name ctrl: True # Endpoint passes control traffic data: True # Endpoint passes data traffic - buff_size_bytes: 32768 # Stream endpoint buffer size + buff_size_bytes: 131072 # Ingress buffer size for data ep1: ctrl: False data: True - buff_size_bytes: 32768 + buff_size_bytes: 131072 ep2: ctrl: False data: True - buff_size_bytes: 32768 + buff_size_bytes: 131072 ep3: ctrl: False data: True - buff_size_bytes: 32768 - ep4: - ctrl: False - data: True - buff_size_bytes: 32768 - ep5: - ctrl: False - data: True - buff_size_bytes: 32768 - ep6: - ctrl: False - data: True - buff_size_bytes: 32768 - ep7: - ctrl: False - data: True - buff_size_bytes: 32768 + buff_size_bytes: 131072 + +# A table of which crossbar routes to include +# ------------------------------------------- +# Rows correspond to input ports and columns correspond to output ports. +# Entering a 1 includes and a 0 removes that route from the crossbar. +crossbar_routes: + # eth0 eth2 eth4 ep0 ep2 + # eth1 eth3 dma ep1 ep3 + - [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0) + - [ 0, 1, 0, 0, 0, 0, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1) + - [ 0, 0, 1, 0, 0, 0, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2) + - [ 0, 0, 0, 1, 0, 0, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3) + - [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth4 (NC) + - [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1 ] # dma + - [ 1, 1, 1, 1, 0, 1, 0, 0, 1, 1 ] # ep0 (radio0.0) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 1, 1 ] # ep1 (radio1.0) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 0, 0 ] # ep2 (replay0.0) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 0, 0 ] # ep3 (replay0.1) # A list of all NoC blocks in design # ---------------------------------- @@ -53,18 +55,18 @@ noc_blocks: radio0: block_desc: 'radio.yml' parameters: - NUM_PORTS: 2 + NUM_PORTS: 1 NIPC: RADIO_NIPC radio1: block_desc: 'radio.yml' parameters: - NUM_PORTS: 2 + NUM_PORTS: 1 NIPC: RADIO_NIPC replay0: block_desc: 'replay.yml' parameters: - NUM_PORTS: 4 - MEM_DATA_W: 128 + NUM_PORTS: 2 + MEM_DATA_W: 512 MEM_ADDR_W: 32 # A list of all static connections in design @@ -74,52 +76,41 @@ noc_blocks: # - srcport = Port on the source block to connect # - dstblk = Destination block to connect # - dstport = Port on the destination block to connect +# connections: # RF A:0 TX - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } # RF A:0 RX - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } - # RF A:1 TX - - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } - # RF A:1 RX - - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } # # RF B:0 TX - - { srcblk: ep2, srcport: out0, dstblk: radio1, dstport: in_0 } + - { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 } # RF B:0 RX - - { srcblk: radio1, srcport: out_0, dstblk: ep2, dstport: in0 } - # RF B:1 TX - - { srcblk: ep3, srcport: out0, dstblk: radio1, dstport: in_1 } - # RF B:1 RX - - { srcblk: radio1, srcport: out_1, dstblk: ep3, dstport: in0 } + - { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 } # # Replay Connections - - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 } - - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 } - - { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 } - - { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 } - - { srcblk: ep6, srcport: out0, dstblk: replay0, dstport: in_2 } - - { srcblk: replay0, srcport: out_2, dstblk: ep6, dstport: in0 } - - { srcblk: ep7, srcport: out0, dstblk: replay0, dstport: in_3 } - - { srcblk: replay0, srcport: out_3, dstblk: ep7, dstport: in0 } + - { srcblk: ep2, srcport: out0, dstblk: replay0, dstport: in_0 } + - { srcblk: replay0, srcport: out_0, dstblk: ep2, dstport: in0 } + - { srcblk: ep3, srcport: out0, dstblk: replay0, dstport: in_1 } + - { srcblk: replay0, srcport: out_1, dstblk: ep3, dstport: in0 } # # BSP Connections - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } - - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } - - { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time } + - { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time } - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } # A list of all clock domain connections in design # ------------------------------------------------ # Format: A list of connection maps (list of key-value pairs) with the following keys -# - srcblk = Source block to connect (Always "_device_") +# - srcblk = Source block to connect (Always "_device"_) # - srcport = Clock domain on the source block to connect # - dstblk = Destination block to connect # - dstport = Clock domain on the destination block to connect clk_domains: - - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } - - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } - - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } diff --git a/top/x400/x440_1600_d_static_router.hex b/top/x400/x440_1600_d_static_router.hex new file mode 100644 index 0000000..3bf392b --- /dev/null +++ b/top/x400/x440_1600_d_static_router.hex @@ -0,0 +1,9 @@ +00000008 +00400140 +01400040 +00800180 +01800080 +00c001c0 +01c000c0 +010001c1 +01c10100 diff --git a/top/x400/x440_1600_rfnoc_image_core.v b/top/x400/x440_1600_rfnoc_image_core.v new file mode 100644 index 0000000..dcc5c1b --- /dev/null +++ b/top/x400/x440_1600_rfnoc_image_core.v @@ -0,0 +1,754 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rfnoc_image_core (for x440) +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// Source: x440_1600_rfnoc_image_core.yml +// + +`default_nettype none + + +module rfnoc_image_core #( + parameter [31:0] CHDR_W = 512, + parameter [31:0] PORT_W = 512, + parameter [31:0] ETH0_W = 64, + parameter [31:0] ETH1_W = 64, + parameter [31:0] ETH2_W = 64, + parameter [31:0] ETH3_W = 64, + parameter [31:0] ETH4_W = 64, + parameter [31:0] DMA_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio0_clk, + input wire radio1_clk, + input wire radio0_2x_clk, + input wire radio1_2x_clk, + input wire dram_clk, + // Basic + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // ctrlport_radio1 + output wire [ 0:0] m_ctrlport_radio1_req_wr, + output wire [ 0:0] m_ctrlport_radio1_req_rd, + output wire [ 19:0] m_ctrlport_radio1_req_addr, + output wire [ 31:0] m_ctrlport_radio1_req_data, + output wire [ 3:0] m_ctrlport_radio1_req_byte_en, + output wire [ 0:0] m_ctrlport_radio1_req_has_time, + output wire [ 63:0] m_ctrlport_radio1_req_time, + input wire [ 0:0] m_ctrlport_radio1_resp_ack, + input wire [ 1:0] m_ctrlport_radio1_resp_status, + input wire [ 31:0] m_ctrlport_radio1_resp_data, + // time0 + input wire [ 63:0] radio_time0, + // time1 + input wire [ 63:0] radio_time1, + // radio0 + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, + // radio1 + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, + // dram + input wire [ 0:0] axi_rst, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [PORT_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [PORT_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [PORT_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [PORT_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (eth2) + input wire [PORT_W-1:0] s_eth2_tdata, + input wire s_eth2_tlast, + input wire s_eth2_tvalid, + output wire s_eth2_tready, + output wire [PORT_W-1:0] m_eth2_tdata, + output wire m_eth2_tlast, + output wire m_eth2_tvalid, + input wire m_eth2_tready, + // Transport 3 (eth3) + input wire [PORT_W-1:0] s_eth3_tdata, + input wire s_eth3_tlast, + input wire s_eth3_tvalid, + output wire s_eth3_tready, + output wire [PORT_W-1:0] m_eth3_tdata, + output wire m_eth3_tlast, + output wire m_eth3_tvalid, + input wire m_eth3_tready, + // Transport 4 (eth4) + input wire [PORT_W-1:0] s_eth4_tdata, + input wire s_eth4_tlast, + input wire s_eth4_tvalid, + output wire s_eth4_tready, + output wire [PORT_W-1:0] m_eth4_tdata, + output wire m_eth4_tlast, + output wire m_eth4_tvalid, + input wire m_eth4_tready, + // Transport 5 (dma) + input wire [PORT_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [PORT_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + localparam BLOCK_CHDR_W = 512; + localparam BYTE_MTU = MTU + $clog2(CHDR_W/8); + localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8); + localparam EP0_W = 512; + localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8); + localparam EP1_W = 512; + localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8); + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + + //--------------------------------------------------------------------------- + // CHDR Crossbar + //--------------------------------------------------------------------------- + + wire [PORT_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [PORT_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [PORT_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + + chdr_crossbar_nxn #( + .PORT_W (PORT_W), + .NPORTS (8), + .CHDR_WIDTHS ({EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}), + .DEFAULT_PORT (0), + .ROUTES ({ 8'b00110001, + 8'b00110001, + 8'b11100000, + 8'b11010000, + 8'b00000000, + 8'b00000000, + 8'b00000000, + 8'b11000001 }), + .BYTE_MTU (BYTE_MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (6), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_crossbar_nxn_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , {PORT_W{1'b0}}, {PORT_W{1'b0}}, {PORT_W{1'b0}}, s_eth0_tdata }), + .s_axis_tlast ({ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , 1'b0, 1'b0, 1'b0, s_eth0_tlast }), + .s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, 1'b0, 1'b0, 1'b0, s_eth0_tvalid}), + .s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, 1'bZ, 1'bZ, 1'bZ, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , {PORT_W{1'bZ}}, {PORT_W{1'bZ}}, {PORT_W{1'bZ}}, m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , 1'bZ, 1'bZ, 1'bZ, m_eth0_tlast }), + .m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, 1'bZ, 1'bZ, 1'bZ, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, 1'b1, 1'b1, 1'b1, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + + //--------------------------------------------------------------------------- + // Stream Endpoints + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 32768; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); + + wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP0_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), + .MTU (EP0_MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 32768; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + + wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP1_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), + .MTU (EP1_MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + + //--------------------------------------------------------------------------- + // Control Crossbar + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata; + wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (4), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + + //--------------------------------------------------------------------------- + // RFNoC Core Kernel + //--------------------------------------------------------------------------- + + wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'hA400), + .DEVICE_FAMILY ("ULTRASCALE"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (2), + .NUM_STREAM_ENDPOINTS(2), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (6), + .NUM_EDGES (4), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + + //--------------------------------------------------------------------------- + // Blocks + //--------------------------------------------------------------------------- + + //----------------------------------- + // radio0 + //----------------------------------- + + wire radio0_radio_clk; + wire [BLOCK_CHDR_W-1:0] s_radio0_in_0_tdata ; + wire s_radio0_in_0_tlast ; + wire s_radio0_in_0_tvalid; + wire s_radio0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio0_out_0_tdata ; + wire m_radio0_out_0_tlast ; + wire m_radio0_out_0_tvalid; + wire m_radio0_out_0_tready; + + // ctrlport + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time + wire [ 63:0] radio0_radio_time; + // radio + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID (2), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (1), + .NIPC (RADIO_NIPC), + .ITEM_W (32), + .MTU (BLOCK_MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) + ); + + //----------------------------------- + // radio1 + //----------------------------------- + + wire radio1_radio_clk; + wire [BLOCK_CHDR_W-1:0] s_radio1_in_0_tdata ; + wire s_radio1_in_0_tlast ; + wire s_radio1_in_0_tvalid; + wire s_radio1_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio1_out_0_tdata ; + wire m_radio1_out_0_tlast ; + wire m_radio1_out_0_tvalid; + wire m_radio1_out_0_tready; + + // ctrlport + wire [ 0:0] radio1_m_ctrlport_req_wr; + wire [ 0:0] radio1_m_ctrlport_req_rd; + wire [ 19:0] radio1_m_ctrlport_req_addr; + wire [ 31:0] radio1_m_ctrlport_req_data; + wire [ 3:0] radio1_m_ctrlport_req_byte_en; + wire [ 0:0] radio1_m_ctrlport_req_has_time; + wire [ 63:0] radio1_m_ctrlport_req_time; + wire [ 0:0] radio1_m_ctrlport_resp_ack; + wire [ 1:0] radio1_m_ctrlport_resp_status; + wire [ 31:0] radio1_m_ctrlport_resp_data; + // time + wire [ 63:0] radio1_radio_time; + // radio + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID (3), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (1), + .NIPC (RADIO_NIPC), + .ITEM_W (32), + .MTU (BLOCK_MTU) + ) b_radio1_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time (radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time (radio1_radio_time), + .radio_rx_data (radio1_radio_rx_data), + .radio_rx_stb (radio1_radio_rx_stb), + .radio_rx_running (radio1_radio_rx_running), + .radio_tx_data (radio1_radio_tx_data), + .radio_tx_stb (radio1_radio_tx_stb), + .radio_tx_running (radio1_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) + ); + + //--------------------------------------------------------------------------- + // Static Router + //--------------------------------------------------------------------------- + + assign s_radio0_in_0_tdata = m_ep0_out0_tdata; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast; + assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_radio0_in_0_tready; + + assign s_ep0_in0_tdata = m_radio0_out_0_tdata; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast; + assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ep0_in0_tready; + + assign s_radio1_in_0_tdata = m_ep1_out0_tdata; + assign s_radio1_in_0_tlast = m_ep1_out0_tlast; + assign s_radio1_in_0_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio1_in_0_tready; + + assign s_ep1_in0_tdata = m_radio1_out_0_tdata; + assign s_ep1_in0_tlast = m_radio1_out_0_tlast; + assign s_ep1_in0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ep1_in0_tready; + + + //--------------------------------------------------------------------------- + // Unused Ports + //--------------------------------------------------------------------------- + + + + //--------------------------------------------------------------------------- + // Clock Domains + //--------------------------------------------------------------------------- + + assign radio0_radio_clk = radio0_clk; + assign radio1_radio_clk = radio1_clk; + + + //--------------------------------------------------------------------------- + // IO Port Connection + //--------------------------------------------------------------------------- + + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time0; + + assign radio1_radio_time = radio_time1; + +endmodule + + +`default_nettype wire diff --git a/top/x400/x440_1600_rfnoc_image_core.vh b/top/x400/x440_1600_rfnoc_image_core.vh new file mode 100644 index 0000000..8c2fbc1 --- /dev/null +++ b/top/x400/x440_1600_rfnoc_image_core.vh @@ -0,0 +1,19 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Header: rfnoc_image_core.vh (for x440) +// +// Description: +// +// This is the header file for the RFNoC Image Core. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// Source: x440_1600_rfnoc_image_core.yml +// + +`define CHDR_WIDTH 512 +`define RFNOC_PROTOVER { 8'd1, 8'd0 } diff --git a/top/x400/x440_1600_rfnoc_image_core.yml b/top/x400/x440_1600_rfnoc_image_core.yml new file mode 100644 index 0000000..f6cb9a9 --- /dev/null +++ b/top/x400/x440_1600_rfnoc_image_core.yml @@ -0,0 +1,91 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: >- # Copyright information used in file headers + Copyright 2023 Ettus Research, a National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later +version: '1.0' # File version +chdr_width: 512 # Bit width of the CHDR bus for this image +device: 'x440' # USRP type +image_core_name: 'x440_1600' # Name to use for the RFNoC Image Core files +default_target: 'X440_CG_1600' # Default make target + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size_bytes: 2097152 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size_bytes: 2097152 + +# A table of which crossbar routes to include +# ------------------------------------------- +# Rows correspond to input ports and columns correspond to output ports. +# Entering a 1 includes and a 0 removes that route from the crossbar. +crossbar_routes: + # eth0 eth2 eth4 ep0 + # eth1 eth3 dma ep1 + - [ 1, 0, 0, 0, 0, 0, 1, 1 ] # eth0 (QSFP Port 0) + - [ 0, 0, 0, 0, 0, 0, 0, 0 ] # eth1 (NC) + - [ 0, 0, 0, 0, 0, 0, 0, 0 ] # eth2 (NC) + - [ 0, 0, 0, 0, 0, 0, 0, 0 ] # eth3 (NC) + - [ 0, 0, 0, 0, 1, 0, 1, 1 ] # eth4 (QSFP Port 1) + - [ 0, 0, 0, 0, 0, 1, 1, 1 ] # dma + - [ 1, 0, 0, 0, 1, 1, 0, 0 ] # ep0 (radio0.0) + - [ 1, 0, 0, 0, 1, 1, 0, 0 ] # ep1 (radio1.0) + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 + NIPC: RADIO_NIPC + radio1: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 1 + NIPC: RADIO_NIPC + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # RF A:0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # RF A:0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # + # RF B:0 TX + - { srcblk: ep1, srcport: out0, dstblk: radio1, dstport: in_0 } + # RF B:0 RX + - { srcblk: radio1, srcport: out_0, dstblk: ep1, dstport: in0 } + # + # BSP Connections + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } diff --git a/top/x400/x440_1600_static_router.hex b/top/x400/x440_1600_static_router.hex new file mode 100644 index 0000000..5807828 --- /dev/null +++ b/top/x400/x440_1600_static_router.hex @@ -0,0 +1,5 @@ +00000004 +004000c0 +00c00040 +00800100 +01000080 diff --git a/top/x400/x440_400_d_rfnoc_image_core.v b/top/x400/x440_400_d_rfnoc_image_core.v new file mode 100644 index 0000000..c6e2668 --- /dev/null +++ b/top/x400/x440_400_d_rfnoc_image_core.v @@ -0,0 +1,2230 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rfnoc_image_core (for x440) +// +// Description: +// +// The RFNoC Image Core contains the Verilog description of the RFNoC design +// to be loaded onto the FPGA. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// Source: x440_400_d_rfnoc_image_core.yml +// + +`default_nettype none + + +module rfnoc_image_core #( + parameter [31:0] CHDR_W = 128, + parameter [31:0] PORT_W = 128, + parameter [31:0] ETH0_W = 64, + parameter [31:0] ETH1_W = 64, + parameter [31:0] ETH2_W = 64, + parameter [31:0] ETH3_W = 64, + parameter [31:0] ETH4_W = 64, + parameter [31:0] DMA_W = 64, + parameter MTU = 10, + parameter [15:0] PROTOVER = {8'd1, 8'd0}, + parameter RADIO_NIPC = 1 +) ( + // Clocks + input wire chdr_aclk, + input wire ctrl_aclk, + input wire core_arst, + input wire radio0_clk, + input wire radio1_clk, + input wire radio0_2x_clk, + input wire radio1_2x_clk, + input wire dram_clk, + // Basic + input wire [ 15:0] device_id, + + // IO ports ///////////////////////// + + // ctrlport_radio0 + output wire [ 0:0] m_ctrlport_radio0_req_wr, + output wire [ 0:0] m_ctrlport_radio0_req_rd, + output wire [ 19:0] m_ctrlport_radio0_req_addr, + output wire [ 31:0] m_ctrlport_radio0_req_data, + output wire [ 3:0] m_ctrlport_radio0_req_byte_en, + output wire [ 0:0] m_ctrlport_radio0_req_has_time, + output wire [ 63:0] m_ctrlport_radio0_req_time, + input wire [ 0:0] m_ctrlport_radio0_resp_ack, + input wire [ 1:0] m_ctrlport_radio0_resp_status, + input wire [ 31:0] m_ctrlport_radio0_resp_data, + // ctrlport_radio1 + output wire [ 0:0] m_ctrlport_radio1_req_wr, + output wire [ 0:0] m_ctrlport_radio1_req_rd, + output wire [ 19:0] m_ctrlport_radio1_req_addr, + output wire [ 31:0] m_ctrlport_radio1_req_data, + output wire [ 3:0] m_ctrlport_radio1_req_byte_en, + output wire [ 0:0] m_ctrlport_radio1_req_has_time, + output wire [ 63:0] m_ctrlport_radio1_req_time, + input wire [ 0:0] m_ctrlport_radio1_resp_ack, + input wire [ 1:0] m_ctrlport_radio1_resp_status, + input wire [ 31:0] m_ctrlport_radio1_resp_data, + // time0 + input wire [ 63:0] radio_time0, + // time1 + input wire [ 63:0] radio_time1, + // radio0 + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, + // radio1 + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, + // dram + input wire [ 0:0] axi_rst, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, + + // Transport Adapters /////////////// + + // Transport 0 (eth0) + input wire [PORT_W-1:0] s_eth0_tdata, + input wire s_eth0_tlast, + input wire s_eth0_tvalid, + output wire s_eth0_tready, + output wire [PORT_W-1:0] m_eth0_tdata, + output wire m_eth0_tlast, + output wire m_eth0_tvalid, + input wire m_eth0_tready, + // Transport 1 (eth1) + input wire [PORT_W-1:0] s_eth1_tdata, + input wire s_eth1_tlast, + input wire s_eth1_tvalid, + output wire s_eth1_tready, + output wire [PORT_W-1:0] m_eth1_tdata, + output wire m_eth1_tlast, + output wire m_eth1_tvalid, + input wire m_eth1_tready, + // Transport 2 (eth2) + input wire [PORT_W-1:0] s_eth2_tdata, + input wire s_eth2_tlast, + input wire s_eth2_tvalid, + output wire s_eth2_tready, + output wire [PORT_W-1:0] m_eth2_tdata, + output wire m_eth2_tlast, + output wire m_eth2_tvalid, + input wire m_eth2_tready, + // Transport 3 (eth3) + input wire [PORT_W-1:0] s_eth3_tdata, + input wire s_eth3_tlast, + input wire s_eth3_tvalid, + output wire s_eth3_tready, + output wire [PORT_W-1:0] m_eth3_tdata, + output wire m_eth3_tlast, + output wire m_eth3_tvalid, + input wire m_eth3_tready, + // Transport 4 (eth4) + input wire [PORT_W-1:0] s_eth4_tdata, + input wire s_eth4_tlast, + input wire s_eth4_tvalid, + output wire s_eth4_tready, + output wire [PORT_W-1:0] m_eth4_tdata, + output wire m_eth4_tlast, + output wire m_eth4_tvalid, + input wire m_eth4_tready, + // Transport 5 (dma) + input wire [PORT_W-1:0] s_dma_tdata, + input wire s_dma_tlast, + input wire s_dma_tvalid, + output wire s_dma_tready, + output wire [PORT_W-1:0] m_dma_tdata, + output wire m_dma_tlast, + output wire m_dma_tvalid, + input wire m_dma_tready +); + + localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; + localparam BLOCK_CHDR_W = 128; + localparam BYTE_MTU = MTU + $clog2(CHDR_W/8); + localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8); + localparam EP0_W = 128; + localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8); + localparam EP1_W = 128; + localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8); + localparam EP2_W = 128; + localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8); + localparam EP3_W = 128; + localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8); + localparam EP4_W = 128; + localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8); + localparam EP5_W = 128; + localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8); + localparam EP6_W = 128; + localparam EP6_MTU = BYTE_MTU - $clog2(EP6_W/8); + localparam EP7_W = 128; + localparam EP7_MTU = BYTE_MTU - $clog2(EP7_W/8); + localparam EP8_W = 128; + localparam EP8_MTU = BYTE_MTU - $clog2(EP8_W/8); + localparam EP9_W = 128; + localparam EP9_MTU = BYTE_MTU - $clog2(EP9_W/8); + localparam EP10_W = 128; + localparam EP10_MTU = BYTE_MTU - $clog2(EP10_W/8); + localparam EP11_W = 128; + localparam EP11_MTU = BYTE_MTU - $clog2(EP11_W/8); + localparam EP12_W = 128; + localparam EP12_MTU = BYTE_MTU - $clog2(EP12_W/8); + localparam EP13_W = 128; + localparam EP13_MTU = BYTE_MTU - $clog2(EP13_W/8); + localparam EP14_W = 128; + localparam EP14_MTU = BYTE_MTU - $clog2(EP14_W/8); + localparam EP15_W = 128; + localparam EP15_MTU = BYTE_MTU - $clog2(EP15_W/8); + + wire rfnoc_chdr_clk, rfnoc_chdr_rst; + wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; + + + //--------------------------------------------------------------------------- + // CHDR Crossbar + //--------------------------------------------------------------------------- + + wire [PORT_W-1:0] xb_to_ep0_tdata ; + wire xb_to_ep0_tlast ; + wire xb_to_ep0_tvalid; + wire xb_to_ep0_tready; + wire [PORT_W-1:0] ep0_to_xb_tdata ; + wire ep0_to_xb_tlast ; + wire ep0_to_xb_tvalid; + wire ep0_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep1_tdata ; + wire xb_to_ep1_tlast ; + wire xb_to_ep1_tvalid; + wire xb_to_ep1_tready; + wire [PORT_W-1:0] ep1_to_xb_tdata ; + wire ep1_to_xb_tlast ; + wire ep1_to_xb_tvalid; + wire ep1_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep2_tdata ; + wire xb_to_ep2_tlast ; + wire xb_to_ep2_tvalid; + wire xb_to_ep2_tready; + wire [PORT_W-1:0] ep2_to_xb_tdata ; + wire ep2_to_xb_tlast ; + wire ep2_to_xb_tvalid; + wire ep2_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep3_tdata ; + wire xb_to_ep3_tlast ; + wire xb_to_ep3_tvalid; + wire xb_to_ep3_tready; + wire [PORT_W-1:0] ep3_to_xb_tdata ; + wire ep3_to_xb_tlast ; + wire ep3_to_xb_tvalid; + wire ep3_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep4_tdata ; + wire xb_to_ep4_tlast ; + wire xb_to_ep4_tvalid; + wire xb_to_ep4_tready; + wire [PORT_W-1:0] ep4_to_xb_tdata ; + wire ep4_to_xb_tlast ; + wire ep4_to_xb_tvalid; + wire ep4_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep5_tdata ; + wire xb_to_ep5_tlast ; + wire xb_to_ep5_tvalid; + wire xb_to_ep5_tready; + wire [PORT_W-1:0] ep5_to_xb_tdata ; + wire ep5_to_xb_tlast ; + wire ep5_to_xb_tvalid; + wire ep5_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep6_tdata ; + wire xb_to_ep6_tlast ; + wire xb_to_ep6_tvalid; + wire xb_to_ep6_tready; + wire [PORT_W-1:0] ep6_to_xb_tdata ; + wire ep6_to_xb_tlast ; + wire ep6_to_xb_tvalid; + wire ep6_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep7_tdata ; + wire xb_to_ep7_tlast ; + wire xb_to_ep7_tvalid; + wire xb_to_ep7_tready; + wire [PORT_W-1:0] ep7_to_xb_tdata ; + wire ep7_to_xb_tlast ; + wire ep7_to_xb_tvalid; + wire ep7_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep8_tdata ; + wire xb_to_ep8_tlast ; + wire xb_to_ep8_tvalid; + wire xb_to_ep8_tready; + wire [PORT_W-1:0] ep8_to_xb_tdata ; + wire ep8_to_xb_tlast ; + wire ep8_to_xb_tvalid; + wire ep8_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep9_tdata ; + wire xb_to_ep9_tlast ; + wire xb_to_ep9_tvalid; + wire xb_to_ep9_tready; + wire [PORT_W-1:0] ep9_to_xb_tdata ; + wire ep9_to_xb_tlast ; + wire ep9_to_xb_tvalid; + wire ep9_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep10_tdata ; + wire xb_to_ep10_tlast ; + wire xb_to_ep10_tvalid; + wire xb_to_ep10_tready; + wire [PORT_W-1:0] ep10_to_xb_tdata ; + wire ep10_to_xb_tlast ; + wire ep10_to_xb_tvalid; + wire ep10_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep11_tdata ; + wire xb_to_ep11_tlast ; + wire xb_to_ep11_tvalid; + wire xb_to_ep11_tready; + wire [PORT_W-1:0] ep11_to_xb_tdata ; + wire ep11_to_xb_tlast ; + wire ep11_to_xb_tvalid; + wire ep11_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep12_tdata ; + wire xb_to_ep12_tlast ; + wire xb_to_ep12_tvalid; + wire xb_to_ep12_tready; + wire [PORT_W-1:0] ep12_to_xb_tdata ; + wire ep12_to_xb_tlast ; + wire ep12_to_xb_tvalid; + wire ep12_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep13_tdata ; + wire xb_to_ep13_tlast ; + wire xb_to_ep13_tvalid; + wire xb_to_ep13_tready; + wire [PORT_W-1:0] ep13_to_xb_tdata ; + wire ep13_to_xb_tlast ; + wire ep13_to_xb_tvalid; + wire ep13_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep14_tdata ; + wire xb_to_ep14_tlast ; + wire xb_to_ep14_tvalid; + wire xb_to_ep14_tready; + wire [PORT_W-1:0] ep14_to_xb_tdata ; + wire ep14_to_xb_tlast ; + wire ep14_to_xb_tvalid; + wire ep14_to_xb_tready; + wire [PORT_W-1:0] xb_to_ep15_tdata ; + wire xb_to_ep15_tlast ; + wire xb_to_ep15_tvalid; + wire xb_to_ep15_tready; + wire [PORT_W-1:0] ep15_to_xb_tdata ; + wire ep15_to_xb_tlast ; + wire ep15_to_xb_tvalid; + wire ep15_to_xb_tready; + + chdr_crossbar_nxn #( + .PORT_W (PORT_W), + .NPORTS (22), + .CHDR_WIDTHS ({EP15_W, EP14_W, EP13_W, EP12_W, EP11_W, EP10_W, EP9_W, EP8_W, EP7_W, EP6_W, EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}), + .DEFAULT_PORT (0), + .ROUTES ({ 22'b0000000011111111101111, + 22'b0000000011111111101111, + 22'b0000000011111111101111, + 22'b0000000011111111101111, + 22'b0000000011111111101111, + 22'b0000000011111111101111, + 22'b0000000011111111101111, + 22'b0000000011111111101111, + 22'b1111111100000000101111, + 22'b1111111100000000101111, + 22'b1111111100000000101111, + 22'b1111111100000000101111, + 22'b1111111100000000101111, + 22'b1111111100000000101111, + 22'b1111111100000000101111, + 22'b1111111100000000101111, + 22'b1111111111111111100000, + 22'b0000000000000000000000, + 22'b1111111111111111001000, + 22'b1111111111111111000100, + 22'b1111111111111111000010, + 22'b1111111111111111000001 }), + .BYTE_MTU (BYTE_MTU), + .ROUTE_TBL_SIZE (6), + .MUX_ALLOC ("ROUND-ROBIN"), + .OPTIMIZE ("AREA"), + .NPORTS_MGMT (6), + .EXT_RTCFG_PORT (0), + .PROTOVER (PROTOVER) + ) chdr_crossbar_nxn_i ( + .clk (rfnoc_chdr_clk), + .reset (rfnoc_chdr_rst), + .device_id (device_id), + .s_axis_tdata ({ep15_to_xb_tdata , ep14_to_xb_tdata , ep13_to_xb_tdata , ep12_to_xb_tdata , ep11_to_xb_tdata , ep10_to_xb_tdata , ep9_to_xb_tdata , ep8_to_xb_tdata , ep7_to_xb_tdata , ep6_to_xb_tdata , ep5_to_xb_tdata , ep4_to_xb_tdata , ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , {PORT_W{1'b0}}, s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }), + .s_axis_tlast ({ep15_to_xb_tlast , ep14_to_xb_tlast , ep13_to_xb_tlast , ep12_to_xb_tlast , ep11_to_xb_tlast , ep10_to_xb_tlast , ep9_to_xb_tlast , ep8_to_xb_tlast , ep7_to_xb_tlast , ep6_to_xb_tlast , ep5_to_xb_tlast , ep4_to_xb_tlast , ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , 1'b0, s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }), + .s_axis_tvalid ({ep15_to_xb_tvalid, ep14_to_xb_tvalid, ep13_to_xb_tvalid, ep12_to_xb_tvalid, ep11_to_xb_tvalid, ep10_to_xb_tvalid, ep9_to_xb_tvalid, ep8_to_xb_tvalid, ep7_to_xb_tvalid, ep6_to_xb_tvalid, ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, 1'b0, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}), + .s_axis_tready ({ep15_to_xb_tready, ep14_to_xb_tready, ep13_to_xb_tready, ep12_to_xb_tready, ep11_to_xb_tready, ep10_to_xb_tready, ep9_to_xb_tready, ep8_to_xb_tready, ep7_to_xb_tready, ep6_to_xb_tready, ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, 1'bZ, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep15_tdata , xb_to_ep14_tdata , xb_to_ep13_tdata , xb_to_ep12_tdata , xb_to_ep11_tdata , xb_to_ep10_tdata , xb_to_ep9_tdata , xb_to_ep8_tdata , xb_to_ep7_tdata , xb_to_ep6_tdata , xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , {PORT_W{1'bZ}}, m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep15_tlast , xb_to_ep14_tlast , xb_to_ep13_tlast , xb_to_ep12_tlast , xb_to_ep11_tlast , xb_to_ep10_tlast , xb_to_ep9_tlast , xb_to_ep8_tlast , xb_to_ep7_tlast , xb_to_ep6_tlast , xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , 1'bZ, m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }), + .m_axis_tvalid ({xb_to_ep15_tvalid, xb_to_ep14_tvalid, xb_to_ep13_tvalid, xb_to_ep12_tvalid, xb_to_ep11_tvalid, xb_to_ep10_tvalid, xb_to_ep9_tvalid, xb_to_ep8_tvalid, xb_to_ep7_tvalid, xb_to_ep6_tvalid, xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, 1'bZ, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep15_tready, xb_to_ep14_tready, xb_to_ep13_tready, xb_to_ep12_tready, xb_to_ep11_tready, xb_to_ep10_tready, xb_to_ep9_tready, xb_to_ep8_tready, xb_to_ep7_tready, xb_to_ep6_tready, xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, 1'b1, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}), + .ext_rtcfg_stb (1'h0), + .ext_rtcfg_addr (16'h0), + .ext_rtcfg_data (32'h0), + .ext_rtcfg_ack () + ); + + + //--------------------------------------------------------------------------- + // Stream Endpoints + //--------------------------------------------------------------------------- + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP0 = 8192; + localparam INGRESS_BUFF_SIZE_EP0 = + REQ_BUFF_SIZE_EP0 == 0 ? 5 : + REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP0); + + wire [BLOCK_CHDR_W-1:0] m_ep0_out0_tdata; + wire m_ep0_out0_tlast; + wire m_ep0_out0_tvalid; + wire m_ep0_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep0_in0_tdata; + wire s_ep0_in0_tlast; + wire s_ep0_in0_tvalid; + wire s_ep0_in0_tready; + wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata; + wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast; + wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; + wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP0_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (1), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (0), + .CTRL_XBAR_PORT (1), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0), + .MTU (EP0_MTU), + .REPORT_STRM_ERRS (1) + ) ep0_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep0_tdata), + .s_axis_chdr_tlast (xb_to_ep0_tlast), + .s_axis_chdr_tvalid (xb_to_ep0_tvalid), + .s_axis_chdr_tready (xb_to_ep0_tready), + .m_axis_chdr_tdata (ep0_to_xb_tdata), + .m_axis_chdr_tlast (ep0_to_xb_tlast), + .m_axis_chdr_tvalid (ep0_to_xb_tvalid), + .m_axis_chdr_tready (ep0_to_xb_tready), + .s_axis_data_tdata ({s_ep0_in0_tdata}), + .s_axis_data_tlast ({s_ep0_in0_tlast}), + .s_axis_data_tvalid ({s_ep0_in0_tvalid}), + .s_axis_data_tready ({s_ep0_in0_tready}), + .m_axis_data_tdata ({m_ep0_out0_tdata}), + .m_axis_data_tlast ({m_ep0_out0_tlast}), + .m_axis_data_tvalid ({m_ep0_out0_tvalid}), + .m_axis_data_tready ({m_ep0_out0_tready}), + .s_axis_ctrl_tdata (s_ep0_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep0_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep0_ctrl_tready), + .m_axis_ctrl_tdata (m_ep0_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep0_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep0_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP1 = 8192; + localparam INGRESS_BUFF_SIZE_EP1 = + REQ_BUFF_SIZE_EP1 == 0 ? 5 : + REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP1); + + wire [BLOCK_CHDR_W-1:0] m_ep1_out0_tdata; + wire m_ep1_out0_tlast; + wire m_ep1_out0_tvalid; + wire m_ep1_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep1_in0_tdata; + wire s_ep1_in0_tlast; + wire s_ep1_in0_tvalid; + wire s_ep1_in0_tready; + wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata; + wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast; + wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; + wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP1_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (1), + .CTRL_XBAR_PORT (2), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1), + .MTU (EP1_MTU), + .REPORT_STRM_ERRS (1) + ) ep1_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep1_tdata), + .s_axis_chdr_tlast (xb_to_ep1_tlast), + .s_axis_chdr_tvalid (xb_to_ep1_tvalid), + .s_axis_chdr_tready (xb_to_ep1_tready), + .m_axis_chdr_tdata (ep1_to_xb_tdata), + .m_axis_chdr_tlast (ep1_to_xb_tlast), + .m_axis_chdr_tvalid (ep1_to_xb_tvalid), + .m_axis_chdr_tready (ep1_to_xb_tready), + .s_axis_data_tdata ({s_ep1_in0_tdata}), + .s_axis_data_tlast ({s_ep1_in0_tlast}), + .s_axis_data_tvalid ({s_ep1_in0_tvalid}), + .s_axis_data_tready ({s_ep1_in0_tready}), + .m_axis_data_tdata ({m_ep1_out0_tdata}), + .m_axis_data_tlast ({m_ep1_out0_tlast}), + .m_axis_data_tvalid ({m_ep1_out0_tvalid}), + .m_axis_data_tready ({m_ep1_out0_tready}), + .s_axis_ctrl_tdata (s_ep1_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep1_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep1_ctrl_tready), + .m_axis_ctrl_tdata (m_ep1_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep1_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep1_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP2 = 8192; + localparam INGRESS_BUFF_SIZE_EP2 = + REQ_BUFF_SIZE_EP2 == 0 ? 5 : + REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP2); + + wire [BLOCK_CHDR_W-1:0] m_ep2_out0_tdata; + wire m_ep2_out0_tlast; + wire m_ep2_out0_tvalid; + wire m_ep2_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep2_in0_tdata; + wire s_ep2_in0_tlast; + wire s_ep2_in0_tvalid; + wire s_ep2_in0_tready; + wire [ 31:0] m_ep2_ctrl_tdata, s_ep2_ctrl_tdata; + wire m_ep2_ctrl_tlast, s_ep2_ctrl_tlast; + wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; + wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP2_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (2), + .CTRL_XBAR_PORT (3), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2), + .MTU (EP2_MTU), + .REPORT_STRM_ERRS (1) + ) ep2_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep2_tdata), + .s_axis_chdr_tlast (xb_to_ep2_tlast), + .s_axis_chdr_tvalid (xb_to_ep2_tvalid), + .s_axis_chdr_tready (xb_to_ep2_tready), + .m_axis_chdr_tdata (ep2_to_xb_tdata), + .m_axis_chdr_tlast (ep2_to_xb_tlast), + .m_axis_chdr_tvalid (ep2_to_xb_tvalid), + .m_axis_chdr_tready (ep2_to_xb_tready), + .s_axis_data_tdata ({s_ep2_in0_tdata}), + .s_axis_data_tlast ({s_ep2_in0_tlast}), + .s_axis_data_tvalid ({s_ep2_in0_tvalid}), + .s_axis_data_tready ({s_ep2_in0_tready}), + .m_axis_data_tdata ({m_ep2_out0_tdata}), + .m_axis_data_tlast ({m_ep2_out0_tlast}), + .m_axis_data_tvalid ({m_ep2_out0_tvalid}), + .m_axis_data_tready ({m_ep2_out0_tready}), + .s_axis_ctrl_tdata (s_ep2_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep2_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep2_ctrl_tready), + .m_axis_ctrl_tdata (m_ep2_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep2_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep2_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP3 = 8192; + localparam INGRESS_BUFF_SIZE_EP3 = + REQ_BUFF_SIZE_EP3 == 0 ? 5 : + REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP3); + + wire [BLOCK_CHDR_W-1:0] m_ep3_out0_tdata; + wire m_ep3_out0_tlast; + wire m_ep3_out0_tvalid; + wire m_ep3_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep3_in0_tdata; + wire s_ep3_in0_tlast; + wire s_ep3_in0_tvalid; + wire s_ep3_in0_tready; + wire [ 31:0] m_ep3_ctrl_tdata, s_ep3_ctrl_tdata; + wire m_ep3_ctrl_tlast, s_ep3_ctrl_tlast; + wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; + wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP3_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (3), + .CTRL_XBAR_PORT (4), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3), + .MTU (EP3_MTU), + .REPORT_STRM_ERRS (1) + ) ep3_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep3_tdata), + .s_axis_chdr_tlast (xb_to_ep3_tlast), + .s_axis_chdr_tvalid (xb_to_ep3_tvalid), + .s_axis_chdr_tready (xb_to_ep3_tready), + .m_axis_chdr_tdata (ep3_to_xb_tdata), + .m_axis_chdr_tlast (ep3_to_xb_tlast), + .m_axis_chdr_tvalid (ep3_to_xb_tvalid), + .m_axis_chdr_tready (ep3_to_xb_tready), + .s_axis_data_tdata ({s_ep3_in0_tdata}), + .s_axis_data_tlast ({s_ep3_in0_tlast}), + .s_axis_data_tvalid ({s_ep3_in0_tvalid}), + .s_axis_data_tready ({s_ep3_in0_tready}), + .m_axis_data_tdata ({m_ep3_out0_tdata}), + .m_axis_data_tlast ({m_ep3_out0_tlast}), + .m_axis_data_tvalid ({m_ep3_out0_tvalid}), + .m_axis_data_tready ({m_ep3_out0_tready}), + .s_axis_ctrl_tdata (s_ep3_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep3_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep3_ctrl_tready), + .m_axis_ctrl_tdata (m_ep3_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep3_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep3_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP4 = 8192; + localparam INGRESS_BUFF_SIZE_EP4 = + REQ_BUFF_SIZE_EP4 == 0 ? 5 : + REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP4); + + wire [BLOCK_CHDR_W-1:0] m_ep4_out0_tdata; + wire m_ep4_out0_tlast; + wire m_ep4_out0_tvalid; + wire m_ep4_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep4_in0_tdata; + wire s_ep4_in0_tlast; + wire s_ep4_in0_tvalid; + wire s_ep4_in0_tready; + wire [ 31:0] m_ep4_ctrl_tdata, s_ep4_ctrl_tdata; + wire m_ep4_ctrl_tlast, s_ep4_ctrl_tlast; + wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; + wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP4_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (4), + .CTRL_XBAR_PORT (5), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4), + .MTU (EP4_MTU), + .REPORT_STRM_ERRS (1) + ) ep4_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep4_tdata), + .s_axis_chdr_tlast (xb_to_ep4_tlast), + .s_axis_chdr_tvalid (xb_to_ep4_tvalid), + .s_axis_chdr_tready (xb_to_ep4_tready), + .m_axis_chdr_tdata (ep4_to_xb_tdata), + .m_axis_chdr_tlast (ep4_to_xb_tlast), + .m_axis_chdr_tvalid (ep4_to_xb_tvalid), + .m_axis_chdr_tready (ep4_to_xb_tready), + .s_axis_data_tdata ({s_ep4_in0_tdata}), + .s_axis_data_tlast ({s_ep4_in0_tlast}), + .s_axis_data_tvalid ({s_ep4_in0_tvalid}), + .s_axis_data_tready ({s_ep4_in0_tready}), + .m_axis_data_tdata ({m_ep4_out0_tdata}), + .m_axis_data_tlast ({m_ep4_out0_tlast}), + .m_axis_data_tvalid ({m_ep4_out0_tvalid}), + .m_axis_data_tready ({m_ep4_out0_tready}), + .s_axis_ctrl_tdata (s_ep4_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep4_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep4_ctrl_tready), + .m_axis_ctrl_tdata (m_ep4_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep4_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep4_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP5 = 8192; + localparam INGRESS_BUFF_SIZE_EP5 = + REQ_BUFF_SIZE_EP5 == 0 ? 5 : + REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP5); + + wire [BLOCK_CHDR_W-1:0] m_ep5_out0_tdata; + wire m_ep5_out0_tlast; + wire m_ep5_out0_tvalid; + wire m_ep5_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep5_in0_tdata; + wire s_ep5_in0_tlast; + wire s_ep5_in0_tvalid; + wire s_ep5_in0_tready; + wire [ 31:0] m_ep5_ctrl_tdata, s_ep5_ctrl_tdata; + wire m_ep5_ctrl_tlast, s_ep5_ctrl_tlast; + wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; + wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP5_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (5), + .CTRL_XBAR_PORT (6), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5), + .MTU (EP5_MTU), + .REPORT_STRM_ERRS (1) + ) ep5_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep5_tdata), + .s_axis_chdr_tlast (xb_to_ep5_tlast), + .s_axis_chdr_tvalid (xb_to_ep5_tvalid), + .s_axis_chdr_tready (xb_to_ep5_tready), + .m_axis_chdr_tdata (ep5_to_xb_tdata), + .m_axis_chdr_tlast (ep5_to_xb_tlast), + .m_axis_chdr_tvalid (ep5_to_xb_tvalid), + .m_axis_chdr_tready (ep5_to_xb_tready), + .s_axis_data_tdata ({s_ep5_in0_tdata}), + .s_axis_data_tlast ({s_ep5_in0_tlast}), + .s_axis_data_tvalid ({s_ep5_in0_tvalid}), + .s_axis_data_tready ({s_ep5_in0_tready}), + .m_axis_data_tdata ({m_ep5_out0_tdata}), + .m_axis_data_tlast ({m_ep5_out0_tlast}), + .m_axis_data_tvalid ({m_ep5_out0_tvalid}), + .m_axis_data_tready ({m_ep5_out0_tready}), + .s_axis_ctrl_tdata (s_ep5_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep5_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep5_ctrl_tready), + .m_axis_ctrl_tdata (m_ep5_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep5_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep5_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP6 = 8192; + localparam INGRESS_BUFF_SIZE_EP6 = + REQ_BUFF_SIZE_EP6 == 0 ? 5 : + REQ_BUFF_SIZE_EP6 < 2*(2**EP6_MTU) ? EP6_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP6); + + wire [BLOCK_CHDR_W-1:0] m_ep6_out0_tdata; + wire m_ep6_out0_tlast; + wire m_ep6_out0_tvalid; + wire m_ep6_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep6_in0_tdata; + wire s_ep6_in0_tlast; + wire s_ep6_in0_tvalid; + wire s_ep6_in0_tready; + wire [ 31:0] m_ep6_ctrl_tdata, s_ep6_ctrl_tdata; + wire m_ep6_ctrl_tlast, s_ep6_ctrl_tlast; + wire m_ep6_ctrl_tvalid, s_ep6_ctrl_tvalid; + wire m_ep6_ctrl_tready, s_ep6_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP6_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (6), + .CTRL_XBAR_PORT (7), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6), + .MTU (EP6_MTU), + .REPORT_STRM_ERRS (1) + ) ep6_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep6_tdata), + .s_axis_chdr_tlast (xb_to_ep6_tlast), + .s_axis_chdr_tvalid (xb_to_ep6_tvalid), + .s_axis_chdr_tready (xb_to_ep6_tready), + .m_axis_chdr_tdata (ep6_to_xb_tdata), + .m_axis_chdr_tlast (ep6_to_xb_tlast), + .m_axis_chdr_tvalid (ep6_to_xb_tvalid), + .m_axis_chdr_tready (ep6_to_xb_tready), + .s_axis_data_tdata ({s_ep6_in0_tdata}), + .s_axis_data_tlast ({s_ep6_in0_tlast}), + .s_axis_data_tvalid ({s_ep6_in0_tvalid}), + .s_axis_data_tready ({s_ep6_in0_tready}), + .m_axis_data_tdata ({m_ep6_out0_tdata}), + .m_axis_data_tlast ({m_ep6_out0_tlast}), + .m_axis_data_tvalid ({m_ep6_out0_tvalid}), + .m_axis_data_tready ({m_ep6_out0_tready}), + .s_axis_ctrl_tdata (s_ep6_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep6_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep6_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep6_ctrl_tready), + .m_axis_ctrl_tdata (m_ep6_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep6_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep6_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep6_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP7 = 8192; + localparam INGRESS_BUFF_SIZE_EP7 = + REQ_BUFF_SIZE_EP7 == 0 ? 5 : + REQ_BUFF_SIZE_EP7 < 2*(2**EP7_MTU) ? EP7_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP7); + + wire [BLOCK_CHDR_W-1:0] m_ep7_out0_tdata; + wire m_ep7_out0_tlast; + wire m_ep7_out0_tvalid; + wire m_ep7_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep7_in0_tdata; + wire s_ep7_in0_tlast; + wire s_ep7_in0_tvalid; + wire s_ep7_in0_tready; + wire [ 31:0] m_ep7_ctrl_tdata, s_ep7_ctrl_tdata; + wire m_ep7_ctrl_tlast, s_ep7_ctrl_tlast; + wire m_ep7_ctrl_tvalid, s_ep7_ctrl_tvalid; + wire m_ep7_ctrl_tready, s_ep7_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP7_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (7), + .CTRL_XBAR_PORT (8), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7), + .MTU (EP7_MTU), + .REPORT_STRM_ERRS (1) + ) ep7_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep7_tdata), + .s_axis_chdr_tlast (xb_to_ep7_tlast), + .s_axis_chdr_tvalid (xb_to_ep7_tvalid), + .s_axis_chdr_tready (xb_to_ep7_tready), + .m_axis_chdr_tdata (ep7_to_xb_tdata), + .m_axis_chdr_tlast (ep7_to_xb_tlast), + .m_axis_chdr_tvalid (ep7_to_xb_tvalid), + .m_axis_chdr_tready (ep7_to_xb_tready), + .s_axis_data_tdata ({s_ep7_in0_tdata}), + .s_axis_data_tlast ({s_ep7_in0_tlast}), + .s_axis_data_tvalid ({s_ep7_in0_tvalid}), + .s_axis_data_tready ({s_ep7_in0_tready}), + .m_axis_data_tdata ({m_ep7_out0_tdata}), + .m_axis_data_tlast ({m_ep7_out0_tlast}), + .m_axis_data_tvalid ({m_ep7_out0_tvalid}), + .m_axis_data_tready ({m_ep7_out0_tready}), + .s_axis_ctrl_tdata (s_ep7_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep7_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep7_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep7_ctrl_tready), + .m_axis_ctrl_tdata (m_ep7_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep7_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep7_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep7_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP8 = 8192; + localparam INGRESS_BUFF_SIZE_EP8 = + REQ_BUFF_SIZE_EP8 == 0 ? 5 : + REQ_BUFF_SIZE_EP8 < 2*(2**EP8_MTU) ? EP8_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP8); + + wire [BLOCK_CHDR_W-1:0] m_ep8_out0_tdata; + wire m_ep8_out0_tlast; + wire m_ep8_out0_tvalid; + wire m_ep8_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep8_in0_tdata; + wire s_ep8_in0_tlast; + wire s_ep8_in0_tvalid; + wire s_ep8_in0_tready; + wire [ 31:0] m_ep8_ctrl_tdata, s_ep8_ctrl_tdata; + wire m_ep8_ctrl_tlast, s_ep8_ctrl_tlast; + wire m_ep8_ctrl_tvalid, s_ep8_ctrl_tvalid; + wire m_ep8_ctrl_tready, s_ep8_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP8_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (8), + .CTRL_XBAR_PORT (9), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP8), + .MTU (EP8_MTU), + .REPORT_STRM_ERRS (1) + ) ep8_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep8_tdata), + .s_axis_chdr_tlast (xb_to_ep8_tlast), + .s_axis_chdr_tvalid (xb_to_ep8_tvalid), + .s_axis_chdr_tready (xb_to_ep8_tready), + .m_axis_chdr_tdata (ep8_to_xb_tdata), + .m_axis_chdr_tlast (ep8_to_xb_tlast), + .m_axis_chdr_tvalid (ep8_to_xb_tvalid), + .m_axis_chdr_tready (ep8_to_xb_tready), + .s_axis_data_tdata ({s_ep8_in0_tdata}), + .s_axis_data_tlast ({s_ep8_in0_tlast}), + .s_axis_data_tvalid ({s_ep8_in0_tvalid}), + .s_axis_data_tready ({s_ep8_in0_tready}), + .m_axis_data_tdata ({m_ep8_out0_tdata}), + .m_axis_data_tlast ({m_ep8_out0_tlast}), + .m_axis_data_tvalid ({m_ep8_out0_tvalid}), + .m_axis_data_tready ({m_ep8_out0_tready}), + .s_axis_ctrl_tdata (s_ep8_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep8_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep8_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep8_ctrl_tready), + .m_axis_ctrl_tdata (m_ep8_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep8_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep8_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep8_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP9 = 8192; + localparam INGRESS_BUFF_SIZE_EP9 = + REQ_BUFF_SIZE_EP9 == 0 ? 5 : + REQ_BUFF_SIZE_EP9 < 2*(2**EP9_MTU) ? EP9_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP9); + + wire [BLOCK_CHDR_W-1:0] m_ep9_out0_tdata; + wire m_ep9_out0_tlast; + wire m_ep9_out0_tvalid; + wire m_ep9_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep9_in0_tdata; + wire s_ep9_in0_tlast; + wire s_ep9_in0_tvalid; + wire s_ep9_in0_tready; + wire [ 31:0] m_ep9_ctrl_tdata, s_ep9_ctrl_tdata; + wire m_ep9_ctrl_tlast, s_ep9_ctrl_tlast; + wire m_ep9_ctrl_tvalid, s_ep9_ctrl_tvalid; + wire m_ep9_ctrl_tready, s_ep9_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP9_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (9), + .CTRL_XBAR_PORT (10), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP9), + .MTU (EP9_MTU), + .REPORT_STRM_ERRS (1) + ) ep9_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep9_tdata), + .s_axis_chdr_tlast (xb_to_ep9_tlast), + .s_axis_chdr_tvalid (xb_to_ep9_tvalid), + .s_axis_chdr_tready (xb_to_ep9_tready), + .m_axis_chdr_tdata (ep9_to_xb_tdata), + .m_axis_chdr_tlast (ep9_to_xb_tlast), + .m_axis_chdr_tvalid (ep9_to_xb_tvalid), + .m_axis_chdr_tready (ep9_to_xb_tready), + .s_axis_data_tdata ({s_ep9_in0_tdata}), + .s_axis_data_tlast ({s_ep9_in0_tlast}), + .s_axis_data_tvalid ({s_ep9_in0_tvalid}), + .s_axis_data_tready ({s_ep9_in0_tready}), + .m_axis_data_tdata ({m_ep9_out0_tdata}), + .m_axis_data_tlast ({m_ep9_out0_tlast}), + .m_axis_data_tvalid ({m_ep9_out0_tvalid}), + .m_axis_data_tready ({m_ep9_out0_tready}), + .s_axis_ctrl_tdata (s_ep9_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep9_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep9_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep9_ctrl_tready), + .m_axis_ctrl_tdata (m_ep9_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep9_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep9_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep9_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP10 = 8192; + localparam INGRESS_BUFF_SIZE_EP10 = + REQ_BUFF_SIZE_EP10 == 0 ? 5 : + REQ_BUFF_SIZE_EP10 < 2*(2**EP10_MTU) ? EP10_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP10); + + wire [BLOCK_CHDR_W-1:0] m_ep10_out0_tdata; + wire m_ep10_out0_tlast; + wire m_ep10_out0_tvalid; + wire m_ep10_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep10_in0_tdata; + wire s_ep10_in0_tlast; + wire s_ep10_in0_tvalid; + wire s_ep10_in0_tready; + wire [ 31:0] m_ep10_ctrl_tdata, s_ep10_ctrl_tdata; + wire m_ep10_ctrl_tlast, s_ep10_ctrl_tlast; + wire m_ep10_ctrl_tvalid, s_ep10_ctrl_tvalid; + wire m_ep10_ctrl_tready, s_ep10_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP10_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (10), + .CTRL_XBAR_PORT (11), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP10), + .MTU (EP10_MTU), + .REPORT_STRM_ERRS (1) + ) ep10_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep10_tdata), + .s_axis_chdr_tlast (xb_to_ep10_tlast), + .s_axis_chdr_tvalid (xb_to_ep10_tvalid), + .s_axis_chdr_tready (xb_to_ep10_tready), + .m_axis_chdr_tdata (ep10_to_xb_tdata), + .m_axis_chdr_tlast (ep10_to_xb_tlast), + .m_axis_chdr_tvalid (ep10_to_xb_tvalid), + .m_axis_chdr_tready (ep10_to_xb_tready), + .s_axis_data_tdata ({s_ep10_in0_tdata}), + .s_axis_data_tlast ({s_ep10_in0_tlast}), + .s_axis_data_tvalid ({s_ep10_in0_tvalid}), + .s_axis_data_tready ({s_ep10_in0_tready}), + .m_axis_data_tdata ({m_ep10_out0_tdata}), + .m_axis_data_tlast ({m_ep10_out0_tlast}), + .m_axis_data_tvalid ({m_ep10_out0_tvalid}), + .m_axis_data_tready ({m_ep10_out0_tready}), + .s_axis_ctrl_tdata (s_ep10_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep10_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep10_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep10_ctrl_tready), + .m_axis_ctrl_tdata (m_ep10_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep10_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep10_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep10_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP11 = 8192; + localparam INGRESS_BUFF_SIZE_EP11 = + REQ_BUFF_SIZE_EP11 == 0 ? 5 : + REQ_BUFF_SIZE_EP11 < 2*(2**EP11_MTU) ? EP11_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP11); + + wire [BLOCK_CHDR_W-1:0] m_ep11_out0_tdata; + wire m_ep11_out0_tlast; + wire m_ep11_out0_tvalid; + wire m_ep11_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep11_in0_tdata; + wire s_ep11_in0_tlast; + wire s_ep11_in0_tvalid; + wire s_ep11_in0_tready; + wire [ 31:0] m_ep11_ctrl_tdata, s_ep11_ctrl_tdata; + wire m_ep11_ctrl_tlast, s_ep11_ctrl_tlast; + wire m_ep11_ctrl_tvalid, s_ep11_ctrl_tvalid; + wire m_ep11_ctrl_tready, s_ep11_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP11_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (11), + .CTRL_XBAR_PORT (12), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP11), + .MTU (EP11_MTU), + .REPORT_STRM_ERRS (1) + ) ep11_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep11_tdata), + .s_axis_chdr_tlast (xb_to_ep11_tlast), + .s_axis_chdr_tvalid (xb_to_ep11_tvalid), + .s_axis_chdr_tready (xb_to_ep11_tready), + .m_axis_chdr_tdata (ep11_to_xb_tdata), + .m_axis_chdr_tlast (ep11_to_xb_tlast), + .m_axis_chdr_tvalid (ep11_to_xb_tvalid), + .m_axis_chdr_tready (ep11_to_xb_tready), + .s_axis_data_tdata ({s_ep11_in0_tdata}), + .s_axis_data_tlast ({s_ep11_in0_tlast}), + .s_axis_data_tvalid ({s_ep11_in0_tvalid}), + .s_axis_data_tready ({s_ep11_in0_tready}), + .m_axis_data_tdata ({m_ep11_out0_tdata}), + .m_axis_data_tlast ({m_ep11_out0_tlast}), + .m_axis_data_tvalid ({m_ep11_out0_tvalid}), + .m_axis_data_tready ({m_ep11_out0_tready}), + .s_axis_ctrl_tdata (s_ep11_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep11_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep11_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep11_ctrl_tready), + .m_axis_ctrl_tdata (m_ep11_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep11_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep11_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep11_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP12 = 8192; + localparam INGRESS_BUFF_SIZE_EP12 = + REQ_BUFF_SIZE_EP12 == 0 ? 5 : + REQ_BUFF_SIZE_EP12 < 2*(2**EP12_MTU) ? EP12_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP12); + + wire [BLOCK_CHDR_W-1:0] m_ep12_out0_tdata; + wire m_ep12_out0_tlast; + wire m_ep12_out0_tvalid; + wire m_ep12_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep12_in0_tdata; + wire s_ep12_in0_tlast; + wire s_ep12_in0_tvalid; + wire s_ep12_in0_tready; + wire [ 31:0] m_ep12_ctrl_tdata, s_ep12_ctrl_tdata; + wire m_ep12_ctrl_tlast, s_ep12_ctrl_tlast; + wire m_ep12_ctrl_tvalid, s_ep12_ctrl_tvalid; + wire m_ep12_ctrl_tready, s_ep12_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP12_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (12), + .CTRL_XBAR_PORT (13), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP12), + .MTU (EP12_MTU), + .REPORT_STRM_ERRS (1) + ) ep12_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep12_tdata), + .s_axis_chdr_tlast (xb_to_ep12_tlast), + .s_axis_chdr_tvalid (xb_to_ep12_tvalid), + .s_axis_chdr_tready (xb_to_ep12_tready), + .m_axis_chdr_tdata (ep12_to_xb_tdata), + .m_axis_chdr_tlast (ep12_to_xb_tlast), + .m_axis_chdr_tvalid (ep12_to_xb_tvalid), + .m_axis_chdr_tready (ep12_to_xb_tready), + .s_axis_data_tdata ({s_ep12_in0_tdata}), + .s_axis_data_tlast ({s_ep12_in0_tlast}), + .s_axis_data_tvalid ({s_ep12_in0_tvalid}), + .s_axis_data_tready ({s_ep12_in0_tready}), + .m_axis_data_tdata ({m_ep12_out0_tdata}), + .m_axis_data_tlast ({m_ep12_out0_tlast}), + .m_axis_data_tvalid ({m_ep12_out0_tvalid}), + .m_axis_data_tready ({m_ep12_out0_tready}), + .s_axis_ctrl_tdata (s_ep12_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep12_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep12_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep12_ctrl_tready), + .m_axis_ctrl_tdata (m_ep12_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep12_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep12_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep12_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP13 = 8192; + localparam INGRESS_BUFF_SIZE_EP13 = + REQ_BUFF_SIZE_EP13 == 0 ? 5 : + REQ_BUFF_SIZE_EP13 < 2*(2**EP13_MTU) ? EP13_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP13); + + wire [BLOCK_CHDR_W-1:0] m_ep13_out0_tdata; + wire m_ep13_out0_tlast; + wire m_ep13_out0_tvalid; + wire m_ep13_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep13_in0_tdata; + wire s_ep13_in0_tlast; + wire s_ep13_in0_tvalid; + wire s_ep13_in0_tready; + wire [ 31:0] m_ep13_ctrl_tdata, s_ep13_ctrl_tdata; + wire m_ep13_ctrl_tlast, s_ep13_ctrl_tlast; + wire m_ep13_ctrl_tvalid, s_ep13_ctrl_tvalid; + wire m_ep13_ctrl_tready, s_ep13_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP13_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (13), + .CTRL_XBAR_PORT (14), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP13), + .MTU (EP13_MTU), + .REPORT_STRM_ERRS (1) + ) ep13_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep13_tdata), + .s_axis_chdr_tlast (xb_to_ep13_tlast), + .s_axis_chdr_tvalid (xb_to_ep13_tvalid), + .s_axis_chdr_tready (xb_to_ep13_tready), + .m_axis_chdr_tdata (ep13_to_xb_tdata), + .m_axis_chdr_tlast (ep13_to_xb_tlast), + .m_axis_chdr_tvalid (ep13_to_xb_tvalid), + .m_axis_chdr_tready (ep13_to_xb_tready), + .s_axis_data_tdata ({s_ep13_in0_tdata}), + .s_axis_data_tlast ({s_ep13_in0_tlast}), + .s_axis_data_tvalid ({s_ep13_in0_tvalid}), + .s_axis_data_tready ({s_ep13_in0_tready}), + .m_axis_data_tdata ({m_ep13_out0_tdata}), + .m_axis_data_tlast ({m_ep13_out0_tlast}), + .m_axis_data_tvalid ({m_ep13_out0_tvalid}), + .m_axis_data_tready ({m_ep13_out0_tready}), + .s_axis_ctrl_tdata (s_ep13_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep13_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep13_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep13_ctrl_tready), + .m_axis_ctrl_tdata (m_ep13_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep13_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep13_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep13_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP14 = 8192; + localparam INGRESS_BUFF_SIZE_EP14 = + REQ_BUFF_SIZE_EP14 == 0 ? 5 : + REQ_BUFF_SIZE_EP14 < 2*(2**EP14_MTU) ? EP14_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP14); + + wire [BLOCK_CHDR_W-1:0] m_ep14_out0_tdata; + wire m_ep14_out0_tlast; + wire m_ep14_out0_tvalid; + wire m_ep14_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep14_in0_tdata; + wire s_ep14_in0_tlast; + wire s_ep14_in0_tvalid; + wire s_ep14_in0_tready; + wire [ 31:0] m_ep14_ctrl_tdata, s_ep14_ctrl_tdata; + wire m_ep14_ctrl_tlast, s_ep14_ctrl_tlast; + wire m_ep14_ctrl_tvalid, s_ep14_ctrl_tvalid; + wire m_ep14_ctrl_tready, s_ep14_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP14_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (14), + .CTRL_XBAR_PORT (15), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP14), + .MTU (EP14_MTU), + .REPORT_STRM_ERRS (1) + ) ep14_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep14_tdata), + .s_axis_chdr_tlast (xb_to_ep14_tlast), + .s_axis_chdr_tvalid (xb_to_ep14_tvalid), + .s_axis_chdr_tready (xb_to_ep14_tready), + .m_axis_chdr_tdata (ep14_to_xb_tdata), + .m_axis_chdr_tlast (ep14_to_xb_tlast), + .m_axis_chdr_tvalid (ep14_to_xb_tvalid), + .m_axis_chdr_tready (ep14_to_xb_tready), + .s_axis_data_tdata ({s_ep14_in0_tdata}), + .s_axis_data_tlast ({s_ep14_in0_tlast}), + .s_axis_data_tvalid ({s_ep14_in0_tvalid}), + .s_axis_data_tready ({s_ep14_in0_tready}), + .m_axis_data_tdata ({m_ep14_out0_tdata}), + .m_axis_data_tlast ({m_ep14_out0_tlast}), + .m_axis_data_tvalid ({m_ep14_out0_tvalid}), + .m_axis_data_tready ({m_ep14_out0_tready}), + .s_axis_ctrl_tdata (s_ep14_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep14_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep14_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep14_ctrl_tready), + .m_axis_ctrl_tdata (m_ep14_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep14_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep14_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep14_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + // If requested buffer size is 0, use the minimum SRL-based FIFO size. + // Otherwise, make sure it's at least two MTU-sized packets. + localparam REQ_BUFF_SIZE_EP15 = 8192; + localparam INGRESS_BUFF_SIZE_EP15 = + REQ_BUFF_SIZE_EP15 == 0 ? 5 : + REQ_BUFF_SIZE_EP15 < 2*(2**EP15_MTU) ? EP15_MTU+1 : + $clog2(REQ_BUFF_SIZE_EP15); + + wire [BLOCK_CHDR_W-1:0] m_ep15_out0_tdata; + wire m_ep15_out0_tlast; + wire m_ep15_out0_tvalid; + wire m_ep15_out0_tready; + wire [BLOCK_CHDR_W-1:0] s_ep15_in0_tdata; + wire s_ep15_in0_tlast; + wire s_ep15_in0_tvalid; + wire s_ep15_in0_tready; + wire [ 31:0] m_ep15_ctrl_tdata, s_ep15_ctrl_tdata; + wire m_ep15_ctrl_tlast, s_ep15_ctrl_tlast; + wire m_ep15_ctrl_tvalid, s_ep15_ctrl_tvalid; + wire m_ep15_ctrl_tready, s_ep15_ctrl_tready; + + chdr_stream_endpoint #( + .DEVICE_FAMILY ("ULTRASCALE"), + .PROTOVER (PROTOVER), + .CHDR_W (EP15_W), + .BLOCK_CHDR_W (BLOCK_CHDR_W), + .AXIS_CTRL_EN (0), + .AXIS_DATA_EN (1), + .NUM_DATA_I (1), + .NUM_DATA_O (1), + .INST_NUM (15), + .CTRL_XBAR_PORT (16), + .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP15), + .MTU (EP15_MTU), + .REPORT_STRM_ERRS (1) + ) ep15_i ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_chdr_rst (rfnoc_chdr_rst), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .rfnoc_ctrl_rst (rfnoc_ctrl_rst), + .device_id (device_id), + .s_axis_chdr_tdata (xb_to_ep15_tdata), + .s_axis_chdr_tlast (xb_to_ep15_tlast), + .s_axis_chdr_tvalid (xb_to_ep15_tvalid), + .s_axis_chdr_tready (xb_to_ep15_tready), + .m_axis_chdr_tdata (ep15_to_xb_tdata), + .m_axis_chdr_tlast (ep15_to_xb_tlast), + .m_axis_chdr_tvalid (ep15_to_xb_tvalid), + .m_axis_chdr_tready (ep15_to_xb_tready), + .s_axis_data_tdata ({s_ep15_in0_tdata}), + .s_axis_data_tlast ({s_ep15_in0_tlast}), + .s_axis_data_tvalid ({s_ep15_in0_tvalid}), + .s_axis_data_tready ({s_ep15_in0_tready}), + .m_axis_data_tdata ({m_ep15_out0_tdata}), + .m_axis_data_tlast ({m_ep15_out0_tlast}), + .m_axis_data_tvalid ({m_ep15_out0_tvalid}), + .m_axis_data_tready ({m_ep15_out0_tready}), + .s_axis_ctrl_tdata (s_ep15_ctrl_tdata), + .s_axis_ctrl_tlast (s_ep15_ctrl_tlast), + .s_axis_ctrl_tvalid (s_ep15_ctrl_tvalid), + .s_axis_ctrl_tready (s_ep15_ctrl_tready), + .m_axis_ctrl_tdata (m_ep15_ctrl_tdata), + .m_axis_ctrl_tlast (m_ep15_ctrl_tlast), + .m_axis_ctrl_tvalid (m_ep15_ctrl_tvalid), + .m_axis_ctrl_tready (m_ep15_ctrl_tready), + .strm_seq_err_stb (), + .strm_data_err_stb (), + .strm_route_err_stb (), + .signal_data_err (1'b0) + ); + + + //--------------------------------------------------------------------------- + // Control Crossbar + //--------------------------------------------------------------------------- + + wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; + wire m_core_ctrl_tlast, s_core_ctrl_tlast; + wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; + wire m_core_ctrl_tready, s_core_ctrl_tready; + wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata; + wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast; + wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; + wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; + wire [31:0] m_radio1_ctrl_tdata, s_radio1_ctrl_tdata; + wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; + wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; + wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; + wire [31:0] m_replay0_ctrl_tdata, s_replay0_ctrl_tdata; + wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast; + wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; + wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; + + axis_ctrl_crossbar_nxn #( + .WIDTH (32), + .NPORTS (5), + .TOPOLOGY ("TORUS"), + .INGRESS_BUFF_SIZE(5), + .ROUTER_BUFF_SIZE (5), + .ROUTING_ALLOC ("WORMHOLE"), + .SWITCH_ALLOC ("PRIO") + ) ctrl_xb_i ( + .clk (rfnoc_ctrl_clk), + .reset (rfnoc_ctrl_rst), + .s_axis_tdata ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .deadlock_detected() + ); + + + //--------------------------------------------------------------------------- + // RFNoC Core Kernel + //--------------------------------------------------------------------------- + + wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; + + rfnoc_core_kernel #( + .PROTOVER (PROTOVER), + .DEVICE_TYPE (16'hA400), + .DEVICE_FAMILY ("ULTRASCALE"), + .SAFE_START_CLKS (0), + .NUM_BLOCKS (3), + .NUM_STREAM_ENDPOINTS(16), + .NUM_ENDPOINTS_CTRL (1), + .NUM_TRANSPORTS (6), + .NUM_EDGES (32), + .CHDR_XBAR_PRESENT (1), + .EDGE_TBL_FILE (EDGE_TBL_FILE) + ) core_kernel_i ( + .chdr_aclk (chdr_aclk), + .chdr_aclk_locked (1'b1), + .ctrl_aclk (ctrl_aclk), + .ctrl_aclk_locked (1'b1), + .core_arst (core_arst), + .core_chdr_clk (rfnoc_chdr_clk), + .core_chdr_rst (rfnoc_chdr_rst), + .core_ctrl_clk (rfnoc_ctrl_clk), + .core_ctrl_rst (rfnoc_ctrl_rst), + .s_axis_ctrl_tdata (s_core_ctrl_tdata), + .s_axis_ctrl_tlast (s_core_ctrl_tlast), + .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), + .s_axis_ctrl_tready (s_core_ctrl_tready), + .m_axis_ctrl_tdata (m_core_ctrl_tdata), + .m_axis_ctrl_tlast (m_core_ctrl_tlast), + .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), + .m_axis_ctrl_tready (m_core_ctrl_tready), + .device_id (device_id), + .rfnoc_core_config (rfnoc_core_config), + .rfnoc_core_status (rfnoc_core_status) + ); + + + //--------------------------------------------------------------------------- + // Blocks + //--------------------------------------------------------------------------- + + //----------------------------------- + // radio0 + //----------------------------------- + + wire radio0_radio_clk; + wire [BLOCK_CHDR_W-1:0] s_radio0_in_3_tdata , s_radio0_in_2_tdata , s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_3_tlast , s_radio0_in_2_tlast , s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_3_tvalid, s_radio0_in_2_tvalid, s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_3_tready, s_radio0_in_2_tready, s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio0_out_3_tdata , m_radio0_out_2_tdata , m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_3_tlast , m_radio0_out_2_tlast , m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_3_tvalid, m_radio0_out_2_tvalid, m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_3_tready, m_radio0_out_2_tready, m_radio0_out_1_tready, m_radio0_out_0_tready; + + // ctrlport + wire [ 0:0] radio0_m_ctrlport_req_wr; + wire [ 0:0] radio0_m_ctrlport_req_rd; + wire [ 19:0] radio0_m_ctrlport_req_addr; + wire [ 31:0] radio0_m_ctrlport_req_data; + wire [ 3:0] radio0_m_ctrlport_req_byte_en; + wire [ 0:0] radio0_m_ctrlport_req_has_time; + wire [ 63:0] radio0_m_ctrlport_req_time; + wire [ 0:0] radio0_m_ctrlport_resp_ack; + wire [ 1:0] radio0_m_ctrlport_resp_status; + wire [ 31:0] radio0_m_ctrlport_resp_data; + // time + wire [ 63:0] radio0_radio_time; + // radio + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID (2), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (4), + .NIPC (RADIO_NIPC), + .ITEM_W (32), + .MTU (BLOCK_MTU) + ) b_radio0_0 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio0_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), + .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), + .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio0_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), + .m_ctrlport_req_time (radio0_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), + .radio_time (radio0_radio_time), + .radio_rx_data (radio0_radio_rx_data), + .radio_rx_stb (radio0_radio_rx_stb), + .radio_rx_running (radio0_radio_rx_running), + .radio_tx_data (radio0_radio_tx_data), + .radio_tx_stb (radio0_radio_tx_stb), + .radio_tx_running (radio0_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio0_in_3_tdata , s_radio0_in_2_tdata , s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_3_tlast , s_radio0_in_2_tlast , s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_3_tvalid, s_radio0_in_2_tvalid, s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_3_tready, s_radio0_in_2_tready, s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_3_tdata , m_radio0_out_2_tdata , m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_3_tlast , m_radio0_out_2_tlast , m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_3_tvalid, m_radio0_out_2_tvalid, m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_3_tready, m_radio0_out_2_tready, m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) + ); + + //----------------------------------- + // radio1 + //----------------------------------- + + wire radio1_radio_clk; + wire [BLOCK_CHDR_W-1:0] s_radio1_in_3_tdata , s_radio1_in_2_tdata , s_radio1_in_1_tdata , s_radio1_in_0_tdata ; + wire s_radio1_in_3_tlast , s_radio1_in_2_tlast , s_radio1_in_1_tlast , s_radio1_in_0_tlast ; + wire s_radio1_in_3_tvalid, s_radio1_in_2_tvalid, s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; + wire s_radio1_in_3_tready, s_radio1_in_2_tready, s_radio1_in_1_tready, s_radio1_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio1_out_3_tdata , m_radio1_out_2_tdata , m_radio1_out_1_tdata , m_radio1_out_0_tdata ; + wire m_radio1_out_3_tlast , m_radio1_out_2_tlast , m_radio1_out_1_tlast , m_radio1_out_0_tlast ; + wire m_radio1_out_3_tvalid, m_radio1_out_2_tvalid, m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; + wire m_radio1_out_3_tready, m_radio1_out_2_tready, m_radio1_out_1_tready, m_radio1_out_0_tready; + + // ctrlport + wire [ 0:0] radio1_m_ctrlport_req_wr; + wire [ 0:0] radio1_m_ctrlport_req_rd; + wire [ 19:0] radio1_m_ctrlport_req_addr; + wire [ 31:0] radio1_m_ctrlport_req_data; + wire [ 3:0] radio1_m_ctrlport_req_byte_en; + wire [ 0:0] radio1_m_ctrlport_req_has_time; + wire [ 63:0] radio1_m_ctrlport_req_time; + wire [ 0:0] radio1_m_ctrlport_resp_ack; + wire [ 1:0] radio1_m_ctrlport_resp_status; + wire [ 31:0] radio1_m_ctrlport_resp_data; + // time + wire [ 63:0] radio1_radio_time; + // radio + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; + + rfnoc_block_radio #( + .THIS_PORTID (3), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (4), + .NIPC (RADIO_NIPC), + .ITEM_W (32), + .MTU (BLOCK_MTU) + ) b_radio1_1 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .radio_clk (radio1_radio_clk), + .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), + .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), + .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), + .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), + .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), + .m_ctrlport_req_data (radio1_m_ctrlport_req_data), + .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), + .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), + .m_ctrlport_req_time (radio1_m_ctrlport_req_time), + .m_ctrlport_resp_ack (radio1_m_ctrlport_resp_ack), + .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), + .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), + .radio_time (radio1_radio_time), + .radio_rx_data (radio1_radio_rx_data), + .radio_rx_stb (radio1_radio_rx_stb), + .radio_rx_running (radio1_radio_rx_running), + .radio_tx_data (radio1_radio_tx_data), + .radio_tx_stb (radio1_radio_tx_stb), + .radio_tx_running (radio1_radio_tx_running), + .s_rfnoc_chdr_tdata ({s_radio1_in_3_tdata , s_radio1_in_2_tdata , s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_3_tlast , s_radio1_in_2_tlast , s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_3_tvalid, s_radio1_in_2_tvalid, s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_3_tready, s_radio1_in_2_tready, s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_3_tdata , m_radio1_out_2_tdata , m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_3_tlast , m_radio1_out_2_tlast , m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_3_tvalid, m_radio1_out_2_tvalid, m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_3_tready, m_radio1_out_2_tready, m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_radio1_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) + ); + + //----------------------------------- + // replay0 + //----------------------------------- + + wire replay0_mem_clk; + wire [BLOCK_CHDR_W-1:0] s_replay0_in_7_tdata , s_replay0_in_6_tdata , s_replay0_in_5_tdata , s_replay0_in_4_tdata , s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ; + wire s_replay0_in_7_tlast , s_replay0_in_6_tlast , s_replay0_in_5_tlast , s_replay0_in_4_tlast , s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ; + wire s_replay0_in_7_tvalid, s_replay0_in_6_tvalid, s_replay0_in_5_tvalid, s_replay0_in_4_tvalid, s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; + wire s_replay0_in_7_tready, s_replay0_in_6_tready, s_replay0_in_5_tready, s_replay0_in_4_tready, s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_replay0_out_7_tdata , m_replay0_out_6_tdata , m_replay0_out_5_tdata , m_replay0_out_4_tdata , m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ; + wire m_replay0_out_7_tlast , m_replay0_out_6_tlast , m_replay0_out_5_tlast , m_replay0_out_4_tlast , m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ; + wire m_replay0_out_7_tvalid, m_replay0_out_6_tvalid, m_replay0_out_5_tvalid, m_replay0_out_4_tvalid, m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; + wire m_replay0_out_7_tready, m_replay0_out_6_tready, m_replay0_out_5_tready, m_replay0_out_4_tready, m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready; + + // axi_ram + wire [ 0:0] replay0_axi_rst; + wire [ 7:0] replay0_m_axi_awid; + wire [ 383:0] replay0_m_axi_awaddr; + wire [ 63:0] replay0_m_axi_awlen; + wire [ 23:0] replay0_m_axi_awsize; + wire [ 15:0] replay0_m_axi_awburst; + wire [ 7:0] replay0_m_axi_awlock; + wire [ 31:0] replay0_m_axi_awcache; + wire [ 23:0] replay0_m_axi_awprot; + wire [ 31:0] replay0_m_axi_awqos; + wire [ 31:0] replay0_m_axi_awregion; + wire [ 7:0] replay0_m_axi_awuser; + wire [ 7:0] replay0_m_axi_awvalid; + wire [ 7:0] replay0_m_axi_awready; + wire [4191:0] replay0_m_axi_wdata; + wire [ 511:0] replay0_m_axi_wstrb; + wire [ 7:0] replay0_m_axi_wlast; + wire [ 7:0] replay0_m_axi_wuser; + wire [ 7:0] replay0_m_axi_wvalid; + wire [ 7:0] replay0_m_axi_wready; + wire [ 7:0] replay0_m_axi_bid; + wire [ 15:0] replay0_m_axi_bresp; + wire [ 7:0] replay0_m_axi_buser; + wire [ 7:0] replay0_m_axi_bvalid; + wire [ 7:0] replay0_m_axi_bready; + wire [ 7:0] replay0_m_axi_arid; + wire [ 383:0] replay0_m_axi_araddr; + wire [ 63:0] replay0_m_axi_arlen; + wire [ 23:0] replay0_m_axi_arsize; + wire [ 15:0] replay0_m_axi_arburst; + wire [ 7:0] replay0_m_axi_arlock; + wire [ 31:0] replay0_m_axi_arcache; + wire [ 31:0] replay0_m_axi_arprot; + wire [ 31:0] replay0_m_axi_arqos; + wire [ 31:0] replay0_m_axi_arregion; + wire [ 7:0] replay0_m_axi_aruser; + wire [ 7:0] replay0_m_axi_arvalid; + wire [ 7:0] replay0_m_axi_arready; + wire [ 7:0] replay0_m_axi_rid; + wire [4191:0] replay0_m_axi_rdata; + wire [ 15:0] replay0_m_axi_rresp; + wire [ 7:0] replay0_m_axi_rlast; + wire [ 7:0] replay0_m_axi_ruser; + wire [ 7:0] replay0_m_axi_rvalid; + wire [ 7:0] replay0_m_axi_rready; + + rfnoc_block_replay #( + .THIS_PORTID (4), + .CHDR_W (BLOCK_CHDR_W), + .NUM_PORTS (8), + .MEM_DATA_W (128), + .MEM_ADDR_W (32), + .MTU (BLOCK_MTU) + ) b_replay0_2 ( + .rfnoc_chdr_clk (rfnoc_chdr_clk), + .rfnoc_ctrl_clk (rfnoc_ctrl_clk), + .mem_clk (replay0_mem_clk), + .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), + .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), + .axi_rst (replay0_axi_rst), + .m_axi_awid (replay0_m_axi_awid), + .m_axi_awaddr (replay0_m_axi_awaddr), + .m_axi_awlen (replay0_m_axi_awlen), + .m_axi_awsize (replay0_m_axi_awsize), + .m_axi_awburst (replay0_m_axi_awburst), + .m_axi_awlock (replay0_m_axi_awlock), + .m_axi_awcache (replay0_m_axi_awcache), + .m_axi_awprot (replay0_m_axi_awprot), + .m_axi_awqos (replay0_m_axi_awqos), + .m_axi_awregion (replay0_m_axi_awregion), + .m_axi_awuser (replay0_m_axi_awuser), + .m_axi_awvalid (replay0_m_axi_awvalid), + .m_axi_awready (replay0_m_axi_awready), + .m_axi_wdata (replay0_m_axi_wdata), + .m_axi_wstrb (replay0_m_axi_wstrb), + .m_axi_wlast (replay0_m_axi_wlast), + .m_axi_wuser (replay0_m_axi_wuser), + .m_axi_wvalid (replay0_m_axi_wvalid), + .m_axi_wready (replay0_m_axi_wready), + .m_axi_bid (replay0_m_axi_bid), + .m_axi_bresp (replay0_m_axi_bresp), + .m_axi_buser (replay0_m_axi_buser), + .m_axi_bvalid (replay0_m_axi_bvalid), + .m_axi_bready (replay0_m_axi_bready), + .m_axi_arid (replay0_m_axi_arid), + .m_axi_araddr (replay0_m_axi_araddr), + .m_axi_arlen (replay0_m_axi_arlen), + .m_axi_arsize (replay0_m_axi_arsize), + .m_axi_arburst (replay0_m_axi_arburst), + .m_axi_arlock (replay0_m_axi_arlock), + .m_axi_arcache (replay0_m_axi_arcache), + .m_axi_arprot (replay0_m_axi_arprot), + .m_axi_arqos (replay0_m_axi_arqos), + .m_axi_arregion (replay0_m_axi_arregion), + .m_axi_aruser (replay0_m_axi_aruser), + .m_axi_arvalid (replay0_m_axi_arvalid), + .m_axi_arready (replay0_m_axi_arready), + .m_axi_rid (replay0_m_axi_rid), + .m_axi_rdata (replay0_m_axi_rdata), + .m_axi_rresp (replay0_m_axi_rresp), + .m_axi_rlast (replay0_m_axi_rlast), + .m_axi_ruser (replay0_m_axi_ruser), + .m_axi_rvalid (replay0_m_axi_rvalid), + .m_axi_rready (replay0_m_axi_rready), + .s_rfnoc_chdr_tdata ({s_replay0_in_7_tdata , s_replay0_in_6_tdata , s_replay0_in_5_tdata , s_replay0_in_4_tdata , s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_replay0_in_7_tlast , s_replay0_in_6_tlast , s_replay0_in_5_tlast , s_replay0_in_4_tlast , s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_replay0_in_7_tvalid, s_replay0_in_6_tvalid, s_replay0_in_5_tvalid, s_replay0_in_4_tvalid, s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_replay0_in_7_tready, s_replay0_in_6_tready, s_replay0_in_5_tready, s_replay0_in_4_tready, s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_replay0_out_7_tdata , m_replay0_out_6_tdata , m_replay0_out_5_tdata , m_replay0_out_4_tdata , m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_replay0_out_7_tlast , m_replay0_out_6_tlast , m_replay0_out_5_tlast , m_replay0_out_4_tlast , m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_replay0_out_7_tvalid, m_replay0_out_6_tvalid, m_replay0_out_5_tvalid, m_replay0_out_4_tvalid, m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_replay0_out_7_tready, m_replay0_out_6_tready, m_replay0_out_5_tready, m_replay0_out_4_tready, m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}), + .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata), + .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast), + .s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid), + .s_rfnoc_ctrl_tready (s_replay0_ctrl_tready), + .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata), + .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast), + .m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid), + .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) + ); + + //--------------------------------------------------------------------------- + // Static Router + //--------------------------------------------------------------------------- + + assign s_radio0_in_0_tdata = m_ep0_out0_tdata; + assign s_radio0_in_0_tlast = m_ep0_out0_tlast; + assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; + assign m_ep0_out0_tready = s_radio0_in_0_tready; + + assign s_ep0_in0_tdata = m_radio0_out_0_tdata; + assign s_ep0_in0_tlast = m_radio0_out_0_tlast; + assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; + assign m_radio0_out_0_tready = s_ep0_in0_tready; + + assign s_radio0_in_1_tdata = m_ep1_out0_tdata; + assign s_radio0_in_1_tlast = m_ep1_out0_tlast; + assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; + assign m_ep1_out0_tready = s_radio0_in_1_tready; + + assign s_ep1_in0_tdata = m_radio0_out_1_tdata; + assign s_ep1_in0_tlast = m_radio0_out_1_tlast; + assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; + assign m_radio0_out_1_tready = s_ep1_in0_tready; + + assign s_radio0_in_2_tdata = m_ep2_out0_tdata; + assign s_radio0_in_2_tlast = m_ep2_out0_tlast; + assign s_radio0_in_2_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_radio0_in_2_tready; + + assign s_ep2_in0_tdata = m_radio0_out_2_tdata; + assign s_ep2_in0_tlast = m_radio0_out_2_tlast; + assign s_ep2_in0_tvalid = m_radio0_out_2_tvalid; + assign m_radio0_out_2_tready = s_ep2_in0_tready; + + assign s_radio0_in_3_tdata = m_ep3_out0_tdata; + assign s_radio0_in_3_tlast = m_ep3_out0_tlast; + assign s_radio0_in_3_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_radio0_in_3_tready; + + assign s_ep3_in0_tdata = m_radio0_out_3_tdata; + assign s_ep3_in0_tlast = m_radio0_out_3_tlast; + assign s_ep3_in0_tvalid = m_radio0_out_3_tvalid; + assign m_radio0_out_3_tready = s_ep3_in0_tready; + + assign s_radio1_in_0_tdata = m_ep4_out0_tdata; + assign s_radio1_in_0_tlast = m_ep4_out0_tlast; + assign s_radio1_in_0_tvalid = m_ep4_out0_tvalid; + assign m_ep4_out0_tready = s_radio1_in_0_tready; + + assign s_ep4_in0_tdata = m_radio1_out_0_tdata; + assign s_ep4_in0_tlast = m_radio1_out_0_tlast; + assign s_ep4_in0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ep4_in0_tready; + + assign s_radio1_in_1_tdata = m_ep5_out0_tdata; + assign s_radio1_in_1_tlast = m_ep5_out0_tlast; + assign s_radio1_in_1_tvalid = m_ep5_out0_tvalid; + assign m_ep5_out0_tready = s_radio1_in_1_tready; + + assign s_ep5_in0_tdata = m_radio1_out_1_tdata; + assign s_ep5_in0_tlast = m_radio1_out_1_tlast; + assign s_ep5_in0_tvalid = m_radio1_out_1_tvalid; + assign m_radio1_out_1_tready = s_ep5_in0_tready; + + assign s_radio1_in_2_tdata = m_ep6_out0_tdata; + assign s_radio1_in_2_tlast = m_ep6_out0_tlast; + assign s_radio1_in_2_tvalid = m_ep6_out0_tvalid; + assign m_ep6_out0_tready = s_radio1_in_2_tready; + + assign s_ep6_in0_tdata = m_radio1_out_2_tdata; + assign s_ep6_in0_tlast = m_radio1_out_2_tlast; + assign s_ep6_in0_tvalid = m_radio1_out_2_tvalid; + assign m_radio1_out_2_tready = s_ep6_in0_tready; + + assign s_radio1_in_3_tdata = m_ep7_out0_tdata; + assign s_radio1_in_3_tlast = m_ep7_out0_tlast; + assign s_radio1_in_3_tvalid = m_ep7_out0_tvalid; + assign m_ep7_out0_tready = s_radio1_in_3_tready; + + assign s_ep7_in0_tdata = m_radio1_out_3_tdata; + assign s_ep7_in0_tlast = m_radio1_out_3_tlast; + assign s_ep7_in0_tvalid = m_radio1_out_3_tvalid; + assign m_radio1_out_3_tready = s_ep7_in0_tready; + + assign s_replay0_in_0_tdata = m_ep8_out0_tdata; + assign s_replay0_in_0_tlast = m_ep8_out0_tlast; + assign s_replay0_in_0_tvalid = m_ep8_out0_tvalid; + assign m_ep8_out0_tready = s_replay0_in_0_tready; + + assign s_ep8_in0_tdata = m_replay0_out_0_tdata; + assign s_ep8_in0_tlast = m_replay0_out_0_tlast; + assign s_ep8_in0_tvalid = m_replay0_out_0_tvalid; + assign m_replay0_out_0_tready = s_ep8_in0_tready; + + assign s_replay0_in_1_tdata = m_ep9_out0_tdata; + assign s_replay0_in_1_tlast = m_ep9_out0_tlast; + assign s_replay0_in_1_tvalid = m_ep9_out0_tvalid; + assign m_ep9_out0_tready = s_replay0_in_1_tready; + + assign s_ep9_in0_tdata = m_replay0_out_1_tdata; + assign s_ep9_in0_tlast = m_replay0_out_1_tlast; + assign s_ep9_in0_tvalid = m_replay0_out_1_tvalid; + assign m_replay0_out_1_tready = s_ep9_in0_tready; + + assign s_replay0_in_2_tdata = m_ep10_out0_tdata; + assign s_replay0_in_2_tlast = m_ep10_out0_tlast; + assign s_replay0_in_2_tvalid = m_ep10_out0_tvalid; + assign m_ep10_out0_tready = s_replay0_in_2_tready; + + assign s_ep10_in0_tdata = m_replay0_out_2_tdata; + assign s_ep10_in0_tlast = m_replay0_out_2_tlast; + assign s_ep10_in0_tvalid = m_replay0_out_2_tvalid; + assign m_replay0_out_2_tready = s_ep10_in0_tready; + + assign s_replay0_in_3_tdata = m_ep11_out0_tdata; + assign s_replay0_in_3_tlast = m_ep11_out0_tlast; + assign s_replay0_in_3_tvalid = m_ep11_out0_tvalid; + assign m_ep11_out0_tready = s_replay0_in_3_tready; + + assign s_ep11_in0_tdata = m_replay0_out_3_tdata; + assign s_ep11_in0_tlast = m_replay0_out_3_tlast; + assign s_ep11_in0_tvalid = m_replay0_out_3_tvalid; + assign m_replay0_out_3_tready = s_ep11_in0_tready; + + assign s_replay0_in_4_tdata = m_ep12_out0_tdata; + assign s_replay0_in_4_tlast = m_ep12_out0_tlast; + assign s_replay0_in_4_tvalid = m_ep12_out0_tvalid; + assign m_ep12_out0_tready = s_replay0_in_4_tready; + + assign s_ep12_in0_tdata = m_replay0_out_4_tdata; + assign s_ep12_in0_tlast = m_replay0_out_4_tlast; + assign s_ep12_in0_tvalid = m_replay0_out_4_tvalid; + assign m_replay0_out_4_tready = s_ep12_in0_tready; + + assign s_replay0_in_5_tdata = m_ep13_out0_tdata; + assign s_replay0_in_5_tlast = m_ep13_out0_tlast; + assign s_replay0_in_5_tvalid = m_ep13_out0_tvalid; + assign m_ep13_out0_tready = s_replay0_in_5_tready; + + assign s_ep13_in0_tdata = m_replay0_out_5_tdata; + assign s_ep13_in0_tlast = m_replay0_out_5_tlast; + assign s_ep13_in0_tvalid = m_replay0_out_5_tvalid; + assign m_replay0_out_5_tready = s_ep13_in0_tready; + + assign s_replay0_in_6_tdata = m_ep14_out0_tdata; + assign s_replay0_in_6_tlast = m_ep14_out0_tlast; + assign s_replay0_in_6_tvalid = m_ep14_out0_tvalid; + assign m_ep14_out0_tready = s_replay0_in_6_tready; + + assign s_ep14_in0_tdata = m_replay0_out_6_tdata; + assign s_ep14_in0_tlast = m_replay0_out_6_tlast; + assign s_ep14_in0_tvalid = m_replay0_out_6_tvalid; + assign m_replay0_out_6_tready = s_ep14_in0_tready; + + assign s_replay0_in_7_tdata = m_ep15_out0_tdata; + assign s_replay0_in_7_tlast = m_ep15_out0_tlast; + assign s_replay0_in_7_tvalid = m_ep15_out0_tvalid; + assign m_ep15_out0_tready = s_replay0_in_7_tready; + + assign s_ep15_in0_tdata = m_replay0_out_7_tdata; + assign s_ep15_in0_tlast = m_replay0_out_7_tlast; + assign s_ep15_in0_tvalid = m_replay0_out_7_tvalid; + assign m_replay0_out_7_tready = s_ep15_in0_tready; + + + //--------------------------------------------------------------------------- + // Unused Ports + //--------------------------------------------------------------------------- + + + + //--------------------------------------------------------------------------- + // Clock Domains + //--------------------------------------------------------------------------- + + assign radio0_radio_clk = radio0_clk; + assign radio1_radio_clk = radio1_clk; + assign replay0_mem_clk = dram_clk; + + + //--------------------------------------------------------------------------- + // IO Port Connection + //--------------------------------------------------------------------------- + + // Master/Slave Connections: + assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; + assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; + assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; + assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; + assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; + assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; + assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; + assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; + assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; + assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; + + assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; + assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; + assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; + assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; + assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; + assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; + assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; + assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; + assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; + assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; + + assign radio0_radio_rx_data = radio_rx_data_radio0; + assign radio0_radio_rx_stb = radio_rx_stb_radio0; + assign radio_rx_running_radio0 = radio0_radio_rx_running; + assign radio_tx_data_radio0 = radio0_radio_tx_data; + assign radio0_radio_tx_stb = radio_tx_stb_radio0; + assign radio_tx_running_radio0 = radio0_radio_tx_running; + + assign radio1_radio_rx_data = radio_rx_data_radio1; + assign radio1_radio_rx_stb = radio_rx_stb_radio1; + assign radio_rx_running_radio1 = radio1_radio_rx_running; + assign radio_tx_data_radio1 = radio1_radio_tx_data; + assign radio1_radio_tx_stb = radio_tx_stb_radio1; + assign radio_tx_running_radio1 = radio1_radio_tx_running; + + assign replay0_axi_rst = axi_rst; + assign m_axi_awid = replay0_m_axi_awid; + assign m_axi_awaddr = replay0_m_axi_awaddr; + assign m_axi_awlen = replay0_m_axi_awlen; + assign m_axi_awsize = replay0_m_axi_awsize; + assign m_axi_awburst = replay0_m_axi_awburst; + assign m_axi_awlock = replay0_m_axi_awlock; + assign m_axi_awcache = replay0_m_axi_awcache; + assign m_axi_awprot = replay0_m_axi_awprot; + assign m_axi_awqos = replay0_m_axi_awqos; + assign m_axi_awregion = replay0_m_axi_awregion; + assign m_axi_awuser = replay0_m_axi_awuser; + assign m_axi_awvalid = replay0_m_axi_awvalid; + assign replay0_m_axi_awready = m_axi_awready; + assign m_axi_wdata = replay0_m_axi_wdata; + assign m_axi_wstrb = replay0_m_axi_wstrb; + assign m_axi_wlast = replay0_m_axi_wlast; + assign m_axi_wuser = replay0_m_axi_wuser; + assign m_axi_wvalid = replay0_m_axi_wvalid; + assign replay0_m_axi_wready = m_axi_wready; + assign replay0_m_axi_bid = m_axi_bid; + assign replay0_m_axi_bresp = m_axi_bresp; + assign replay0_m_axi_buser = m_axi_buser; + assign replay0_m_axi_bvalid = m_axi_bvalid; + assign m_axi_bready = replay0_m_axi_bready; + assign m_axi_arid = replay0_m_axi_arid; + assign m_axi_araddr = replay0_m_axi_araddr; + assign m_axi_arlen = replay0_m_axi_arlen; + assign m_axi_arsize = replay0_m_axi_arsize; + assign m_axi_arburst = replay0_m_axi_arburst; + assign m_axi_arlock = replay0_m_axi_arlock; + assign m_axi_arcache = replay0_m_axi_arcache; + assign m_axi_arprot = replay0_m_axi_arprot; + assign m_axi_arqos = replay0_m_axi_arqos; + assign m_axi_arregion = replay0_m_axi_arregion; + assign m_axi_aruser = replay0_m_axi_aruser; + assign m_axi_arvalid = replay0_m_axi_arvalid; + assign replay0_m_axi_arready = m_axi_arready; + assign replay0_m_axi_rid = m_axi_rid; + assign replay0_m_axi_rdata = m_axi_rdata; + assign replay0_m_axi_rresp = m_axi_rresp; + assign replay0_m_axi_rlast = m_axi_rlast; + assign replay0_m_axi_ruser = m_axi_ruser; + assign replay0_m_axi_rvalid = m_axi_rvalid; + assign m_axi_rready = replay0_m_axi_rready; + + // Broadcaster/Listener Connections: + assign radio0_radio_time = radio_time0; + + assign radio1_radio_time = radio_time1; + +endmodule + + +`default_nettype wire diff --git a/top/x400/x410_400_128_rfnoc_image_core.vh b/top/x400/x440_400_d_rfnoc_image_core.vh similarity index 82% rename from top/x400/x410_400_128_rfnoc_image_core.vh rename to top/x400/x440_400_d_rfnoc_image_core.vh index a6c719b..8fbc3f4 100644 --- a/top/x400/x410_400_128_rfnoc_image_core.vh +++ b/top/x400/x440_400_d_rfnoc_image_core.vh @@ -3,7 +3,7 @@ // // SPDX-License-Identifier: LGPL-3.0-or-later // -// Header: rfnoc_image_core.vh (for x410) +// Header: rfnoc_image_core.vh (for x440) // // Description: // @@ -12,7 +12,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: x410_400_128_rfnoc_image_core.yml +// Source: x440_400_d_rfnoc_image_core.yml // `define CHDR_WIDTH 128 diff --git a/top/x400/x440_400_d_rfnoc_image_core.yml b/top/x400/x440_400_d_rfnoc_image_core.yml new file mode 100644 index 0000000..dc73ff1 --- /dev/null +++ b/top/x400/x440_400_d_rfnoc_image_core.yml @@ -0,0 +1,211 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: >- # Copyright information used in file headers + Copyright 2023 Ettus Research, a National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later +version: '1.0' # File version +chdr_width: 128 # Bit width of the CHDR bus for this image +device: 'x440' # USRP type +image_core_name: 'x440_400_d' # Name to use for the RFNoC Image Core files +default_target: 'X440_X4_400' # Default make target + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size_bytes: 131072 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size_bytes: 131072 + ep2: + ctrl: False + data: True + buff_size_bytes: 131072 + ep3: + ctrl: False + data: True + buff_size_bytes: 131072 + ep4: + ctrl: False + data: True + buff_size_bytes: 131072 + ep5: + ctrl: False + data: True + buff_size_bytes: 131072 + ep6: + ctrl: False + data: True + buff_size_bytes: 131072 + ep7: + ctrl: False + data: True + buff_size_bytes: 131072 + ep8: + ctrl: False + data: True + buff_size_bytes: 131072 + ep9: + ctrl: False + data: True + buff_size_bytes: 131072 + ep10: + ctrl: False + data: True + buff_size_bytes: 131072 + ep11: + ctrl: False + data: True + buff_size_bytes: 131072 + ep12: + ctrl: False + data: True + buff_size_bytes: 131072 + ep13: + ctrl: False + data: True + buff_size_bytes: 131072 + ep14: + ctrl: False + data: True + buff_size_bytes: 131072 + ep15: + ctrl: False + data: True + buff_size_bytes: 131072 + +# A table of which crossbar routes to include +# ------------------------------------------- +# Rows correspond to input ports and columns correspond to output ports. +# Entering a 1 includes and a 0 removes that route from the crossbar. +crossbar_routes: + # eth0 eth2 eth4 ep0 ep2 ep4 ep6 ep8 ep10 ep12 ep14 + # eth1 eth3 dma ep1 ep3 ep5 ep7 ep9 ep11 ep13 ep15 + - [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0, Lane 0) + - [ 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth1 (QSFP Port 0, Lane 1) + - [ 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth2 (QSFP Port 0, Lane 2) + - [ 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth3 (QSFP Port 0, Lane 3) + - [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth4 (NC) + - [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep0 (radio0.0) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep1 (radio0.1) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep2 (radio0.2) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep3 (radio0.3) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep4 (radio1.0) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep5 (radio1.1) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep6 (radio1.2) + - [ 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # ep7 (radio1.3) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep8 (replay0.0) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep9 (replay0.1) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep10 (replay0.2) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep11 (replay0.3) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep12 (replay0.4) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep13 (replay0.5) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep14 (replay0.6) + - [ 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep15 (replay0.7) + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 4 + NIPC: RADIO_NIPC + radio1: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 4 + NIPC: RADIO_NIPC + replay0: + block_desc: 'replay.yml' + parameters: + NUM_PORTS: 8 + MEM_DATA_W: 128 + MEM_ADDR_W: 32 + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # RF A:0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # RF A:0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # RF A:1 TX + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + # RF A:1 RX + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + # RF A:2 TX + - { srcblk: ep2, srcport: out0, dstblk: radio0, dstport: in_2 } + # RF A:2 RX + - { srcblk: radio0, srcport: out_2, dstblk: ep2, dstport: in0 } + # RF A:3 TX + - { srcblk: ep3, srcport: out0, dstblk: radio0, dstport: in_3 } + # RF A:3 RX + - { srcblk: radio0, srcport: out_3, dstblk: ep3, dstport: in0 } + # + # RF B:0 TX + - { srcblk: ep4, srcport: out0, dstblk: radio1, dstport: in_0 } + # RF B:0 RX + - { srcblk: radio1, srcport: out_0, dstblk: ep4, dstport: in0 } + # RF B:1 TX + - { srcblk: ep5, srcport: out0, dstblk: radio1, dstport: in_1 } + # RF B:1 RX + - { srcblk: radio1, srcport: out_1, dstblk: ep5, dstport: in0 } + # RF B:2 TX + - { srcblk: ep6, srcport: out0, dstblk: radio1, dstport: in_2 } + # RF B:2 RX + - { srcblk: radio1, srcport: out_2, dstblk: ep6, dstport: in0 } + # RF B:3 TX + - { srcblk: ep7, srcport: out0, dstblk: radio1, dstport: in_3 } + # RF B:3 RX + - { srcblk: radio1, srcport: out_3, dstblk: ep7, dstport: in0 } + # + # Replay Connections + - { srcblk: ep8, srcport: out0, dstblk: replay0, dstport: in_0 } + - { srcblk: replay0, srcport: out_0, dstblk: ep8, dstport: in0 } + - { srcblk: ep9, srcport: out0, dstblk: replay0, dstport: in_1 } + - { srcblk: replay0, srcport: out_1, dstblk: ep9, dstport: in0 } + - { srcblk: ep10, srcport: out0, dstblk: replay0, dstport: in_2 } + - { srcblk: replay0, srcport: out_2, dstblk: ep10, dstport: in0 } + - { srcblk: ep11, srcport: out0, dstblk: replay0, dstport: in_3 } + - { srcblk: replay0, srcport: out_3, dstblk: ep11, dstport: in0 } + - { srcblk: ep12, srcport: out0, dstblk: replay0, dstport: in_4 } + - { srcblk: replay0, srcport: out_4, dstblk: ep12, dstport: in0 } + - { srcblk: ep13, srcport: out0, dstblk: replay0, dstport: in_5 } + - { srcblk: replay0, srcport: out_5, dstblk: ep13, dstport: in0 } + - { srcblk: ep14, srcport: out0, dstblk: replay0, dstport: in_6 } + - { srcblk: replay0, srcport: out_6, dstblk: ep14, dstport: in0 } + - { srcblk: ep15, srcport: out0, dstblk: replay0, dstport: in_7 } + - { srcblk: replay0, srcport: out_7, dstblk: ep15, dstport: in0 } + # + # BSP Connections + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time } + - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } diff --git a/top/x400/x440_400_d_static_router.hex b/top/x400/x440_400_d_static_router.hex new file mode 100644 index 0000000..a23c4a3 --- /dev/null +++ b/top/x400/x440_400_d_static_router.hex @@ -0,0 +1,33 @@ +00000020 +00400440 +04400040 +00800441 +04410080 +00c00442 +044200c0 +01000443 +04430100 +01400480 +04800140 +01800481 +04810180 +01c00482 +048201c0 +02000483 +04830200 +024004c0 +04c00240 +028004c1 +04c10280 +02c004c2 +04c202c0 +030004c3 +04c30300 +034004c4 +04c40340 +038004c5 +04c50380 +03c004c6 +04c603c0 +040004c7 +04c70400 diff --git a/top/x400/x410_400_128_rfnoc_image_core.v b/top/x400/x440_400_rfnoc_image_core.v similarity index 69% rename from top/x400/x410_400_128_rfnoc_image_core.v rename to top/x400/x440_400_rfnoc_image_core.v index 6d77013..b3c93fc 100644 --- a/top/x400/x410_400_128_rfnoc_image_core.v +++ b/top/x400/x440_400_rfnoc_image_core.v @@ -3,7 +3,7 @@ // // SPDX-License-Identifier: LGPL-3.0-or-later // -// Module: rfnoc_image_core (for x410) +// Module: rfnoc_image_core (for x440) // // Description: // @@ -13,15 +13,15 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: x410_400_128_rfnoc_image_core.yml +// Source: x440_400_rfnoc_image_core.yml // `default_nettype none module rfnoc_image_core #( - parameter [31:0] CHDR_W = 128, - parameter [31:0] PORT_W = 128, + parameter [31:0] CHDR_W = 512, + parameter [31:0] PORT_W = 512, parameter [31:0] ETH0_W = 64, parameter [31:0] ETH1_W = 64, parameter [31:0] ETH2_W = 64, @@ -36,8 +36,10 @@ module rfnoc_image_core #( input wire chdr_aclk, input wire ctrl_aclk, input wire core_arst, - input wire radio_clk, - input wire radio_2x_clk, + input wire radio0_clk, + input wire radio1_clk, + input wire radio0_2x_clk, + input wire radio1_2x_clk, input wire dram_clk, // Basic input wire [ 15:0] device_id, @@ -66,68 +68,70 @@ module rfnoc_image_core #( input wire [ 0:0] m_ctrlport_radio1_resp_ack, input wire [ 1:0] m_ctrlport_radio1_resp_status, input wire [ 31:0] m_ctrlport_radio1_resp_data, - // time - input wire [ 63:0] radio_time, + // time0 + input wire [ 63:0] radio_time0, + // time1 + input wire [ 63:0] radio_time1, // radio0 - input wire [ 255:0] radio_rx_data_radio0, - input wire [ 7:0] radio_rx_stb_radio0, - output wire [ 7:0] radio_rx_running_radio0, - output wire [ 255:0] radio_tx_data_radio0, - input wire [ 7:0] radio_tx_stb_radio0, - output wire [ 7:0] radio_tx_running_radio0, + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, // radio1 - input wire [ 255:0] radio_rx_data_radio1, - input wire [ 7:0] radio_rx_stb_radio1, - output wire [ 7:0] radio_rx_running_radio1, - output wire [ 255:0] radio_tx_data_radio1, - input wire [ 7:0] radio_tx_stb_radio1, - output wire [ 7:0] radio_tx_running_radio1, + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, // dram input wire [ 0:0] axi_rst, - output wire [ 3:0] m_axi_awid, - output wire [ 191:0] m_axi_awaddr, - output wire [ 31:0] m_axi_awlen, - output wire [ 11:0] m_axi_awsize, - output wire [ 7:0] m_axi_awburst, - output wire [ 3:0] m_axi_awlock, - output wire [ 15:0] m_axi_awcache, - output wire [ 11:0] m_axi_awprot, - output wire [ 15:0] m_axi_awqos, - output wire [ 15:0] m_axi_awregion, - output wire [ 3:0] m_axi_awuser, - output wire [ 3:0] m_axi_awvalid, - input wire [ 3:0] m_axi_awready, - output wire [2047:0] m_axi_wdata, - output wire [ 255:0] m_axi_wstrb, - output wire [ 3:0] m_axi_wlast, - output wire [ 3:0] m_axi_wuser, - output wire [ 3:0] m_axi_wvalid, - input wire [ 3:0] m_axi_wready, - input wire [ 3:0] m_axi_bid, - input wire [ 7:0] m_axi_bresp, - input wire [ 3:0] m_axi_buser, - input wire [ 3:0] m_axi_bvalid, - output wire [ 3:0] m_axi_bready, - output wire [ 3:0] m_axi_arid, - output wire [ 191:0] m_axi_araddr, - output wire [ 31:0] m_axi_arlen, - output wire [ 11:0] m_axi_arsize, - output wire [ 7:0] m_axi_arburst, - output wire [ 3:0] m_axi_arlock, - output wire [ 15:0] m_axi_arcache, - output wire [ 11:0] m_axi_arprot, - output wire [ 15:0] m_axi_arqos, - output wire [ 15:0] m_axi_arregion, - output wire [ 3:0] m_axi_aruser, - output wire [ 3:0] m_axi_arvalid, - input wire [ 3:0] m_axi_arready, - input wire [ 3:0] m_axi_rid, - input wire [2047:0] m_axi_rdata, - input wire [ 7:0] m_axi_rresp, - input wire [ 3:0] m_axi_rlast, - input wire [ 3:0] m_axi_ruser, - input wire [ 3:0] m_axi_rvalid, - output wire [ 3:0] m_axi_rready, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, // Transport Adapters /////////////// @@ -191,21 +195,21 @@ module rfnoc_image_core #( localparam BLOCK_CHDR_W = 128; localparam BYTE_MTU = MTU + $clog2(CHDR_W/8); localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8); - localparam EP0_W = 128; + localparam EP0_W = 512; localparam EP0_MTU = BYTE_MTU - $clog2(EP0_W/8); - localparam EP1_W = 128; + localparam EP1_W = 512; localparam EP1_MTU = BYTE_MTU - $clog2(EP1_W/8); - localparam EP2_W = 128; + localparam EP2_W = 512; localparam EP2_MTU = BYTE_MTU - $clog2(EP2_W/8); - localparam EP3_W = 128; + localparam EP3_W = 512; localparam EP3_MTU = BYTE_MTU - $clog2(EP3_W/8); - localparam EP4_W = 128; + localparam EP4_W = 512; localparam EP4_MTU = BYTE_MTU - $clog2(EP4_W/8); - localparam EP5_W = 128; + localparam EP5_W = 512; localparam EP5_MTU = BYTE_MTU - $clog2(EP5_W/8); - localparam EP6_W = 128; + localparam EP6_W = 512; localparam EP6_MTU = BYTE_MTU - $clog2(EP6_W/8); - localparam EP7_W = 128; + localparam EP7_W = 512; localparam EP7_MTU = BYTE_MTU - $clog2(EP7_W/8); wire rfnoc_chdr_clk, rfnoc_chdr_rst; @@ -286,19 +290,19 @@ module rfnoc_image_core #( .NPORTS (14), .CHDR_WIDTHS ({EP7_W, EP6_W, EP5_W, EP4_W, EP3_W, EP2_W, EP1_W, EP0_W, DMA_W, ETH4_W, ETH3_W, ETH2_W, ETH1_W, ETH0_W}), .DEFAULT_PORT (0), - .ROUTES ({ 14'b11111111111111, - 14'b11111111111111, - 14'b11111111111111, - 14'b11111111111111, - 14'b11111111111111, - 14'b11111111111111, - 14'b11111111111111, - 14'b11111111111111, + .ROUTES ({ 14'b00000000110001, + 14'b00000000110001, + 14'b00000000110001, + 14'b00000000110001, + 14'b00000000110001, + 14'b00000000110001, + 14'b00000000110001, + 14'b00000000110001, 14'b11111111100000, 14'b11111111010000, - 14'b11111111001000, - 14'b11111111000100, - 14'b11111111000010, + 14'b00000000000000, + 14'b00000000000000, + 14'b00000000000000, 14'b11111111000001 }), .BYTE_MTU (BYTE_MTU), .ROUTE_TBL_SIZE (6), @@ -311,14 +315,14 @@ module rfnoc_image_core #( .clk (rfnoc_chdr_clk), .reset (rfnoc_chdr_rst), .device_id (device_id), - .s_axis_tdata ({ep7_to_xb_tdata , ep6_to_xb_tdata , ep5_to_xb_tdata , ep4_to_xb_tdata , ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , s_eth3_tdata , s_eth2_tdata , s_eth1_tdata , s_eth0_tdata }), - .s_axis_tlast ({ep7_to_xb_tlast , ep6_to_xb_tlast , ep5_to_xb_tlast , ep4_to_xb_tlast , ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , s_eth3_tlast , s_eth2_tlast , s_eth1_tlast , s_eth0_tlast }), - .s_axis_tvalid ({ep7_to_xb_tvalid, ep6_to_xb_tvalid, ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, s_eth3_tvalid, s_eth2_tvalid, s_eth1_tvalid, s_eth0_tvalid}), - .s_axis_tready ({ep7_to_xb_tready, ep6_to_xb_tready, ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, s_eth3_tready, s_eth2_tready, s_eth1_tready, s_eth0_tready}), - .m_axis_tdata ({xb_to_ep7_tdata , xb_to_ep6_tdata , xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , m_eth3_tdata , m_eth2_tdata , m_eth1_tdata , m_eth0_tdata }), - .m_axis_tlast ({xb_to_ep7_tlast , xb_to_ep6_tlast , xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , m_eth3_tlast , m_eth2_tlast , m_eth1_tlast , m_eth0_tlast }), - .m_axis_tvalid ({xb_to_ep7_tvalid, xb_to_ep6_tvalid, xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, m_eth3_tvalid, m_eth2_tvalid, m_eth1_tvalid, m_eth0_tvalid}), - .m_axis_tready ({xb_to_ep7_tready, xb_to_ep6_tready, xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, m_eth3_tready, m_eth2_tready, m_eth1_tready, m_eth0_tready}), + .s_axis_tdata ({ep7_to_xb_tdata , ep6_to_xb_tdata , ep5_to_xb_tdata , ep4_to_xb_tdata , ep3_to_xb_tdata , ep2_to_xb_tdata , ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata , s_eth4_tdata , {PORT_W{1'b0}}, {PORT_W{1'b0}}, {PORT_W{1'b0}}, s_eth0_tdata }), + .s_axis_tlast ({ep7_to_xb_tlast , ep6_to_xb_tlast , ep5_to_xb_tlast , ep4_to_xb_tlast , ep3_to_xb_tlast , ep2_to_xb_tlast , ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast , s_eth4_tlast , 1'b0, 1'b0, 1'b0, s_eth0_tlast }), + .s_axis_tvalid ({ep7_to_xb_tvalid, ep6_to_xb_tvalid, ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth4_tvalid, 1'b0, 1'b0, 1'b0, s_eth0_tvalid}), + .s_axis_tready ({ep7_to_xb_tready, ep6_to_xb_tready, ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth4_tready, 1'bZ, 1'bZ, 1'bZ, s_eth0_tready}), + .m_axis_tdata ({xb_to_ep7_tdata , xb_to_ep6_tdata , xb_to_ep5_tdata , xb_to_ep4_tdata , xb_to_ep3_tdata , xb_to_ep2_tdata , xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata , m_eth4_tdata , {PORT_W{1'bZ}}, {PORT_W{1'bZ}}, {PORT_W{1'bZ}}, m_eth0_tdata }), + .m_axis_tlast ({xb_to_ep7_tlast , xb_to_ep6_tlast , xb_to_ep5_tlast , xb_to_ep4_tlast , xb_to_ep3_tlast , xb_to_ep2_tlast , xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast , m_eth4_tlast , 1'bZ, 1'bZ, 1'bZ, m_eth0_tlast }), + .m_axis_tvalid ({xb_to_ep7_tvalid, xb_to_ep6_tvalid, xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth4_tvalid, 1'bZ, 1'bZ, 1'bZ, m_eth0_tvalid}), + .m_axis_tready ({xb_to_ep7_tready, xb_to_ep6_tready, xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth4_tready, 1'b1, 1'b1, 1'b1, m_eth0_tready}), .ext_rtcfg_stb (1'h0), .ext_rtcfg_addr (16'h0), .ext_rtcfg_data (32'h0), @@ -332,7 +336,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP0 = 2048; + localparam REQ_BUFF_SIZE_EP0 = 8192; localparam INGRESS_BUFF_SIZE_EP0 = REQ_BUFF_SIZE_EP0 == 0 ? 5 : REQ_BUFF_SIZE_EP0 < 2*(2**EP0_MTU) ? EP0_MTU+1 : @@ -403,7 +407,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP1 = 2048; + localparam REQ_BUFF_SIZE_EP1 = 8192; localparam INGRESS_BUFF_SIZE_EP1 = REQ_BUFF_SIZE_EP1 == 0 ? 5 : REQ_BUFF_SIZE_EP1 < 2*(2**EP1_MTU) ? EP1_MTU+1 : @@ -474,7 +478,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP2 = 2048; + localparam REQ_BUFF_SIZE_EP2 = 8192; localparam INGRESS_BUFF_SIZE_EP2 = REQ_BUFF_SIZE_EP2 == 0 ? 5 : REQ_BUFF_SIZE_EP2 < 2*(2**EP2_MTU) ? EP2_MTU+1 : @@ -545,7 +549,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP3 = 2048; + localparam REQ_BUFF_SIZE_EP3 = 8192; localparam INGRESS_BUFF_SIZE_EP3 = REQ_BUFF_SIZE_EP3 == 0 ? 5 : REQ_BUFF_SIZE_EP3 < 2*(2**EP3_MTU) ? EP3_MTU+1 : @@ -616,7 +620,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP4 = 2048; + localparam REQ_BUFF_SIZE_EP4 = 8192; localparam INGRESS_BUFF_SIZE_EP4 = REQ_BUFF_SIZE_EP4 == 0 ? 5 : REQ_BUFF_SIZE_EP4 < 2*(2**EP4_MTU) ? EP4_MTU+1 : @@ -687,7 +691,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP5 = 2048; + localparam REQ_BUFF_SIZE_EP5 = 8192; localparam INGRESS_BUFF_SIZE_EP5 = REQ_BUFF_SIZE_EP5 == 0 ? 5 : REQ_BUFF_SIZE_EP5 < 2*(2**EP5_MTU) ? EP5_MTU+1 : @@ -758,7 +762,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP6 = 2048; + localparam REQ_BUFF_SIZE_EP6 = 8192; localparam INGRESS_BUFF_SIZE_EP6 = REQ_BUFF_SIZE_EP6 == 0 ? 5 : REQ_BUFF_SIZE_EP6 < 2*(2**EP6_MTU) ? EP6_MTU+1 : @@ -829,7 +833,7 @@ module rfnoc_image_core #( // If requested buffer size is 0, use the minimum SRL-based FIFO size. // Otherwise, make sure it's at least two MTU-sized packets. - localparam REQ_BUFF_SIZE_EP7 = 2048; + localparam REQ_BUFF_SIZE_EP7 = 8192; localparam INGRESS_BUFF_SIZE_EP7 = REQ_BUFF_SIZE_EP7 == 0 ? 5 : REQ_BUFF_SIZE_EP7 < 2*(2**EP7_MTU) ? EP7_MTU+1 : @@ -915,14 +919,10 @@ module rfnoc_image_core #( wire m_radio1_ctrl_tlast, s_radio1_ctrl_tlast; wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; - wire [31:0] m_replay0_ctrl_tdata, s_replay0_ctrl_tdata; - wire m_replay0_ctrl_tlast, s_replay0_ctrl_tlast; - wire m_replay0_ctrl_tvalid, s_replay0_ctrl_tvalid; - wire m_replay0_ctrl_tready, s_replay0_ctrl_tready; axis_ctrl_crossbar_nxn #( .WIDTH (32), - .NPORTS (5), + .NPORTS (4), .TOPOLOGY ("TORUS"), .INGRESS_BUFF_SIZE(5), .ROUTER_BUFF_SIZE (5), @@ -931,14 +931,14 @@ module rfnoc_image_core #( ) ctrl_xb_i ( .clk (rfnoc_ctrl_clk), .reset (rfnoc_ctrl_rst), - .s_axis_tdata ({m_replay0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), - .s_axis_tvalid ({m_replay0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), - .s_axis_tlast ({m_replay0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), - .s_axis_tready ({m_replay0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), - .m_axis_tdata ({s_replay0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), - .m_axis_tvalid ({s_replay0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), - .m_axis_tlast ({s_replay0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), - .m_axis_tready ({s_replay0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), + .s_axis_tdata ({m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), + .s_axis_tvalid ({m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), + .s_axis_tlast ({m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), + .s_axis_tready ({m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), + .m_axis_tdata ({s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), + .m_axis_tvalid ({s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), + .m_axis_tlast ({s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), + .m_axis_tready ({s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), .deadlock_detected() ); @@ -947,14 +947,14 @@ module rfnoc_image_core #( // RFNoC Core Kernel //--------------------------------------------------------------------------- - wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; + wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status; rfnoc_core_kernel #( .PROTOVER (PROTOVER), .DEVICE_TYPE (16'hA400), .DEVICE_FAMILY ("ULTRASCALE"), .SAFE_START_CLKS (0), - .NUM_BLOCKS (3), + .NUM_BLOCKS (2), .NUM_STREAM_ENDPOINTS(8), .NUM_ENDPOINTS_CTRL (1), .NUM_TRANSPORTS (6), @@ -994,14 +994,14 @@ module rfnoc_image_core #( //----------------------------------- wire radio0_radio_clk; - wire [BLOCK_CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; - wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; - wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; - wire s_radio0_in_1_tready, s_radio0_in_0_tready; - wire [BLOCK_CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; - wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; - wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; - wire m_radio0_out_1_tready, m_radio0_out_0_tready; + wire [BLOCK_CHDR_W-1:0] s_radio0_in_3_tdata , s_radio0_in_2_tdata , s_radio0_in_1_tdata , s_radio0_in_0_tdata ; + wire s_radio0_in_3_tlast , s_radio0_in_2_tlast , s_radio0_in_1_tlast , s_radio0_in_0_tlast ; + wire s_radio0_in_3_tvalid, s_radio0_in_2_tvalid, s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; + wire s_radio0_in_3_tready, s_radio0_in_2_tready, s_radio0_in_1_tready, s_radio0_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio0_out_3_tdata , m_radio0_out_2_tdata , m_radio0_out_1_tdata , m_radio0_out_0_tdata ; + wire m_radio0_out_3_tlast , m_radio0_out_2_tlast , m_radio0_out_1_tlast , m_radio0_out_0_tlast ; + wire m_radio0_out_3_tvalid, m_radio0_out_2_tvalid, m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; + wire m_radio0_out_3_tready, m_radio0_out_2_tready, m_radio0_out_1_tready, m_radio0_out_0_tready; // ctrlport wire [ 0:0] radio0_m_ctrlport_req_wr; @@ -1017,17 +1017,17 @@ module rfnoc_image_core #( // time wire [ 63:0] radio0_radio_time; // radio - wire [ 255:0] radio0_radio_rx_data; - wire [ 7:0] radio0_radio_rx_stb; - wire [ 7:0] radio0_radio_rx_running; - wire [ 255:0] radio0_radio_tx_data; - wire [ 7:0] radio0_radio_tx_stb; - wire [ 7:0] radio0_radio_tx_running; + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (2), .CHDR_W (BLOCK_CHDR_W), - .NUM_PORTS (2), + .NUM_PORTS (4), .NIPC (RADIO_NIPC), .ITEM_W (32), .MTU (BLOCK_MTU) @@ -1054,14 +1054,14 @@ module rfnoc_image_core #( .radio_tx_data (radio0_radio_tx_data), .radio_tx_stb (radio0_radio_tx_stb), .radio_tx_running (radio0_radio_tx_running), - .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), - .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), - .s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), - .m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), - .m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}), + .s_rfnoc_chdr_tdata ({s_radio0_in_3_tdata , s_radio0_in_2_tdata , s_radio0_in_1_tdata , s_radio0_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio0_in_3_tlast , s_radio0_in_2_tlast , s_radio0_in_1_tlast , s_radio0_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio0_in_3_tvalid, s_radio0_in_2_tvalid, s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio0_in_3_tready, s_radio0_in_2_tready, s_radio0_in_1_tready, s_radio0_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio0_out_3_tdata , m_radio0_out_2_tdata , m_radio0_out_1_tdata , m_radio0_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio0_out_3_tlast , m_radio0_out_2_tlast , m_radio0_out_1_tlast , m_radio0_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio0_out_3_tvalid, m_radio0_out_2_tvalid, m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio0_out_3_tready, m_radio0_out_2_tready, m_radio0_out_1_tready, m_radio0_out_0_tready}), .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata), .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast), .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid), @@ -1077,14 +1077,14 @@ module rfnoc_image_core #( //----------------------------------- wire radio1_radio_clk; - wire [BLOCK_CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; - wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; - wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; - wire s_radio1_in_1_tready, s_radio1_in_0_tready; - wire [BLOCK_CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; - wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; - wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; - wire m_radio1_out_1_tready, m_radio1_out_0_tready; + wire [BLOCK_CHDR_W-1:0] s_radio1_in_3_tdata , s_radio1_in_2_tdata , s_radio1_in_1_tdata , s_radio1_in_0_tdata ; + wire s_radio1_in_3_tlast , s_radio1_in_2_tlast , s_radio1_in_1_tlast , s_radio1_in_0_tlast ; + wire s_radio1_in_3_tvalid, s_radio1_in_2_tvalid, s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; + wire s_radio1_in_3_tready, s_radio1_in_2_tready, s_radio1_in_1_tready, s_radio1_in_0_tready; + wire [BLOCK_CHDR_W-1:0] m_radio1_out_3_tdata , m_radio1_out_2_tdata , m_radio1_out_1_tdata , m_radio1_out_0_tdata ; + wire m_radio1_out_3_tlast , m_radio1_out_2_tlast , m_radio1_out_1_tlast , m_radio1_out_0_tlast ; + wire m_radio1_out_3_tvalid, m_radio1_out_2_tvalid, m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; + wire m_radio1_out_3_tready, m_radio1_out_2_tready, m_radio1_out_1_tready, m_radio1_out_0_tready; // ctrlport wire [ 0:0] radio1_m_ctrlport_req_wr; @@ -1100,17 +1100,17 @@ module rfnoc_image_core #( // time wire [ 63:0] radio1_radio_time; // radio - wire [ 255:0] radio1_radio_rx_data; - wire [ 7:0] radio1_radio_rx_stb; - wire [ 7:0] radio1_radio_rx_running; - wire [ 255:0] radio1_radio_tx_data; - wire [ 7:0] radio1_radio_tx_stb; - wire [ 7:0] radio1_radio_tx_running; + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (3), .CHDR_W (BLOCK_CHDR_W), - .NUM_PORTS (2), + .NUM_PORTS (4), .NIPC (RADIO_NIPC), .ITEM_W (32), .MTU (BLOCK_MTU) @@ -1137,14 +1137,14 @@ module rfnoc_image_core #( .radio_tx_data (radio1_radio_tx_data), .radio_tx_stb (radio1_radio_tx_stb), .radio_tx_running (radio1_radio_tx_running), - .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), - .s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), - .s_rfnoc_chdr_tready ({s_radio1_in_1_tready, s_radio1_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), - .m_rfnoc_chdr_tvalid ({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), - .m_rfnoc_chdr_tready ({m_radio1_out_1_tready, m_radio1_out_0_tready}), + .s_rfnoc_chdr_tdata ({s_radio1_in_3_tdata , s_radio1_in_2_tdata , s_radio1_in_1_tdata , s_radio1_in_0_tdata }), + .s_rfnoc_chdr_tlast ({s_radio1_in_3_tlast , s_radio1_in_2_tlast , s_radio1_in_1_tlast , s_radio1_in_0_tlast }), + .s_rfnoc_chdr_tvalid ({s_radio1_in_3_tvalid, s_radio1_in_2_tvalid, s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), + .s_rfnoc_chdr_tready ({s_radio1_in_3_tready, s_radio1_in_2_tready, s_radio1_in_1_tready, s_radio1_in_0_tready}), + .m_rfnoc_chdr_tdata ({m_radio1_out_3_tdata , m_radio1_out_2_tdata , m_radio1_out_1_tdata , m_radio1_out_0_tdata }), + .m_rfnoc_chdr_tlast ({m_radio1_out_3_tlast , m_radio1_out_2_tlast , m_radio1_out_1_tlast , m_radio1_out_0_tlast }), + .m_rfnoc_chdr_tvalid ({m_radio1_out_3_tvalid, m_radio1_out_2_tvalid, m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), + .m_rfnoc_chdr_tready ({m_radio1_out_3_tready, m_radio1_out_2_tready, m_radio1_out_1_tready, m_radio1_out_0_tready}), .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata), .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast), .s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid), @@ -1155,143 +1155,6 @@ module rfnoc_image_core #( .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) ); - //----------------------------------- - // replay0 - //----------------------------------- - - wire replay0_mem_clk; - wire [BLOCK_CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ; - wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ; - wire s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid; - wire s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready; - wire [BLOCK_CHDR_W-1:0] m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata ; - wire m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast ; - wire m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid; - wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready; - - // axi_ram - wire [ 0:0] replay0_axi_rst; - wire [ 3:0] replay0_m_axi_awid; - wire [ 191:0] replay0_m_axi_awaddr; - wire [ 31:0] replay0_m_axi_awlen; - wire [ 11:0] replay0_m_axi_awsize; - wire [ 7:0] replay0_m_axi_awburst; - wire [ 3:0] replay0_m_axi_awlock; - wire [ 15:0] replay0_m_axi_awcache; - wire [ 11:0] replay0_m_axi_awprot; - wire [ 15:0] replay0_m_axi_awqos; - wire [ 15:0] replay0_m_axi_awregion; - wire [ 3:0] replay0_m_axi_awuser; - wire [ 3:0] replay0_m_axi_awvalid; - wire [ 3:0] replay0_m_axi_awready; - wire [2047:0] replay0_m_axi_wdata; - wire [ 255:0] replay0_m_axi_wstrb; - wire [ 3:0] replay0_m_axi_wlast; - wire [ 3:0] replay0_m_axi_wuser; - wire [ 3:0] replay0_m_axi_wvalid; - wire [ 3:0] replay0_m_axi_wready; - wire [ 3:0] replay0_m_axi_bid; - wire [ 7:0] replay0_m_axi_bresp; - wire [ 3:0] replay0_m_axi_buser; - wire [ 3:0] replay0_m_axi_bvalid; - wire [ 3:0] replay0_m_axi_bready; - wire [ 3:0] replay0_m_axi_arid; - wire [ 191:0] replay0_m_axi_araddr; - wire [ 31:0] replay0_m_axi_arlen; - wire [ 11:0] replay0_m_axi_arsize; - wire [ 7:0] replay0_m_axi_arburst; - wire [ 3:0] replay0_m_axi_arlock; - wire [ 15:0] replay0_m_axi_arcache; - wire [ 11:0] replay0_m_axi_arprot; - wire [ 15:0] replay0_m_axi_arqos; - wire [ 15:0] replay0_m_axi_arregion; - wire [ 3:0] replay0_m_axi_aruser; - wire [ 3:0] replay0_m_axi_arvalid; - wire [ 3:0] replay0_m_axi_arready; - wire [ 3:0] replay0_m_axi_rid; - wire [2047:0] replay0_m_axi_rdata; - wire [ 7:0] replay0_m_axi_rresp; - wire [ 3:0] replay0_m_axi_rlast; - wire [ 3:0] replay0_m_axi_ruser; - wire [ 3:0] replay0_m_axi_rvalid; - wire [ 3:0] replay0_m_axi_rready; - - rfnoc_block_replay #( - .THIS_PORTID (4), - .CHDR_W (BLOCK_CHDR_W), - .NUM_PORTS (4), - .MEM_DATA_W (128), - .MEM_ADDR_W (32), - .MTU (BLOCK_MTU) - ) b_replay0_2 ( - .rfnoc_chdr_clk (rfnoc_chdr_clk), - .rfnoc_ctrl_clk (rfnoc_ctrl_clk), - .mem_clk (replay0_mem_clk), - .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), - .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), - .axi_rst (replay0_axi_rst), - .m_axi_awid (replay0_m_axi_awid), - .m_axi_awaddr (replay0_m_axi_awaddr), - .m_axi_awlen (replay0_m_axi_awlen), - .m_axi_awsize (replay0_m_axi_awsize), - .m_axi_awburst (replay0_m_axi_awburst), - .m_axi_awlock (replay0_m_axi_awlock), - .m_axi_awcache (replay0_m_axi_awcache), - .m_axi_awprot (replay0_m_axi_awprot), - .m_axi_awqos (replay0_m_axi_awqos), - .m_axi_awregion (replay0_m_axi_awregion), - .m_axi_awuser (replay0_m_axi_awuser), - .m_axi_awvalid (replay0_m_axi_awvalid), - .m_axi_awready (replay0_m_axi_awready), - .m_axi_wdata (replay0_m_axi_wdata), - .m_axi_wstrb (replay0_m_axi_wstrb), - .m_axi_wlast (replay0_m_axi_wlast), - .m_axi_wuser (replay0_m_axi_wuser), - .m_axi_wvalid (replay0_m_axi_wvalid), - .m_axi_wready (replay0_m_axi_wready), - .m_axi_bid (replay0_m_axi_bid), - .m_axi_bresp (replay0_m_axi_bresp), - .m_axi_buser (replay0_m_axi_buser), - .m_axi_bvalid (replay0_m_axi_bvalid), - .m_axi_bready (replay0_m_axi_bready), - .m_axi_arid (replay0_m_axi_arid), - .m_axi_araddr (replay0_m_axi_araddr), - .m_axi_arlen (replay0_m_axi_arlen), - .m_axi_arsize (replay0_m_axi_arsize), - .m_axi_arburst (replay0_m_axi_arburst), - .m_axi_arlock (replay0_m_axi_arlock), - .m_axi_arcache (replay0_m_axi_arcache), - .m_axi_arprot (replay0_m_axi_arprot), - .m_axi_arqos (replay0_m_axi_arqos), - .m_axi_arregion (replay0_m_axi_arregion), - .m_axi_aruser (replay0_m_axi_aruser), - .m_axi_arvalid (replay0_m_axi_arvalid), - .m_axi_arready (replay0_m_axi_arready), - .m_axi_rid (replay0_m_axi_rid), - .m_axi_rdata (replay0_m_axi_rdata), - .m_axi_rresp (replay0_m_axi_rresp), - .m_axi_rlast (replay0_m_axi_rlast), - .m_axi_ruser (replay0_m_axi_ruser), - .m_axi_rvalid (replay0_m_axi_rvalid), - .m_axi_rready (replay0_m_axi_rready), - .s_rfnoc_chdr_tdata ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }), - .s_rfnoc_chdr_tlast ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }), - .s_rfnoc_chdr_tvalid ({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), - .s_rfnoc_chdr_tready ({s_replay0_in_3_tready, s_replay0_in_2_tready, s_replay0_in_1_tready, s_replay0_in_0_tready}), - .m_rfnoc_chdr_tdata ({m_replay0_out_3_tdata , m_replay0_out_2_tdata , m_replay0_out_1_tdata , m_replay0_out_0_tdata }), - .m_rfnoc_chdr_tlast ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }), - .m_rfnoc_chdr_tvalid ({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}), - .m_rfnoc_chdr_tready ({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}), - .s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata), - .s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast), - .s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid), - .s_rfnoc_ctrl_tready (s_replay0_ctrl_tready), - .m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata), - .m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast), - .m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid), - .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) - ); - //--------------------------------------------------------------------------- // Static Router //--------------------------------------------------------------------------- @@ -1316,65 +1179,65 @@ module rfnoc_image_core #( assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; assign m_radio0_out_1_tready = s_ep1_in0_tready; - assign s_radio1_in_0_tdata = m_ep2_out0_tdata; - assign s_radio1_in_0_tlast = m_ep2_out0_tlast; - assign s_radio1_in_0_tvalid = m_ep2_out0_tvalid; - assign m_ep2_out0_tready = s_radio1_in_0_tready; + assign s_radio0_in_2_tdata = m_ep2_out0_tdata; + assign s_radio0_in_2_tlast = m_ep2_out0_tlast; + assign s_radio0_in_2_tvalid = m_ep2_out0_tvalid; + assign m_ep2_out0_tready = s_radio0_in_2_tready; - assign s_ep2_in0_tdata = m_radio1_out_0_tdata; - assign s_ep2_in0_tlast = m_radio1_out_0_tlast; - assign s_ep2_in0_tvalid = m_radio1_out_0_tvalid; - assign m_radio1_out_0_tready = s_ep2_in0_tready; + assign s_ep2_in0_tdata = m_radio0_out_2_tdata; + assign s_ep2_in0_tlast = m_radio0_out_2_tlast; + assign s_ep2_in0_tvalid = m_radio0_out_2_tvalid; + assign m_radio0_out_2_tready = s_ep2_in0_tready; - assign s_radio1_in_1_tdata = m_ep3_out0_tdata; - assign s_radio1_in_1_tlast = m_ep3_out0_tlast; - assign s_radio1_in_1_tvalid = m_ep3_out0_tvalid; - assign m_ep3_out0_tready = s_radio1_in_1_tready; + assign s_radio0_in_3_tdata = m_ep3_out0_tdata; + assign s_radio0_in_3_tlast = m_ep3_out0_tlast; + assign s_radio0_in_3_tvalid = m_ep3_out0_tvalid; + assign m_ep3_out0_tready = s_radio0_in_3_tready; - assign s_ep3_in0_tdata = m_radio1_out_1_tdata; - assign s_ep3_in0_tlast = m_radio1_out_1_tlast; - assign s_ep3_in0_tvalid = m_radio1_out_1_tvalid; - assign m_radio1_out_1_tready = s_ep3_in0_tready; + assign s_ep3_in0_tdata = m_radio0_out_3_tdata; + assign s_ep3_in0_tlast = m_radio0_out_3_tlast; + assign s_ep3_in0_tvalid = m_radio0_out_3_tvalid; + assign m_radio0_out_3_tready = s_ep3_in0_tready; - assign s_replay0_in_0_tdata = m_ep4_out0_tdata; - assign s_replay0_in_0_tlast = m_ep4_out0_tlast; - assign s_replay0_in_0_tvalid = m_ep4_out0_tvalid; - assign m_ep4_out0_tready = s_replay0_in_0_tready; + assign s_radio1_in_0_tdata = m_ep4_out0_tdata; + assign s_radio1_in_0_tlast = m_ep4_out0_tlast; + assign s_radio1_in_0_tvalid = m_ep4_out0_tvalid; + assign m_ep4_out0_tready = s_radio1_in_0_tready; - assign s_ep4_in0_tdata = m_replay0_out_0_tdata; - assign s_ep4_in0_tlast = m_replay0_out_0_tlast; - assign s_ep4_in0_tvalid = m_replay0_out_0_tvalid; - assign m_replay0_out_0_tready = s_ep4_in0_tready; + assign s_ep4_in0_tdata = m_radio1_out_0_tdata; + assign s_ep4_in0_tlast = m_radio1_out_0_tlast; + assign s_ep4_in0_tvalid = m_radio1_out_0_tvalid; + assign m_radio1_out_0_tready = s_ep4_in0_tready; - assign s_replay0_in_1_tdata = m_ep5_out0_tdata; - assign s_replay0_in_1_tlast = m_ep5_out0_tlast; - assign s_replay0_in_1_tvalid = m_ep5_out0_tvalid; - assign m_ep5_out0_tready = s_replay0_in_1_tready; + assign s_radio1_in_1_tdata = m_ep5_out0_tdata; + assign s_radio1_in_1_tlast = m_ep5_out0_tlast; + assign s_radio1_in_1_tvalid = m_ep5_out0_tvalid; + assign m_ep5_out0_tready = s_radio1_in_1_tready; - assign s_ep5_in0_tdata = m_replay0_out_1_tdata; - assign s_ep5_in0_tlast = m_replay0_out_1_tlast; - assign s_ep5_in0_tvalid = m_replay0_out_1_tvalid; - assign m_replay0_out_1_tready = s_ep5_in0_tready; + assign s_ep5_in0_tdata = m_radio1_out_1_tdata; + assign s_ep5_in0_tlast = m_radio1_out_1_tlast; + assign s_ep5_in0_tvalid = m_radio1_out_1_tvalid; + assign m_radio1_out_1_tready = s_ep5_in0_tready; - assign s_replay0_in_2_tdata = m_ep6_out0_tdata; - assign s_replay0_in_2_tlast = m_ep6_out0_tlast; - assign s_replay0_in_2_tvalid = m_ep6_out0_tvalid; - assign m_ep6_out0_tready = s_replay0_in_2_tready; + assign s_radio1_in_2_tdata = m_ep6_out0_tdata; + assign s_radio1_in_2_tlast = m_ep6_out0_tlast; + assign s_radio1_in_2_tvalid = m_ep6_out0_tvalid; + assign m_ep6_out0_tready = s_radio1_in_2_tready; - assign s_ep6_in0_tdata = m_replay0_out_2_tdata; - assign s_ep6_in0_tlast = m_replay0_out_2_tlast; - assign s_ep6_in0_tvalid = m_replay0_out_2_tvalid; - assign m_replay0_out_2_tready = s_ep6_in0_tready; + assign s_ep6_in0_tdata = m_radio1_out_2_tdata; + assign s_ep6_in0_tlast = m_radio1_out_2_tlast; + assign s_ep6_in0_tvalid = m_radio1_out_2_tvalid; + assign m_radio1_out_2_tready = s_ep6_in0_tready; - assign s_replay0_in_3_tdata = m_ep7_out0_tdata; - assign s_replay0_in_3_tlast = m_ep7_out0_tlast; - assign s_replay0_in_3_tvalid = m_ep7_out0_tvalid; - assign m_ep7_out0_tready = s_replay0_in_3_tready; + assign s_radio1_in_3_tdata = m_ep7_out0_tdata; + assign s_radio1_in_3_tlast = m_ep7_out0_tlast; + assign s_radio1_in_3_tvalid = m_ep7_out0_tvalid; + assign m_ep7_out0_tready = s_radio1_in_3_tready; - assign s_ep7_in0_tdata = m_replay0_out_3_tdata; - assign s_ep7_in0_tlast = m_replay0_out_3_tlast; - assign s_ep7_in0_tvalid = m_replay0_out_3_tvalid; - assign m_replay0_out_3_tready = s_ep7_in0_tready; + assign s_ep7_in0_tdata = m_radio1_out_3_tdata; + assign s_ep7_in0_tlast = m_radio1_out_3_tlast; + assign s_ep7_in0_tvalid = m_radio1_out_3_tvalid; + assign m_radio1_out_3_tready = s_ep7_in0_tready; //--------------------------------------------------------------------------- @@ -1387,9 +1250,8 @@ module rfnoc_image_core #( // Clock Domains //--------------------------------------------------------------------------- - assign radio0_radio_clk = radio_clk; - assign radio1_radio_clk = radio_clk; - assign replay0_mem_clk = dram_clk; + assign radio0_radio_clk = radio0_clk; + assign radio1_radio_clk = radio1_clk; //--------------------------------------------------------------------------- @@ -1433,56 +1295,10 @@ module rfnoc_image_core #( assign radio1_radio_tx_stb = radio_tx_stb_radio1; assign radio_tx_running_radio1 = radio1_radio_tx_running; - assign replay0_axi_rst = axi_rst; - assign m_axi_awid = replay0_m_axi_awid; - assign m_axi_awaddr = replay0_m_axi_awaddr; - assign m_axi_awlen = replay0_m_axi_awlen; - assign m_axi_awsize = replay0_m_axi_awsize; - assign m_axi_awburst = replay0_m_axi_awburst; - assign m_axi_awlock = replay0_m_axi_awlock; - assign m_axi_awcache = replay0_m_axi_awcache; - assign m_axi_awprot = replay0_m_axi_awprot; - assign m_axi_awqos = replay0_m_axi_awqos; - assign m_axi_awregion = replay0_m_axi_awregion; - assign m_axi_awuser = replay0_m_axi_awuser; - assign m_axi_awvalid = replay0_m_axi_awvalid; - assign replay0_m_axi_awready = m_axi_awready; - assign m_axi_wdata = replay0_m_axi_wdata; - assign m_axi_wstrb = replay0_m_axi_wstrb; - assign m_axi_wlast = replay0_m_axi_wlast; - assign m_axi_wuser = replay0_m_axi_wuser; - assign m_axi_wvalid = replay0_m_axi_wvalid; - assign replay0_m_axi_wready = m_axi_wready; - assign replay0_m_axi_bid = m_axi_bid; - assign replay0_m_axi_bresp = m_axi_bresp; - assign replay0_m_axi_buser = m_axi_buser; - assign replay0_m_axi_bvalid = m_axi_bvalid; - assign m_axi_bready = replay0_m_axi_bready; - assign m_axi_arid = replay0_m_axi_arid; - assign m_axi_araddr = replay0_m_axi_araddr; - assign m_axi_arlen = replay0_m_axi_arlen; - assign m_axi_arsize = replay0_m_axi_arsize; - assign m_axi_arburst = replay0_m_axi_arburst; - assign m_axi_arlock = replay0_m_axi_arlock; - assign m_axi_arcache = replay0_m_axi_arcache; - assign m_axi_arprot = replay0_m_axi_arprot; - assign m_axi_arqos = replay0_m_axi_arqos; - assign m_axi_arregion = replay0_m_axi_arregion; - assign m_axi_aruser = replay0_m_axi_aruser; - assign m_axi_arvalid = replay0_m_axi_arvalid; - assign replay0_m_axi_arready = m_axi_arready; - assign replay0_m_axi_rid = m_axi_rid; - assign replay0_m_axi_rdata = m_axi_rdata; - assign replay0_m_axi_rresp = m_axi_rresp; - assign replay0_m_axi_rlast = m_axi_rlast; - assign replay0_m_axi_ruser = m_axi_ruser; - assign replay0_m_axi_rvalid = m_axi_rvalid; - assign m_axi_rready = replay0_m_axi_rready; - // Broadcaster/Listener Connections: - assign radio0_radio_time = radio_time; + assign radio0_radio_time = radio_time0; - assign radio1_radio_time = radio_time; + assign radio1_radio_time = radio_time1; endmodule diff --git a/top/x400/x440_400_rfnoc_image_core.vh b/top/x400/x440_400_rfnoc_image_core.vh new file mode 100644 index 0000000..0fd34c6 --- /dev/null +++ b/top/x400/x440_400_rfnoc_image_core.vh @@ -0,0 +1,19 @@ +// +// Copyright 2023 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Header: rfnoc_image_core.vh (for x440) +// +// Description: +// +// This is the header file for the RFNoC Image Core. +// +// This file was automatically generated by the RFNoC image builder tool. +// Re-running that tool will overwrite this file! +// +// Source: x440_400_rfnoc_image_core.yml +// + +`define CHDR_WIDTH 512 +`define RFNOC_PROTOVER { 8'd1, 8'd0 } diff --git a/top/x400/x440_400_rfnoc_image_core.yml b/top/x400/x440_400_rfnoc_image_core.yml new file mode 100644 index 0000000..a3591ba --- /dev/null +++ b/top/x400/x440_400_rfnoc_image_core.yml @@ -0,0 +1,146 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: >- # Copyright information used in file headers + Copyright 2023 Ettus Research, a National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later +version: '1.0' # File version +chdr_width: 512 # Bit width of the CHDR bus for this image +device: 'x440' # USRP type +image_core_name: 'x440_400' # Name to use for the RFNoC Image Core files +default_target: 'X440_CG_400' # Default make target + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size_bytes: 524288 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size_bytes: 524288 + ep2: + ctrl: False + data: True + buff_size_bytes: 524288 + ep3: + ctrl: False + data: True + buff_size_bytes: 524288 + ep4: + ctrl: False + data: True + buff_size_bytes: 524288 + ep5: + ctrl: False + data: True + buff_size_bytes: 524288 + ep6: + ctrl: False + data: True + buff_size_bytes: 524288 + ep7: + ctrl: False + data: True + buff_size_bytes: 524288 + +# A table of which crossbar routes to include +# ------------------------------------------- +# Rows correspond to input ports and columns correspond to output ports. +# Entering a 1 includes and a 0 removes that route from the crossbar. +crossbar_routes: + # eth0 eth2 eth4 ep0 ep2 ep4 ep6 + # eth1 eth3 dma ep1 ep3 ep5 ep7 + - [ 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth0 (QSFP Port 0) + - [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth1 (NC) + - [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth2 (NC) + - [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] # eth3 (NC) + - [ 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1 ] # eth4 (QSFP Port 1) + - [ 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 ] # dma + - [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep0 (radio0.0) + - [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep1 (radio0.1) + - [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep2 (radio0.2) + - [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep3 (radio0.3) + - [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep4 (radio1.0) + - [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep5 (radio1.1) + - [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep6 (radio1.2) + - [ 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 ] # ep7 (radio1.3) + +# A list of all NoC blocks in design +# ---------------------------------- +block_chdr_width: 128 # Bit width of the CHDR bus between blocks +noc_blocks: + radio0: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 4 + NIPC: RADIO_NIPC + radio1: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 4 + NIPC: RADIO_NIPC + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # RF A:0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # RF A:0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # RF A:1 TX + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + # RF A:1 RX + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + # RF A:2 TX + - { srcblk: ep2, srcport: out0, dstblk: radio0, dstport: in_2 } + # RF A:2 RX + - { srcblk: radio0, srcport: out_2, dstblk: ep2, dstport: in0 } + # RF A:3 TX + - { srcblk: ep3, srcport: out0, dstblk: radio0, dstport: in_3 } + # RF A:3 RX + - { srcblk: radio0, srcport: out_3, dstblk: ep3, dstport: in0 } + # + # RF B:0 TX + - { srcblk: ep4, srcport: out0, dstblk: radio1, dstport: in_0 } + # RF B:0 RX + - { srcblk: radio1, srcport: out_0, dstblk: ep4, dstport: in0 } + # RF B:1 TX + - { srcblk: ep5, srcport: out0, dstblk: radio1, dstport: in_1 } + # RF B:1 RX + - { srcblk: radio1, srcport: out_1, dstblk: ep5, dstport: in0 } + # RF B:2 TX + - { srcblk: ep6, srcport: out0, dstblk: radio1, dstport: in_2 } + # RF B:2 RX + - { srcblk: radio1, srcport: out_2, dstblk: ep6, dstport: in0 } + # RF B:3 TX + - { srcblk: ep7, srcport: out0, dstblk: radio1, dstport: in_3 } + # RF B:3 RX + - { srcblk: radio1, srcport: out_3, dstblk: ep7, dstport: in0 } + # + # BSP Connections + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } + - { srcblk: _device_, srcport: time0, dstblk: radio0, dstport: time } + - { srcblk: _device_, srcport: time1, dstblk: radio1, dstport: time } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio } diff --git a/top/x400/x440_400_static_router.hex b/top/x400/x440_400_static_router.hex new file mode 100644 index 0000000..82ce269 --- /dev/null +++ b/top/x400/x440_400_static_router.hex @@ -0,0 +1,17 @@ +00000010 +00400240 +02400040 +00800241 +02410080 +00c00242 +024200c0 +01000243 +02430100 +01400280 +02800140 +01800281 +02810180 +01c00282 +028201c0 +02000283 +02830200 diff --git a/top/x400/x4xx.v b/top/x400/x4xx.v index 89c2277..f346d6f 100644 --- a/top/x400/x4xx.v +++ b/top/x400/x4xx.v @@ -27,7 +27,16 @@ module x4xx ( // Analog ports - `ifdef X410 + `ifdef X440 + input wire [3:0] DB0_RX_P, + input wire [3:0] DB0_RX_N, + input wire [3:0] DB1_RX_P, + input wire [3:0] DB1_RX_N, + output wire [3:0] DB0_TX_P, + output wire [3:0] DB0_TX_N, + output wire [3:0] DB1_TX_P, + output wire [3:0] DB1_TX_N, + `else // X410 input wire [1:0] DB0_RX_P, input wire [1:0] DB0_RX_N, input wire [1:0] DB1_RX_P, @@ -246,11 +255,17 @@ module x4xx ( ); // Variant-dependent register map. - `ifdef X410 + `ifdef X440 + `include "regmap/x440/versioning_regs_regmap_utils.vh" + `else // Use X410 as the default variant for regmap. `include "regmap/x410/versioning_regs_regmap_utils.vh" `endif - `ifdef X410 + // Both of these provide the same values for what we need, but we'll keep the + // if/else clause for consistency with other includes. + `ifdef X440 + `include "regmap/x440/rfdc_regs_regmap_utils.vh" + `else // Use X410 as the default variant for regmap. `include "regmap/x410/rfdc_regs_regmap_utils.vh" `endif @@ -302,8 +317,8 @@ module x4xx ( localparam NUM_DBOARDS = 2; - `ifdef X410 - localparam NUM_TIMEKEEPERS = 1; + `ifdef X440 + localparam NUM_TIMEKEEPERS = NUM_DBOARDS; `else localparam NUM_TIMEKEEPERS = 1; `endif @@ -454,6 +469,19 @@ module x4xx ( assign clk40_rstn = ~clk40_rst; assign bus_clk_rstn = ~bus_clk_rst; + // Need a 5 MHz pulse on X440 to use as a sync ref + `ifdef X440 + wire clk5; + + clock_div #( + .N(2) + ) clock_div_5mhz ( + .clk_in (base_ref_clk), + .clk_in_rst (brc_rst), + .clk_out (clk5) + ); + `endif + //--------------------------------------------------------------------------- // PPS Handling //--------------------------------------------------------------------------- @@ -641,6 +669,8 @@ module x4xx ( `ifdef X410 localparam NUM_CH_PER_DB = 2; + `elsif X440 + localparam NUM_CH_PER_DB = 4; `else localparam NUM_CH_PER_DB = 2; `endif @@ -1250,6 +1280,468 @@ module x4xx ( .s_axi_hpc1_aruser (), .s_axi_hpc1_awuser () ); + `elsif X440 + x440_ps_rfdc_bd x440_ps_rfdc_bd_i ( + .adc_data_out_resetn_dclk (adc_data_out_resetn_dclk), + .adc_enable_data_rclk (adc_enable_data_rclk), + .adc_reset_pulse_dclk (adc_reset_pulse), + .adc_rfdc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk), + .bus_clk (bus_clk), + .bus_rstn (bus_clk_rstn), + .clk40 (clk40), + .clk40_rstn (clk40_rstn), + .dac_data_in_resetn_dclk (dac_data_in_resetn_dclk), + .dac_data_in_resetn_dclk2x (dac_data_in_resetn_dclk2x), + .dac_data_in_resetn_rclk (dac_data_in_resetn_rclk), + .dac_data_in_resetn_rclk2x (dac_data_in_resetn_rclk2x), + .dac_reset_pulse_dclk (dac_reset_pulse), + .data_clk (data_clk), + .data_clk_2x (data_clk_2x), + .data_clock_locked (), + .enable_gated_clocks_clk40 (1'b1), + .enable_sysref_rclk (1'b1), + .fir_resetn_rclk2x (fir_resetn_rclk2x), + .gated_base_clks_valid_clk40 (), + .radio0_invert_adc_iq_r0clk (invert_adc_iq_rclk2[3:0]), + .radio0_invert_dac_iq_r0clk (invert_dac_iq_rclk2[3:0]), + .radio1_invert_adc_iq_r1clk (invert_adc_iq_rclk2[7:4]), + .radio1_invert_dac_iq_r1clk (invert_dac_iq_rclk2[7:4]), + .irq0_lpd_rpu_n (1'b1), + .irq1_lpd_rpu_n (1'b1), + .jtag0_tck (), + .jtag0_tdi (), + .jtag0_tdo (), + .jtag0_tms (), + .nco_reset_done_dclk (nco_reset_done), + .pl_clk40 (clk40), + .pl_clk100 (clk100), + .pl_clk166 (clk166), + .pl_clk200 (clk200), + .pl_ps_irq0 (pl_ps_irq0), + .pl_ps_irq1 (pl_ps_irq1), + .pl_resetn0 (pl_resetn0), + .pl_resetn1 (), + .pl_resetn2 (), + .pl_resetn3 (), + .pll_ref_clk_in (pll_ref_clk_in), + .pll_ref_clk_out (pll_ref_clk), + .rf_axi_status_clk40 (rf_axi_status_clk40), + .rf_dsp_info_clk40 (rf_dsp_info_clk40), + .rf_rfdc_info_clk40 (rf_rfdc_info_clk40), + .radio0_rfdc_clk_1x (rfdc_clk[0]), + .radio0_rfdc_clk_2x (rfdc_clk_2x[0]), + .radio1_rfdc_clk_1x (rfdc_clk[1]), + .radio1_rfdc_clk_2x (rfdc_clk_2x[1]), + .rfdc_irq (), + .s_axi_hp0_aclk (clk40), + .s_axi_hp1_aclk (clk40), + .s_axi_hpc0_aclk (), + .start_nco_reset_dclk (start_nco_reset), + .sysref_out_pclk (), + .sysref_out_rclk (), + .sysref_pl_in (sysref_pl), + `ifdef QSFP0_0 + .s_axi_hp0_aruser (axi_hp0_aruser), + .s_axi_hp0_awuser (axi_hp0_awuser), + .s_axi_hp0_awid (axi_hp0_awid), + .s_axi_hp0_awaddr (axi_hp0_awaddr), + .s_axi_hp0_awlen (axi_hp0_awlen), + .s_axi_hp0_awsize (axi_hp0_awsize), + .s_axi_hp0_awburst (axi_hp0_awburst), + .s_axi_hp0_awlock (axi_hp0_awlock), + .s_axi_hp0_awcache (axi_hp0_awcache), + .s_axi_hp0_awprot (axi_hp0_awprot), + .s_axi_hp0_awvalid (axi_hp0_awvalid), + .s_axi_hp0_awready (axi_hp0_awready), + .s_axi_hp0_wdata (axi_hp0_wdata), + .s_axi_hp0_wstrb (axi_hp0_wstrb), + .s_axi_hp0_wlast (axi_hp0_wlast), + .s_axi_hp0_wvalid (axi_hp0_wvalid), + .s_axi_hp0_wready (axi_hp0_wready), + .s_axi_hp0_bid (), + .s_axi_hp0_bresp (axi_hp0_bresp), + .s_axi_hp0_bvalid (axi_hp0_bvalid), + .s_axi_hp0_bready (axi_hp0_bready), + .s_axi_hp0_arid (axi_hp0_arid), + .s_axi_hp0_araddr (axi_hp0_araddr), + .s_axi_hp0_arlen (axi_hp0_arlen), + .s_axi_hp0_arsize (axi_hp0_arsize), + .s_axi_hp0_arburst (axi_hp0_arburst), + .s_axi_hp0_arlock (axi_hp0_arlock), + .s_axi_hp0_arcache (axi_hp0_arcache), + .s_axi_hp0_arprot (axi_hp0_arprot), + .s_axi_hp0_arvalid (axi_hp0_arvalid), + .s_axi_hp0_arready (axi_hp0_arready), + .s_axi_hp0_rid (), + .s_axi_hp0_rdata (axi_hp0_rdata), + .s_axi_hp0_rresp (axi_hp0_rresp), + .s_axi_hp0_rlast (axi_hp0_rlast), + .s_axi_hp0_rvalid (axi_hp0_rvalid), + .s_axi_hp0_rready (axi_hp0_rready), + .s_axi_hp0_awqos (axi_hp0_awqos), + .s_axi_hp0_arqos (axi_hp0_arqos), + `else + // Disconnect the DMA interface if the associated QSFP port is not used. + .s_axi_hp0_awvalid (1'b0), + .s_axi_hp0_wvalid (1'b0), + .s_axi_hp0_bready (1'b1), + .s_axi_hp0_arvalid (1'b0), + .s_axi_hp0_rready (1'b1), + `endif + .s_axis_eth_dma_tdata (e2h_dma_tdata), + .s_axis_eth_dma_tkeep (e2h_dma_tkeep), + .s_axis_eth_dma_tlast (e2h_dma_tlast), + .s_axis_eth_dma_tready (e2h_dma_tready), + .s_axis_eth_dma_tvalid (e2h_dma_tvalid), + `ifdef QSFP1_0 + .s_axi_hp1_aruser (axi_hp1_aruser), + .s_axi_hp1_awuser (axi_hp1_awuser), + .s_axi_hp1_awid (axi_hp1_awid), + .s_axi_hp1_awaddr (axi_hp1_awaddr), + .s_axi_hp1_awlen (axi_hp1_awlen), + .s_axi_hp1_awsize (axi_hp1_awsize), + .s_axi_hp1_awburst (axi_hp1_awburst), + .s_axi_hp1_awlock (axi_hp1_awlock), + .s_axi_hp1_awcache (axi_hp1_awcache), + .s_axi_hp1_awprot (axi_hp1_awprot), + .s_axi_hp1_awvalid (axi_hp1_awvalid), + .s_axi_hp1_awready (axi_hp1_awready), + .s_axi_hp1_wdata (axi_hp1_wdata), + .s_axi_hp1_wstrb (axi_hp1_wstrb), + .s_axi_hp1_wlast (axi_hp1_wlast), + .s_axi_hp1_wvalid (axi_hp1_wvalid), + .s_axi_hp1_wready (axi_hp1_wready), + .s_axi_hp1_bid (), + .s_axi_hp1_bresp (axi_hp1_bresp), + .s_axi_hp1_bvalid (axi_hp1_bvalid), + .s_axi_hp1_bready (axi_hp1_bready), + .s_axi_hp1_arid (axi_hp1_arid), + .s_axi_hp1_araddr (axi_hp1_araddr), + .s_axi_hp1_arlen (axi_hp1_arlen), + .s_axi_hp1_arsize (axi_hp1_arsize), + .s_axi_hp1_arburst (axi_hp1_arburst), + .s_axi_hp1_arlock (axi_hp1_arlock), + .s_axi_hp1_arcache (axi_hp1_arcache), + .s_axi_hp1_arprot (axi_hp1_arprot), + .s_axi_hp1_arvalid (axi_hp1_arvalid), + .s_axi_hp1_arready (axi_hp1_arready), + .s_axi_hp1_rid (), + .s_axi_hp1_rdata (axi_hp1_rdata), + .s_axi_hp1_rresp (axi_hp1_rresp), + .s_axi_hp1_rlast (axi_hp1_rlast), + .s_axi_hp1_rvalid (axi_hp1_rvalid), + .s_axi_hp1_rready (axi_hp1_rready), + .s_axi_hp1_awqos (axi_hp1_awqos), + .s_axi_hp1_arqos (axi_hp1_arqos), + `else + // Disconnect the DMA interface if the associated QSFP port is not used. + .s_axi_hp1_awvalid (1'b0), + .s_axi_hp1_wvalid (1'b0), + .s_axi_hp1_bready (1'b1), + .s_axi_hp1_arvalid (1'b0), + .s_axi_hp1_rready (1'b1), + `endif + .s_axi_hpc0_aruser (), + .s_axi_hpc0_awuser (), + .s_axi_hpc0_awid (), + .s_axi_hpc0_awaddr (), + .s_axi_hpc0_awlen (), + .s_axi_hpc0_awsize (), + .s_axi_hpc0_awburst (), + .s_axi_hpc0_awlock (), + .s_axi_hpc0_awcache (), + .s_axi_hpc0_awprot (), + .s_axi_hpc0_awvalid (), + .s_axi_hpc0_awready (), + .s_axi_hpc0_wdata (), + .s_axi_hpc0_wstrb (), + .s_axi_hpc0_wlast (), + .s_axi_hpc0_wvalid (), + .s_axi_hpc0_wready (), + .s_axi_hpc0_bid (), + .s_axi_hpc0_bresp (), + .s_axi_hpc0_bvalid (), + .s_axi_hpc0_bready (), + .s_axi_hpc0_arid (), + .s_axi_hpc0_araddr (), + .s_axi_hpc0_arlen (), + .s_axi_hpc0_arsize (), + .s_axi_hpc0_arburst (), + .s_axi_hpc0_arlock (), + .s_axi_hpc0_arcache (), + .s_axi_hpc0_arprot (), + .s_axi_hpc0_arvalid (), + .s_axi_hpc0_arready (), + .s_axi_hpc0_rid (), + .s_axi_hpc0_rdata (), + .s_axi_hpc0_rresp (), + .s_axi_hpc0_rlast (), + .s_axi_hpc0_rvalid (), + .s_axi_hpc0_rready (), + .s_axi_hpc0_awqos (), + .s_axi_hpc0_arqos (), + .adc0_clk_clk_n (ADC_CLK_N[0]), + .adc0_clk_clk_p (ADC_CLK_P[0]), + .adc1_clk_clk_n (ADC_CLK_N[0]), + .adc1_clk_clk_p (ADC_CLK_P[0]), + .adc2_clk_clk_n (ADC_CLK_N[2]), + .adc2_clk_clk_p (ADC_CLK_P[2]), + .adc3_clk_clk_n (ADC_CLK_N[2]), + .adc3_clk_clk_p (ADC_CLK_P[2]), + .m_axi_app_awaddr (m_axi_app_awaddr), + .m_axi_app_awprot (m_axi_app_awprot), + .m_axi_app_awvalid (m_axi_app_awvalid), + .m_axi_app_awready (m_axi_app_awready), + .m_axi_app_wdata (m_axi_app_wdata), + .m_axi_app_wstrb (m_axi_app_wstrb), + .m_axi_app_wvalid (m_axi_app_wvalid), + .m_axi_app_wready (m_axi_app_wready), + .m_axi_app_bresp (m_axi_app_bresp), + .m_axi_app_bvalid (m_axi_app_bvalid), + .m_axi_app_bready (m_axi_app_bready), + .m_axi_app_araddr (m_axi_app_araddr), + .m_axi_app_arprot (m_axi_app_arprot), + .m_axi_app_arvalid (m_axi_app_arvalid), + .m_axi_app_arready (m_axi_app_arready), + .m_axi_app_rdata (m_axi_app_rdata), + .m_axi_app_rresp (m_axi_app_rresp), + .m_axi_app_rvalid (m_axi_app_rvalid), + .m_axi_app_rready (m_axi_app_rready), + .dac0_clk_clk_n (DAC_CLK_N[0]), + .dac0_clk_clk_p (DAC_CLK_P[0]), + .dac1_clk_clk_n (DAC_CLK_N[1]), + .dac1_clk_clk_p (DAC_CLK_P[1]), + .gpio_0_tri_i (gpio_0_tri_i), + .gpio_0_tri_o (gpio_0_tri_o), + .gpio_0_tri_t (gpio_0_tri_t), + .m_axi_eth_internal_awaddr (axi_eth_internal_awaddr), + .m_axi_eth_internal_awprot (), + .m_axi_eth_internal_awvalid (axi_eth_internal_awvalid), + .m_axi_eth_internal_awready (axi_eth_internal_awready), + .m_axi_eth_internal_wdata (axi_eth_internal_wdata), + .m_axi_eth_internal_wstrb (axi_eth_internal_wstrb), + .m_axi_eth_internal_wvalid (axi_eth_internal_wvalid), + .m_axi_eth_internal_wready (axi_eth_internal_wready), + .m_axi_eth_internal_bresp (axi_eth_internal_bresp), + .m_axi_eth_internal_bvalid (axi_eth_internal_bvalid), + .m_axi_eth_internal_bready (axi_eth_internal_bready), + .m_axi_eth_internal_araddr (axi_eth_internal_araddr), + .m_axi_eth_internal_arprot (), + .m_axi_eth_internal_arvalid (axi_eth_internal_arvalid), + .m_axi_eth_internal_arready (axi_eth_internal_arready), + .m_axi_eth_internal_rdata (axi_eth_internal_rdata), + .m_axi_eth_internal_rresp (axi_eth_internal_rresp), + .m_axi_eth_internal_rvalid (axi_eth_internal_rvalid), + .m_axi_eth_internal_rready (axi_eth_internal_rready), + .m_axis_eth_dma_tdata (h2e_dma_tdata), + .m_axis_eth_dma_tkeep (h2e_dma_tkeep), + .m_axis_eth_dma_tlast (h2e_dma_tlast), + .m_axis_eth_dma_tready (h2e_dma_tready), + .m_axis_eth_dma_tvalid (h2e_dma_tvalid), + .m_axi_rpu_awaddr (), + .m_axi_rpu_awprot (), + .m_axi_rpu_awvalid (), + .m_axi_rpu_awready (), + .m_axi_rpu_wdata (), + .m_axi_rpu_wstrb (), + .m_axi_rpu_wvalid (), + .m_axi_rpu_wready (), + .m_axi_rpu_bresp (), + .m_axi_rpu_bvalid (), + .m_axi_rpu_bready (), + .m_axi_rpu_araddr (), + .m_axi_rpu_arprot (), + .m_axi_rpu_arvalid (), + .m_axi_rpu_arready (), + .m_axi_rpu_rdata (), + .m_axi_rpu_rresp (), + .m_axi_rpu_rvalid (), + .m_axi_rpu_rready (), + .m_axi_core_awaddr (axi_core_awaddr), + .m_axi_core_awprot (), + .m_axi_core_awvalid (axi_core_awvalid), + .m_axi_core_awready (axi_core_awready), + .m_axi_core_wdata (axi_core_wdata), + .m_axi_core_wstrb (axi_core_wstrb), + .m_axi_core_wvalid (axi_core_wvalid), + .m_axi_core_wready (axi_core_wready), + .m_axi_core_bresp (axi_core_bresp), + .m_axi_core_bvalid (axi_core_bvalid), + .m_axi_core_bready (axi_core_bready), + .m_axi_core_araddr (axi_core_araddr), + .m_axi_core_arprot (), + .m_axi_core_arvalid (axi_core_arvalid), + .m_axi_core_arready (axi_core_arready), + .m_axi_core_rdata (axi_core_rdata), + .m_axi_core_rresp (axi_core_rresp), + .m_axi_core_rvalid (axi_core_rvalid), + .m_axi_core_rready (axi_core_rready), + .m_axi_mpm_ep_awaddr (m_axi_mpm_ep_awaddr), + .m_axi_mpm_ep_awprot (), + .m_axi_mpm_ep_awvalid (m_axi_mpm_ep_awvalid), + .m_axi_mpm_ep_awready (m_axi_mpm_ep_awready), + .m_axi_mpm_ep_wdata (m_axi_mpm_ep_wdata), + .m_axi_mpm_ep_wstrb (m_axi_mpm_ep_wstrb), + .m_axi_mpm_ep_wvalid (m_axi_mpm_ep_wvalid), + .m_axi_mpm_ep_wready (m_axi_mpm_ep_wready), + .m_axi_mpm_ep_bresp (m_axi_mpm_ep_bresp), + .m_axi_mpm_ep_bvalid (m_axi_mpm_ep_bvalid), + .m_axi_mpm_ep_bready (m_axi_mpm_ep_bready), + .m_axi_mpm_ep_araddr (m_axi_mpm_ep_araddr), + .m_axi_mpm_ep_arprot (), + .m_axi_mpm_ep_arvalid (m_axi_mpm_ep_arvalid), + .m_axi_mpm_ep_arready (m_axi_mpm_ep_arready), + .m_axi_mpm_ep_rdata (m_axi_mpm_ep_rdata), + .m_axi_mpm_ep_rresp (m_axi_mpm_ep_rresp), + .m_axi_mpm_ep_rvalid (m_axi_mpm_ep_rvalid), + .m_axi_mpm_ep_rready (m_axi_mpm_ep_rready), + .adc_tile224_ch0_dout_i_tdata (adc_tile_dout_i_tdata[0]), + .adc_tile224_ch0_dout_i_tready (adc_tile_dout_i_tready[0]), + .adc_tile224_ch0_dout_i_tvalid (adc_tile_dout_i_tvalid[0]), + .adc_tile224_ch0_dout_q_tdata (adc_tile_dout_q_tdata[0]), + .adc_tile224_ch0_dout_q_tready (adc_tile_dout_q_tready[0]), + .adc_tile224_ch0_dout_q_tvalid (adc_tile_dout_q_tvalid[0]), + .adc_tile224_ch1_dout_i_tdata (adc_tile_dout_i_tdata[1]), + .adc_tile224_ch1_dout_i_tready (adc_tile_dout_i_tready[1]), + .adc_tile224_ch1_dout_i_tvalid (adc_tile_dout_i_tvalid[1]), + .adc_tile224_ch1_dout_q_tdata (adc_tile_dout_q_tdata[1]), + .adc_tile224_ch1_dout_q_tready (adc_tile_dout_q_tready[1]), + .adc_tile224_ch1_dout_q_tvalid (adc_tile_dout_q_tvalid[1]), + .adc_tile225_ch0_dout_i_tdata (adc_tile_dout_i_tdata[2]), + .adc_tile225_ch0_dout_i_tready (adc_tile_dout_i_tready[2]), + .adc_tile225_ch0_dout_i_tvalid (adc_tile_dout_i_tvalid[2]), + .adc_tile225_ch0_dout_q_tdata (adc_tile_dout_q_tdata[2]), + .adc_tile225_ch0_dout_q_tready (adc_tile_dout_q_tready[2]), + .adc_tile225_ch0_dout_q_tvalid (adc_tile_dout_q_tvalid[2]), + .adc_tile225_ch1_dout_i_tdata (adc_tile_dout_i_tdata[3]), + .adc_tile225_ch1_dout_i_tready (adc_tile_dout_i_tready[3]), + .adc_tile225_ch1_dout_i_tvalid (adc_tile_dout_i_tvalid[3]), + .adc_tile225_ch1_dout_q_tdata (adc_tile_dout_q_tdata[3]), + .adc_tile225_ch1_dout_q_tready (adc_tile_dout_q_tready[3]), + .adc_tile225_ch1_dout_q_tvalid (adc_tile_dout_q_tvalid[3]), + .adc_tile226_ch0_dout_i_tdata (adc_tile_dout_i_tdata[4]), + .adc_tile226_ch0_dout_i_tready (adc_tile_dout_i_tready[4]), + .adc_tile226_ch0_dout_i_tvalid (adc_tile_dout_i_tvalid[4]), + .adc_tile226_ch0_dout_q_tdata (adc_tile_dout_q_tdata[4]), + .adc_tile226_ch0_dout_q_tready (adc_tile_dout_q_tready[4]), + .adc_tile226_ch0_dout_q_tvalid (adc_tile_dout_q_tvalid[4]), + .adc_tile226_ch1_dout_i_tdata (adc_tile_dout_i_tdata[5]), + .adc_tile226_ch1_dout_i_tready (adc_tile_dout_i_tready[5]), + .adc_tile226_ch1_dout_i_tvalid (adc_tile_dout_i_tvalid[5]), + .adc_tile226_ch1_dout_q_tdata (adc_tile_dout_q_tdata[5]), + .adc_tile226_ch1_dout_q_tready (adc_tile_dout_q_tready[5]), + .adc_tile226_ch1_dout_q_tvalid (adc_tile_dout_q_tvalid[5]), + .adc_tile227_ch0_dout_i_tdata (adc_tile_dout_i_tdata[6]), + .adc_tile227_ch0_dout_i_tready (adc_tile_dout_i_tready[6]), + .adc_tile227_ch0_dout_i_tvalid (adc_tile_dout_i_tvalid[6]), + .adc_tile227_ch0_dout_q_tdata (adc_tile_dout_q_tdata[6]), + .adc_tile227_ch0_dout_q_tready (adc_tile_dout_q_tready[6]), + .adc_tile227_ch0_dout_q_tvalid (adc_tile_dout_q_tvalid[6]), + .adc_tile227_ch1_dout_i_tdata (adc_tile_dout_i_tdata[7]), + .adc_tile227_ch1_dout_i_tready (adc_tile_dout_i_tready[7]), + .adc_tile227_ch1_dout_i_tvalid (adc_tile_dout_i_tvalid[7]), + .adc_tile227_ch1_dout_q_tdata (adc_tile_dout_q_tdata[7]), + .adc_tile227_ch1_dout_q_tready (adc_tile_dout_q_tready[7]), + .adc_tile227_ch1_dout_q_tvalid (adc_tile_dout_q_tvalid[7]), + .dac_tile228_ch0_vout_v_n (DB0_TX_N[0]), + .dac_tile228_ch0_vout_v_p (DB0_TX_P[0]), + .dac_tile228_ch1_vout_v_n (DB0_TX_N[1]), + .dac_tile228_ch1_vout_v_p (DB0_TX_P[1]), + .dac_tile228_ch2_vout_v_n (DB0_TX_N[2]), + .dac_tile228_ch2_vout_v_p (DB0_TX_P[2]), + .dac_tile228_ch3_vout_v_n (DB0_TX_N[3]), + .dac_tile228_ch3_vout_v_p (DB0_TX_P[3]), + .dac_tile229_ch0_vout_v_n (DB1_TX_N[0]), + .dac_tile229_ch0_vout_v_p (DB1_TX_P[0]), + .dac_tile229_ch1_vout_v_n (DB1_TX_N[1]), + .dac_tile229_ch1_vout_v_p (DB1_TX_P[1]), + .dac_tile229_ch2_vout_v_n (DB1_TX_N[2]), + .dac_tile229_ch2_vout_v_p (DB1_TX_P[2]), + .dac_tile229_ch3_vout_v_n (DB1_TX_N[3]), + .dac_tile229_ch3_vout_v_p (DB1_TX_P[3]), + .dac_tile228_ch0_din_tdata (dac_tile_din_tdata[0]), + .dac_tile228_ch0_din_tvalid (dac_tile_din_tvalid[0]), + .dac_tile228_ch0_din_tready (dac_tile_din_tready[0]), + .dac_tile228_ch1_din_tdata (dac_tile_din_tdata[1]), + .dac_tile228_ch1_din_tvalid (dac_tile_din_tvalid[1]), + .dac_tile228_ch1_din_tready (dac_tile_din_tready[1]), + .dac_tile228_ch2_din_tdata (dac_tile_din_tdata[2]), + .dac_tile228_ch2_din_tvalid (dac_tile_din_tvalid[2]), + .dac_tile228_ch2_din_tready (dac_tile_din_tready[2]), + .dac_tile228_ch3_din_tdata (dac_tile_din_tdata[3]), + .dac_tile228_ch3_din_tvalid (dac_tile_din_tvalid[3]), + .dac_tile228_ch3_din_tready (dac_tile_din_tready[3]), + .dac_tile229_ch0_din_tdata (dac_tile_din_tdata[4]), + .dac_tile229_ch0_din_tvalid (dac_tile_din_tvalid[4]), + .dac_tile229_ch0_din_tready (dac_tile_din_tready[4]), + .dac_tile229_ch1_din_tdata (dac_tile_din_tdata[5]), + .dac_tile229_ch1_din_tvalid (dac_tile_din_tvalid[5]), + .dac_tile229_ch1_din_tready (dac_tile_din_tready[5]), + .dac_tile229_ch2_din_tdata (dac_tile_din_tdata[6]), + .dac_tile229_ch2_din_tvalid (dac_tile_din_tvalid[6]), + .dac_tile229_ch2_din_tready (dac_tile_din_tready[6]), + .dac_tile229_ch3_din_tdata (dac_tile_din_tdata[7]), + .dac_tile229_ch3_din_tvalid (dac_tile_din_tvalid[7]), + .dac_tile229_ch3_din_tready (dac_tile_din_tready[7]), + .s_axi_hpc1_awid (), + .s_axi_hpc1_awaddr (), + .s_axi_hpc1_awlen (), + .s_axi_hpc1_awsize (), + .s_axi_hpc1_awburst (), + .s_axi_hpc1_awlock (), + .s_axi_hpc1_awcache (), + .s_axi_hpc1_awprot (), + .s_axi_hpc1_awqos (), + .s_axi_hpc1_awvalid (), + .s_axi_hpc1_awready (), + .s_axi_hpc1_wdata (), + .s_axi_hpc1_wstrb (), + .s_axi_hpc1_wlast (), + .s_axi_hpc1_wvalid (), + .s_axi_hpc1_wready (), + .s_axi_hpc1_bid (), + .s_axi_hpc1_bresp (), + .s_axi_hpc1_bvalid (), + .s_axi_hpc1_bready (), + .s_axi_hpc1_arid (), + .s_axi_hpc1_araddr (), + .s_axi_hpc1_arlen (), + .s_axi_hpc1_arsize (), + .s_axi_hpc1_arburst (), + .s_axi_hpc1_arlock (), + .s_axi_hpc1_arcache (), + .s_axi_hpc1_arprot (), + .s_axi_hpc1_arqos (), + .s_axi_hpc1_arvalid (), + .s_axi_hpc1_arready (), + .s_axi_hpc1_rid (), + .s_axi_hpc1_rdata (), + .s_axi_hpc1_rresp (), + .s_axi_hpc1_rlast (), + .s_axi_hpc1_rvalid (), + .s_axi_hpc1_rready (), + .sysref_rf_in_diff_n (SYSREF_RF_N), + .sysref_rf_in_diff_p (SYSREF_RF_P), + .adc_tile224_ch0_vin_v_n (DB0_RX_N[0]), + .adc_tile224_ch0_vin_v_p (DB0_RX_P[0]), + .adc_tile224_ch1_vin_v_n (DB0_RX_N[1]), + .adc_tile224_ch1_vin_v_p (DB0_RX_P[1]), + .adc_tile225_ch0_vin_v_n (DB0_RX_N[2]), + .adc_tile225_ch0_vin_v_p (DB0_RX_P[2]), + .adc_tile225_ch1_vin_v_n (DB0_RX_N[3]), + .adc_tile225_ch1_vin_v_p (DB0_RX_P[3]), + .adc_tile226_ch0_vin_v_n (DB1_RX_N[0]), + .adc_tile226_ch0_vin_v_p (DB1_RX_P[0]), + .adc_tile226_ch1_vin_v_n (DB1_RX_N[1]), + .adc_tile226_ch1_vin_v_p (DB1_RX_P[1]), + .adc_tile227_ch0_vin_v_n (DB1_RX_N[2]), + .adc_tile227_ch0_vin_v_p (DB1_RX_P[2]), + .adc_tile227_ch1_vin_v_n (DB1_RX_N[3]), + .adc_tile227_ch1_vin_v_p (DB1_RX_P[3]), + .s_axi_hpc1_aruser (), + .s_axi_hpc1_awuser (), + .clk_adc0 () + ); `endif @@ -1672,7 +2164,152 @@ module x4xx ( end // gen_rf_core_full end // gen_rf_cores - `ifdef X410 + `ifdef X440 + + wire [NUM_DBOARDS-1:0] sync_clk; + + // Import LED register offsets in MB CPLD + `include "cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh" + `include "regmap/pl_cpld_regmap_utils.vh" + + for ( db_i = 0; db_i < (NUM_DBOARDS); db_i = db_i + 1) begin : db_gpio_gen + + localparam LED_REGISTER_ADDRESS = (db_i == 0) ? MB_CPLD + PL_DB0_LED_REGISTERS + : (db_i == 1) ? MB_CPLD + PL_DB1_LED_REGISTERS + : 0; + + db_gpio_interface#( + .LED_REGISTER_ADDRESS (LED_REGISTER_ADDRESS) + ) db_gpio_interface_i ( + .radio_clk (radio_clk[db_i]), + .pll_ref_clk (pll_ref_clk), + .db_state (db_state[db_i]), + .in_sync_clk (clk5), + .out_sync_clk (sync_clk[db_i]), + .ctrlport_rst (radio_rst[db_i]), + .s_ctrlport_req_wr (db_ctrlport_req_wr[db_i]), + .s_ctrlport_req_rd (db_ctrlport_req_rd[db_i]), + .s_ctrlport_req_addr (db_ctrlport_req_addr[db_i]), + .s_ctrlport_req_data (db_ctrlport_req_data[db_i]), + .s_ctrlport_resp_ack (db_ctrlport_resp_ack[db_i]), + .s_ctrlport_resp_status (db_ctrlport_resp_status[db_i]), + .s_ctrlport_resp_data (db_ctrlport_resp_data[db_i]), + .m_ctrlport_req_wr (db_to_cpld_ctrlport_req_wr[db_i]), + .m_ctrlport_req_rd (db_to_cpld_ctrlport_req_rd[db_i]), + .m_ctrlport_req_addr (db_to_cpld_ctrlport_req_addr[db_i]), + .m_ctrlport_req_data (db_to_cpld_ctrlport_req_data[db_i]), + .m_ctrlport_req_byte_en (db_to_cpld_ctrlport_req_byte_en[db_i]), + .m_ctrlport_resp_ack (db_to_cpld_ctrlport_resp_ack[db_i]), + .m_ctrlport_resp_status (db_to_cpld_ctrlport_resp_status[db_i]), + .m_ctrlport_resp_data (db_to_cpld_ctrlport_resp_data[db_i]), + .gpio_in (db_gpio_in_int[db_i]), + .gpio_out (db_gpio_out_int[db_i]), + .gpio_out_en (db_gpio_out_en_int[db_i]), + .version_info (db_gpio_ifc_version[db_i]) + ); + end + + // The sync_clk flip-flop is driven in single-ended mode. The _n side is + // set statically via a voltage divider with DB0_GPIO[12] and + // DB1_GPIO[16] providing the source voltages. + assign DB0_GPIO[12] = 1'b1; + assign DB0_GPIO[13] = sync_clk[0]; + assign DB1_GPIO[16] = 1'b1; + assign DB1_GPIO[17] = sync_clk[1]; + + // GPIO to CPLD ctrlport interface for db1 and radio_clk[0] + wire db1_to_cpld_radio0_ctrlport_req_rd; + wire db1_to_cpld_radio0_ctrlport_req_wr; + wire [19:0] db1_to_cpld_radio0_ctrlport_req_addr; + wire [31:0] db1_to_cpld_radio0_ctrlport_req_data; + wire [ 3:0] db1_to_cpld_radio0_ctrlport_req_byte_en; + wire db1_to_cpld_radio0_ctrlport_req_has_time; + wire [63:0] db1_to_cpld_radio0_ctrlport_req_time; + wire db1_to_cpld_radio0_ctrlport_resp_ack; + wire [31:0] db1_to_cpld_radio0_ctrlport_resp_data; + wire [ 1:0] db1_to_cpld_radio0_ctrlport_resp_status; + + // Need to cross clocks from radio_clk[1] to radio_clk[0] to combine the + // ctrlport buses. + ctrlport_clk_cross ctrlport_clk_cross_i ( + .rst (radio_rst[1]), + .s_ctrlport_clk (radio_clk[1]), + .s_ctrlport_req_wr (db_to_cpld_ctrlport_req_wr[1]), + .s_ctrlport_req_rd (db_to_cpld_ctrlport_req_rd[1]), + .s_ctrlport_req_addr (db_to_cpld_ctrlport_req_addr[1]), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data (db_to_cpld_ctrlport_req_data[1]), + .s_ctrlport_req_byte_en (db_to_cpld_ctrlport_req_byte_en[1]), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack (db_to_cpld_ctrlport_resp_ack[1]), + .s_ctrlport_resp_status (db_to_cpld_ctrlport_resp_status[1]), + .s_ctrlport_resp_data (db_to_cpld_ctrlport_resp_data[1]), + .m_ctrlport_clk (radio_clk[0]), + .m_ctrlport_req_wr (db1_to_cpld_radio0_ctrlport_req_wr), + .m_ctrlport_req_rd (db1_to_cpld_radio0_ctrlport_req_rd), + .m_ctrlport_req_addr (db1_to_cpld_radio0_ctrlport_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (db1_to_cpld_radio0_ctrlport_req_data), + .m_ctrlport_req_byte_en (db1_to_cpld_radio0_ctrlport_req_byte_en), + .m_ctrlport_req_has_time (), + .m_ctrlport_req_time (), + .m_ctrlport_resp_ack (db1_to_cpld_radio0_ctrlport_resp_ack), + .m_ctrlport_resp_status (db1_to_cpld_radio0_ctrlport_resp_status), + .m_ctrlport_resp_data (db1_to_cpld_radio0_ctrlport_resp_data) + ); + + // after both ctrlport buses are on radio_clk[0], combine them to go + // into cpld_interface + ctrlport_combiner #( + .NUM_MASTERS (NUM_DBOARDS), + .PRIORITY (0) + ) ctrlport_combiner_db_i ( + .ctrlport_clk (radio_clk[0]), + .ctrlport_rst (radio_rst[0]), + .s_ctrlport_req_wr ({db1_to_cpld_radio0_ctrlport_req_wr,db_to_cpld_ctrlport_req_wr[0]}), + .s_ctrlport_req_rd ({db1_to_cpld_radio0_ctrlport_req_rd,db_to_cpld_ctrlport_req_rd[0]}), + .s_ctrlport_req_addr ({db1_to_cpld_radio0_ctrlport_req_addr,db_to_cpld_ctrlport_req_addr[0]}), + .s_ctrlport_req_portid (), + .s_ctrlport_req_rem_epid (), + .s_ctrlport_req_rem_portid (), + .s_ctrlport_req_data ({db1_to_cpld_radio0_ctrlport_req_data,db_to_cpld_ctrlport_req_data[0]}), + .s_ctrlport_req_byte_en ({db1_to_cpld_radio0_ctrlport_req_byte_en,db_to_cpld_ctrlport_req_byte_en[0]}), + .s_ctrlport_req_has_time (), + .s_ctrlport_req_time (), + .s_ctrlport_resp_ack ({db1_to_cpld_radio0_ctrlport_resp_ack,db_to_cpld_ctrlport_resp_ack[0]}), + .s_ctrlport_resp_status ({db1_to_cpld_radio0_ctrlport_resp_status,db_to_cpld_ctrlport_resp_status[0]}), + .s_ctrlport_resp_data ({db1_to_cpld_radio0_ctrlport_resp_data,db_to_cpld_ctrlport_resp_data[0]}), + .m_ctrlport_req_wr (db_to_cpld_comb_ctrlport_req_wr), + .m_ctrlport_req_rd (db_to_cpld_comb_ctrlport_req_rd), + .m_ctrlport_req_addr (db_to_cpld_comb_ctrlport_req_addr), + .m_ctrlport_req_portid (), + .m_ctrlport_req_rem_epid (), + .m_ctrlport_req_rem_portid (), + .m_ctrlport_req_data (db_to_cpld_comb_ctrlport_req_data), + .m_ctrlport_req_byte_en (db_to_cpld_comb_ctrlport_req_byte_en), + .m_ctrlport_req_has_time (db_to_cpld_comb_ctrlport_req_has_time), + .m_ctrlport_req_time (db_to_cpld_comb_ctrlport_req_time), + .m_ctrlport_resp_ack (db_to_cpld_comb_ctrlport_resp_ack), + .m_ctrlport_resp_status (db_to_cpld_comb_ctrlport_resp_status), + .m_ctrlport_resp_data (db_to_cpld_comb_ctrlport_resp_data) + ); + + // on X440, some gpio are used to drive sync clk, and not tri-state. + for (db_gpio_i = 0; db_gpio_i < 20; db_gpio_i = db_gpio_i + 1) begin: db_gpio_tristate_gen + if (db_gpio_i != 12 || db_gpio_i != 13) begin + assign DB0_GPIO[db_gpio_i] = (db_gpio_out_en_ext[0][db_gpio_i]) ? db_gpio_out_ext[0][db_gpio_i] : 1'bz; + end + if (db_gpio_i != 16 || db_gpio_i != 17) begin + assign DB1_GPIO[db_gpio_i] = (db_gpio_out_en_ext[1][db_gpio_i]) ? db_gpio_out_ext[1][db_gpio_i] : 1'bz; + end + end + + `else // X410 for ( db_i = 0; db_i < (NUM_DBOARDS); db_i = db_i + 1) begin : db_gpio_gen db_gpio_interface db_gpio_interface_i ( @@ -2213,7 +2850,38 @@ module x4xx ( wire mfg_test_en_gty_rcv_clk; // Map RFDC ports to x4xx_core ports - `ifdef X410 + `ifdef X440 + + `include "regmap/x440/rfdc_mapping_regmap_utils.vh" + + assign rx_data_qi = { adc_data_out_tdata [CH7_RX_MAPPING], adc_data_out_tdata [CH6_RX_MAPPING], + adc_data_out_tdata [CH5_RX_MAPPING], adc_data_out_tdata [CH4_RX_MAPPING], + adc_data_out_tdata [CH3_RX_MAPPING], adc_data_out_tdata [CH2_RX_MAPPING], + adc_data_out_tdata [CH1_RX_MAPPING], adc_data_out_tdata [CH0_RX_MAPPING] }; + assign rx_stb = { adc_data_out_tvalid[CH7_RX_MAPPING], adc_data_out_tvalid[CH6_RX_MAPPING], + adc_data_out_tvalid[CH5_RX_MAPPING], adc_data_out_tvalid[CH4_RX_MAPPING], + adc_data_out_tvalid[CH3_RX_MAPPING], adc_data_out_tvalid[CH2_RX_MAPPING], + adc_data_out_tvalid[CH1_RX_MAPPING], adc_data_out_tvalid[CH0_RX_MAPPING] }; + + assign { dac_data_in_tdata[CH7_TX_MAPPING], dac_data_in_tdata[CH6_TX_MAPPING], + dac_data_in_tdata[CH5_TX_MAPPING], dac_data_in_tdata[CH4_TX_MAPPING], + dac_data_in_tdata[CH3_TX_MAPPING], dac_data_in_tdata[CH2_TX_MAPPING], + dac_data_in_tdata[CH1_TX_MAPPING], dac_data_in_tdata[CH0_TX_MAPPING] } = tx_data_qi; + assign { tx_stb [CH7_TX_MAPPING], tx_stb [CH6_TX_MAPPING], + tx_stb [CH5_TX_MAPPING], tx_stb [CH4_TX_MAPPING], + tx_stb [CH3_TX_MAPPING], tx_stb [CH2_TX_MAPPING], + tx_stb [CH1_TX_MAPPING], tx_stb [CH0_TX_MAPPING] } = dac_data_in_tready; + + + assign { swapped_invert_adc_iq_rclk2[CH7_RX_MAPPING], swapped_invert_adc_iq_rclk2[CH6_RX_MAPPING], + swapped_invert_adc_iq_rclk2[CH5_RX_MAPPING], swapped_invert_adc_iq_rclk2[CH4_RX_MAPPING], + swapped_invert_adc_iq_rclk2[CH3_RX_MAPPING], swapped_invert_adc_iq_rclk2[CH2_RX_MAPPING], + swapped_invert_adc_iq_rclk2[CH1_RX_MAPPING], swapped_invert_adc_iq_rclk2[CH0_RX_MAPPING] } = invert_adc_iq_rclk2; + assign { swapped_invert_dac_iq_rclk2[CH7_TX_MAPPING], swapped_invert_dac_iq_rclk2[CH6_TX_MAPPING], + swapped_invert_dac_iq_rclk2[CH5_TX_MAPPING], swapped_invert_dac_iq_rclk2[CH4_TX_MAPPING], + swapped_invert_dac_iq_rclk2[CH3_TX_MAPPING], swapped_invert_dac_iq_rclk2[CH2_TX_MAPPING], + swapped_invert_dac_iq_rclk2[CH1_TX_MAPPING], swapped_invert_dac_iq_rclk2[CH0_TX_MAPPING] } = invert_dac_iq_rclk2; + `else // X410 // IMPORTANT! For ZBX RevB, there is a RX channel swap in layout // that we need to correct for here in HDL. assign rx_data_qi = { adc_data_out_tdata [2], adc_data_out_tdata [3], @@ -2507,6 +3175,13 @@ endmodule // // // +// +// +// This map contains register windows for controlling the different sources +// that drive the state of FBX control lines. +// +// +// // // // diff --git a/top/x400/x4xx_core.v b/top/x400/x4xx_core.v index e2f6a65..12a3f81 100644 --- a/top/x400/x4xx_core.v +++ b/top/x400/x4xx_core.v @@ -605,8 +605,15 @@ module x4xx_core #( .chdr_aclk (rfnoc_chdr_clk), .ctrl_aclk (rfnoc_ctrl_clk), .core_arst (rfnoc_ctrl_rst), + `ifdef X440 + .radio0_clk (radio_clk[0]), + .radio0_2x_clk (radio_clk_2x[0]), + .radio1_clk (radio_clk[1]), + .radio1_2x_clk (radio_clk_2x[1]), + `else .radio_clk (radio_clk[0]), .radio_2x_clk (radio_clk_2x[0]), + `endif .dram_clk (dram_clk), .device_id (device_id), .m_ctrlport_radio0_req_wr (ctrlport_radio_req_wr [0* 1+: 1]), @@ -641,7 +648,12 @@ module x4xx_core #( .radio_tx_stb_radio0 ({ tx_stb0}), .radio_tx_data_radio0 ({ tx_data0}), .radio_tx_running_radio0 ({ tx_running0}), + `ifdef X440 + .radio_time0 (radio_time[0*64+:64]), + .radio_time1 (radio_time[1*64+:64]), + `else .radio_time (radio_time[0*64+:64]), + `endif .axi_rst (dram_rst), .m_axi_awid (dram_axi_awid), .m_axi_awaddr (dram_axi_awaddr), diff --git a/top/x400/x4xx_core_common.v b/top/x400/x4xx_core_common.v index 42492c9..27eff80 100644 --- a/top/x400/x4xx_core_common.v +++ b/top/x400/x4xx_core_common.v @@ -85,7 +85,7 @@ module x4xx_core_common #( // Timekeeper (Domain: radio_clk) input wire [ 7:0] radio_spc, - input wire sample_rx_stb, + input wire [NUM_TIMEKEEPERS-1:0] sample_rx_stb, input wire [ 3:0] time_ignore_bits, output wire [64*NUM_TIMEKEEPERS-1:0] radio_time, @@ -352,11 +352,12 @@ module x4xx_core_common #( .s_ctrlport_resp_ack (timekeeper_resp_ack[tk_i]), .s_ctrlport_resp_data (timekeeper_resp_data[CTRLPORT_DATA_W*tk_i+:CTRLPORT_DATA_W]), .time_increment (radio_spc), - .sample_rx_stb (sample_rx_stb), + .sample_rx_stb (sample_rx_stb[tk_i]), .pps (pps_radioclk[tk_i]), .tb_timestamp (radio_time[64*tk_i+:64]), .tb_timestamp_last_pps (), - .tb_period_ns_q32 () + .tb_period_ns_q32 (), + .tb_changed () ); end endgenerate @@ -428,10 +429,13 @@ module x4xx_core_common #( ) ctrlport_timer_i ( .clk (radio_clk[db_i]), .rst (radio_rst[db_i]), - `ifdef X410 + `ifdef X440 + .time_now (radio_time[64*db_i+:64]), + .time_now_stb (sample_rx_stb[db_i]), + `else .time_now (radio_time), - `endif .time_now_stb (sample_rx_stb), + `endif .time_ignore_bits (time_ignore_bits), .s_ctrlport_req_wr (s_radio_ctrlport_req_wr [ 1*db_i+: 1]), .s_ctrlport_req_rd (s_radio_ctrlport_req_rd [ 1*db_i+: 1]), @@ -553,7 +557,8 @@ module x4xx_core_common #( end x4xx_gpio_atr #( - .REG_SIZE (RADIO_GPIO_ATR_REGS_SIZE) + .REG_SIZE (RADIO_GPIO_ATR_REGS_SIZE), + .NUM_CH_PER_DB (NUM_CH_PER_DB) ) x4xx_gpio_atr_i ( .ctrlport_clk (radio_clk[db_i]), .ctrlport_rst (radio_rst[db_i]), diff --git a/top/x400/x4xx_dram.v b/top/x400/x4xx_dram.v index 203c0c3..453f2b7 100644 --- a/top/x400/x4xx_dram.v +++ b/top/x400/x4xx_dram.v @@ -1285,7 +1285,11 @@ module x4xx_dram #( ERROR_invalid_dwidth(); end - ddr4_64bits ddr4_64bits_i ( + `ifdef X440 + ddr4_64bits_x440 ddr4_64bits_i ( + `else + ddr4_64bits ddr4_64bits_i ( + `endif .sys_rst (sys_rst ), .c0_sys_clk_p (dram0_sys_clk_p ), .c0_sys_clk_n (dram0_sys_clk_n ), @@ -1978,7 +1982,11 @@ module x4xx_dram #( ERROR_invalid_dwidth(); end - ddr4_64bits ddr4_64bits_i ( + `ifdef X440 + ddr4_64bits_x440 ddr4_64bits_i ( + `else + ddr4_64bits ddr4_64bits_i ( + `endif .sys_rst (sys_rst ), .c0_sys_clk_p (dram1_sys_clk_p ), .c0_sys_clk_n (dram1_sys_clk_n ), diff --git a/top/x400/x4xx_global_regs.v b/top/x400/x4xx_global_regs.v index f39d4e2..8c9e2f9 100644 --- a/top/x400/x4xx_global_regs.v +++ b/top/x400/x4xx_global_regs.v @@ -80,7 +80,11 @@ module x4xx_global_regs #( `include "regmap/global_regs_regmap_utils.vh" // Variant-dependent register map. - `include "regmap/x410/versioning_regs_regmap_utils.vh" + `ifdef X440 + `include "regmap/x440/versioning_regs_regmap_utils.vh" + `else // Use X410 as the default variant for regmap. + `include "regmap/x410/versioning_regs_regmap_utils.vh" + `endif // Make DEVICE_ID default to anything but 0, since that has special meaning diff --git a/top/x400/x4xx_gpio_spi.v b/top/x400/x4xx_gpio_spi.v index 1d4e774..25591d5 100644 --- a/top/x400/x4xx_gpio_spi.v +++ b/top/x400/x4xx_gpio_spi.v @@ -343,8 +343,32 @@ module x4xx_gpio_spi #( // SPI master //--------------------------------------------------------------------------- - `ifdef X410 + `ifdef X440 + simple_spi_core #( + .BASE (0), + .WIDTH (NUM_SLAVES), + .CLK_IDLE (0), + .SEN_IDLE ({NUM_SLAVES{1'b1}}) + ) simple_spi_core_i ( + .clock (ctrlport_clk), + .reset (ctrlport_rst), + .set_stb (set_stb), + .set_addr (set_addr), + .set_data (set_data), + .readback (readback), + .readback_stb (readback_stb), + .ready (), + .sen (ss[NUM_SLAVES-1:0]), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .debug () + ); + + assign readback_stb_extended = readback_stb; + + `else // X410 // Register set_stb for use in 2x domain. reg set_stb_2x = 1'b0; reg ctrlport_clk_phase = 1'b1; @@ -423,7 +447,13 @@ module x4xx_gpio_spi #( assign gated_sclk[i] = gpio_is_sclk[i] ? sclk : 1'b0; // register signals once remapping logic is resolved - `ifdef X410 + `ifdef X440 + always @ (posedge ctrlport_clk) begin + mosi_mux_out_dlyd[i] <= mosi_mux_out[i]; + gpio_is_sclk_dlyd[i] <= gpio_is_sclk[i]; + gated_sclk_dlyd[i] <= gated_sclk[i]; + end + `else // X410 always @ (posedge ctrlport_clk_2x) begin mosi_mux_out_dlyd[i] <= mosi_mux_out[i]; gpio_is_sclk_dlyd[i] <= gpio_is_sclk[i]; diff --git a/top/x400/x4xx_versioning_regs.v b/top/x400/x4xx_versioning_regs.v index a51c121..41685f2 100644 --- a/top/x400/x4xx_versioning_regs.v +++ b/top/x400/x4xx_versioning_regs.v @@ -69,7 +69,9 @@ module x4xx_versioning_regs #( ); // Variant-dependent register map. - `ifdef X410 + `ifdef X440 + `include "regmap/x440/versioning_regs_regmap_utils.vh" + `else // Use X410 as the default variant for regmap. `include "regmap/x410/versioning_regs_regmap_utils.vh" `endif