Wade Fife b2684c42a7 fpga: e31x: Fix DRAM traffic gen IP name ...

Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to
IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.


Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3

2022-03-23 08:55:36 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Fix PPS edge detection

2022-03-09 17:49:38 -06:00

sim

fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svh

2022-01-25 14:09:15 -07:00

tools

fpga: tools: Add CG_400 image to X410 binaries package

2022-03-15 08:49:25 -05:00

top

fpga: e31x: Fix DRAM traffic gen IP name

2022-03-23 08:55:36 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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