Wade Fife 21091fb07c fpga: e31x: Add PROTOVER to eth_internal ...

Original-commit: 4d85a77d5f1a97020a7ad7d06a1ce75d94964309

2022-09-01 14:41:55 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add eth_ipv4_interface_tb

2022-08-29 17:01:45 -05:00

sim

fpga: sim: Support unused tkeep in AxiStreamPacket::dump_bytes()

2022-08-29 17:01:45 -05:00

tools

fpga: lib: Add eth_ipv4_interface_tb

2022-08-29 17:01:45 -05:00

top

fpga: e31x: Add PROTOVER to eth_internal

2022-09-01 14:41:55 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%