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//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_ipv4_interface_tb
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//
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// Description:
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//
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// Testbench for eth_ipv4_interface. It uses the eth_ipv4_interface_wrapper
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// to instantiate it to test the wrapper also.
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//
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// Parameters:
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//
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// ENET_W : Ethernet MAC data port width
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// CPU_W : CPU data port width
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// CHDR_W : CHDR width and bus width on the RFNoC CHDR interface
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// NET_CHDR_W : CHDR width of network traffic (as generated on the host; may
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// be different from the bus width).
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// EN_RAW_UDP : Enable raw UDP testing
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//
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`default_nettype none
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module eth_ipv4_interface_tb #(
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parameter int ENET_W = 64,
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parameter int CPU_W = 64,
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parameter int CHDR_W = 64,
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parameter int NET_CHDR_W = CHDR_W,
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parameter bit EN_RAW_UDP = 1
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);
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//---------------------------------------------------------------------------
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// Includes
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//---------------------------------------------------------------------------
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`include "test_exec.svh"
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// Eth parameters must be defined before including eth_regs.vh
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localparam int BASE = 0;
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localparam int REG_AWIDTH = 14;
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`include "../../xport_sv/eth_regs.vh"
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import PkgTestExec::*;
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import PkgChdrUtils::*;
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import PkgChdrIfaceBfm::*;
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import PkgAxiStreamBfm::*;
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import PkgChdrBfm::*;
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import PkgEthernet::*;
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import PkgRandom::*;
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//---------------------------------------------------------------------------
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// Testbench Parameters
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//---------------------------------------------------------------------------
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localparam real ETH_CLK_PERIOD = 8.0;
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localparam real BUS_CLK_PERIOD = 5.0;
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localparam real CPU_CLK_PERIOD = 25.0;
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localparam int ITEM_W = 8; // Use bytes for this simulation
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localparam int MAX_ITEM_PER_PACKET = 8192;
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// The DUT's MAC, IP, UDP info
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localparam bit [47:0] MAC_ADDR = 48'hFEEDEADDBEEF;
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localparam bit [31:0] IP_ADDR = { 8'd192, 8'd168, 8'd10, 8'd2 };
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localparam bit [15:0] UDP_PORT = 49153;
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// RFNoC device and node instance
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localparam bit [15:0] DEVICE_ID = 16'h1234;
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localparam bit [31:0] NODE_INST = 32'hF1B0412A;
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// Enable debug prints
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localparam bit DEBUG = 0;
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// Number of unique endpoints to simulate
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localparam int NUM_EPID = 8;
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//---------------------------------------------------------------------------
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// Clocks and Resets
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//---------------------------------------------------------------------------
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bit bus_clk, eth_clk, cpu_clk;
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bit bus_rst, eth_rst, cpu_rst;
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sim_clock_gen #(.PERIOD(BUS_CLK_PERIOD), .AUTOSTART(0))
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bus_clk_gen (.clk(bus_clk), .rst(bus_rst));
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sim_clock_gen #(.PERIOD(ETH_CLK_PERIOD), .AUTOSTART(0))
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eth_clk_gen (.clk(eth_clk), .rst(eth_rst));
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sim_clock_gen #(.PERIOD(CPU_CLK_PERIOD), .AUTOSTART(0))
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cpu_clk_gen (.clk(cpu_clk), .rst(cpu_rst));
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//---------------------------------------------------------------------------
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// Bus Functional Models
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//---------------------------------------------------------------------------
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localparam int ENET_USER_W =
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eth_ipv4_interface_wrapper_dut.ENET_USER_W;
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localparam int CPU_USER_W =
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eth_ipv4_interface_wrapper_dut.CPU_USER_W;
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localparam bit [7:0] COMPAT_MAJOR =
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eth_ipv4_interface_wrapper_dut.eth_ipv4_interface_i.COMPAT_MAJOR;
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localparam bit [7:0] COMPAT_MINOR =
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eth_ipv4_interface_wrapper_dut.eth_ipv4_interface_i.COMPAT_MINOR;
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AxiStreamIf #(.DATA_WIDTH(ENET_W), .USER_WIDTH(ENET_USER_W))
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eth_rx (eth_clk, eth_rst);
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AxiStreamIf #(.DATA_WIDTH(ENET_W), .USER_WIDTH(ENET_USER_W))
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eth_tx (eth_clk, eth_rst);
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logic [ENET_W/8-1:0] eth_tx_tkeep;
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AxiStreamIf #(.DATA_WIDTH(CHDR_W))
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v2e (bus_clk, bus_rst);
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AxiStreamIf #(.DATA_WIDTH(CHDR_W))
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e2v (bus_clk, bus_rst);
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W))
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c2e (cpu_clk, cpu_rst);
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AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W))
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e2c (cpu_clk, cpu_rst);
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regport_if #(REG_AWIDTH) regport (bus_clk, bus_rst);
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ChdrIfaceBfm #(CHDR_W, ITEM_W) chdr_bfm =
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new(v2e, e2v, MAX_ITEM_PER_PACKET*ITEM_W/8, CHDR_W/ITEM_W);
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AxiStreamBfm #(ENET_W, ENET_USER_W) eth_bfm = new(eth_rx, eth_tx);
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typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
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typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t;
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typedef AxiStreamPacket #(ENET_W, ENET_USER_W)::AxisPacket_t AxisEthPacket_t;
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// Drive unused ports
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assign c2e.tvalid = 1'b0;
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assign e2c.tready = 1'b1;
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//---------------------------------------------------------------------------
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// DUT
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//---------------------------------------------------------------------------
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// DUT parameters
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localparam logic [15:0] PROTOVER = {8'd1, 8'd0};
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localparam int CPU_FIFO_SIZE = $clog2(8*1024);
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localparam int CHDR_FIFO_SIZE = $clog2(8*1024);
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localparam int RT_TBL_SIZE = 6;
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localparam bit DROP_UNKNOWN_MAC = 0;
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localparam bit DROP_MIN_PACKET = 0;
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localparam int PREAMBLE_BYTES = 6;
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localparam bit ADD_SOF = 1;
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localparam bit SYNC = 0;
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localparam bit PAUSE_EN = 0;
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localparam bit EN_RX_KV_MAP_CFG = EN_RAW_UDP;
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localparam bit EN_RX_RAW_PYLD = EN_RAW_UDP;
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logic [47:0] my_mac;
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logic [31:0] my_ip;
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logic [15:0] my_udp_chdr_port;
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eth_ipv4_interface_wrapper #(
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.PROTOVER (PROTOVER ),
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.CPU_FIFO_SIZE (CPU_FIFO_SIZE ),
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.CHDR_FIFO_SIZE (CHDR_FIFO_SIZE ),
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.NODE_INST (NODE_INST ),
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.RT_TBL_SIZE (RT_TBL_SIZE ),
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.REG_AWIDTH (REG_AWIDTH ),
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.BASE (BASE ),
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.DROP_UNKNOWN_MAC (DROP_UNKNOWN_MAC),
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.DROP_MIN_PACKET (DROP_MIN_PACKET ),
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.PREAMBLE_BYTES (PREAMBLE_BYTES ),
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.ADD_SOF (ADD_SOF ),
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.SYNC (SYNC ),
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.PAUSE_EN (PAUSE_EN ),
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.ENET_W (ENET_W ),
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.CPU_W (CPU_W ),
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.CHDR_W (CHDR_W ),
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.NET_CHDR_W (NET_CHDR_W ),
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.EN_RX_KV_MAP_CFG (EN_RX_KV_MAP_CFG),
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.EN_RX_RAW_PYLD (EN_RX_RAW_PYLD )
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) eth_ipv4_interface_wrapper_dut (
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.bus_clk (bus_clk ),
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.bus_rst (bus_rst ),
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.device_id (DEVICE_ID ),
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.reg_wr_req (regport.wr_req ),
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.reg_wr_addr (regport.wr_addr ),
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.reg_wr_data (regport.wr_data ),
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.reg_rd_req (regport.rd_req ),
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.reg_rd_addr (regport.rd_addr ),
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.reg_rd_resp (regport.rd_resp ),
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.reg_rd_data (regport.rd_data ),
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.my_mac (my_mac ),
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.my_ip (my_ip ),
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.my_udp_chdr_port(my_udp_chdr_port),
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.eth_clk (eth_clk ),
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.eth_rst (eth_rst ),
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.eth_pause_req ( ),
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.eth_tx_tdata (eth_tx.tdata ),
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.eth_tx_tuser (eth_tx.tuser ),
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.eth_tx_tkeep (eth_tx_tkeep ),
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.eth_tx_tlast (eth_tx.tlast ),
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.eth_tx_tvalid (eth_tx.tvalid ),
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.eth_tx_tready (eth_tx.tready ),
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.eth_rx_tdata (eth_rx.tdata ),
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.eth_rx_tuser (eth_rx.tuser ),
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.eth_rx_tlast (eth_rx.tlast ),
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.eth_rx_tvalid (eth_rx.tvalid ),
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.eth_rx_tready (eth_rx.tready ),
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.e2v_tdata (e2v.tdata ),
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.e2v_tlast (e2v.tlast ),
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.e2v_tvalid (e2v.tvalid ),
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.e2v_tready (e2v.tready ),
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.v2e_tdata (v2e.tdata ),
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.v2e_tlast (v2e.tlast ),
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.v2e_tvalid (v2e.tvalid ),
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.v2e_tready (v2e.tready ),
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.cpu_clk (cpu_clk ),
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.cpu_rst (cpu_rst ),
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.e2c_tdata (e2c.tdata ),
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.e2c_tuser (e2c.tuser ),
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.e2c_tlast (e2c.tlast ),
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.e2c_tvalid (e2c.tvalid ),
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.e2c_tready (e2c.tready ),
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.c2e_tdata (c2e.tdata ),
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.c2e_tuser (c2e.tuser ),
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.c2e_tlast (c2e.tlast ),
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.c2e_tvalid (c2e.tvalid ),
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.c2e_tready (c2e.tready )
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);
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//---------------------------------------------------------------------------
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// TKEEP/TUSER Checker
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//---------------------------------------------------------------------------
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//
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// The DUT has both a TKEEP on eth_tx as well as TUSER, which gives the
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// number of valid trailing bytes. Devices can use either. This testbench
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// uses TUSER, so here we confirm that TKEEP matches TKEEP at all times.
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//
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//---------------------------------------------------------------------------
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always @(posedge eth_clk) begin
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if (eth_tx.tvalid && eth_tx.tready) begin
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// TUSER will be 0 if all the bytes are valid, which is the most common.
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if (eth_tx.tuser == 0) begin
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`ASSERT_ERROR(eth_tx_tkeep == '1, "TKEEP should be all ones");
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end else begin
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// Count the number of consecutive TKEEP bits
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automatic int valid_bytes = 0;
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for (int i = 0; i < eth_tx.DATA_WIDTH/8; i++) begin
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if (eth_tx_tkeep[i]) valid_bytes += 1;
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else break;
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end
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// Make sure there are no other bits set
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`ASSERT_ERROR(eth_tx_tkeep == 2**valid_bytes-1, "eth_tx.TKEEP ones are not contiguous");
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// Make sure TKEEP matches TUSER
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`ASSERT_ERROR(valid_bytes == eth_tx.tuser, "eth_tx.TKEEP/TUSER mismatch");
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// Make sure TUSER does not exceed its range (it should be 0 when all
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// bytes are valid).
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`ASSERT_ERROR(eth_tx.tuser < eth_tx.DATA_WIDTH/8, "eth_tx.TUSER exceeds range")
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end
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end
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end
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//---------------------------------------------------------------------------
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// Helper Tasks
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//---------------------------------------------------------------------------
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// 4-state byte queue data type
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typedef logic [7:0] logic_byte_queue_t[$];
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// Structure to describe a stream configuration
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typedef struct packed {
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bit [15:0] dst_epid;
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bit [47:0] eth_mac;
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bit [15:0] udp_port;
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bit [31:0] ip_addr;
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bit raw_udp;
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} stream_cfg_t;
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// Queue of stream configurations to use for the simulation
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stream_cfg_t stream_cfgs[$];
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// Convert 2-state byte queue to 4-state byte queue
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function automatic logic_byte_queue_t bytes_to_logic_queue(byte bytes[$]);
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logic [7:0] logic_bytes[$];
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foreach(bytes[i]) logic_bytes[i] = bytes[i];
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return logic_bytes;
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endfunction : bytes_to_logic_queue
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// Setup a stream route through the transport adapter. This can be CHDR or
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// raw UDP.
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task automatic config_stream(input stream_cfg_t cfg);
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logic [31:0] val;
|
|
|
|
|
|
|
|
|
|
// Poll on BUSY bit
|
|
|
|
|
do begin
|
|
|
|
|
regport.read(REG_XPORT_KV_CFG, val);
|
|
|
|
|
end while(val & (1 << 31));
|
|
|
|
|
|
|
|
|
|
// Add route to KV map
|
|
|
|
|
regport.write(REG_XPORT_KV_MAC_LO, cfg.eth_mac & 32'hFFFFFFFF);
|
|
|
|
|
regport.write(REG_XPORT_KV_MAC_HI, (cfg.eth_mac >> 32) & 32'hFFFFFFFF);
|
|
|
|
|
regport.write(REG_XPORT_KV_IP, cfg.ip_addr);
|
|
|
|
|
regport.write(REG_XPORT_KV_UDP, cfg.udp_port);
|
|
|
|
|
regport.write(REG_XPORT_KV_CFG, {cfg.raw_udp, cfg.dst_epid});
|
|
|
|
|
|
|
|
|
|
// Make sure config is complete before attempting to use it
|
|
|
|
|
do begin
|
|
|
|
|
regport.read(REG_XPORT_KV_CFG, val);
|
|
|
|
|
end while(val & (1 << 31));
|
|
|
|
|
endtask : config_stream
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Generate the list streams to use for simulation and program stream
|
|
|
|
|
// configurations into the DUT's KV map.
|
|
|
|
|
task automatic config_test_streams();
|
|
|
|
|
for (int count=0; count < NUM_EPID; count++) begin
|
|
|
|
|
stream_cfg_t cfg;
|
|
|
|
|
// Stream configuration to use for this test
|
|
|
|
|
cfg.eth_mac = Rand#(48)::rand_bit();
|
|
|
|
|
cfg.ip_addr = Rand#(32)::rand_bit();
|
|
|
|
|
cfg.udp_port = Rand#(16)::rand_bit();
|
|
|
|
|
cfg.dst_epid = Rand#(16)::rand_bit();
|
|
|
|
|
// If raw UDP is enabled, make half the streams CHDR and half raw UDP
|
|
|
|
|
cfg.raw_udp = (count % 2 == 0);
|
|
|
|
|
if (cfg.raw_udp) $display("Adding raw UDP route");
|
|
|
|
|
else $display("Adding normal CHDR route");
|
|
|
|
|
|
|
|
|
|
// Setup route for this data stream
|
|
|
|
|
config_stream(cfg);
|
|
|
|
|
|
|
|
|
|
// Save configuration in the list of streams to refer to later
|
|
|
|
|
stream_cfgs.push_back(cfg);
|
|
|
|
|
end
|
|
|
|
|
endtask : config_test_streams
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
// Tests
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
task automatic test_reset();
|
|
|
|
|
test.start_test("Reset", 1us);
|
|
|
|
|
bus_clk_gen.reset();
|
|
|
|
|
eth_clk_gen.reset();
|
|
|
|
|
cpu_clk_gen.reset();
|
|
|
|
|
if (bus_rst) @bus_rst;
|
|
|
|
|
if (eth_rst) @eth_rst;
|
|
|
|
|
if (cpu_rst) @cpu_rst;
|
|
|
|
|
test.end_test();
|
|
|
|
|
endtask : test_reset
|
|
|
|
|
|
|
|
|
|
// Initialize all the registers for the testbench to run, testing them in
|
|
|
|
|
// the process.
|
|
|
|
|
task automatic test_regs();
|
|
|
|
|
logic [31:0] val;
|
|
|
|
|
|
|
|
|
|
test.start_test("Initialize registers", 10us);
|
|
|
|
|
|
|
|
|
|
// Configure the registers
|
|
|
|
|
regport.write(REG_MAC_LSB, MAC_ADDR);
|
|
|
|
|
regport.write(REG_MAC_MSB, MAC_ADDR >> 32);
|
|
|
|
|
regport.write(REG_IP, IP_ADDR);
|
|
|
|
|
regport.write(REG_UDP, UDP_PORT);
|
|
|
|
|
// Give the bridge different values to make sure they're unique
|
|
|
|
|
regport.write(REG_BRIDGE_MAC_LSB, MAC_ADDR+1);
|
|
|
|
|
regport.write(REG_BRIDGE_MAC_MSB, (MAC_ADDR >> 32)+1);
|
|
|
|
|
regport.write(REG_BRIDGE_IP, IP_ADDR+1);
|
|
|
|
|
regport.write(REG_BRIDGE_UDP, UDP_PORT+1);
|
|
|
|
|
regport.write(REG_BRIDGE_ENABLE, 1'b1);
|
|
|
|
|
|
|
|
|
|
// Verify the registers
|
|
|
|
|
regport.read(REG_MAC_LSB, val);
|
|
|
|
|
`ASSERT_ERROR(val == (MAC_ADDR & 32'hFFFFFFFF), "REG_MAC_LSB does not match");
|
|
|
|
|
regport.read(REG_MAC_MSB, val);
|
|
|
|
|
`ASSERT_ERROR(val == ((MAC_ADDR >> 32) & 32'hFFFFFFFF), "REG_MAC_MSB does not match");
|
|
|
|
|
regport.read(REG_IP, val);
|
|
|
|
|
`ASSERT_ERROR(val == IP_ADDR, "REG_IP does not match");
|
|
|
|
|
regport.read(REG_UDP, val);
|
|
|
|
|
`ASSERT_ERROR(val == UDP_PORT, "REG_UDP does not match");
|
|
|
|
|
regport.read(REG_BRIDGE_MAC_LSB, val);
|
|
|
|
|
`ASSERT_ERROR(val == (MAC_ADDR & 32'hFFFFFFFF)+1, "REG_BRIDGE_MAC_LSB does not match");
|
|
|
|
|
regport.read(REG_BRIDGE_MAC_MSB, val);
|
|
|
|
|
`ASSERT_ERROR(val == ((MAC_ADDR >> 32) & 32'hFFFFFFFF)+1, "REG_BRIDGE_MAC_MSB does not match");
|
|
|
|
|
regport.read(REG_BRIDGE_IP, val);
|
|
|
|
|
`ASSERT_ERROR(val == IP_ADDR+1, "REG_BRIDGE_IP does not match");
|
|
|
|
|
regport.read(REG_BRIDGE_UDP, val);
|
|
|
|
|
`ASSERT_ERROR(val == UDP_PORT+1, "REG_BRIDGE_UDP does not match");
|
|
|
|
|
regport.read(REG_BRIDGE_ENABLE, val);
|
|
|
|
|
`ASSERT_ERROR(val == 1'b1, "REG_BRIDGE_ENABLE does not match");
|
|
|
|
|
regport.read(REG_XPORT_COMPAT, val);
|
|
|
|
|
`ASSERT_ERROR(val == (COMPAT_MAJOR << 8) | (COMPAT_MINOR << 0),
|
|
|
|
|
"REG_XPORT_COMPAT does not match");
|
|
|
|
|
regport.read(REG_XPORT_INFO, val);
|
|
|
|
|
`ASSERT_ERROR(val == (EN_RX_RAW_PYLD << 1) | (EN_RX_KV_MAP_CFG << 0),
|
|
|
|
|
"REG_XPORT_INFO does not match");
|
|
|
|
|
regport.read(REG_XPORT_NODE_INST, val);
|
|
|
|
|
`ASSERT_ERROR(val == NODE_INST, "REG_XPORT_NODE_INST does not match");
|
|
|
|
|
|
|
|
|
|
// Disable the bridge for now
|
|
|
|
|
regport.write(REG_BRIDGE_ENABLE, 0);
|
|
|
|
|
regport.read(REG_BRIDGE_ENABLE, val);
|
|
|
|
|
`ASSERT_ERROR(val == 1'b0, "REG_BRIDGE_ENABLE does not match");
|
|
|
|
|
|
|
|
|
|
// Check the ports that mirror registers
|
|
|
|
|
`ASSERT_ERROR(my_mac == MAC_ADDR, "my_mac does not match");
|
|
|
|
|
`ASSERT_ERROR(my_ip == IP_ADDR, "my_ip does not match");
|
|
|
|
|
`ASSERT_ERROR(my_udp_chdr_port == UDP_PORT, "my_udp_chdr_port does not match");
|
|
|
|
|
|
|
|
|
|
test.end_test();
|
|
|
|
|
endtask : test_regs
|
|
|
|
|
|
|
|
|
|
// Do a constrained random test using a mixture of CHDR and raw UDP packets
|
|
|
|
|
// in the RX direction (RFNoC to Ethernet).
|
|
|
|
|
//
|
|
|
|
|
// num_pkts : Number of random packets to generate and test
|
|
|
|
|
// eth_stall_prob : Ethernet stall probability
|
|
|
|
|
// chdr_stall_prob : RFNoC stall probability
|
|
|
|
|
// max_length : Maximum payload length in bytes
|
|
|
|
|
//
|
|
|
|
|
task automatic test_rand_raw_udp_rx(
|
|
|
|
|
int num_pkts = 100,
|
|
|
|
|
int eth_stall_prob = 50,
|
|
|
|
|
int chdr_stall_prob = 50,
|
|
|
|
|
int max_length = 512
|
|
|
|
|
);
|
|
|
|
|
mailbox #(logic_byte_queue_t) mb_payloads;
|
|
|
|
|
mailbox #(stream_cfg_t) mb_stream_cfgs;
|
|
|
|
|
logic [31:0] val;
|
|
|
|
|
string test_str;
|
|
|
|
|
|
|
|
|
|
mb_payloads = new();
|
|
|
|
|
mb_stream_cfgs = new();
|
|
|
|
|
|
|
|
|
|
test_str = $sformatf(
|
|
|
|
|
"Test rand raw UDP (RX)\nArgs: num_pkts=%0d, eth_stall_prob=%0d, chdr_stall_prob=%0d, max_length=%0d",
|
|
|
|
|
num_pkts, eth_stall_prob, chdr_stall_prob, max_length
|
|
|
|
|
);
|
|
|
|
|
test.start_test(test_str, 10us*max_length);
|
|
|
|
|
|
|
|
|
|
// Set the stall probabilities
|
|
|
|
|
eth_bfm.set_slave_stall_prob(eth_stall_prob);
|
|
|
|
|
chdr_bfm.set_master_stall_prob(chdr_stall_prob);
|
|
|
|
|
|
|
|
|
|
fork
|
|
|
|
|
begin : packet_generation_process
|
|
|
|
|
int iter = 0;
|
|
|
|
|
repeat(num_pkts) begin : send_packet
|
|
|
|
|
item_t items[$];
|
|
|
|
|
packet_info_t pkt_info = 0;
|
|
|
|
|
stream_cfg_t stream_cfg;
|
|
|
|
|
int length;
|
|
|
|
|
|
|
|
|
|
// Choose a random stream to use for this packet
|
|
|
|
|
stream_cfg = stream_cfgs[$urandom_range(stream_cfgs.size()-1)];
|
|
|
|
|
|
|
|
|
|
// Generate a random packet
|
|
|
|
|
length = $urandom_range(1, max_length);
|
|
|
|
|
items = {};
|
|
|
|
|
for (int i=0; i < length; i++) begin
|
|
|
|
|
items.push_back(i);
|
|
|
|
|
end
|
|
|
|
|
chdr_bfm.dst_epid = stream_cfg.dst_epid;
|
|
|
|
|
|
|
|
|
|
// Put packet info into mailboxes
|
|
|
|
|
mb_payloads.put(items);
|
|
|
|
|
mb_stream_cfgs.put(stream_cfg);
|
|
|
|
|
|
|
|
|
|
// Send the packet
|
|
|
|
|
chdr_bfm.send_items(items);
|
|
|
|
|
|
|
|
|
|
iter++;
|
|
|
|
|
end : send_packet
|
|
|
|
|
end : packet_generation_process
|
|
|
|
|
|
|
|
|
|
begin : packet_checker_process
|
|
|
|
|
int iter = 0;
|
|
|
|
|
repeat(num_pkts) begin : recv_packet
|
|
|
|
|
item_t sent_items[$], rcvd_items[$];
|
|
|
|
|
stream_cfg_t stream_cfg;
|
|
|
|
|
int trailing_bytes;
|
|
|
|
|
int udp_payload_length;
|
|
|
|
|
AxisEthPacket_t axis_eth_pkt;
|
|
|
|
|
raw_pkt_t raw_pkt;
|
|
|
|
|
raw_pkt_t payload;
|
|
|
|
|
eth_hdr_t eth_hdr;
|
|
|
|
|
ipv4_hdr_t ipv4_hdr;
|
|
|
|
|
udp_hdr_t udp_hdr;
|
|
|
|
|
|
|
|
|
|
// Get packet info from mailboxes
|
|
|
|
|
mb_payloads.get(sent_items);
|
|
|
|
|
mb_stream_cfgs.get(stream_cfg);
|
|
|
|
|
|
|
|
|
|
// Grab the next packet
|
|
|
|
|
eth_bfm.get(axis_eth_pkt);
|
|
|
|
|
raw_pkt = axis_eth_pkt.dump_bytes();
|
|
|
|
|
|
|
|
|
|
// Figure out how many bytes of the last word are valid
|
|
|
|
|
if (axis_eth_pkt.user[$] > 0) begin
|
|
|
|
|
trailing_bytes = ENET_W/8 - axis_eth_pkt.user[$];
|
|
|
|
|
end else begin
|
|
|
|
|
trailing_bytes = 0;
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
// Extract the packet info
|
|
|
|
|
raw_pkt = raw_pkt[PREAMBLE_BYTES:$-trailing_bytes];
|
|
|
|
|
decode_udp_pkt(raw_pkt, eth_hdr, ipv4_hdr, udp_hdr, payload);
|
|
|
|
|
udp_payload_length = udp_hdr.length - 8;
|
|
|
|
|
rcvd_items = bytes_to_logic_queue(payload);
|
|
|
|
|
if (stream_cfg.raw_udp) begin
|
|
|
|
|
// Drop the trailing bytes
|
|
|
|
|
rcvd_items = rcvd_items[0:(udp_payload_length-1)];
|
|
|
|
|
end else begin
|
|
|
|
|
// Drop the CHDR header and trailing bytes
|
|
|
|
|
rcvd_items = rcvd_items[NET_CHDR_W/8:(udp_payload_length-1)];
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
// Debug prints
|
|
|
|
|
if (DEBUG) begin
|
|
|
|
|
$display("UDP payload length is %0d", udp_payload_length);
|
|
|
|
|
$display("Expecting is_raw=%0b, sent_items=%p", stream_cfg.raw_udp, sent_items);
|
|
|
|
|
$display("Received rcvd_items=%p", rcvd_items);
|
|
|
|
|
$display("Finished iteration %0d", iter);
|
|
|
|
|
end
|
|
|
|
|
iter++;
|
|
|
|
|
|
|
|
|
|
// Check the UDP/IP/Eth layers for correct information
|
|
|
|
|
`ASSERT_ERROR(eth_hdr.dest_mac == stream_cfg.eth_mac, "Incorrect dest MAC addr");
|
|
|
|
|
`ASSERT_ERROR(ipv4_hdr.dest_ip == stream_cfg.ip_addr, "Incorrect dest IP addr");
|
|
|
|
|
`ASSERT_ERROR(udp_hdr.dest_port == stream_cfg.udp_port, "Incorrect dest UDP port");
|
|
|
|
|
|
|
|
|
|
// Check the payload
|
|
|
|
|
`ASSERT_ERROR(
|
|
|
|
|
ChdrData #(CHDR_W, ITEM_W)::item_equal(sent_items, rcvd_items),
|
|
|
|
|
"UDP payload doesn't match packet sent"
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
end : recv_packet
|
|
|
|
|
end : packet_checker_process
|
|
|
|
|
join
|
|
|
|
|
|
|
|
|
|
test.end_test();
|
|
|
|
|
|
|
|
|
|
endtask : test_rand_raw_udp_rx
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
// Main
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
initial begin : tb_main
|
|
|
|
|
string tb_name;
|
|
|
|
|
|
|
|
|
|
//----------
|
|
|
|
|
// TB Setup
|
|
|
|
|
//----------
|
|
|
|
|
|
|
|
|
|
tb_name = $sformatf(
|
|
|
|
|
"eth_ipv4_interface_tb\nENET_W = %0D, CPU_W = %0D, CHDR_W = %0D, NET_CHDR_W = %0D",
|
|
|
|
|
ENET_W, CPU_W, CHDR_W, NET_CHDR_W
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
test.start_tb(tb_name);
|
|
|
|
|
|
|
|
|
|
// Initialize the regport bus
|
|
|
|
|
regport.init();
|
|
|
|
|
|
|
|
|
|
// Don't start the clocks until after start_tb() returns. This ensures that
|
|
|
|
|
// the clocks aren't toggling while other instances of this testbench are
|
|
|
|
|
// running, which speeds up simulation time.
|
|
|
|
|
bus_clk_gen.start();
|
|
|
|
|
eth_clk_gen.start();
|
|
|
|
|
cpu_clk_gen.start();
|
|
|
|
|
|
|
|
|
|
// Start the BFMs running
|
|
|
|
|
chdr_bfm.run();
|
|
|
|
|
eth_bfm.run();
|
|
|
|
|
|
|
|
|
|
//-----------
|
|
|
|
|
// Run tests
|
|
|
|
|
//-----------
|
|
|
|
|
|
|
|
|
|
test_reset();
|
|
|
|
|
test_regs();
|
|
|
|
|
|
|
|
|
|
if (EN_RAW_UDP) begin
|
|
|
|
|
// Configure streams for testing of raw UDP feature
|
|
|
|
|
config_test_streams();
|
|
|
|
|
test_rand_raw_udp_rx(500, 0, 0); // No back-pressure
|
|
|
|
|
test_rand_raw_udp_rx(500, 75, 0); // Back-pressure
|
|
|
|
|
test_rand_raw_udp_rx(500, 0, 75); // Underflow
|
|
|
|
|
test_rand_raw_udp_rx(500, 50, 50); // Random-balanced
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
//--------------------
|
|
|
|
|
// Finish
|
|
|
|
|
//--------------------
|
|
|
|
|
|
|
|
|
|
// End the TB, but don't $finish, since we don't want to kill other
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// instances of this testbench that may be running.
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test.end_tb(0);
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// Kill the clocks to end this instance of the testbench
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bus_clk_gen.kill();
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eth_clk_gen.kill();
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cpu_clk_gen.kill();
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end : tb_main
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endmodule : eth_ipv4_interface_tb
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`default_nettype wire
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Wade Fife