Wade Fife f9d20d2a7f fpga: tools: Fix error detection in run_testbenches.py ...

This fixes recognition of $error and $fatal statements in the output of
XSim when running run_testbenches.py. XSim apparently prints a "shift
in" character (0x15) as part of its error statements, so the regular
expression was not matching.


Original-commit: ee36d7fabcf73f773edae00fbb1604a600db992d

2023-01-09 15:40:17 -06:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: rfnoc: Add timed sample alignment to radio

2022-12-19 08:57:18 -06:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Fix error detection in run_testbenches.py

2023-01-09 15:40:17 -06:00

top

fpga: e320 Change MIG arbitration to RD_PRI_REG

2022-11-08 08:20:48 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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