miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: e320 Change MIG arbitration to RD_PRI_REG

Browse Source 
Original-commit: 2a27f72f86e74c569e5ea158a5ca9cde68c41a97
This commit is contained in:
Wade Fife
2022-11-08 08:20:48 -06:00
parent 104ae54542
commit 7dc93d0e8c
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj
+1 -1
View File
@@ -150,7 +150,7 @@
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>31</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>