From 7dc93d0e8cb2cc1153b0490ea4f3ac96d830ed01 Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Thu, 3 Nov 2022 10:51:11 -0500
Subject: [PATCH] fpga: e320 Change MIG arbitration to RD_PRI_REG

Original-commit: 2a27f72f86e74c569e5ea158a5ca9cde68c41a97
---
 top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj b/top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj
index eebc03e..f6364c4 100644
--- a/top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj
+++ b/top/e320/ip/ddr3_32bit/mig_xc7z045ffg900-3.prj
@@ -150,7 +150,7 @@
         <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
         <PortInterface>AXI</PortInterface>
         <AXIParameters>
-            <C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
+            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
             <C0_S_AXI_ADDR_WIDTH>31</C0_S_AXI_ADDR_WIDTH>
             <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
             <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>