Wade Fife 6981891978 fpga: lib: Add verilog-compatible wrapper for eth_ipv4_interface ...

Original-commit: 7052a4f02bb5cab0a2ee7339af5f1e15da087a7b

2022-08-29 17:01:45 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add verilog-compatible wrapper for eth_ipv4_interface

2022-08-29 17:01:45 -05:00

sim

fpga: sim: Workaround Vivado bug in ChdrIfaceBfm_tb

2022-08-25 13:55:30 -05:00

tools

fpga: tools: Fix HLS IP builder for Vivado 2021.1

2022-08-25 13:55:30 -05:00

top

fpga: x400: Bump FPGA compat to 7.9

2022-08-29 17:01:45 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%