Wade Fife a40550497a fpga: lib: Add align_samples module ...

This module supports timed sample alignment by shifting radio words
with multiple samples per cycle to put the first sample into the
correct position for the required timestamp.


Original-commit: 0a13db4afaaf88dda3bd194bbf20271c690d5c7f

2022-12-19 08:57:18 -06:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add align_samples module

2022-12-19 08:57:18 -06:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Detect check_timing issues during build

2022-11-18 14:53:41 -06:00

top

fpga: e320 Change MIG arbitration to RD_PRI_REG

2022-11-08 08:20:48 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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