Wade Fife 82321919dd fpga: lib: Add verilog-compatible wrapper for eth_ipv4_chdr_adapter ...

Original-commit: 100a3f07938ab4746d8cec132ae5d83c0065c4d1

2023-01-10 14:18:59 -08:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add verilog-compatible wrapper for eth_ipv4_chdr_adapter

2023-01-10 14:18:59 -08:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Fix error detection in run_testbenches.py

2023-01-09 15:40:17 -06:00

top

fpga: e320 Change MIG arbitration to RD_PRI_REG

2022-11-08 08:20:48 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

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Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%