Wade Fife 2a74e8cd67 fpga: lib: Add RegPort SystemVerilog interface ...

Original-commit: d628c136a0cca7dddc47711f86f52f2c9e2ca089

2022-08-29 17:01:45 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add RegPort SystemVerilog interface

2022-08-29 17:01:45 -05:00

sim

fpga: sim: Support unused tkeep in AxiStreamPacket::dump_bytes()

2022-08-29 17:01:45 -05:00

tools

fpga: tools: Fix HLS IP builder for Vivado 2021.1

2022-08-25 13:55:30 -05:00

top

fpga: n3xx: Bump FPGA compat to 8.1

2022-08-29 17:01:45 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

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