Wade Fife 20340f7054 fpga: lib: Add compat to Verilog transport adapter ...

Original-commit: e716c8c720718f69d39823b722f5e013df99a3d5

2022-08-29 17:01:45 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add compat to Verilog transport adapter

2022-08-29 17:01:45 -05:00

sim

fpga: sim: Workaround Vivado bug in ChdrIfaceBfm_tb

2022-08-25 13:55:30 -05:00

tools

fpga: tools: Fix HLS IP builder for Vivado 2021.1

2022-08-25 13:55:30 -05:00

top

fpga: e320: Support advanced transport adapter

2022-08-29 17:01:45 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%