This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that
can be used to stitch onto Verilog port_maps.
Original-commit: 6ef642e3ac44c52b98b124f30dc84b1683859989
This module takes an AXI-Stream without TLAST and outputs the
same AXI-Stream with TLAST based on the provided packet size
input.
Original-commit: b0b3849a18e1f2d3cb255a507b01ac5e7a9416a0
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
- Fixed some incorrect comments
- Fixed some missing wire declarations for internal NIC
- Fix wire declarations for GPIO (they were declared too late)
Original-commit: b18eaa75de2d1dcba2a1be0ee0b862a57e976cca
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
Contains a fix for the AXI4LITE_ASSIGN macro, and adds
AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and
AXI4LITE_DEBUG_ASSIGN macros.
Original-commit: c718faf3387a07a9a1b86ab473f6ed7ac4cb493a
Components are connected together with AxiStreamIfc. Some features
include:
(1) Add bytes to the start of a packet
(2) Remove bytes from a packet
(3) Wrappers for some older components
a. fifo - buffer but imediately pass a packet
b. packet_gate - buffer and hold till end of packet
c. width_conv - cross clock domains and change width of axi bus
The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
- reached_packet_byte - notify when tdata contains a paritcular byte
- get_packet_byte/get_packet_field - extract a byte or field from axi
- put_packet_byte/put_packet_field - overwrite a byte or field onto axi
Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
(1) Synthesizable AxiLiteIf
(2) Simulation model for AxiLite contains an AxiLiteTransaction class
and an AxiLiteBfm class.
Important Methods
a. wr - performs non-blocking write and checks for expected response
b. wr_block - performs a blocking write and provides response
c. rd - performs a non-blocking read and checks for expected response
d. rd_block - persforms a blocking read and provides response
The model allows parallel execution of reads and writes, but enforces
rd and write ordering when using the above methods. When transactions
are posted directly, ordering is not guaranteed, and reads and writes
are put on the interface immediately.
Original-commit: afee1888dd7c2d9d95e537f505ce7ab36252763a
Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.
Used in xport when calculating new UDP headers for CHDR traffic.
Original-commit: dd9847c5c3c3fac17658b526a7d8894711af086e
This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and
chdr_stream_endpoint blocks so that wider CHDR widths are properly
supported. It also updates PkgChdrBfm to able to properly test these
blocks. The testbenches have been updated to test both 64 and 512-bit
widths.
Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This
commit adds a second spi core with capability to transfer up to 64 bits
while keeping the same amount of resources when using generic setting
MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the
edges of sclk. The register stages were not aligned in the existing
version.
Original-commit: 366cab1fef44f1132a2acf8046ecaeac80793ccc
During recreation of block diagrams any RTL modules will be kept in
hidden directories within the build directory. Updates of the RTL
sources might not be taken into account. Solution is to remove Xilinx's
hidden project directories before calling vivado.
Original-commit: f17a5113e228ac1bc5312193eb8f687e127184a3
Previously, if a write occurred before the FIFO was ready then a
write could hang as the data channel would complete but leave the
address channel in a state where it would never complete. The fix is
to hold off acknowledging on the data channel until the FIFO is ready.
Original-commit: 3f6ad749b06094b0e16b412a791ba3f2ac509600
Add DEFAULT_M and DEFAULT_N parameters for rate changing cores.
This allows the host to not need to configure fixed rate change
cores.
Original-commit: 983fad664436301c31c3bc8c81b538a41537598b
This change allows detection of attempting to execute setupenv.sh
rather than sourcing it, which is required.
Original-commit: 6faec1d4a14a1af52681aabf19c9040dcee772ff
This adds support for colored output and support for directories added
to the list of source files (for HLS support).
Original-commit: 5b3d66e5b7cedb7098de3e4dbbee70af04a3626e
For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.
Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a
The address ranges configured for the AXI interconnect IP limited the
amount of accessible DRAM to two 32 MB regions. This change makes the
full 1G available to all DRAM ports.
Original-commit: bba0cddfadcb744e8a6fae27d57ba8d3995eaf64
Andrew Moch