Max Köhler 8875582763 fpga: lib: add extended spi core for 64bit ...

The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This
commit adds a second spi core with capability to transfer up to 64 bits
while keeping the same amount of resources when using generic setting
MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the
edges of sclk. The register stages were not aligned in the existing
version.


Original-commit: 366cab1fef44f1132a2acf8046ecaeac80793ccc

2020-06-17 07:13:20 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: add extended spi core for 64bit

2020-06-17 07:13:20 -05:00

sim

fpga: sim: Add packet_info_equal function

2020-05-28 15:04:05 -05:00

tools

fpga: tools: remove temporary Xilinx directories for BD recreation

2020-06-15 13:54:35 -05:00

top

fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin

2020-06-12 15:50:16 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%