RobertWalstab 0361a8fa3b e31x: Swap out liberio for internal Ethernet ...

Original-commit: 3f823004600472c7f4b173a0da83a3bd53968c40

2020-07-16 10:00:12 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax

2020-07-10 15:12:55 -05:00

sim

fpga: lib: Add synthesizable AXI4-Stream SV components

2020-06-25 14:44:04 -05:00

tools

fpga: lib: Add width agnostic version of Ethernet Interface

2020-06-30 10:29:35 -05:00

top

e31x: Swap out liberio for internal Ethernet

2020-07-16 10:00:12 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

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Verilog 42.5%

VHDL 13%

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