b210-k7-fpga

T

Andrew Moch cb90fe98ef fpga: lib: Fix writes in axil_regport_master

Previously, if a write occurred before the FIFO was ready then a
write could hang as the data channel would complete but leave the
address channel in a state where it would never complete. The fix is
to hold off acknowledging on the data channel until the FIFO is ready.


Original-commit: 3f6ad749b06094b0e16b412a791ba3f2ac509600

2020-06-04 11:53:10 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Fix writes in axil_regport_master

2020-06-04 11:53:10 -05:00

sim

fpga: sim: Add packet_info_equal function

2020-05-28 15:04:05 -05:00

tools

fpga: tools: Improve detection of setupenv sourcing