miegl/b210-k7-fpga
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b210-k7-fpga/lib
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Andrew Moch cb90fe98ef fpga: lib: Fix writes in axil_regport_master 
Previously, if a write occurred before the FIFO was ready then a
write could hang as the data channel would complete but leave the
address channel in a state where it would never complete. The fix is
to hold off acknowledging on the data channel until the FIFO is ready.


Original-commit: 3f6ad749b06094b0e16b412a791ba3f2ac509600
2020-06-04 11:53:10 -05:00
..
axi
fpga: lib: Add AXI-Stream splitter (axis_split)
2020-04-14 16:37:43 -05:00
control
fpga: lib: Fix writes in axil_regport_master
2020-06-04 11:53:10 -05:00
control_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dsp
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00
extramfifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gpif2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
hls
fpga: rfnoc: Add RFNoC Add/Sub block
2020-05-28 15:04:05 -05:00
io_cap_gen
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
io_port2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ip
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
packet_proc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
packet_proc_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
radio_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
rfnoc
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
sim
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
simple_gemac
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing
fixup! lib: add option for output register in pps generator
2020-02-05 09:26:57 -06:00
vita_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
vivado_ipi
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
wb_spi
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
white_rabbit/wr_cores_v4_2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
wishbone
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge_interface
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zpu
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zynq_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00