Andrew Moch 6606757fa7 fpga: lib: Update AxiLiteIf ...

This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that
can be used to stitch onto Verilog port_maps.


Original-commit: 6ef642e3ac44c52b98b124f30dc84b1683859989

2020-07-31 11:55:47 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Update AxiLiteIf

2020-07-31 11:55:47 -05:00

sim

fpga: lib: Add synthesizable AXI4-Stream SV components

2020-06-25 14:44:04 -05:00

tools

fpga: tools: RESOLVE_PATH checks for an empty path

2020-07-30 15:00:06 -05:00

top

fpga, mpm: Bump FPGA compat number

2020-07-24 15:24:14 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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