Andrew Moch 9b0e42678f fpga: lib: Add features to axi_lite.vh ...

Contains a fix for the AXI4LITE_ASSIGN macro, and adds
AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and
AXI4LITE_DEBUG_ASSIGN macros.


Original-commit: c718faf3387a07a9a1b86ab473f6ed7ac4cb493a

2020-06-26 10:36:37 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Add features to axi_lite.vh

2020-06-26 10:36:37 -05:00

sim

fpga: lib: Add synthesizable AXI4-Stream SV components

2020-06-25 14:44:04 -05:00

tools

fpga: lib: Add synthesizable AXI4-Stream SV components

2020-06-25 14:44:04 -05:00

top

fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin

2020-06-12 15:50:16 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%