miegl/b210-k7-fpga
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Max Köhler 2a8ec5df90 fpga: tools: remove temporary Xilinx directories for BD recreation 
During recreation of block diagrams any RTL modules will be kept in
hidden directories within the build directory. Updates of the RTL
sources might not be taken into account. Solution is to remove Xilinx's
hidden project directories before calling vivado.


Original-commit: f17a5113e228ac1bc5312193eb8f687e127184a3
2020-06-15 13:54:35 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: lib: extend wb_spi ability to limit transmission length
2020-06-04 14:46:19 -05:00
sim
fpga: sim: Add packet_info_equal function
2020-05-28 15:04:05 -05:00
tools
fpga: tools: remove temporary Xilinx directories for BD recreation
2020-06-15 13:54:35 -05:00
top
fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin
2020-06-12 15:50:16 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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