Andrew Moch b76ad2aef5 fpga: lib: Pipeline and add clken to ip_hdr_checksum ...

Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.

Used in xport when calculating new UDP headers for CHDR traffic.


Original-commit: dd9847c5c3c3fac17658b526a7d8894711af086e

2020-06-24 09:55:14 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga: lib: Pipeline and add clken to ip_hdr_checksum

2020-06-24 09:55:14 -05:00

sim

fpga: rfnoc: Add support for 512-bit CHDR widths

2020-06-18 09:09:34 -05:00

tools

fpga: tools: Fix ModelSim return status

2020-06-18 15:26:07 -05:00

top

fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin

2020-06-12 15:50:16 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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