miegl/b210-k7-fpga
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RobertWalstab 6dfa273771 fpga: remove liberio 
Original-commit: 83a4756c957dd7698baeb56e13260d8edaa7bc2e
2020-07-20 16:01:03 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: remove liberio
2020-07-20 16:01:03 -05:00
sim
fpga: lib: Add synthesizable AXI4-Stream SV components
2020-06-25 14:44:04 -05:00
tools
fpga: lib: Add width agnostic version of Ethernet Interface
2020-06-30 10:29:35 -05:00
top
fpga: remove liberio
2020-07-20 16:01:03 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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84 MiB
Languages
Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%