This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to
the location of the UHD "fpga" directory. This allows you to include
files in your out-of-tree modules relative to the FPGA directory. For
example, you could include the library header file rfnoc_chdr_utils.vh
using the following:
`include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
Some simulators may not support `" outside of the context of a `define,
in which case you can do the following:
`define RFNOC_CHDR_UTILS_PATH \
`"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
`include `RFNOC_CHDR_UTILS_PATH
Original-commit: 66267f515802ff3f965fd44e1f0d3097ada7484f
This sets the ARCH and PART_ID environment variables so that the
selected part family is used for simulations by default. This can be
overridden by changing them in the Makefile for the testbench if a
testbench requires a specific part family. Prior to this change, the
default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which
required support for that part to be installed.
Original-commit: c176046dff4941bcec27b0b72e5a68264c4808e5
The script was previously only Python 2 compatible.
Python 2 support is now removed, so we don't maintain backwards
compatibility with Python 2.
This also fixes all linter warnings.
Original-commit: 6046e1a812ba2065d6ae13b4c4afdce8abc99d4f
Modified to send 2 packets back to back at each packet size to test
output during sequential input packets. Also fixed whitespace.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 439770b964be45e6160cf99a0b1551fdd2002fa9
Added delay to error packets so overrun error is back in-band. Avoids
dropping good data packets in the case of an overrun.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: a69e6fcdc79dfa1ea48c99092b6edb9633b6fb24
Re-wrote converter to remove clock cycle delay on i_tready when handling
residual output and fixed improper handling of tlast during residual
data processing. Resolves some USB overflow issues when using sc12 data
type on B200 devices.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 1fecf446e0358aa2b6a2d1f73a0daeac516435a0
There were some rare corner cases where the EOB could get lost in the
DUC due to the dds_timed logic not always passing it through as it
should. This resulted in an underflow error message at the end of
transmission.
This commit also fixes an issue where part of the last packet
used a frequency shift of 0 instead of the requested frequency
shift, and an issue where the first few samples of a burst used the
wrong frequency shift value.
Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only.
The TUSER port is built into the IP but was disabled. It is now
enabled and set to 1 bit wide. This has a very small effect on
resource usage and can be left unconnected when not needed.
The dds_freq_tune block was shared by the DUC and DDC. To avoid
affecting the DDC, a new version, dds_freq_tune_duc, is being
added for the DUC to use that has the necessary fixes.
The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP.
This IP has the undesirable behavior that new inputs must be provided
to push previous outputs through the IP. This wrapper hides that
complexity by adding some logic to ensure all data gets pushed through
automatically. This logic uses the TUSER port on the IP.
Finally, a testbench for dds_timed was added.
Original-commit: 77975d108a704ce18ec52b4ee1764381b1893752
PkgComplex adds functions for doing complex arithmetic in SystemVerilog
simulation.
PkgMath provides mathematical operations and constants that aren't
built into SystemVerilog, such as a constant for pi and the function
round().
PkgRandom adds randomization functions beyond what standard Verilog
supports but that don't require any special licenses or simulators.
Original-commit: da4202e6f74796603072aa14544581604e81df02
Updated some comments that still referenced the old CORDIC
implementation, which is no longer used.
Original-commit: 18e5bdfa100a40376147d1a497645345b2a938b1
Reconnect the signals from the White Rabbit module to the TDC in the
FPGA.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: c0637bae1e4a0ddb996cf2b7eadfad22f782874b
White Rabbit is not supported in X410, however the register map included an
incorrect reference to this unsupported feature.
This commit removes the WR reference from both the source and html files.
Original-commit: 7edd92dbcf2da1a1c0fabe02a97fdb6afdc89077
This change allows assertion errors/failures in ModelSim to be
detected and causes ModelSim to return a non-zero value when such
an assertion error occurs. This allows the return value of ModelSim
to be used to determine whether or not the testbench passed.
Original-commit: 574146ec8909da367c3441189c2877a287892f7e
VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.
Original-commit: b85b796cbc1f897a69ded1f3ecfba8ec92684c11
This updates the existing PART_NAME generation used in simulation
makefiles to work with newer part families by calling
viv_gen_part_id.py to generate the part name needed by Vivado.
Original-commit: 648c70ae758ab1d15c7ec6cbe57672e8c27640cd
This is a list of testbenches that don't work with ModelSim and should
be excluded when running run_testbenches.py.
Original-commit: 6190eca14ec13db7456a059cbd69c93550aa45c7
This adds the MSIM_VIV_COMPLIBDIR environment variable to specify
a non-default location for the compilation libraries.
This also allows a modelsim.ini other than the one in the ModelSim
installation folder to be used. By default, the one in the simulation
libraries compilation directory will be used. This can be changed by
setting MSIM_MODELSIM_INI to the one you want to use, or set it to an
empty string to use the one in the ModelSim installation folder.
Original-commit: 08473776b28a949027ec8cf2596d8d1b438b979b
Run "make ip" in a separate step for each testbench. This allows some
testbenches to work better with ModelSim because it needs IP files that
aren't known until after the IP is generated.
Make run_testbenches.py more log friendly. Add a -l/--logged option for
when the output is being logged. In this case, we don't want to display
elapsed time every second.
Add "Begin TB Log:" and "End TB Log:" to the output to more easily tell
where the output from one testbench ends and another begins.
Use the basedir argument as the base directory in which to search for
testbenches so that a subset of the repo can be easily specified.
Original-commit: 5a4f0470919440819ab71f44fbc6f5f89a671e41
Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.
Original-commit: b0033158a4c520063540881451d8daac91e98714
The script setupenv_base.sh, which is used to setup the development
environmnet in the open source toolchain, adds some functions to the
shell that are used to interact with vivado. Some of the functions were
looking in the wrong argument for the product name. This commit fixes
the bug.
In addition, supplying an incorrect part name returned a rather opaque
error message. This commit also fixes the error handling so that the
intended error message is displayed.
Signed-off-by: Sam O'Brien <sam.obrien@ni.com>
Original-commit: 471de61e4d9e53a038942f21f61d4b481b5f9853
Change version from a numeric to a string, in order to
differentiate between versions like "1.1" and "1.10".
Original-commit: ca21048bd2f832b20bb36763f76d46b861b697a5
Adds a time_increment port for situations in which the parameter
TIME_INCREMENT can't be used. They offer the same behavior.
Original-commit: f9c97371048bfc69182187e6d8904a01efbe6d79
This pipelines ctrlport_timer to eliminate the long combinational path
caused by the time comparisons. This change also removes the
PRECISION_BITS parameter and converts it to a signal named
time_ignore_bits.
Original-commit: c6035320215f270d7658cfb6195a96a0b84d6aa7
Add a SystemVerilog interface for connecting AXI4 ports, and an
associated header file with helper macros.
Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
This adds the ability to call BUILD_VIVADO_IP, as before, followed by
REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and
then rebuild the IP with the patched file.
Original-commit: 78315eca698333ad4dc32818e24c7bf6a740c0cb
This commit includes the following changes to the tools:
- Change part definition in XCI and BD editors for the RFSoC family
- Resolve part name in Vivado IP management utilities with
viv_gen_part_id.py
Original-commit: fba23eb42c91ca1bc1108b5ba50c1b567cb9b59d
Wade Fife